CN100550396C - Pixel and forming method thereof, storage capacitance, display floater and electrooptical device - Google Patents
Pixel and forming method thereof, storage capacitance, display floater and electrooptical device Download PDFInfo
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- CN100550396C CN100550396C CNB2007101010782A CN200710101078A CN100550396C CN 100550396 C CN100550396 C CN 100550396C CN B2007101010782 A CNB2007101010782 A CN B2007101010782A CN 200710101078 A CN200710101078 A CN 200710101078A CN 100550396 C CN100550396 C CN 100550396C
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Abstract
A kind of pixel and forming method thereof, and a kind of storage capacitance, display floater and electrooptical device.Storage capacitance is arranged on the substrate, and this storage capacitance comprises semiconductor layer, first dielectric layer, first conductive layer, second dielectric layer and second conductive layer.Wherein semiconductor layer is arranged on the substrate, and first dielectric layer then covers semiconductor layer and substrate, and first conductive layer partly is arranged on first dielectric layer.Second dielectric layer is arranged on first conductive layer, and the side of second dielectric layer and first conductive layer has a gradient.Second conductive layer then part is arranged on second dielectric layer.The present invention can promote the capacitance of storage capacitance, and keeps the stability of pixel imaging.
Description
Technical field
The present invention relates to a kind of flat-panel monitor, particularly relate to a kind of storage capacitance of flat-panel monitor.
Background technology
The viewing area of flat-panel monitor is made of several pixels.Each pixel has the thin-film transistor that a pixel electrode and connects this pixel electrode, and opens or close to thin-film transistor by the signal wire transmits signal.After pixel electrode provides voltage, thin-film transistor will cut out, and again voltage be write pixel electrode once more or delete from pixel electrode when being opened thin-film transistor by scan line next time.
Yet, for before scan line is opened thin-film transistor next time, can keep originally writing the voltage of pixel electrode, need storage capacitance (Storage Capacitor, C
St) increase whole capacitance, and make the voltage that writes pixel electrode can keep the long time.The electric weight that storage capacitance can be stored and the area of its two electrode are directly proportional, and are inversely proportional to its two distance between electrodes.
Yet, because the requirement of product resolution is increased day by day, cause Pixel Dimensions to reduce gradually, in order not influence aperture opening ratio, the area of storage capacitance certainly will will be compressed, and cause the decline of capacitance.In addition, by the prepared storage capacitance of known manufacturing process, its medium thickness is greater than 3000 dusts at least
Make the storage capacity of electric weight of storage capacitance be subjected to further restriction.In order to promote the capacitance of storage capacitance, become an important problem with the stability that keeps the pixel imaging.
Summary of the invention
The invention provides a kind of storage capacitance and manufacture method thereof, can promote the capacitance of storage capacitance.
The present invention proposes a kind of storage capacitance, it comprises the semiconductor layer that is arranged on the substrate, be covered in first dielectric layer on semiconductor layer and the substrate, be arranged at first conductive layer on the part of first dielectric layer, be arranged at second dielectric layer on first conductive layer, and be arranged at second conductive layer on part second dielectric layer.And the side that piles up of second dielectric layer and first conductive layer has a gradient (taper).
Aforesaid storage capacitance, wherein, at least one comprises transparent material, non-transparent material or above-mentioned combination in this first conductive layer and this second conductive layer.
Aforesaid storage capacitance, wherein, at least one comprises organic material, inorganic material or above-mentioned combination in this first dielectric layer and this second dielectric layer.
Aforesaid storage capacitance, wherein, this semiconductor layer comprises monocrystalline silicon, polysilicon, amorphous silicon, microcrystal silicon or above-mentioned combination.
Aforesaid storage capacitance, wherein, this semiconductor layer is this semiconductor layer of doped N-type, P type or above-mentioned combination.
Aforesaid storage capacitance, wherein, this semiconductor layer comprises at least one first doped region and at least one non-doped region.
Aforesaid storage capacitance, wherein, this semiconductor layer comprises at least one first doped region, at least one non-doped region and at least one light doping section.
Aforesaid storage capacitance wherein, also comprises etch stop layer, has at least one first, is arranged on part second dielectric layer.
Aforesaid storage capacitance, wherein, also comprise etch stop layer, have at least one first and at least one second portion, this first is arranged at the two ends of this second dielectric layer on one of them, and this second portion is arranged on the other end away from this second dielectric layer.
Aforesaid storage capacitance, wherein, the thickness of this second dielectric layer is in fact less than 3000 dusts
Aforesaid storage capacitance, wherein, the thickness of this second dielectric layer is in fact less than 1000 dusts
Aforesaid storage capacitance, wherein, the thickness of this second dielectric layer is in fact between 200 dusts
To 3000 dusts
Aforesaid storage capacitance, wherein, this second conductive layer is electrically connected at this semiconductor layer.
Aforesaid storage capacitance, wherein, this etch stop layer comprises the material layer.
The storage capacitance that the present invention proposes is applicable among a kind of pixel.Pixel is arranged on the substrate, and comprises switching device district and capacitive region.This pixel comprises semiconductor layer, first dielectric layer, first conductive layer, second dielectric layer, inner layer dielectric layer, source/drain electrode, protective layer and second conductive layer.Wherein semiconductor layer is arranged on the substrate, and first dielectric layer covers semiconductor layer and substrate.First conductive layer then is arranged at respectively on first dielectric layer of switching device district and capacitive region.Second dielectric layer then is positioned on first conductive layer.Partially-etched stop layer is arranged on second dielectric layer in switching device district.Inner layer dielectric layer is covered on the substrate.Source/drain electrode is arranged on the part inner layer dielectric layer in this switching device district, and is electrically connected at the semiconductor layer in the switching device district.Protective layer used in covered substrate.Second conductive layer is arranged on the partial protection layer, and electrically connect this source/drain electrode one of them, and via in the protective layer and this inner layer dielectric layer at least one opening, be arranged on part second dielectric layer.
Aforesaid pixel, wherein, at least one comprises transparent material, non-transparent material or above-mentioned combination in this first conductive layer and this second conductive layer.
Aforesaid pixel, wherein, at least one comprises organic material, inorganic material or above-mentioned combination in this first dielectric layer, this second dielectric layer and this inner layer dielectric layer.
Aforesaid pixel, wherein, this semiconductor layer comprises monocrystalline silicon, polysilicon, amorphous silicon, microcrystal silicon or above-mentioned combination.
Aforesaid pixel, wherein, at least one is this semiconductor layer of doped N-type, P type or above-mentioned combination in this semiconductor layer on this switching device district and this capacitive region.
Aforesaid pixel, wherein, at least one comprises at least one first doped region and at least one non-doped region in this semiconductor layer on this switching device district and this capacitive region.
Aforesaid pixel, wherein, at least one comprises at least one first doped region, at least one non-doped region and at least one light doping section in this semiconductor layer on this switching device district and this capacitive region.
Aforesaid pixel, wherein, another part etch stop layer has at least one first, is arranged on part second dielectric layer.
Aforesaid pixel, wherein, another part etch stop layer has at least one first and at least one second portion, and this first is arranged at the two ends of this second dielectric layer on one of them, and this second portion is arranged on the other end away from this second dielectric layer.
Aforesaid pixel, wherein, this etch stop layer comprises the material layer.
Aforesaid pixel, wherein, the side that piles up of this second dielectric layer and this first conductive layer has gradient (taper) in fact.
Aforesaid pixel, wherein, the thickness of this second dielectric layer is in fact less than 3000 dusts
Aforesaid pixel, wherein, the thickness of this second dielectric layer is in fact less than 1000 dusts
Aforesaid pixel, wherein, the thickness of this second dielectric layer is in fact between 200 dusts
To 3000 dusts
Aforesaid pixel wherein, also comprises articulamentum, to electrically connect this semiconductor layer on this switching device district and this capacitive region.
Aforesaid pixel, wherein, this articulamentum comprises monocrystalline silicon, polysilicon, amorphous silicon, microcrystal silicon, transparent material, non-transparent material or above-mentioned combination.
Pixel provided by the present invention is applicable in the display floater that display floater comprises above-mentioned pixel and holding wire.
Display floater provided by the present invention then is applicable to and is assembled into display.Display comprises backlight and above-mentioned display floater.Backlight is as the main light of display source.
Display provided by the present invention is applicable to a kind of electrooptical device.Electrooptical device comprises electronic component and above-mentioned display.
The present invention proposes a kind of manufacture method of pixel in addition, and this pixel is arranged on the substrate, and has switching device district and capacitive region.The method comprises: form at least semi-conductor layer on this substrate of switching device district and capacitive region; Form at least one first dielectric layer, to cover semiconductor layer and substrate; Form at least one first conductive layer, at least one second dielectric layer and at least one etch stop layer successively on first dielectric layer; Patterning first conductive layer, second dielectric layer and etch stop layer pile up so that form a gate stack and form an electric capacity in the switching device district on capacitive region; Form at least one inner layer dielectric layer, with cover gate pile up, electric capacity piles up and first dielectric layer; Form at least one source/drain on the part inner layer dielectric layer in switching device district, wherein source/drain electrode is electrically connected at the semiconductor layer in switching device district; Form at least one protective layer, with covering source/drain electrode and inner layer dielectric layer; Patterning protective layer and inner layer dielectric layer, forming contact hole and to be opened among the protective layer, and opening exposes this etch stop layer; This etch stop layer of selective etch is till part second dielectric layer comes out; And form at least one second conductive layer on partial protection layer, wherein second conductive layer via the contact hole source of being electrically connected at/drain electrode one of them, and be arranged on part second dielectric layer that is exposed via the opening in the protective layer.
Aforesaid formation method, wherein, at least one comprises transparent material, non-transparent material or above-mentioned combination in this first conductive layer and this second conductive layer.
Aforesaid formation method, wherein, at least one comprises organic material, inorganic material or above-mentioned combination in this first dielectric layer, this second dielectric layer and this inner layer dielectric layer.
Aforesaid formation method, wherein, this semiconductor layer comprises monocrystalline silicon, polysilicon, amorphous silicon, microcrystal silicon or above-mentioned combination.
Aforesaid formation method, wherein, at least one is this semiconductor layer of doped N-type, P type or above-mentioned combination in this semiconductor layer on this switching device district and this capacitive region.
Aforesaid formation method, wherein, at least one comprises at least one first doped region and at least one non-doped region in this semiconductor layer on this switching device district and this capacitive region.
Aforesaid formation method, wherein, at least one comprises at least one first doped region, at least one non-doped region and at least one light doping section in this semiconductor layer on this switching device district and this capacitive region.
Aforesaid formation method, wherein, this etch stop layer comprises the material layer.
Aforesaid formation method, wherein, the side that piles up of this second dielectric layer and this first conductive layer has gradient in fact.
Aforesaid formation method, wherein, the thickness of this second dielectric layer is in fact less than 3000 dusts
Aforesaid formation method, wherein, the thickness of this second dielectric layer is in fact less than 1000 dusts
Aforesaid formation method, wherein, the thickness of this second dielectric layer is essentially 200 dusts
To 3000 dusts
Aforesaid formation method, wherein, this gate stack comprises this first conductive layer, this second dielectric layer and this etch stop layer.
Aforesaid formation method, wherein, at this first conductive layer of patterning, this second dielectric layer and this etch stop layer, so that when the formation gate stack reaches the step that formation electric capacity piles up on this capacitive region in this switching device district, use has the gold-tinted technology of the mask of different light transmittances, to delete the partially-etched stop layer on this gate stack.
Aforesaid formation method, wherein, this gate stack comprises this first conductive layer.
Aforesaid formation method, wherein, the thickness of this etch stop layer is that about 200 dusts are to about 3000 dusts.
Aforesaid formation method, wherein, in the step of this protective layer of patterning and this inner layer dielectric layer, this inner layer dielectric layer has different etch-rates with this etch stop layer.
Aforesaid formation method, wherein, in the step of this etch stop layer of selective etch, this etch stop layer has different etch-rates with this second dielectric layer.
The present invention can promote the capacitance of storage capacitance, and keeps the stability of pixel imaging.Compare down with traditional storage capacitance, above-mentioned storage capacitance not only can be reduced to the thickness of dielectric layer 3000 dusts
Below, make outside capacitance greatly promotes, also can be on demand the thickness of control capacitance dielectric layer voluntarily, possess better opening ratio simultaneously.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below the spy enumerate preferred embodiment, and conjunction with figs. elaborates.
Description of drawings
For above-mentioned and other purposes of the present invention, feature, advantage and embodiment can be become apparent, being described in detail as follows of accompanying drawing:
Fig. 1 is according to the vertical view of pixel in a kind of LCD that shows one embodiment of the invention.
The vertical view of each layer of pixel of Fig. 2 A-2E displayed map 1.
The pixel of Fig. 3 displayed map 1 is along the profile of AA ' line.
The pixel of Fig. 4 A-4F displayed map 3 is at each operation stage profile.
Fig. 5 shows the vertical view of bigrid pixel according to an embodiment of the invention.
Fig. 6 is the schematic diagram of electrooptical device of the present invention.
Wherein, description of reference numerals is as follows:
100: pixel 102: the switching device district
104: capacitive region 106: substrate
107: light doping section 108: semiconductor layer
109: 110: the first dielectric layers of channel region
116: sacrifice layer 117: electric capacity piles up
118: gate stack 120: inner layer dielectric layer
122: source/drain electrode 124: source/drain electrode
126: protective layer 128: opening
130: contact hole 132: pixel electrode
132a: electrode 136: holding wire
134: scan line 140: grid
138: grid 200: electrooptical device
210: display floater 220: electronic component
Embodiment
Please refer to Fig. 1, it shows the pixel schematic top plan view in a kind of according to an embodiment of the invention LCD.In Fig. 1, pixel 100 is positioned on the substrate 106, by the zones that scan line 134 and holding wire 136 staggered institutes divide out, and it has a switching element region 102 and a capacitive region 104.In the present embodiment, be provided with an electric capacity in capacitive region 104 places and pile up 117, and be provided with a thin-film transistor in 102 places, switching device district, in order to switch control as pixel, wherein the gate stack 118 of thin-film transistor is connected with scan line 134, source/122 of drain electrodes electrically connect with holding wire 136 and the semiconductor layer 108 that is positioned at 102 places, switching device district respectively, and another source/124 semiconductor layer 108 and pixel electrodes 132 with capacitive region 104 places of drain electrode electrically connect.In addition, the electric capacity at capacitive region 104 places piles up 117 to be used as storage capacitance, electric capacity piles up 117 dielectric layer (not shown)s between including part semiconductor layer 108 and part first conductive layer 112, electrode 132a and being positioned in twos, and wherein electrode 132a is the part of pixel electrode 132.
Fig. 2 A-2E shows the vertical view of each layer of pixel as shown in Figure 1.Shown in Fig. 2 A, at first, has semi-conductor layer 108 on the substrate 106, and in the semiconductor layer 108 at 102 places, switching device district, then pre-defined where go out semiconductor layer 108 be first doped region 105 and channel region 109, and channel region 109, because of not mixing any impurity, be also referred to as not doped region.
Please refer to Fig. 2 B, on semiconductor layer 108, have by the formed insulating barrier (not shown) of first dielectric layer, on the insulating barrier of the semiconductor layer 108 of capacitive region 104, have first conductive layer 112, the second dielectric layer (not shown) and sacrifice layer (not shown) successively.And on the channel region 109 of the semiconductor layer 108 at 102 places, switching device district, then be provided with gate stack 118, and gate stack 118 links to each other with scan line 134.In the present embodiment, be with after forming at first conductive layer, that is, and after gate stack 118 forms, make with first doping process pre-defined where go out semiconductor layer be first doped region 105 and channel region 109 parts to semiconductor layer, and forming first doped region and channel region is example.In addition, in one of both sides of channel region 109, then be to be that mask carries out second doping process with gate stack 118, the doped region 107 that selectivity defines out.Because the concentration of doped region 107 preferably, less than the concentration of first doped region 105, therefore is also referred to as light doping section 107 in fact.And first doped region 105 is also referred to as heavily doped region or source/drain region.Though first doped region 105, channel region 109 and light doping section 107 are that present embodiment forms at different time, also can form at one time.Secondly, form first doped region 105, light doping section 107 and channel region 109 also optionally formed by one a gold-tinted technology and an ion implantation technology before gate stack 118 forms, for example: form photoresist on the semiconductor layer 108 or first dielectric layer, make photoresist form stepped (stepped) or ramped shaped (taper) via exposure process, and utilize first doping process to form first doped region 105 simultaneously, light doping section 107 and channel region 109, or before forming, gate stack 118 forms by one a gold-tinted technology and an ion implantation technology, for example: form photoresist on first dielectric layer or first conductive layer, make win dielectric layer and/or first conductive layer form stepped (stepped) or ramped shaped (taper) through gold-tinted and etch process, and utilize first doping process to form first doped region 105 simultaneously, light doping section 107 and channel region 109.Secondly, form light doping section 107 and first doped region 105 and channel region 109 in different time, then can select in first doped region 105 and channel region 109 be formed at semiconductor layer form after, this first dielectric layer form after and after first conductive layer one of them, form again photoresist on the semiconductor layer 108, on first dielectric layer and first conductive layer one of them, make photoresist expose predetermined light doping section 107 positions via exposure process, and utilize second doping process to form light doping section 107.
Then, shown in Fig. 2 C, be provided with an inner layer dielectric layer (not shown), to cover the element of above-mentioned all formation in substrate 106.And on the inner layer dielectric layer of gate stack 118, then being provided with source/drain electrode 122 away from one of capacitive region 104 side, it is electrically connected at first doped region 105 of holding wire 136 and semiconductor layer 108.And on the inner layer dielectric layer of gate stack 118 near the opposite side of capacitive region 104, then be provided with source/drain electrode 124 and electrically connect via first doped region 105 of a hole (not mark) with semiconductor layer.
Come again, shown in Fig. 2 D, a protective layer (not shown) is set on substrate, to cover all elements.And in protective layer, inner layer dielectric layer and sacrifice layer (not shown), form opening 128, to expose second dielectric layer 114 of below, simultaneously in the source/drain electrode 124 tops be provided with contact hole 130 in protective layer to expose part source/drain electrode 124.In addition, contact hole 130 can be selected to aim in fact or misalignment hole (not mark).
At last, shown in Fig. 2 E, a pixel electrode 132 is arranged on the protective layer (not shown), and inserts contact hole 130 and opening 128, and then electric connection source/drain electrode 124, and formation electric capacity piles up the electrode 132a in 117.Preferably, pixel electrode 132 is sequentially to be formed in this contact hole 130 and the opening 128.
Then in detail, the structure of above-mentioned storage capacitance and each layer of pixel will be described in detail hereinafter, and explain orally in order to simplify accompanying drawing and to be easy to, Fig. 3 draws corresponding to the AA ' line of Fig. 1.As shown in Figure 3, substrate 106 and position semiconductor layer 108 thereon have switching device district 102 and capacitive region 104.Pile up 117 as the electric capacity of storage capacitance and be positioned on the capacitive region 104, include semiconductor layer 108, first dielectric layer 110, first conductive layer 112, second dielectric layer 114 and electrode 132a.The two side of storage capacitance is covered by inner layer dielectric layer 120.As shown in the figure, 110 of first dielectric layers are covered on semiconductor layer 108 and the substrate 106.On part of first dielectric layer 110, then have first conductive layer 112 and second dielectric layer 114 successively, in addition, the side that piles up of second dielectric layer 114 and first conductive layer 112 has a gradient (taper) in fact, is also referred to as a ramp structure.Protective layer 126 is covered on the established structure.Have an opening 128 in the protective layer 126 and expose the second part or all of dielectric layer 114.Pixel electrode 132 parts are arranged on the protective layer 126 and are arranged in the opening 128, and are positioned at the electrode 132a of the pixel electrode of opening 128 bottoms as storage capacitance.Residual layer 113,115 residues in the sacrifice layer on second dielectric layer 114 in the technology of deletion sacrifice layer (not shown).Therefore, residual layer 113,115 optionally lays respectively on the end that on the end of second dielectric layer 114, all is positioned at second dielectric layer 114 (for example: have only more than one residual layer 113/115) or residual layer 113,115 is not present on second dielectric layer 114 of capacitive region 104, but be not limited thereto, residual layer 113/115 also can be arranged on part second dielectric layer 114, for example: be positioned at the centre or other position or the above-mentioned combination that are positioned at second dielectric layer on the two ends away from second dielectric layer, in fact in fact.Secondly, embodiments of the invention are to be embodiment with two residual layers, also can be implemented on a residual layer or not have the situation of residual layer.
Then, referring again to Fig. 3, on the substrate 106 in switching device district 102, have semiconductor layer 108, the first dielectric layers 110 and cover semiconductor layer 108 and substrate 106.One gate stack 118 is positioned on first dielectric layer 110 in switching device district 102.Gate stack 118 comprises first conductive layer 112 and second dielectric layer 114, optionally comprises sacrifice layer 116 in addition.Inner layer dielectric layer 120 is covered on the substrate 106.Source/drain electrode 122/124 is arranged on the part inner layer dielectric layer 120 in switching device district 102, and is electrically connected at the semiconductor layer 108 in the switching device district 102.126 of protective layers are covered on the substrate 106.Pixel electrode 132 is arranged on the partial protection layer 126, and electric connection source/drain electrode 124.Semiconductor layer 108 has the below that a channel region 109 is positioned at gate stack 118 in fact, and in one of both sides of channel region 109, has at least one light doping section 107, embodiments of the invention are that to have light doping section 107 be embodiment to the both sides with channel region 109, but are not limited thereto structure.The contact point of source/drain electrode 122/124 and semiconductor layer 108 lays respectively at the outside of light doping section 107, just is connected in first doped region 105 of semiconductor layer 108.In addition; at least one comprises organic material (as: photoresist, poly-methyl propionyl acid methyl esters, Merlon, polyalcohols, polyalkenes, poly-imines class (polyimide), benzocyclobutene (Benzocyclobutene, BCB), parylene-N (PA), carbon containing oxygen hydrogen silicide or other material or above-mentioned combination), inorganic material (as: silica, silicon nitride, silicon oxynitride, carborundum or other material or above-mentioned combination) or above-mentioned combination in said first dielectric layer, second dielectric layer, inner layer dielectric layer and the protective layer.
See also Fig. 4 A-4F, show the stage profile of each technology of pixel of above-mentioned Fig. 3 according to the present invention.See also Fig. 4 A, for corresponding to the profile of Fig. 2 A along AA ' line.This pixel is arranged on the substrate 106, and can divide into switching device district 102 and capacitive region 104.On substrate 106, form semiconductor layer 108.Then, patterned semiconductor layer 108, and behind patterning, become the channel region part in preboarding with a mask layer shaded portions semiconductor layer 108, semiconductor layer is carried out first doping process, to form first doped region 105 and non-doped region, wherein non-doped region is as channel region 109.The formation method and the patterning method of semiconductor layer 108, for example can be chemical vapour deposition technique and photoetching, but be not limited thereto, also can select other method, for example: rubbing method, screen painting method, ink jet printing method or other method form patterned semiconductor layer 108.In this embodiment, semiconductor layer 108 can be material, for example monocrystalline silicon, polysilicon, amorphous silicon, microcrystal silicon or other siliceous material or above-mentioned combination in any.And the first above-mentioned doping process can be the N doping or P mixes, so that semiconductor layer 108 becomes the semiconductor of N type, P type or above-mentioned combination.
Fig. 4 B is for corresponding to the profile of Fig. 2 B along AA ' line.At first, behind the deletion mask layer, then on semiconductor layer 108 and substrate 106, form first dielectric layer 110.On first dielectric layer 110, forming first conductive layer 112, second dielectric layer 114 and sacrifice layer 116 again, preferably, is to form above-mentioned layer not (first conductive layer 112, second dielectric layer 114 and sacrifice layer 116) successively.Then, patterning first conductive layer 112, second dielectric layer 114 and sacrifice layer 116, preferably, be the above-mentioned layer of while patterning not (first conductive layer 112, second dielectric layer 114 and sacrifice layer 116), to pile up 117 with partition capacitance respectively at forming gate stack 118 on switching device district 102 and the capacitive region 104.And in order to reduce short-channel effect, can carry out second doping process for mask by gate stack 118, and then at least one side optionally forms light doping section 107 in channel region 109, and then makes semiconductor layer 108 comprise non-doped region, light doping section 107 and first doped region 105.Yet semiconductor layer also optionally only comprises the non-doped region and first doped region.Secondly, must it should be noted that, above-mentioned doping process is to form non-doped region with secondary doping process, the light doping section 107 and first doped region 105 are in semiconductor layer, yet, be not limited thereto, also optionally form simultaneously, for example: form photoresist on patterned semiconductor layer 108, make photoresist form stepped (stepped) or slope (taper) via exposure process, and utilize first doping process to form first doped region 105 simultaneously, light doping section 107 and channel region 109 or by one gold-tinted technology, one etch process and an ion implantation technology form, for example: etching first dielectric layer makes it form stepped or slope, and utilizes first doping process to form first doped region 105 simultaneously, light doping section 107 and channel region 109.In addition, present embodiment is with when the patterned semiconductor layer, promptly implement the first doping program, but also optionally after forming first dielectric layer, form wherein at least two of one gold-tinted technology, one etch process and ion implantation technologies, make patterned semiconductor layer form simultaneously or non-first doped region 105, light doping section 107 and the channel region 109 of forming simultaneously.Or after forming first dielectric layer, implement the first doping program, after forming first doped region 105 and channel region 109, again after gate stack or patterning first conductive layer form, implement the second doping program or patterning first conductive layer and/or mask layer with gate stack and/or mask layer again and implement the second doping program, to form light doping section.Or after forming gate stack or patterning first conductive layer, form wherein at least two of one gold-tinted technology, one etch process and ion implantation technologies, make patterned semiconductor layer form simultaneously or non-first doped region 105, light doping section 107 and the channel region 109 of forming simultaneously.
In this embodiment, during the step of patterning first conductive layer 112, second dielectric layer 114 and sacrifice layer 116, can use the gold-tinted technology of general photomask.In addition, above-mentioned sacrifice layer 116 comprises material layer (as: amorphous silicon, monocrystalline silicon, polysilicon, microcrystal silicon, or other siliceous material or above-mentioned combination), and the thickness of second dielectric layer 114 is essentially 200 dusts
To 3000 dusts
Preferably in fact less than 1000 dusts
But be not limited thereto.And the thickness of sacrifice layer is preferably between about 200 dusts
To about 3000 dusts
But be not limited thereto.At least one piled up side and has a gradient (taper) in fact during gate stack after the patterning and electric capacity piled up, and gradient is in fact less than 90 degree, and preferably, gradient is in fact less than 70 degree, but is not limited thereto.In addition, also optionally use the gold-tinted technology of photomask (as: half tone photomask, diffraction photomask, palisade pattern photomask or other similar photomask) during the step of patterning first conductive layer 112, second dielectric layer 114 and sacrifice layer 116 with different light transmittances, form gate stack and electric capacity piles up, use the photomask of different light transmittances to carry out etch process and the sacrifice layer 116 of gate stack top can be deleted in the lump.
Please refer to Fig. 4 C, for corresponding to the profile of Fig. 2 C along AA ' line.Pile up on 117 and first dielectric layer 110 in gate stack 118, partition capacitance, form inner layer dielectric layer 120.Then, the part inner layer dielectric layer 120 at 102 places, patterning switching device district and first dielectric layer 110 are to expose part semiconductor layer 108 surface.The formation method of inner layer dielectric layer 120 for example can be chemical vapour deposition technique, but is not limited thereto, and also can select other method, and for example: rubbing method, screen painting method, ink jet printing method or other method form inner layer dielectric layer 120.Then, on the part inner layer dielectric layer 120 in switching device district 102, formation source/drain electrode 122/124 electrically connects with first doped region 105 with semiconductor layer 108 again.
Please refer to Fig. 4 D, be the profile of corresponding diagram 2D along AA ' line.On source/drain electrode 122/124 and inner layer dielectric layer 120, form protective layer 126.Then, as etch stop layer, patterning protective layer 126 and inner layer dielectric layer 120 with respectively at switching device district 102 and capacitive region 104, form contact hole 130 and opening 128 with sacrifice layer 116.And then expose part or all of sacrifice layer 116, and expose part or all of source/drain electrode 124 in contact hole 130 places in opening 128 places.
In the process of patterning, if use engraving method, then for fear of the situation that over etching takes place, both have different etch-rates inner layer dielectric layer 120 and sacrifice layer 116, to carry out selective etch.In view of the above, behind the inner layer dielectric layer 120 at deletion opening 128 places, sacrifice layer 116 surfaces that exposed can make etch-rate be tending towards slowing down.Certainly, also optionally make otherwise, form required patterning.
Then, Fig. 4 E also is the profile of corresponding diagram 2D along AA ' line.In Fig. 4 E, the sacrifice layer 116 that expose in opening 128 places in patterning electric capacity district 104.With etch process sacrificial patterned 116 time, optionally on second dielectric layer, 114 two ends at capacitive region 104 places, keep residual layer 113 and 115, perhaps, only on arbitrary end of part second dielectric layer 114, keep and contain arbitrary residual layer 113 or 115, or residual layer 113 and 115 deleted fully, or residual layer 113/115 is arranged on part second dielectric layer, for example: be positioned in fact on the two ends away from second dielectric layer, be positioned at the centre of second dielectric layer in fact, or other position, or above-mentioned combination, this exposes sacrifice layer 116 wholly or in part on opening 128 and decides.But, no matter whether sacrifice layer 116 residues on second dielectric layer 114, can electrically not causing any impact to whole storage capacitance.
Similarly, when patterning, for fear of the situation generation of over etching, sacrifice layer 116 also has different etch-rates with second dielectric layer 114, therefore behind the sacrifice layer 116 at deletion capacitive region 104 places, part second dielectric layer 114 surfaces of being exposed can make etch-rate descend once again.Preferably, the etching selectivity of the sacrifice layer 116 and second dielectric layer 114 in fact greater than or equal 2 in fact, just, the etch-rate of sacrifice layer 116 is in fact greater than the etch-rate of second dielectric layer 114.And the sacrifice layer 116 in the above embodiment of the present invention and second dielectric layer 114 are respectively to be embodiment with amorphous silicon layer and silicon oxide layer, but be not limited thereto, also can distinguish optionally select sacrifice layer 116 etch-rate in fact greater than the material of the etch-rate of second dielectric layer 114.Therefore, be example with the sacrifice layer 116 that amorphous silicon layer was constituted, its etch-rate is about 200A/min to being about 10000A/min, and is example with second dielectric layer 114 that silicon oxide layer was constituted, its etch-rate be about less than or approximate 100A/min.So, the etching selectivity of amorphous silicon layer and silicon oxide layer is about 2 in fact to being about 100, that is to say, the etching selectivity of the two in fact greater than or equal 2 in fact, and the etch-rate of amorphous silicon layer is in fact greater than silicon oxide layer, but is not limited thereto material and relevent information thereof in the example.
Please refer to Fig. 4 F, be the profile of corresponding diagram 2E along AA ' line.In Fig. 4 F, one second conductive layer is formed on the partial protection layer 126, to use as pixel electrode 132.Formed pixel electrode 132 in the source/drain electrode 124 at 102 places, switching device district wherein can and then electrically connect with first doped region 105 of patterned semiconductor layer 108.And formed pixel electrode 132 on part second dielectric layer 114 that the opening 128 in capacitive region 104 place's protective layers 126 is exposed then piles up an electrode 132a in 117 as electrode.
In the above-described embodiments, at least one comprises transparent material (as: indium tin oxide, aluminium zinc oxide, indium-zinc oxide, cadmium tin-oxide or other material or above-mentioned combination), non-transparent material (as: oxide of the alloy of gold, silver, copper, iron, tin, lead, cadmium, molybdenum, neodymium, titanium, Tan, Han, tungsten or above-mentioned material or the nitride of above-mentioned material or above-mentioned material or the oxynitrides of above-mentioned material or other material or above-mentioned combination) or above-mentioned combination in first conductive layer and second conductive layer.As at least one comprises organic material (as: photoresist, poly-methyl propionyl acid methyl esters, Merlon, polyalcohols, polyalkenes or other material or above-mentioned combination), inorganic material (as: silica, silicon nitride, silicon oxynitride, carborundum or other material or above-mentioned combination) or above-mentioned combination in first dielectric layer, second dielectric layer, inner layer dielectric layer and the protective layer.Secondly, pixel electrode of the present invention is with transparent material (as: indium tin oxide, the aluminium zinc oxide, indium-zinc oxide, the cadmium tin-oxide, or other material, or above-mentioned combination) be example, also optionally use non-transparent material (as: gold, silver, copper, iron, tin, plumbous, cadmium, molybdenum, neodymium, titanium, tantalum Han, tungsten, or the alloy of above-mentioned material, or the nitride of above-mentioned material, or the oxide of above-mentioned material, or the oxynitrides of above-mentioned material, or other material, or above-mentioned combination), or the material of semi-penetrate through reflective (as: be transparent material partly, and another part is a non-transparent material, material itself just has semi-penetrate through reflective character etc.).
In addition, the described pixel of the above embodiment of the present invention also can have the above structure of two grid structure or bigrid, and grid 138 as shown in Figure 5 and 140 is a double-grid structure.Because the many variations of dot structure is well known to those of ordinary skill in the art, therefore give unnecessary details no longer one by one.Secondly, the switching device in the switching device district of the foregoing description is to be embodiment with the top gate type structure, but is not limited thereto, and also optionally uses top gate type structure, bottom gate type structure, other switching device structure of other form.
In addition, the structure that gate stack in the described pixel 100 of the above embodiment of the present invention and electric capacity pile up, all be to remain on second dielectric layer having sacrifice layer 116 on the gate stack, but be not limited to this, second dielectric layer that yet optionally partial sacrifice layer 116 is remained on second dielectric layer that electric capacity piles up, second dielectric layer on the gate stack does not have sacrifice layer 116, electric capacity to pile up does not have sacrifice layer 116 or above-mentioned combination.Secondly, semiconductor layer in capacitive region of the above embodiment of the present invention and the switching device district is to be embodiment with integrally formed, but be not limited thereto, also can select the semiconductor layer in capacitive region and the switching device district to disconnect, and via the semiconductor layer in articulamentum (not shown) connection capacitive region and the switching device district, or the semiconductor layer in capacitive region and the switching device district is integrally formed, again via the semiconductor layer in articulamentum (not shown) connection capacitive region and the switching device district, to increase its electron transport ability.Wherein, the material of this articulamentum comprises transparent material (as: indium tin oxide, aluminium zinc oxide, indium-zinc oxide, cadmium tin-oxide or other material or above-mentioned combination), non-transparent material (as: oxide of the alloy of gold, silver, copper, iron, tin, lead, cadmium, molybdenum, neodymium, titanium, Tan, Han, tungsten or above-mentioned material or the nitride of above-mentioned material or above-mentioned material or the oxynitrides of above-mentioned material or siliceous material or other material or above-mentioned combination) or above-mentioned combination.In other words, articulamentum optionally forms when first conductive layer, semiconductor layer, second conductive layer and source/drain wherein form one of at least.
Fig. 6 is the schematic diagram of electrooptical device of the present invention.Please refer to Fig. 6, the described display floater 210 of the above embodiments of the present invention also is applied in the electrooptical device 200, and display floater 210 comprises that a matrix base plate (not shown) and corresponds to the common electrode substrate (not shown) of this matrix base plate, and this matrix base plate has the described pixel 100 of a plurality of the above embodiments of the present invention.This electrooptical device 300 also has an electronic component 220 that is connected with display floater 210, as: control element; executive component; treatment element; input element; memory element; driving element; light-emitting component (as: inorganic light-emitting diode; Organic Light Emitting Diode; cold cathode fluorescent lamp; the plane fluorescent tube; HCFL; the outer electrode fluorescent tube; or other type fluorescent tube; or above-mentioned combination); sensing element (as: touch control component; Photosensing Units; temperature sensor; the image sensing element; or other type; or above-mentioned combination); charge member; heating element; protection component; or other function element; or above-mentioned combination.And the type of electrooptical device comprises the panel in portable product (as mobile phone, video camera, camera, notebook computer, game machine, wrist-watch, music player, E-mail receiver/send device, map navigator, electronics photograph or similar products like), video and audio product (as audio-visual projector or similar products like), screen, TV, indoor or billboards or the projecting apparatus etc.In addition, display floater 210 comprises display panels (as: transmission-type panel, the Semitransmissive panel, the reflection-type panel, double-sided display profile plate, vertical orientation profile plate (VA), plane switch type panel (IPS), multi-domain perpendicular alignment-type panel (MVA), twisted nematic panel (TN), super-twist nematic panel (STN), pattern vertical orientation profile plate (PVA), super pattern vertical orientation profile plate (S-PVA), improved super large visual angle profile plate (ASV), boundary electric field switch type panel (FFS), continuous fireworks shape arrange type panel (CPA), axial symmetry is arranged micro unit panel (ASM), optical compensation curved arrange type panel (OCB), super plane switch type panel (S-IPS), improved super plane switch type panel (AS-IPS), extreme edge electric field switch type panel (UFFS), stabilizing polymer alignment-type panel (PSA), double vision angle profile plate (dual-view), three visual angle profile plates (triple-view), or colored filter is combined in (color filter on array on the matrix; COA) profile plate or matrix are combined in (array oncolor filter on the colored filter; AOC) profile plate or other profile plate or above-mentioned combination), organic electric-excitation luminescent displaying panel, as for selecting what panel, look the material that at least one institute electrically contacts in pixel electrode in its panel and the drain electrode, as: liquid crystal layer, organic luminous layer (as: micromolecule, macromolecule or above-mentioned combination) or above-mentioned combination and decide.
According to the above embodiment of the present invention as can be known, compare down with traditional storage capacitance, the prepared storage capacitance of above-mentioned manufacturing process not only can be reduced to the thickness of dielectric layer 3000 dusts
Below, make outside capacitance greatly promotes, also can be on demand the thickness of control capacitance dielectric layer voluntarily, possess better opening ratio simultaneously.
Though the present invention discloses as above with an embodiment; right its is not in order to limit the present invention; any those of ordinary skills; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking the scope that claim defined of enclosing.
Claims (50)
1. a storage capacitance is arranged on the substrate, comprising:
At least one semiconductor layer is arranged on this substrate;
At least one first dielectric layer covers this semiconductor layer and this substrate;
At least one first conductive layer is arranged on the part of first dielectric layer;
At least one second dielectric layer is arranged on this first conductive layer, and the side that piles up of this second dielectric layer and this first conductive layer has gradient; And
At least one second conductive layer is arranged on part second dielectric layer.
2. storage capacitance as claimed in claim 1, wherein, at least one comprises transparent material, non-transparent material or above-mentioned combination in this first conductive layer and this second conductive layer.
3. storage capacitance as claimed in claim 1, wherein, at least one comprises organic material, inorganic material or above-mentioned combination in this first dielectric layer and this second dielectric layer.
4. storage capacitance as claimed in claim 1, wherein, this semiconductor layer comprises monocrystalline silicon, polysilicon, amorphous silicon, microcrystal silicon or above-mentioned combination.
5. storage capacitance as claimed in claim 1, wherein, this semiconductor layer is the semiconductor layer of doped N-type, P type or above-mentioned combination.
6. storage capacitance as claimed in claim 1, wherein, this semiconductor layer comprises at least one first doped region and at least one non-doped region.
7. storage capacitance as claimed in claim 1, wherein, this semiconductor layer comprises at least one first doped region, at least one non-doped region and at least one light doping section.
8. storage capacitance as claimed in claim 1 wherein, also comprises etch stop layer, has at least one first, is arranged on part second dielectric layer.
9. storage capacitance as claimed in claim 1, wherein, also comprise etch stop layer, have at least one first and at least one second portion, this first is arranged at the two ends of this second dielectric layer on one of them, and this second portion is arranged on the other end away from this second dielectric layer.
10. storage capacitance as claimed in claim 1, wherein, the thickness of this second dielectric layer is less than 3000 dusts.
11. storage capacitance as claimed in claim 1, wherein, the thickness of this second dielectric layer is less than 1000 dusts.
12. storage capacitance as claimed in claim 1, wherein, the thickness of this second dielectric layer is between 200 dust to 3000 dusts.
13. storage capacitance as claimed in claim 1, wherein, this second conductive layer is electrically connected at this semiconductor layer.
14. storage capacitance as claimed in claim 8 or 9, wherein, this etch stop layer comprises the material layer.
15. a pixel is arranged on the substrate, and this pixel has at least one switching device district and at least one capacitive region, this pixel comprises:
At least one semiconductor layer is formed at respectively on this substrate of this switching device district and this capacitive region;
At least one first dielectric layer covers this semiconductor layer and this substrate;
At least one first conductive layer is formed at respectively on the part of first dielectric layer of this switching device district and this capacitive region;
At least one second dielectric layer is formed at respectively on this first conductive layer of this switching device district and this capacitive region;
At least one etch stop layer, partially-etched stop layer are formed on this second dielectric layer in this switching device district;
At least one inner layer dielectric layer is covered on this substrate;
At least one source/drain electrode is formed on the part inner layer dielectric layer in this switching device district, and is electrically connected at this semiconductor layer in this switching device district;
At least one protective layer covers this substrate; And
At least one second conductive layer is arranged on the partial protection layer, and be electrically connected at this source/drain electrode one of them, and via in this protective layer and this inner layer dielectric layer at least one opening, be arranged on part second dielectric layer.
16. pixel as claimed in claim 15, wherein, at least one comprises transparent material, non-transparent material or above-mentioned combination in this first conductive layer and this second conductive layer.
17. pixel as claimed in claim 15, wherein, at least one comprises organic material, inorganic material or above-mentioned combination in this first dielectric layer, this second dielectric layer and this inner layer dielectric layer.
18. pixel as claimed in claim 15, wherein, this semiconductor layer comprises monocrystalline silicon, polysilicon, amorphous silicon, microcrystal silicon or above-mentioned combination.
19. pixel as claimed in claim 15, wherein, at least one is the semiconductor layer of doped N-type, P type or above-mentioned combination in this semiconductor layer on this switching device district and this capacitive region.
20. pixel as claimed in claim 15, wherein, at least one comprises at least one first doped region and at least one non-doped region in this semiconductor layer on this switching device district and this capacitive region.
21. pixel as claimed in claim 15, wherein, at least one comprises at least one first doped region, at least one non-doped region and at least one light doping section in this semiconductor layer on this switching device district and this capacitive region.
22. pixel as claimed in claim 15, wherein, another part etch stop layer has at least one first, is arranged on part second dielectric layer.
23. pixel as claimed in claim 15, wherein, another part etch stop layer has at least one first and at least one second portion, and this first is arranged at the two ends of this second dielectric layer on one of them, and this second portion is arranged on the other end away from this second dielectric layer.
24. pixel as claimed in claim 15, wherein, this etch stop layer comprises the material layer.
25. pixel as claimed in claim 15, wherein, the side that piles up of this second dielectric layer and this first conductive layer has gradient.
26. pixel as claimed in claim 15, wherein, the thickness of this second dielectric layer is less than 3000 dusts.
27. pixel as claimed in claim 15, wherein, the thickness of this second dielectric layer is less than 1000 dusts.
28. pixel as claimed in claim 15, wherein, the thickness of this second dielectric layer is between 200 dust to 3000 dusts.
29. pixel as claimed in claim 15 wherein, also comprises articulamentum, to electrically connect this semiconductor layer on this switching device district and this capacitive region.
30. pixel as claimed in claim 29, wherein, this articulamentum comprises monocrystalline silicon, polysilicon, amorphous silicon, microcrystal silicon, transparent material, non-transparent material or above-mentioned combination.
31. a display floater comprises at least one holding wire and pixel as claimed in claim 15.
32. an electrooptical device comprises at least one electronic component and display floater as claimed in claim 31.
33. the formation method of a pixel, this pixel is arranged on the substrate, and this pixel has at least one switching device district and at least one capacitive region, and this method comprises:
Form at least semi-conductor layer on this substrate of this switching device district and this capacitive region;
Form at least one first dielectric layer, to cover this semiconductor layer and this substrate;
Form at least one first conductive layer, at least one second dielectric layer and at least one etch stop layer successively on this first dielectric layer;
This first conductive layer of patterning, this second dielectric layer and this etch stop layer pile up so that form gate stack and form electric capacity in this switching device district on this capacitive region;
Form at least one inner layer dielectric layer, with cover this gate stack, this electric capacity piles up and this first dielectric layer;
Form at least one source/drain on the part inner layer dielectric layer in this switching device district, this source/drain electrode is electrically connected at this semiconductor layer in this switching device district;
Form at least one protective layer, to cover this source/drain electrode and this inner layer dielectric layer;
This protective layer of patterning and this inner layer dielectric layer, forming contact hole and to be opened among this protective layer, and this opening exposes this etch stop layer;
This etch stop layer of selective etch is till part second dielectric layer comes out; And
Form at least one second conductive layer on partial protection layer, this second conductive layer via this contact hole be electrically connected at this source/drain electrode one of them, and be arranged on part second dielectric layer that is exposed via this opening in this protective layer.
34. formation method as claimed in claim 33, wherein, at least one comprises transparent material, non-transparent material or above-mentioned combination in this first conductive layer and this second conductive layer.
35. formation method as claimed in claim 33, wherein, at least one comprises organic material, inorganic material or above-mentioned combination in this first dielectric layer, this second dielectric layer and this inner layer dielectric layer.
36. formation method as claimed in claim 33, wherein, this semiconductor layer comprises monocrystalline silicon, polysilicon, amorphous silicon, microcrystal silicon or above-mentioned combination.
37. formation method as claimed in claim 33, wherein, at least one is the semiconductor layer of doped N-type, P type or above-mentioned combination in this semiconductor layer on this switching device district and this capacitive region.
38. formation method as claimed in claim 33, wherein, at least one comprises at least one first doped region and at least one non-doped region in this semiconductor layer on this switching device district and this capacitive region.
39. formation method as claimed in claim 33, wherein, at least one comprises at least one first doped region, at least one non-doped region and at least one light doping section in this semiconductor layer on this switching device district and this capacitive region.
40. formation method as claimed in claim 33, wherein, this etch stop layer comprises the material layer.
41. formation method as claimed in claim 33, wherein, the side that piles up of this second dielectric layer and this first conductive layer has gradient.
42. formation method as claimed in claim 33, wherein, the thickness of this second dielectric layer is less than 3000 dusts.
43. formation method as claimed in claim 33, wherein, the thickness of this second dielectric layer is less than 1000 dusts.
44. formation method as claimed in claim 33, wherein, the thickness of this second dielectric layer is 200 dust to 3000 dusts.
45. formation method as claimed in claim 33, wherein, this gate stack comprises this first conductive layer, this second dielectric layer and this etch stop layer.
46. formation method as claimed in claim 45, wherein, at this first conductive layer of patterning, this second dielectric layer and this etch stop layer, so that when the formation gate stack reaches the step that formation electric capacity piles up on this capacitive region in this switching device district, use has the gold-tinted technology of the photomask of different light transmittances, to delete the partially-etched stop layer on this gate stack.
47. formation method as claimed in claim 33, wherein, this gate stack comprises this first conductive layer.
48. formation method as claimed in claim 33, wherein, the thickness of this etch stop layer is 200 dust to 3000 dusts.
49. formation method as claimed in claim 33, wherein, in the step of this protective layer of patterning and this inner layer dielectric layer, this inner layer dielectric layer has different etch-rates with this etch stop layer.
50. formation method as claimed in claim 33, wherein, in the step of this etch stop layer of selective etch, this etch stop layer has different etch-rates with this second dielectric layer.
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| JP5312294B2 (en) * | 2009-10-30 | 2013-10-09 | キヤノン株式会社 | Light emitting apparatus and exposure apparatus |
| KR101783352B1 (en) * | 2010-06-17 | 2017-10-10 | 삼성디스플레이 주식회사 | Flat panel display apparatus and manufacturing method of the same |
| TWI694292B (en) * | 2019-03-04 | 2020-05-21 | 友達光電股份有限公司 | Display panel |
| CN110993657B (en) * | 2019-11-28 | 2023-11-24 | 云谷（固安）科技有限公司 | Display panel, device and preparation method of display panel |
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