CN100461379C - Picture element structure of liquid crystal display and producing method thereof - Google Patents
Picture element structure of liquid crystal display and producing method thereof Download PDFInfo
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- CN100461379C CN100461379C CNB2007100889877A CN200710088987A CN100461379C CN 100461379 C CN100461379 C CN 100461379C CN B2007100889877 A CNB2007100889877 A CN B2007100889877A CN 200710088987 A CN200710088987 A CN 200710088987A CN 100461379 C CN100461379 C CN 100461379C
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Abstract
This invention discloses a manufacturing method for a pixel structure, which utilizes five paths of photomasks to finish the pixel structure of a LCD by forming a metal shading layer at the bottom of a film transistor to reduce generation of photocurrent and utilizing a metal lead to increase the storage capacitance volume of a storage capacitor.
Description
Technical field
The present invention relates to a kind of LCD and manufacture method thereof, and be particularly related to a kind of dot structure and manufacture method thereof of LCD.
Background technology
Recently photoelectric technology is constantly weeded out the old and bring forth the new, and adds the arrival of digital times, has promoted the flourish of LCD market.LCD because have that high image quality, volume are little, in light weight, numerous advantages such as low driving voltage and low consumpting power.Therefore be widely used in PDA(Personal Digital Assistant), mobile phone, shoot with video-corder projector, on consumer communication such as notebook computer, desktop display, automobile-used display and projection TV or the electronic product, and replace cathode ray tube gradually, and become the main flow of display.
The manufacture method of the thin film transistor (TFT) array of LCD (TFT Array) substrate mainly is to combine with deposition, photoetching and three kinds of different process of etching now.In these three kinds of technologies, the production cost shared with photoetching process is the highest.Therefore to how to reduce the needed photoetching process number of tft array substrate whole manufacturing process, that is reduce required photomask number, just become panel big factory in various countries' to reduce the primary problem of production of liquid crystal displays cost.
Summary of the invention
Therefore the objective of the invention is a kind of dot structure and manufacture method thereof that is applicable to LCD is being provided.
On substrate, form earlier the first metal layer, first dielectric layer and silicon layer in regular turn, patterning the first metal layer, first dielectric layer and silicon layer then, defining the transistor stack that is constituted by the first metal layer, first dielectric layer and the silicon layer, and define the data wire and first electrode that constitutes by the first metal layer respectively.Then, form the gate dielectric layer and second metal level in regular turn on substrate, transistor stack, data wire and first electrode, patterning second metal level again is to define the grid and second electrode respectively on the transistor stack and first electrode.With the grid is doping mask, and the silicon layer of transistor stack is carried out heavy doping technology, forms first heavily doped region and second heavily doped region respectively with the both sides at silicon layer.
On gate dielectric layer, grid and second electrode, form second dielectric layer, patterning second dielectric layer then is to form first opening, second opening, the 3rd opening and the 4th opening to expose data wire, first heavily doped region, second heavily doped region and first electrode respectively.Subsequently, form the 3rd metal level to be covered on second dielectric layer, then patterning the 3rd metal level is to define first lead and second lead.Wherein, first lead electrically connects the data wire and first heavily doped region by first opening and second opening, and second lead electrically connect second heavily doped region and first electrode by the 3rd opening and the 4th opening, and second lead extends on this second electrode to constitute holding capacitor with first electrode and second electrode.
Then, form transparency conducting layer on second dielectric layer, first lead and second lead, patterned transparent conductive layer again is to define pixel electrode on second lead and second dielectric layer.
Description of drawings
State with other purposes, feature, advantage and embodiment and can become apparent, appended graphic being described in detail as follows on the present invention for allowing:
Figure 1A-1F illustrates the manufacturing process generalized section figure according to the picture element array structure of a kind of LCD of embodiments of the invention.
Fig. 2 illustrates the cross-sectional view of general LCD.
Description of reference numerals
100: substrate 105: the first metal layer
105a: metal light shield layer 105b: data wire
105c: 110: the first dielectric layers of first electrode
115: silicon layer 120: gate dielectric layer
130a: grid 130b: second electrode
135: source electrode 140: drain electrode
142: 145: the second dielectric layers of light doping section
150a: the first opening 150b: second opening
150c: the 3rd opening 150d: the 4th opening
155a: the first lead 155b: second lead
160: pixel electrode 165: protective layer
190: data wire district 192: the active element district
194: storage capacitance district 196: pixel region
210: the second substrates of 205: the first substrates
215: liquid crystal layer 220: LCD
Embodiment
Please refer to Figure 1A-1F, it illustrates the manufacturing process generalized section according to the picture element array structure of a kind of LCD of embodiments of the invention.
In Figure 1A, on substrate 100, deposit the first metal layer 105, first dielectric layer 110 and silicon layer 115 in regular turn, wherein the material of silicon layer for example is polysilicon or amorphous silicon, and the material of first dielectric layer for example is a silica.Can divide into data wire district 190, active element district 192 and storage capacitance district 194 on the substrate 100.
In Figure 1B, patterning the first metal layer 105, first dielectric layer 110 and silicon layer 115.In data wire district 190 and 194 in storage capacitance district stay the first metal layer, with respectively as the data wire 105b and the first electrode 105c.192 define the transistor stack that is made of metal light shield layer 105a, the first dielectric layer 110a and silicon layer 115a in the active element district.The method of above-mentioned patterning for example can be used the photoetching etching method; And the employed photomask of photoetching for example can be semi-modulation type photomask.
In Fig. 1 C, on substrate 100, data wire 105b, the first electrode 105c and silicon layer 115a, form the gate dielectric layer 120 and second metal level in regular turn, wherein the material of this gate dielectric layer comprises silica, silicon nitride or silicon oxynitride.Patterning second metal level with formation grid 130a on silicon layer 115a, and forms the second electrode 130b on the first electrode 105c then.Then, silicon layer 115a is carried out doping process, form first heavily doped region and second heavily doped region, with respectively as source electrode 135 usefulness with drain electrode 140 with both sides at silicon layer 115a.Therefore above-mentioned metal light shield layer 105a position can help and be in the light, to reduce the photoelectric current of thin-film transistor by below grid 130a, source electrode 135 and drain electrode 140 thin-film transistors that constituted.
At this, also can select further isotropic etching grid 130a, afterwards silicon layer 115a is carried out light dope technology, form light doping section 142 with inboard in source electrode 135 and drain electrode 140.
In Fig. 1 D, on gate dielectric layer 120, grid 130a and the second electrode 130b, form second dielectric layer 145, wherein the material of second dielectric layer 145 for example is a silica.Then, patterning second dielectric layer 145 is to form the first, second, third and the 4th opening 150a, 150b, 150c, 150d to expose data wire 105b, source electrode 135 (first heavily doped region), drain electrode 140 (second heavily doped regions) and the first electrode 105c respectively in second dielectric layer 145.In Fig. 1 E, on second dielectric layer 145 with among the first, second, third and the 4th opening 150a, 150b, 150c, the 150d, form the 3rd metal level earlier.Then, patterning the 3rd metal level electrically connects source electrode 135 and the first lead 155a of data wire 105b and the second lead 155b that electrically connects the drain electrode 140 and first electrode 105c to form.The first above-mentioned electrode 105c, the second electrode 130b and the second lead 155b formation holding capacitor overlapping with the second electrode 130b.Wherein be electrical connected, and increase the amount of storage capacity of holding capacitor greatly with the overlapping second lead 155b and the first electrode 105c of the second electrode 130b.
In Fig. 1 F, on second dielectric layer 145, the first lead 155a and the second lead 155b, form transparency conducting layer earlier, wherein the material of this transparency conducting layer for example is tin indium oxide, indium zinc oxide or aluminum zinc oxide.Patterned transparent conductive layer then, with the overlapping pixel region 196 in storage capacitance district 194 on form pixel electrode 160, and it is oxidized to prevent the first lead 155a to form protective layer 165 on the first lead 155a.
Above-mentioned picture element array structure can be applicable on any suitable flat-panel screens, for example LCD.Please refer to Fig. 2, it illustrates the cross-sectional view of general LCD.In Fig. 2, the liquid crystal layer 215 that LCD 220 has first substrate 205, second substrate 210 and is clipped in the middle.If on first substrate 205, picture element array structure is set, the array structure of colored filter then can be set on second substrate 210, make second substrate 210 as color filter.Because the many variations of liquid crystal display device structure is known by those skilled in the art, therefore give unnecessary details no longer one by one, in Fig. 2, do not show detailed structure yet.
By the invention described above preferred embodiment as can be known, use five road photomasks can finish the technology of entire pixel array structure.And by the dot structure shown in Fig. 1 F as can be known, holding capacitor is made of the first electrode 105c, the second electrode 130b and the second lead 155b.In addition, therefore the position can help and be in the light, to reduce the photoelectric current of thin-film transistor by the metal light shield layer 105a below grid 130a, source electrode 135 and 140 thin-film transistors that constituted that drain.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (19)
1. an one pixel structure process method is applicable to LCD, and this manufacture method comprises:
Form the first metal layer, first dielectric layer and silicon layer in regular turn on substrate;
This first metal layer of patterning, this first dielectric layer and this silicon layer defining the transistor stack that is made of this first metal layer, this first dielectric layer and this silicon layer, and define the data wire and first electrode that is made of this first metal layer respectively;
Form the gate dielectric layer and second metal level in regular turn on this substrate, this transistor stack, this data wire and this first electrode;
This second metal level of patterning is to define the grid and second electrode respectively on this transistor stack and this first electrode;
With this grid is doping mask, and this silicon layer of this transistor stack is carried out heavy doping technology, forms first heavily doped region and second heavily doped region respectively with the both sides at this silicon layer;
Form second dielectric layer on this gate dielectric layer, this grid and this second electrode;
This second dielectric layer of patterning is to form first opening, second opening, the 3rd opening and the 4th opening to expose this data wire, this first heavily doped region, this second heavily doped region and this first electrode respectively;
Form the 3rd metal level, be covered on this second dielectric layer;
Patterning the 3rd metal level is to define first lead and second lead, wherein this first lead electrically connects this data wire and this first heavily doped region by this first opening and this second opening, and this second lead electrically connects this second heavily doped region and this first electrode by the 3rd opening and the 4th opening, and this second lead extends on this second electrode to constitute holding capacitor with this first electrode and this second electrode;
Form transparency conducting layer on this second dielectric layer, this first lead and this second lead; And
This transparency conducting layer of patterning is to define pixel electrode on this second lead and this second dielectric layer.
2. one pixel structure process method as claimed in claim 1, wherein the material of this silicon layer comprises polysilicon or amorphous silicon.
3. one pixel structure process method as claimed in claim 1, wherein the material of this first dielectric layer and this second dielectric layer comprises silica.
4. one pixel structure process method as claimed in claim 1, wherein the material of this gate dielectric layer comprises silica, silicon nitride or silicon oxynitride.
5. one pixel structure process method as claimed in claim 1, wherein the material of this transparency conducting layer comprises tin indium oxide, indium zinc oxide or aluminum zinc oxide.
6. one pixel structure process method as claimed in claim 1 also comprises between the step of carrying out this heavy doping technology and this second dielectric layer of formation:
This grid of isotropic etching is to reduce the size of this grid; And
With this grid after the etching is doping mask, and this silicon layer of this transistor stack is carried out light dope technology, forms light doping section respectively with the inboard at this first heavily doped region and this second heavily doped region.
7. one pixel structure process method as claimed in claim 1, wherein the step of this second metal level of patterning comprises that also the formation scan line is to electrically connect this grid.
8. a dot structure is applicable to LCD, and this dot structure comprises at least:
Transistor stack is positioned in the active element district of substrate, and this transistor stack is made of metal light shield layer, first dielectric layer and silicon layer from the bottom to top in regular turn, and the two ends of this silicon layer have first heavily doped region and second heavily doped region;
Data wire is positioned at the data wire district of this substrate;
First electrode is positioned at the storage capacitance district of this substrate;
Gate dielectric layer is positioned on this substrate, this transistor stack, this data wire and this first electrode;
Grid is positioned on this gate dielectric layer of this transistor stack top;
Second electrode is positioned on this gate dielectric layer of this first electrode top;
Second dielectric layer, be positioned on this gate dielectric layer, this grid and this second electrode, this second dielectric layer has first opening, second opening, the 3rd opening and the 4th opening to expose this data wire, this first heavily doped region, this second heavily doped region and this first electrode respectively;
First lead is positioned on this second dielectric layer and by this first opening and this second opening and electrically connects this data wire and this first heavily doped region;
Second lead, be positioned on this second dielectric layer, and electrically connect this second heavily doped region and this first electrode and extend on this second electrode by the 3rd opening and the 4th opening, wherein this first electrode, this second electrode and this second lead constitute holding capacitor; And
Pixel electrode is positioned at the pixel region on this second lead and this second dielectric layer.
9. dot structure as claimed in claim 8, wherein this grid is positioned on this gate dielectric layer of this transistor stack central authorities top.
10. dot structure as claimed in claim 8, wherein this metal light shield layer, this data wire and this first electrode are formed by the first metal layer, this grid and this second electrode are formed by second metal level, and this first lead and this second lead are formed by the 3rd metal level.
11. dot structure as claimed in claim 10 also comprises scan line, electrically connects this grid.
12. dot structure as claimed in claim 11, wherein this scan line is made of this second metal level.
13. dot structure as claimed in claim 8, wherein the material of this silicon layer comprises polysilicon or amorphous silicon.
14. dot structure as claimed in claim 8, wherein the material of this first dielectric layer and this second dielectric layer comprises silica.
15. dot structure as claimed in claim 8, wherein the material of this gate dielectric layer comprises silica, silicon nitride or silicon oxynitride.
16. dot structure as claimed in claim 8, wherein the material of this pixel electrode comprises tin indium oxide, indium zinc oxide or aluminum zinc oxide.
17. dot structure as claimed in claim 8, wherein this first heavily doped region of these silicon layer both sides and this second heavily doped region are respectively as source electrode and drain electrode, and this grid, this source electrode and this drain electrode constitute thin-film transistor.
18. dot structure as claimed in claim 8 also comprises protective layer, is positioned on this first lead.
19. dot structure as claimed in claim 18, wherein the material of this protective layer comprises tin indium oxide, indium zinc oxide or aluminum zinc oxide.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2007100889877A CN100461379C (en) | 2007-03-29 | 2007-03-29 | Picture element structure of liquid crystal display and producing method thereof |
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| CNB2007100889877A CN100461379C (en) | 2007-03-29 | 2007-03-29 | Picture element structure of liquid crystal display and producing method thereof |
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| CN100461379C true CN100461379C (en) | 2009-02-11 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102420183B (en) * | 2011-12-07 | 2014-02-05 | 深圳市华星光电技术有限公司 | Manufacturing method of TFT (Thin Film Transistor) array substrate and TFT array substrate |
| CN103681693B (en) | 2013-12-05 | 2017-05-24 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate and display device |
| CN108257977B (en) | 2018-01-10 | 2021-01-01 | 京东方科技集团股份有限公司 | Display back plate and manufacturing method thereof, display panel and display device |
| TWI714266B (en) * | 2019-09-18 | 2020-12-21 | 力晶積成電子製造股份有限公司 | Image sensor |
| CN115598892B (en) * | 2022-11-08 | 2023-04-18 | 北京京东方技术开发有限公司 | Array substrate and display device |
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| US5346833A (en) * | 1993-04-05 | 1994-09-13 | Industrial Technology Research Institute | Simplified method of making active matrix liquid crystal display |
| US5804500A (en) * | 1995-06-02 | 1998-09-08 | Actel Corporation | Fabrication process for raised tungsten plug antifuse |
| US5828082A (en) * | 1992-04-29 | 1998-10-27 | Industrial Technology Research Institute | Thin film transistor having dual insulation layer with a window above gate electrode |
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| US20060102905A1 (en) * | 2004-11-12 | 2006-05-18 | Park Yong I | Liquid crystal display device and method of fabricating the same |
| CN1797143A (en) * | 2004-12-28 | 2006-07-05 | 中华映管股份有限公司 | Method for manufacturing pixel structure |
| CN1877432A (en) * | 2006-07-18 | 2006-12-13 | 友达光电股份有限公司 | Pixel structure of panel display device and method for fabricating same |
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| US5828082A (en) * | 1992-04-29 | 1998-10-27 | Industrial Technology Research Institute | Thin film transistor having dual insulation layer with a window above gate electrode |
| US5346833A (en) * | 1993-04-05 | 1994-09-13 | Industrial Technology Research Institute | Simplified method of making active matrix liquid crystal display |
| US5804500A (en) * | 1995-06-02 | 1998-09-08 | Actel Corporation | Fabrication process for raised tungsten plug antifuse |
| CN1649110A (en) * | 2004-01-19 | 2005-08-03 | 财团法人工业技术研究院 | Forming method for thin film transistor element with static discharge protection |
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