JP2020202223A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device including a TFT formed of polysilicon and a TFT formed of oxide semiconductor, in which the number of layers is reduced so that the manufacturing cost can be reduced.SOLUTION: A semiconductor device includes a first TFT in which a first polysilicon 102 is used as a channel and a second polysilicon 1022 obtained by adding conductivity to the first polysilicon is used as a source and a drain, and a second TFT in which an oxide semiconductor 108 is used as a channel and the oxide semiconductor having conductivity is used as a source and a drain. A first gate electrode 104 in the first TFT is formed of the same material as the source and the drain of the oxide semiconductor.SELECTED DRAWING: Figure 5

Description

The present invention relates to a semiconductor device including a display device and an optical sensor device using an oxide semiconductor TFT and a polysilicon TFT.

A TFT (Thin Film Transistor) using an oxide semiconductor (Oxide Semiconductor, hereafter referred to as an OS) can have a larger OFF resistance than a TFT using polysilicon (Poly-Silicon), and a-Si ( Since the mobility can be increased as compared with a TFT using amorphous silicon (amorphous silicon), it can be used for a display device such as a liquid crystal display device or an organic EL display device, or a semiconductor device such as a sensor. On the other hand, since the polysilicon TFT has a large carrier mobility, the operating speed can be increased.

Therefore, it has been proposed to use an oxide semiconductor TFT as a switching TFT in a pixel and a polysilicon TFT as a driving circuit for scanning lines and signal lines. The method of forming an oxide semiconductor TFT and a polysilicon TFT on one substrate is also called a hybrid method.

Patent Document 1 describes a configuration in which a polysilicon TFT is used as a light-shielding film for an oxide semiconductor in a hybrid semiconductor circuit board.

JP-A-2018-64020

The oxide semiconductor in the oxide semiconductor TFT and the polysilicon in the polysilicon TFT cannot be formed in the same layer. Therefore, the number of layers is large in the semiconductor circuit board on which the oxide semiconductor TFT and the polysilicon TFT are formed. As the number of layers increases, the manufacturing cost increases and the manufacturing yield also decreases.

An object of the present invention is to reduce the number of layers in such a hybrid type semiconductor circuit board and reduce the manufacturing cost of the semiconductor circuit board. Further, it is possible to reduce the manufacturing cost of a display device such as a liquid crystal display device or an organic EL display device having such a hybrid semiconductor circuit board, or a semiconductor device such as a sensor.

The present invention overcomes the above problems, and specific means are as follows.

(1) A first TFT having a channel made of a first polysilicon and a second polyvinyl obtained by imparting conductivity to the first polysilicon at a source and a drain, a channel made of an oxide semiconductor, and the oxide semiconductor. A semiconductor device having a second TFT having a source and a drain imparted with conductivity to the semiconductor device, wherein the first gate electrode constituting the first TFT is made of the same material as the source and drain of the oxide semiconductor. A semiconductor device characterized by being formed.

(2) A first TFT having a channel made of first polysilicon and a second polysilicon imparting conductivity to the first polysilicon as a source and a drain, a channel made of an oxide semiconductor, and the oxide semiconductor. A semiconductor device having a second TFT having a source and a drain imparted with conductivity to the second TFT, the second gate electrode constituting the second TFT is formed of the same material as the second polysilicon. A semiconductor device characterized by being formed of a third polysilicon.

It is a top view of the liquid crystal display device. It is a top view of the display area of a liquid crystal display device. It is sectional drawing of the liquid crystal display device which has a hybrid structure. It is an enlarged sectional view of the TFT substrate part of FIG. It is sectional drawing which shows the structure of Example 1. FIG. It is sectional drawing which shows the 1st step for forming the structure of FIG. It is sectional drawing which shows the 2nd step for forming the structure of FIG. It is sectional drawing which shows the 3rd step for forming the structure of FIG. It is an equivalent circuit of an inverter circuit. It is a top view which shows the example of the layout which formed the circuit of FIG. 9 by the structure of Example 1. It is sectional drawing which shows the structure of Example 2. FIG. It is a top view which shows the structure of Example 2. FIG. It is sectional drawing which shows the structure of Example 3. FIG. It is an equivalent circuit of pixels of an organic EL display device. It is sectional drawing of the pixel of the organic EL display device which has a hybrid structure. It is sectional drawing which shows the example of an optical sensor. It is a top view of an optical sensor.

Hereinafter, the contents of the present invention will be described in detail with reference to Examples. In the following examples, the present invention will be described mainly by taking a liquid crystal display device as an example, but the present invention uses not only a liquid crystal display device but also another display device such as an organic EL display device or a hybrid semiconductor circuit board. It can also be applied to the sensor used or other semiconductor devices.

FIG. 1 is a plan view of a liquid crystal display device to which the present invention is applied. In FIG. 1, the TFT substrate 100 and the opposing substrate 200 are adhered to each other by the sealing material 16, and a liquid crystal layer is sandwiched between the TFT substrate 100 and the opposing substrate 200. A display region 14 is formed in a portion where the TFT substrate 100 and the facing substrate 200 overlap.

Scanning lines 11 extend in the horizontal direction (x direction) and are arranged in the vertical direction (y direction) in the display area 14 of the TFT substrate 100. Further, the video signal lines 12 extend in the vertical direction and are arranged in the horizontal direction. The area surrounded by the scanning line 11 and the video signal line 12 is the pixel 13.
The TFT substrate 100 is formed larger than the opposing substrate 200, and the portion where the TFT substrate 100 does not overlap the opposing substrate 200 is a terminal region 15. A flexible wiring board 17 is connected to the terminal area 15. The driver IC that drives the liquid crystal display device is mounted on the flexible wiring board 17.

Since the liquid crystal does not emit light by itself, a backlight is arranged on the back surface of the TFT substrate 100. The liquid crystal display panel forms an image by controlling the light from the backlight for each pixel. The flexible wiring board 17 is bent to the back surface of the backlight to reduce the outer shape of the liquid crystal display device as a whole.

In the liquid crystal display device of the present invention, the TFT used for the display region 14 is a TFT using an oxide semiconductor having a small leakage current. Further, for example, a scanning line driving circuit is formed in the frame portion near the sealing material 16, and a TFT using a polysilicon semiconductor having a high mobility is used for the scanning line driving circuit.

FIG. 2 is a plan view of pixels in a liquid crystal display device. FIG. 2 is a liquid crystal display device of a system called FFS (Fringe Field Switching) in an IPS (In Plane Switching) system. In FIG. 2, a TFT using an oxide semiconductor 108 is used. Since the oxide semiconductor TFT has a small leakage current, it is suitable as a switching TFT. A polysilicon TFT is used for a scanning line drive circuit or the like formed around the display area.

In FIG. 2, the scanning lines 11 extend in the horizontal direction (x direction) and are arranged in the vertical direction (y direction). Further, the video signal lines 12 extend in the vertical direction and are arranged in the horizontal direction. A pixel electrode 121 is formed in a region surrounded by the scanning line 11 and the video signal line 12. In FIG. 2, an oxide semiconductor TFT having an oxide semiconductor 108 is formed between the video signal line 12 and the pixel electrode 121. In the oxide semiconductor TFT, the video signal line 12 constitutes the drain electrode, and the scanning line 11 branches to form the gate electrode 111 of the oxide semiconductor TFT. The source electrode 117 of the oxide semiconductor TFT extends to the pixel electrode 121 side and is connected to the pixel electrode 121 via a through hole 130.

The pixel electrode 121 is formed in a comb-teeth shape. A common electrode 119 is formed in a plane on the lower side of the pixel electrode 121 via a capacitive insulating film. The common electrode 119 is continuously and commonly formed in each pixel. When a video signal is supplied to the pixel electrode 121, electric lines of force passing through the liquid crystal layer are formed between the pixel electrode 121 and the common electrode 119, and an image is formed by rotating the liquid crystal molecules 301. In FIG. 2, the light-shielding film (shield electrode) formed between the TFT and the substrate 100 is omitted.

FIG. 3 is a cross-sectional view of a display area and a peripheral circuit area of the liquid crystal display device. The right side of FIG. 3 is a cross-sectional view of the display area, and the left side is a cross-sectional view of the polysilicon TFT constituting the drive circuit in the peripheral circuit area. In the display region, the liquid crystal layer 300 exists between the TFT substrate 100 and the facing substrate 200, but the peripheral circuit is often formed so as to overlap the sealing material 16 in a plane. On the left side of 3, the sealing material 16 exists between the TFT substrate 100 and the opposing substrate 200. The peripheral circuit and the display area are simultaneously formed on the same substrate 100.

In FIG. 3, the base film 101 is formed on the TFT substrate 100 made of a resin such as glass or polyimide. The base film 101 is formed of a laminated film such as a silicon oxide (hereinafter SiO) film or a silicon nitride (hereinafter SiN) film. This is to prevent impurities from the substrate 100 from contaminating the semiconductor layer 102 and the like.

The polysilicon layer 102 is formed on the base film 101. The polysilicon layer 102 is initially formed of a-Si by CVD, and is converted into polysilicon by irradiating the a-Si with an excimer laser. Since such polysilicon can be formed at a low temperature, it is also called LTPS (Low Temperature Poly Silicon). The thickness of the polysilicon layer is, for example, 50 nm.

After patterning the polysilicon layer 102, the first gate insulating film 103 is formed by CVD. A first gate electrode 104 for a polysilicon TFT is formed of a metal or an alloy on the gate insulating film 103 (hereinafter, the alloy is also simply referred to as a metal). The metal constituting the first gate electrode 104 is, for example, MoW, Ti, or the like. In the process of patterning the first gate electrode 104, n-region 1021 and n + region 1022 are formed in the polysilicon layer by ion implantation. The n- region is also called an LDD (Light Doped Drain) region 1021, and the n + region is also called a conductive region 1022. The n + region 1022 forms a source or drain, and the LDD region 1021 composed of the n− region prevents dielectric breakdown between the channel 102 and the drain 1022. At the same time as the first gate electrode 104, a light-shielding film 105 for the oxide semiconductor TFT is formed in the display region.

The first interlayer insulating film 106 is formed of a SiN film and the second interlayer insulating film 107 is formed of a SiO film on the first gate electrode 104 and the light-shielding film 105. An oxide semiconductor layer 108 is formed on the SiO film 107 in the display region. Oxide semiconductor 108 includes IGZO (Indium Gallium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ZnON (Zinc Oxide Nitride), IGO (Indium Galium Oxide) and the like. In this embodiment, IGZO is used as the oxide semiconductor 108.

In the oxide semiconductor layer 108, a protective film 109 made of metal is formed at a portion where the drain electrode 116 and the source electrode 117 come into contact with each other. The through holes 114 and 115 for the drain electrode 116 and the source electrode 117 are formed at the same time as the through holes 123 and 124 for the drain electrodes 125 and the source electrode 126 of the polysilicon semiconductors 1021 and 1022. On the polysilicon side, an oxide film is formed on the surface inside the through hole, and it is necessary to wash it with hydrofluoric acid (HF) to remove it. However, if this hydrofluoric acid (HF) invades the through holes 114 and 115 on the oxide semiconductor 108 side, the oxide semiconductor 108 is dissolved. In order to protect the oxide semiconductor layer 108 from hydrofluoric acid (HF), a protective film 109 made of metal is formed.

The second gate insulating film 110 is formed by, for example, a SiO film, covering the oxide semiconductor layer 108 and the protective film 109. Oxygen is supplied to the oxide semiconductor 108 from this SiO film to maintain the characteristics of the oxide semiconductor 108. The second gate electrode 111 is formed so as to cover the second gate insulating film 110. The second gate electrode 111 can be formed of the same material as the first gate electrode 104. The third interlayer insulating film 112 is formed by, for example, SiO, covering the second gate electrode 111, and the fourth interlayer insulating film 113 is formed, for example, by SiN, covering the third interlayer insulating film 112.

Through holes 114 and 115 are formed on the oxide semiconductor TFT side to form drain electrodes 116 and source electrodes 117, and at the same time, through holes 123 and 124 are formed on the polysilicon TFT side to form drain electrodes 125 and source electrodes 126. To do. The drain electrode 116 on the oxide semiconductor TFT side is connected to the video signal line, and the source electrode 117 is connected to the pixel electrode 121 via through holes 130 and 131. On the other hand, the drain electrode 125 and the source electrode 126 on the polysilicon TFT side form the wiring of the drive circuit.

An organic passivation film 118 is formed so as to cover the drain electrode 116 and the source electrode 117. Since the organic passivation film 118 also serves as a flattening film, it is formed as thick as about 2 to 4 μm. In the display region, a through hole 130 is formed in the organic passivation film 118 in order to connect the pixel electrode 121 and the source electrode 117. Further, in the display region, the common electrode 119 is formed in a plane shape on the organic passivation film 118.

A capacitive insulating film 120 is formed of SiN so as to cover the common electrode 119. The capacitive insulating film 120 is so called because it forms a pixel capacitance between the common electrode 119 and the pixel electrode 121. A pixel electrode 121 is formed in a comb-like shape on the capacitive insulating film 120. The planar shape of the pixel electrode 121 is, for example, as shown in FIG. An alignment film 122 for initially orienting the liquid crystal molecules 301 is formed so as to cover the pixel electrode 121. Since IPS does not require the pretilt angle of the liquid crystal molecule 301, photo-alignment using polarized ultraviolet rays is advantageous for the alignment treatment of the alignment film 122. When a voltage is applied between the common electrode 119 and the pixel electrode 121, electric lines of force are generated in the liquid crystal layer 300, which causes the liquid crystal molecules 301 to rotate, and the transmittance of the liquid crystal layer 300 is increased for each pixel. It is controlled and an image is formed.

In FIG. 3, the opposing substrate 200 is arranged with the liquid crystal layer 300 interposed therebetween. A color filter 201 and a black matrix 202 are formed on the facing substrate 200, and an overcoat film 203 is formed on the color filter 201 and the black matrix 202. The alignment film 204 is formed on the overcoat film 203. The action and alignment treatment of the alignment film 204 are the same as those of the alignment film 116 on the TFT substrate 100 side.

In FIG. 3, the cross-sectional structure of the peripheral circuit portion on the left side is the same as that of the display region except that the polysilicon TFT is formed instead of the oxide semiconductor TFT. However, in the peripheral circuit portion of FIG. 3, a sealing material 16 for adhering the TFT substrate 100 and the opposing substrate 200 is formed instead of the liquid crystal layer 300. Further, the pixel electrode 121 does not exist in this portion.

FIG. 4 is an enlarged cross-sectional view of the polysilicon TFT and the oxide semiconductor TFT portion of FIG. The configuration of FIG. 4 is the same as that described with reference to FIG. 3, but the fourth passivation film 113 is omitted in FIG. Further, in FIG. 4, the polysilicon TFT and the oxide semiconductor TFT are arranged side by side for comparison.

Further, in FIG. 4, the structure of the oxide semiconductor 108 is described in more detail. In the oxide semiconductor 108, the channel is below the second gate electrode 111. The thickness of the oxide semiconductor 108 is, for example, 10 nm to 100 nm. In FIG. 4, after the second gate electrode 111 is formed, impurities are doped into the oxide semiconductor 108 by ion implantation (I / I) using the second gate electrode 111 as a mask, so that the oxide semiconductor 108 is not under the second gate electrode 111. The oxide semiconductor of is the conductive region 1081. The ions implanted by ion implantation may be, for example, phosphorus (P), boron (B), argon (Ar), or the like. The lattice structure of the oxide semiconductor 108 is destroyed by ion implantation to generate conductivity.

One of the conductive regions 1081 is covered with a protective electrode 109 made of metal and connected to the drain electrode 116, and the other is covered with a protective electrode 109 made of metal and connected to the source electrode 117. There is. The protective electrode 109 can be formed of, for example, the same metal as the first gate electrode 104 or the second gate electrode 111.

FIG. 5 is a cross-sectional view of a portion of the polysilicon TFT and the oxide semiconductor TFT according to the first embodiment. The feature of FIG. 5 is that an oxide semiconductor 1081 imparted with conductivity is used as the gate electrode 104 of the polysilicon TFT. Therefore, in FIG. 5, it is not necessary to form the first interlayer insulating film 106 and the second interlayer insulating film 107 in FIG. Therefore, the throughput can be improved by the amount that the number of layers is reduced. The conductive oxide semiconductor 1081 constituting the first gate electrode 104 is formed and patterned at the same time as the drain region 1081 and the source region 1081 in the oxide semiconductor TFT.

In FIG. 5, a light-shielding film 105 is formed on the TFT substrate 100 at a portion corresponding to the oxide semiconductor TFT. Since the oxide semiconductor TFT is formed in the display region and is premised on being irradiated with the backlight, the light-shielding film 105 is formed, but the polysilicon TFT is formed in the peripheral drive circuit, and this portion is formed. Since it is assumed that the backlight is shielded by other light-shielding means, the light-shielding film 105 is not formed. However, when the polysilicon TFT is formed in the display region, the light-shielding film 105 is poly. It is also formed on the portion corresponding to the silicon TFT at the same time.

In FIG. 5, the undercoat film 101 is formed so as to cover the light-shielding film 105. Polysilicon 102 is formed on the base film 101, which is the LTPS described in FIG. In addition to the channel region 102, the LDD region 1021 and the conductive region 1022 are formed on the polysilicon 102. The forming method covers the polysilicon 102 described with reference to FIGS. 6 to 8 and covers the first gate insulating film made of SiО. 103 is formed. The oxide semiconductor 108 is formed on the entire surface of the substrate by sputtering so as to cover the first gate insulating film 103 and is patterned. In the peripheral circuit region, the oxide semiconductor 108 is imparted with conductivity to form the first gate electrode 104, and in the display region, it constitutes an active region of the oxide semiconductor TFT. That is, the oxide semiconductor 108 is formed simultaneously in the polysilicon TFT portion and the oxide semiconductor TFT portion until patterning, but the treatment such as imparting conductivity is separate between the polysilicon TFT portion and the oxide semiconductor TFT portion. It is done in. After that, in the oxide semiconductor TFT, the protective electrode 109 is formed, the second gate insulating film 110 and the second gate electrode 111 are formed, and the third interlayer insulating film 112 is formed over these. It is the same.

By the way, in the configuration of FIG. 5, a SiO film is formed on the oxide semiconductor 1081 imparted with conductivity constituting the polysilicon TFT. Normally, when oxygen is supplied to the SiO film, the resistance of the oxide semiconductor 1081 increases. However, when the conductivity of the oxide semiconductor 108 is imparted by ion implantation of phosphorus (P), boron (B), argon (Ar), etc., the conductivity is increased by destroying the lattice structure of the oxide semiconductor 108. Since it is imparted, even if oxygen is implanted from the SiO film, the resistivity does not increase significantly.

6 to 8 are cross-sectional views showing a process of forming a polysilicon TFT composed of a gate electrode 104 by an oxide semiconductor 1081. 6 to 8 show a case where an N-channel TFT and a P-channel TFT are formed as the polysilicon TFT. N-type polysilicon is used for the polysilicon TFT on the left side to form an N-channel TFT, and P-type polysilicon is used for the polysilicon TFT on the right side to form a P-channel TFT.

In FIG. 6, polysilicon 102 and 1025 are formed and patterned on the base film 101. The first gate insulating film 103 made of SiО is formed over the patterned polysilicon 102 and 1025. An oxide semiconductor 1081 to which conductivity is imparted is formed on the first gate insulating film 103. In FIG. 6, the oxide semiconductors 108 and 1081 are described in a state of being covered with a resist 250 for patterning.

In FIG. 6, the oxide semiconductor in the polysilicon TFT region is a conductive oxide semiconductor 1081 in a state where conductivity is imparted by ion implantation or the like, but the oxide semiconductor 108 on the oxide semiconductor TFT side is , It is in a state where conductivity has not been imparted yet. Conductivity is imparted to the oxide semiconductor 108 on the oxide semiconductor TFT side after the first gate electrode 104 is formed by the oxide semiconductor 1081 on the polysilicon TFT side.

In FIG. 6, the polysilicon TFT on the left side is an N-channel TFT, and the polysilicon TFT on the right side is a P-channel TFT. In the state of FIG. 6, for example, phosphorus (P) is doped by ion implantation (I / I) to form an n + region. As a result, the drain region 1022 and the source region 1022 are formed in the N-channel TFT. At this time, the oxide semiconductor 108 covered with the resist 250, the oxide semiconductor 1081 to which conductivity is imparted, the N-type polysilicon 102, the P-type polysilicon 1025, and the like are not affected by the ion implantation.

In FIG. 7, for example, a plasma asher is applied to retract the resist 250 from the state of FIG. 6, and the oxide semiconductor 1081 of the portion exposed from the resist is etched. Then, phosphorus (P) or the like is ion-implanted to form an n- region, that is, an LDD region. In this process, the P-type polysilicon 1025 of the P-channel TFT, the oxide semiconductor 108 on the oxide semiconductor side, and the like are covered with a resist and are not affected by n- ion implantation.

FIG. 8 shows a process of forming a P-channel type TFT. In FIG. 8, the resist 250 used in FIG. 7 is removed, and the resist 250 is newly patterned for forming the P-channel TFT. In this state, the entire N-channel TFT and the oxide semiconductor 108 that constitutes the oxide semiconductor TFT are covered with the resist 250.

In the state of FIG. 8, impurities such as boron (B) are doped into the P-type polysilicon 1025 using the resist 250 as a mask to form the drain region 1026 and the source region 1026 in the P-type polysilicon 1025. At this time, since the N-channel TFT and the oxide semiconductor 108 constituting the oxide semiconductor TFT are covered with the resist 250, they are not affected by the ion implantation of boron (B).

By the process of FIGS. 6 to 8, N-channel TFTs and P-channel TFTs using the conductive oxide semiconductor 1081 as the gate electrode 104 can be formed. After that, an oxide semiconductor TFT is formed, and the forming method is as described with reference to FIG.

FIG. 9 shows, for example, an equivalent circuit when an inverter circuit is formed by an N-channel TFT and a P-channel TFT in a peripheral drive circuit. In FIG. 9, the drain of the P-type TFT is connected to the power supply voltage Vdd, and the source of the N-type TFT is connected to the reference voltage Vss. An input In is commonly applied to the gates of the N-type TFT and the P-type TFT. Then, the output Out is output in common from the source of the P-type TFT and the drain of the N-type TFT.

FIG. 10 is a plan view showing a layout in which the inverter of FIG. 9 is composed of a TFT in which a gate electrode 104 is formed of an oxide semiconductor 1081 imparted with conductivity. The hierarchical relationship of FIG. 10 is aligned with that of FIG. In FIG. 10, the framed Pch-LTPS means a P-channel LTPS TFT, and the framed Nch-LTPS means an N-channel LTPS TFT. In FIG. 10, the wiring 921 uses the same layer as the video signal line 12. In FIG. 10, Vdd extends in the lateral direction (x direction) and Vss extends in the lateral direction. Polysilicon extends in the vertical direction (y direction) so as to connect Vss and Vdd. The polysilicon 1022 is connected to Vss by the contact hole CH1, and the polysilicon 1026 is connected to Vdd by the contact hole CH2.

The polysilicon 1026 and 1022 are connected to the output line Out by the contact hole CH4. The one closer to Vss is N-type polysilicon, and the one closer to Vdd is P-type polysilicon. On the other hand, between Vdd and Vss, the input line (In) extending in the lateral direction is connected to the protective electrode 109 via the through hole CH3. One of the oxide semiconductor 1081 imparted with conductivity is bent to be the gate electrode of the N-type TFT, and the other is bent to be the gate of the P-type TFT.

The resistivity of the oxide semiconductor 1081 to which the conductivity is imparted is higher than that of the metal, but since the routing wiring for the gate electrode uses the metal of the same material as the video signal line, the resistance of the oxide semiconductor 1081 Rate is not a big issue. Further, in FIG. 10, the protective electrode 109 is used only in the portion of the contact hole CH3, but if the protective electrode 109 is extended to the vicinity of the TFT channel, the oxide semiconductor 1081 can be used as a gate electrode. The resistivity problem when used is further reduced.

FIG. 11 is a cross-sectional view showing the configuration of the second embodiment. The feature of FIG. 11 is that the oxide semiconductor TFT is used as the bottom gate, and the second gate electrode 111 constituting the top gate is omitted. The bottom gate electrode 1111 is made of polysilicon 1022 having conductivity. Therefore, since the second gate electrode 111 made of metal can be omitted, the number of layers can be further reduced as compared with the case of the first embodiment.

In FIG. 11, the left side is a polysilicon TFT, and as described with reference to FIG. 5, the gate electrode 104 is formed of an oxide semiconductor 1081 imparted with conductivity. The right side in FIG. 11 is an oxide semiconductor TFT, and the difference from FIG. 5 of the first embodiment is that the top gate 111 does not exist, and the bottom gate electrode 1111 is configured by polysilicon 1022 to which conductivity is imparted instead. That is. The bottom gate electrode 1111 can be formed at the same time when the drain region 1022 or the source region 1022 is formed in the polysilicon TFT. Therefore, the process load can be further reduced as compared with the case of FIG.

In FIG. 11, even if the top gate electrode 111 is omitted, the second gate insulating film 110 formed of SiO remains. That is, this is to supply oxygen to the oxide semiconductor 108 from the SiO film forming the second gate insulating film 110. However, if the third interlayer insulating film 112 is formed of SiO and oxygen can be supplied to the oxide semiconductor 108 from this SiO film, the second gate insulating film can be omitted.

Further, the gate insulating film 103 made of SiО is formed between the oxide semiconductor 108 and the conductive polysilicon 1022 which is the bottom gate 1111. However, the oxide semiconductor 108 from the gate insulating film 103 made of SiО When the supply of oxygen to the oxide semiconductor 108 is insufficient, it is necessary to form the SiO film by another method such as sputtering so that the necessary oxygen supply from the gate insulating film 103 to the oxide semiconductor 108 can be secured. ..

FIG. 12 is a plan view showing a layout when the bottom gate 1111 of the oxide semiconductor TFT is formed of polysilicon 1022 to which conductivity is imparted. In FIG. 12, the Bottom Gate OS-TFT surrounded by a frame means a Bottom Gate oxide semiconductor TFT. In FIG. 12, the video signal line 12 extends vertically and rearward (y direction), and an oxide semiconductor TFT is formed between the two video signal lines 12. A shielded wire 105 having a role as a light-shielding film 105 extends below the video signal line 12 in the lateral direction (x direction). The shielded wire 105 in FIG. 12 may be the gate wiring 11.

In FIG. 12, a shield electrode 105 and a bottom gate electrode 1111 formed of polysilicon 1022 imparted with conductivity are connected via a through hole CH6. The connection is usually made by two through holes, but is represented by the contact hole CH6 in FIG. This connection is made via an electrode 922 formed in the same layer as the video signal line 12. The shield electrode 105 in FIG. 12 can also be used as the scanning line 91.

In FIG. 12, the protective electrode 109 is connected to the video signal line 92 by the contact hole CH5. That is, in FIG. 12, the protective electrode 109 constitutes the drain electrode. In FIG. 12, when viewed in a plane, a source electrode composed of a protective electrode 109 is arranged across a channel formed of the oxide semiconductor 108, and the contact hole CH7 is the same as the video signal line 12. Connect with the electrode 923 of the layer. Then, the electrode 923 is connected to the pixel electrode.

FIG. 13 is a cross-sectional view showing the third embodiment. The difference from FIG. 11 in FIG. 13 is that the polysilicon TFT is not a top gate but a bottom gate. Then, at the gate of the polysilicon TFT, a bottom gate electrode 1041 formed simultaneously with the same material in the same layer as the light shielding layer 105 is formed. In FIG. 13, the base film 101 constitutes the gate insulating film of the polysilicon TFT. Therefore, it is desirable that the base film 101 of FIG. 13 is not a thick film. In FIG. 13, for example, a SiN film or a laminated film of a SiN film and a SiO film is used as the base film 101.

The structure of the oxide semiconductor TFT in FIG. 13 is the same as that in FIG. Therefore, in FIG. 13, both the polysilicon TFT and the oxide semiconductor TFT are bottom gates. The LDD region 1021 and the conductive region 1022 of polysilicon in the polysilicon TFT in FIG. 13 can be formed by the process described with reference to FIGS. 6 to 8.

Other configurations of FIG. 13 are the same as those described with reference to FIG. In FIG. 13, the number of layers can be reduced and the manufacturing yield is improved by using polysilicon as the bottom gate and at the same time configuring the gate electrode 1111 of the oxide semiconductor TFT with polysilicon 1022 imparted with conductivity. It is possible to reduce the manufacturing cost.

As described above, in the first to third embodiments, the polysilicon TFT is arranged closer to the substrate than the oxide semiconductor TFT, but the oxide semiconductor TFT is arranged closer to the substrate than the polysilicon TFT. You may.

In Examples 1 to 3, the case where the present invention is applied to a liquid crystal display device has been described. The present invention can also be applied to an organic EL display device. FIG. 14 is an equivalent circuit of the pixel portion of the display area of the organic EL display device. In FIG. 14, the video signal line 12 and the power supply line 93 extend in the vertical direction and are arranged in the horizontal direction. Further, the scanning lines 11 extend in the horizontal direction and are arranged in the vertical direction. The area surrounded by the video signal line 12, the power supply line 93, and the scanning line 11 is a pixel.

In FIG. 14, the current flowing through the organic EL layer (EL) as the light emitting layer is controlled by the control TFT (T2), the drain of the control TFT (T2) is connected to the power supply line 93, and the power supply line 93 and the control TFT ( A holding capacity (Ch) is connected between the drains of T2). Further, the gate of the control TFT (T2) is connected to the source of the switching TFT (T1). The gate of the switching TFT (T1) is connected to the scanning line 11, and the drain is connected to the video signal line 12.

In FIG. 14, when the gate of the switching TFT (T1) is turned on, a video signal is supplied from the video signal line 12 to one electrode of the holding capacitance Ch, and a charge corresponding to this is supplied to the holding capacitance Ch of the power supply line 93. Supplied from. As a result, the gate of the driving TFT (T2) is held at a predetermined potential, and the corresponding current flows to the organic EL layer (EL) via the control TFT (T2).

As shown in FIG. 14, there are two TFTs (T1, T2) in the pixels of the organic EL display device. Both TFTs can be formed of oxide semiconductors. In this embodiment as well, the peripheral drive circuit is formed of the polysilicon TFT in the same manner. That is, the semiconductor circuit board has a hybrid configuration.

FIG. 15 is an example of a cross-sectional view of the pixel portion when the control TFT in the pixel is composed of an oxide semiconductor. As can be seen by comparing FIGS. 15 and 3, in both the liquid crystal display device and the organic EL display device, the organic passage film 118 is formed by covering the drain electrode 116 and the source electrode 117 of the TFT to form the organic passivation film. It is the same as FIG. 3 which is a liquid crystal display device until the through hole 130 is formed in the liquid crystal display device. Therefore, the configuration of the present invention described in Examples 1 to 3 can be applied to the organic EL display device as it is.

The following is a part where FIG. 15 showing an organic EL display device is different from FIG. 3 showing a liquid crystal display device. In FIG. 15, a lower electrode 150 as an anode is formed on the organic passivation film 118. A bank 160 having a hole is formed on the lower electrode 150. An organic EL layer 151 as a light emitting layer is formed in the hole of the bank 160. An upper electrode 152 as a cathode is formed on the organic EL layer 151. The upper electrode 152 is formed in common with each pixel. A protective film 153 having a SiN film or the like is formed so as to cover the upper electrode 152. A circularly polarizing plate 155 for preventing reflection of external light is attached on the protective film 153 via an adhesive 154.

By the way, since the organic EL display device does not require a backlight, a light-shielding film 105 for light is not always necessary. However, when the substrate 100 is made of a resin such as polyimide, the resin is easily charged, so that the influence of the charge on the substrate 100 The light-shielding film 105 may need to be maintained as a shield electrode because it is necessary to remove the light-shielding film 105.

When the control TFT in the pixel is formed of a polysilicon TFT, the TFT can be changed to the configuration of FIG. 15 to have a polysilicon TFT configuration as shown in FIG. 5, for example. In this case, if necessary, a shield electrode or a light-shielding film similar to the light-shielding film 105 formed below the oxide semiconductor can be formed below the polysilicon.

The present invention can be applied not only to display devices but also to various semiconductor devices such as sensor devices. There are many types of sensor devices. FIG. 16 shows an example in which a configuration similar to that of the organic EL display device of FIG. 15 is used as an optical sensor. That is, the organic EL display device is used as a light emitting element. In FIG. 16, in the display region (light emitting element) of the organic EL display device described with reference to FIG. 15, the light receiving element 500 is arranged on the lower surface of the TFT substrate 100. On the upper surface of the light emitting element, a face plate 600 formed of a transparent glass substrate or a transparent resin substrate is arranged via an adhesive material 601. The object to be measured 700 is placed on the face plate 600.

In the light emitting element, the light emitting region is composed of an organic EL layer 151, a lower electrode 150, and an upper electrode 152. A window 400 in which the organic EL layer, the lower electrode, and the upper electrode do not exist is formed in the central portion of the light emitting region, and light can pass through this portion. A reflective electrode is formed in the lower layer of the lower electrode 150, and the light L emitted by the organic EL layer 151 goes upward.

In FIG. 16, the light L emitted from the organic EL layer 151 is reflected by the object to be measured 700 and received through the window 400 by the light receiving element 500 arranged under the TFT substrate 100, and the object to be measured 700 is present. Detects that. When the object 700 to be measured does not exist, the reflected light does not exist, so that no current flows through the light receiving element 500. Therefore, the presence or absence of the object to be measured 700 can be measured.

FIG. 17 is a plan view of an optical sensor in which the sensor elements shown in FIG. 16 are arranged in a matrix. In FIG. 17, scanning lines 91 extend in the lateral direction (x direction) from scanning circuits 95 arranged on both sides in the x direction. The signal line 92 extends in the vertical direction (y direction) from the signal circuit 96 arranged on the lower side in the y direction, and the power supply line 93 extends in the downward direction (-y direction) from the power supply circuit 97 arranged on the upper side. ing. The region surrounded by the scanning line 91 and the signal line 92 or the scanning line 91 and the power supply line 93 is the sensor element 94.

In the optical sensor of this embodiment, the two-dimensional image can be read not only by measuring the presence or absence of the object to be measured 700 but also by measuring the intensity of reflection from the object to be measured 700. It is also possible to detect a color image or a spectroscopic image by sensing for each color. The resolution of the sensor is determined by the size of the sensor element 94 in FIG. 17, but the effective size of the sensor element can be adjusted by driving a plurality of sensor elements 94 together as needed.

In the examples of FIGS. 16 and 17, the same configuration as that of the organic EL display device is applied to the optical sensor, but the present invention applies not only to such a configuration but also to an optical sensor using another detection method. Can also be applied. Furthermore, the present invention can be applied not only to optical sensors but also to other sensors using a semiconductor device substrate, such as a capacitance sensor.

11 ... scanning line, 12 ... video signal line, 13 ... pixel, 14 ... display area, 15 ... terminal area, 16 ... sealing material, 17 ... flexible wiring board, 20 ... foreign matter, 30 ... connection wiring, 51 ... light-shielding film, 52 ... Undercoat, 53 ... Polysilicon, 54 ... Gate insulating film, 55 ... Gate electrode, 56 ... Gate insulating film, 90 ... Detection area, 91 ... Scan line, 92 ... Signal line, 93 ... Power line, 94 ... Sensor Element, 95 ... Scanning circuit, 96 ... Signal circuit, 97 ... Power supply circuit, 100 ... TFT substrate, 101 ... Base film, 102 ... Polysilicon semiconductor, 103 ... First gate insulating film, 104 ... First gate electrode, 105 ... Light-shielding film, 106 ... 1st interlayer insulating film, 107 ... 2nd interlayer insulating film, 108 ... Oxide semiconductor, 109 ... Protective electrode, 110 ... 2nd gate insulating film, 111 ... 2nd gate electrode, 112 ... 3rd interlayer Insulating film, 113 ... 4th interlayer insulating film, 114 ... Through hole, 115 ... Through hole, 116 ... Drain electrode, 117 ... Source electrode, 118 ... Organic passivation film, 119 ... Common electrode, 120 ... Capacitive insulating film, 121 ... Pixel electrode, 122 ... Alignment film, 123 ... Through hole, 124 ... Through hole, 125 ... Drain electrode, 126 ... Source electrode, 130 ... Through hole, 131 ... Through hole, 135 ... Through hole, 136 ... Through hole, 150 ... Lower electrode, 151 ... Organic EL layer, 152 ... Cathode, 153 ... Protective layer, 154 ... Adhesive material, 155 ... Plate plate, 160 ... Bank, 200 ... Opposite substrate, 201 ... Color filter, 202 ... Black matrix, 203 ... Over Coated film, 204 ... alignment film, 250 ... resist, 300 ... liquid crystal layer, 301 ... liquid crystal molecule, 400 ... window, 500 ... light receiving element, 600 ... face plate, 601 ... adhesive material, 700 ... object to be measured, 800 ... resist , 921 ... Wiring layer, 922 ... Electrode, 923 ... Electrode, 1021 ... LDD region (n-region), 1022 ... Polysilicon conductive region, 1025 ... P-channel polysilicon, 1026 ... Polysilicon conductive region, 1041 ... Bottom gate electrode , 1081 ... Conductive oxide semiconductor, 1111 ... Bottom gate electrode, EL ... Organic EL layer, CH ... Contact hole, Ch ... Holding capacity, L ... Light, Va ... Anode voltage, Vcc ... Reference voltage, Vdd ... Power supply Voltage, Vk ... Cathode voltage, Vp ... Pixel voltage, Vsig ... Signal voltage

Claims (16)

A first TFT having a channel made of first polysilicon and a second polysilicon imparting conductivity to the first polysilicon in a source and a drain, a channel made of an oxide semiconductor, and conductivity to the oxide semiconductor. A semiconductor device having a second TFT having a source and a drain.
A semiconductor device characterized in that the first gate electrode constituting the first TFT is made of the same material as the source or drain of the oxide semiconductor. The semiconductor device according to claim 1, wherein the source or drain of the oxide semiconductor is imparted with conductivity by ion implantation. The semiconductor device according to claim 1, wherein the first TFT is a top gate, and the second TFT is a top gate. The semiconductor device according to claim 1, wherein the first TFT is an N-channel type and has LDD (Light Doped Drain) regions on both sides of the channel. The semiconductor device according to claim 1, wherein the first TFT is a P-channel type. The semiconductor device according to claim 1, wherein the first gate insulating film constituting the first TFT and the second gate insulating film constituting the second TFT are directly laminated. The second TFT is a bottom gate, and the second gate electrode constituting the second TFT is formed of a third polysilicon made of the same material as the second polysilicon. The semiconductor device according to claim 1. The semiconductor device according to claim 7, wherein the first TFT is a top gate. The seventh aspect of claim 7, wherein the first gate insulating film constituting the first TFT and the second gate insulating film constituting the second TFT are formed of a common insulating film. Semiconductor device. A first TFT having a channel made of first polysilicon and a second polysilicon imparting conductivity to the first polysilicon in a source and a drain, a channel made of an oxide semiconductor, and conductivity to the oxide semiconductor. A semiconductor device having a second TFT having a source and a drain.
A semiconductor device characterized in that the second gate electrode constituting the second TFT is formed of a third polysilicon formed of the same material as the second polysilicon. The semiconductor device according to claim 10, wherein the first TFT is a bottom gate. The second TFT has a light-shielding film on the back surface of the second gate electrode.
The semiconductor device according to claim 10, wherein the first gate electrode of the first TFT is made of the same material as the light-shielding film and is formed on the same layer. The semiconductor device according to any one of claims 1 to 12, wherein the first TFT is used in a drive circuit, and the second TFT is used as a switching element. The semiconductor device according to any one of claims 1 to 12, wherein the semiconductor device is a liquid crystal display device. The semiconductor device according to any one of claims 1 to 12, wherein the semiconductor device is an organic EL display device. The semiconductor device according to any one of claims 1 to 12, wherein the semiconductor device is an optical sensor.

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