TWI694273B - 半導體結構及其製造方法 - Google Patents
半導體結構及其製造方法 Download PDFInfo
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- TWI694273B TWI694273B TW105123927A TW105123927A TWI694273B TW I694273 B TWI694273 B TW I694273B TW 105123927 A TW105123927 A TW 105123927A TW 105123927 A TW105123927 A TW 105123927A TW I694273 B TWI694273 B TW I694273B
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- dielectric waveguide
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- dielectric
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Abstract
一種半導體結構和製造方法於此公開。半導體結構包含垂直設置在第一層與第二層之間的介電質波導,用以在第一輸出節點處生成驅動信號的驅動器晶片,沿著介電質波導的第一側放置並且用以接收來自第一輸出節點的驅動信號的第一傳輸電極,沿著介電質波導的第一側放置的第一接收器電極,沿著該介電質波導的一第二側配置並電性耦接於一接收接地的第二接收電極,以及用以從第一接收電極接收接收信號的接收器晶片。
Description
本發明實施例係關於封裝製程和結構,且特別是關於一種整合扇出型(InFO)封裝製程和結構。
積體光波導常作為集成多種光學功能之積體光學電路中的元件。積體光波導用以在最小衰減的情況下,將光從積體晶片(IC)上的第一點約束和引導至積體晶片上的第二點。一般情況下,積體光波導用以為處於可見光譜之波長內的信號提供功能。
一種半導體結構於此公開。半導體結構包含:介電質波導,垂直設置在第一層與第二層之間;驅動器晶片,用以在第一輸出節點處生成驅動信號;第一傳輸電極,沿著介電質波導的第一側放置並且用以接收來自第一輸出節點的驅動信號;第一接收電極,沿著介電質波導的第一側放置;一第二接收電極,沿著該介電質波導的一第二側配置並電性耦接於一接收接地,其中該第一接收電極和該第二接
收電極為鏡像圖像;以及接收器晶片,用以接收從第一接收電極接收的信號。
本案的另一些實施例是關於一種半導體結構。半導體結構包含:介電質波導,設置在第一介電材料與第二介電材料之間並且具有基本為矩形的截面;第一金屬層,沿著介電質波導的第一側設置;以及第二金屬層,沿著介電質波導的第二側設置。其中第二介電材料設置在模封層上,並且模封層圍繞驅動器晶片和接收器晶片。第一接收電極配置於該第一金屬層中並耦接於該接收器晶片,一第二接收電極配置於該第二金屬層中並耦接於一接收器接地,以及該第一接收電極與該第二接收電極為鏡像圖案。
本案的另一些實施例是關於一種製造半導體結構的方法,該方法包含:將驅動器晶片和接收器晶片附著在封裝中;應用模封材料以圍繞驅動器晶片和接收器晶片;在驅動器晶片和接收器晶片以及模封材料上方形成第一層;在第一層上形成介電質波導;在介電質波導上形成第二層;以及,形成分別沿著該介電質波導的一第一側與一第二側配置的一第一接收電極與一第二接收電極。其中該第一接收電極是被形成以耦接該接收器晶片,以及該第二接收電極是被形成以耦接一接收器接地;其中該第一接收器電極與該第二接收器電極是鏡像圖像。
為讓本案之上述和其他目的、特徵、優點與實
施例能更明顯易懂,所附符號之說明如下:
100:半導體結構
101:介電質波導
101a~101c:介電質波導
102:驅動器電路
102a~102c:驅動器元件
1021、1121:輸出節點
103:傳輸線
104、106:傳輸電極
104a~104c、106a~106c:傳輸電極
105:傳輸耦合元件
107a、107b:接地端
108、110:接收電極
108a~108c:電極
111:傳輸線
112:接收器電路
112a~112c:接收器元件
212、214:過渡區域
216、218:方向
312、314:過渡區域
400:方法
S410~S570:步驟
500:封裝
601:載體
602:黏合層
603:聚合物基層
604:背側RDL
6041:導電部件
605、605b、605a:光阻層
606:開口
607:晶種層
608:導電材料
609:導電通孔
610:開口
611A:驅動器晶片
611B:接收器晶片
6111A、6111B:導電柱
612:模封材料
613:聚合物層
614:波導介電材料
615:聚合物層
616:聚合物層
617:聚合物層
618:球下金屬部
619A、619B:連接件
SIN:輸入信號
S1:傳輸信號
S1’:信號
SOUT:輸出信號
第1A圖是根據本揭示內容的部分實施例所繪示的半導體結構的示意圖。
第1B圖是根據本揭示內容的部分實施例所繪示的第1A圖中示出的半導體結構的三維(3D)視圖。
第2圖是根據本揭示內容的其他部分實施例所繪示的半導體結構的側視圖。
第3圖是根據本揭示內容的部分實施例所繪示的第2圖中所示的半導體結構的頂視圖。
第4圖是根據本揭示內容的部分實施例所繪示的形成包含第1A圖中所示的半導體件結構的整合扇出型(InFO)封裝的方法的流程圖。
第5圖至第24圖是根據本揭示內容的部分實施例所繪示的包含第1A圖中所示的半導體結構的整合扇出型(InFO)封裝在製程的不同階段中的截面圖。
以下揭示內容提供了多個不同實施例,或釋例以實現所本揭示內容主題的不同特徵。具體的元件和設置方式將以實施例描述於後以更好地理解本揭示內容的態樣,但所提供之實施例並非用以限制本揭露所涵蓋的範圍。舉例而言,在以下描述中,在第二部件上方或上形成第一部件可包含第一部件和第二部件直接接觸的實施例,亦可包含形成於第一部件和第二部件之間的附加部件,使得第一部件和第二部件不直接接觸的實施例。此外,本揭示內容在各個實施例中,相同
元件可以相同之符號標示來進行說明以便於理解,但其重複僅是為了說明上的簡潔和清晰,本身並不代表所描述的各個實施例之間的配置和/或關係。
在全篇說明書與申請專利範圍所使用之用詞(terms),除有特別註明外,通常具有每個用詞使用在此領域中、在此揭露之內容中與特殊內容中的平常意義。本說明書中所舉之實例,包含本文所討論的任何用詞之實例,僅是示例性的,並非用以限制本揭示內容之任何示例性用詞的範圍和/或意義。相似地,本揭示內容並不限定於說明書中給出的各個實施例。
此外,雖然本文中使用『第一』、『第二』、…等用語描述不同元件,該用語僅是用以區別以相同技術用語描述的元件或操作。除非上下文清楚指明,否則該用語並非特別指稱或暗示次序或順位,亦非用以限定本發明。舉例而言,在不脫離本揭示內容範圍的情況下,可以將第一元件叫做第二元件,相似地,亦可以將第二元件叫做第一元件。此外,本文中所使用之『及/或』,包含相關列舉項目中一或多個項目的任意一個以及其所有組合。
此外,於本文中可使用諸如『在…下方』、『在…下面』、『下部』、『在…上面』、『上部』或其他相似的空間關係用語,以描述圖中所示的一個元件或部件與另一元件或部件的關係。除了圖中所示的方位外,空間關係用語旨在包含器件在使用或操作過程中的不同方位。裝置亦可以其他方式定位(旋轉90度或在其他方位),並且在本文中使
用的空間關係描述符亦可同樣地作相應解釋。
於本文中,當一元件被稱為『連接』或『耦接』時,可指『電性連接』或『電性耦接』。『連接』或『耦接』亦可用以表示二或多個元件間相互搭配操作或互動。
第1A圖是根據本揭示內容的部分實施例繪示的半導體結構100的示意圖。第1B圖是根據本揭示內容的部分實施例繪示的第1A圖中所示的半導體結構100的三維(3D)視圖。如第1A圖和第1B圖所繪示,半導體結構100包含用以傳播信號的介電質波導101、驅動器電路102和接收器電路112。在部分實施例中,通過介電質波導101傳播的信號是單端信號。在另一部分的實施例中,通過介電質波導101傳播的信號是差分信號。
在部分實施例中,驅動器電路102用以接收輸入信號SIN,並且在輸出節點1021處輸出傳輸信號S1。傳輸信號S1係通過傳輸線103提供至傳輸耦合元件105。在部分實施例中,傳輸耦合元件105包含設置在介電質波導101的相對側上的一對金屬結構,例如包含微帶線。舉例而言,傳輸耦合元件105包含位於介電質波導101的相對側上的傳輸電極104和106。在部分實施例中,傳輸電極104和106係相對於介電質波導101為對稱。在部分實施例中,傳輸電極104和106的形狀和/或圖案為鏡像圖像。
如第1A圖中所繪示,傳輸電極104係沿著介電質波導101的第一側(例如,上側)設置。在部分實施例中,傳輸電極104沿著介電質波導101的頂面設置在金屬互連層
內,並用以接收來自驅動器電路102的傳輸信號S1。
傳輸電極104係通過傳輸線103連接至驅動器電路102,其中傳輸線103對傳輸信號S1從驅動器電路102提供寬頻寬傳輸至傳輸電極104。在部分實施例中,傳輸電極104包含在傳輸線103內。
傳輸電極106係沿著介電質波導101的第二側(例如,下側)設置。在部分實施例中,傳輸電極106沿著介電質波導101的底面設置在另一金屬互連層內,並且連接至接地端107a。
介電質波導101用以將傳輸信號S1傳輸至接收器耦合元件109。介電質波導101設置在層間介電(Inter-Level Dielectric,ILD)材料內,且介電質波導101包含具有比周圍的ILD材料的介電常數(或介電質常數)大之介電常數的介電材料。
在部分實施例中,接收器耦合元件109包含設置在介電質波導101的相對側上的一對金屬結構,例如包含微帶線。舉例而言,接收器耦合元件109包含位於介電質波導101的相對側上的接收電極108和110。在部分實施例中,接收電極108和110係相對於介電質波導101為對稱。在部分實施例中,接收電極108和110的形狀和/或圖案為鏡像圖像。
接收電極108係沿著介電質波導101的第一側(例如,上側)放置。在部分實施例中,接收電極108沿著介電質波導101的頂面設置於其中設置有傳輸電極104的金
屬互連層內,並且用以接收來自介電質波導101的信號S1',該信號S1’等效於傳輸信號S1。接收電極108通過傳輸線111連接至接收器電路112。傳輸線111對接收信號S1'從接收電極108提供寬頻寬傳輸至接收器電路112。
接收電極110係沿著介電質波導101的第二側(例如,下側)放置。在部分實施例中,接收電極110沿著介電質波導101的底面設置於其中設置有傳輸電極106的金屬互連層內,並且連接至接地端107b。
第一對金屬結構以間隔S與第二對金屬結構橫向分離,從而使得上部傳輸電極104和接收電極108以及下部傳輸電極106和接收電極110沿著介電質波導101的長度方向上是非連續的。在部分實施例中,間隔S為數微米至數十毫米的數量級。
在部分實施例中,接收器電路112用以接收接收信號S1',並且在輸出節點1121處輸出輸出信號SOUT。接收信號S1'係自接收器耦合元件109通過傳輸線111傳輸。
具有較大介電常數的介電質波導101使得引入介電質波導101內的電磁輻射通過全內反射而限制在介電質波導101內,從而使得電磁輻射從驅動器電路102導向至接收器電路112。在部分實施例中,介電質波導101包含氮化矽(SiN)或碳化矽(SiC)。在部分實施例中,介電質波導101包含室溫(如,25℃)液相高K聚合物,例如,包含聚醯亞胺(Polyimide,PI)、聚苯並惡唑(polybenzoxazole,PBO)等。在其他部分實施例中,
介電質波導101包含室溫或低溫(如,250℃以下)液相SiO2或旋塗玻璃(Spin-On Glass,SOG),其介電常數大於或等於大約4。在其他部分實施例中,介電質波導101包含液相SiNx或其他高K電介質。在其他部分實施例中,介電質波導101包含低溫(如,180℃)化學氣相沉積(例如,包含常壓化學氣相沉積(Atmospheric Pressure Chemical Vapor Deposition,APCVD)、次常壓化學氣相沉積(Sub-Atmospheric Chemical Vapor Deposition,SACVD)、電漿促進化學氣相沉積(Plasma-Enhanced Chemical Vapor Deposition,PECVD)、有機金屬化學氣相沉積(Metalorganic Chemical Vapor Deposition,MOCVD)等)的SiO2(CVD-SiO2)、SiNx或SiOxNy沉積。在其他部分實施例中,介電質波導101包含低溫(如,210℃)高K電介質沉積,例如,包含ZrO2-Al2O3-ZrO2(ZAZ),或其他高K電介質沉積,例如,包含ZrO2、Al2O3、HfOx、HfSiOx、ZrTiOx、TiO2、TaOx等。在其他部分實施例中,介電質波導101包含混合原子層沉積的SrO(ALD-SrO)和化學氣相沉積的RuO2(CVD-RuO2)。例如,在其他部分實施例中,介電質波導101包含SrTiO3(STO)介電層。
以上所述材料僅是為了說明方便起見所給出的示例。各種材料的介電質波導101都在本揭示內容所考慮的範圍內。
在部分實施例中,ILD材料包含二氧化矽
(SiO2)。在其他部分實施例中,ILD材料包含低K介電材料,例如包含摻雜氟的二氧化矽、摻雜碳的二氧化矽、多孔二氧化矽或其他類似的材料。
第2圖是根據本揭示內容的部分實施例所繪示的半導體結構100的側視圖。在部分實施例中,介電質波導101包含具有沿著方向216遞減的寬度w之一個或多個錐形端。換言之,寬度從第一寬度沿著過渡區域之長的方向218減小至較窄的第二寬度。舉例而言,介電質波導101包含第一錐形端和第二錐形端,第一錐形端具有隨著過渡區域212而減小的寬度,並且第二錐形端具有隨著過渡區域214而減小的寬度。
介電質波導101的錐形端用以藉由減小傳輸電極104和/或接收電極108與介電質波導101之間的輻射的反射來提高傳輸效率,其中,電磁輻射透過介電質波導101的錐形端,在傳輸電極104和/或接收電極108與介電質波導101之間耦合。舉例而言,錐形過渡區域改變電磁輻射與介電質波導的側壁相互作用的角度。由於全內反射為電磁輻射入射於表面上之角度的函數,因此傳輸電極104和/或接收電極108與介電質波導101之間的電磁輻射的耦合相應地增加。
第3圖是根據本揭示內容的部分實施例的第2圖中所示的半導體結構的頂視圖。第3圖所繪示的半導體結構100包含用以平行傳播電磁輻射的集成介電質波導101a~101c。
在部分實施例中,半導體結構100包含設置在驅動器電路102與接收器電路112之間的介電質波導101a~101c。在部分實施例中,介電質波導101a~101c空間上彼此平行佈置。在部分實施例中,介電質波導101a~101c彼此鄰接。在其他部分實施例中,介電質波導101a~101c彼此空間分離。
驅動器電路102包含用以分別生成電信號之彼此分離的驅動器元件102a~102c。電信號平行地提供至傳輸電極104a~104c,傳輸電極104a~104c將電信號作為電磁輻射耦合至平行傳播信號的介電質波導101a~101c內。由於電信號平行傳輸,所以藉由每一個介電質波導101a~101c傳播更小幅度的信號,進而進一步減小了傳輸電極104a~104c與介電質波導101a~101c之間的損失。換言之,由驅動器元件102a~102c輸出並且由接收器元件112a~112c接收的更小幅度的信號使得傳輸耦合元件105和接收器耦合元件109具有更少的損失。
如第3圖所繪示,在部分實施例中,傳輸電極104a~104c和/或電極108a~108c亦具有或選擇性地具有錐形寬度,以進一步增加傳輸耦合元件105和/或接收器耦合元件109與介電質波導101之間的耦合效率。在這些實施例中,傳輸電極104a~104c和電極108a~108c具有隨著過渡區域312和314減小的寬度。在部分實施例中,傳輸電極104a~104c和電極108a~108c的錐形寬度的長度可以不同。換言之,與介電質波導101的錐形寬度相比,傳輸電
極104a~104c和/或電極108a~108c具有不同尺寸的過渡區域。
第4圖是根據本揭示內容部分實施例的形成包含第1A圖中所示的半導體結構100的整合扇出型(Integrated Fan-Out,InFO)封裝的方法400的流程圖。為了更好地理解本揭示內容,方法400將參考第1圖至第3圖所示的半導體結構100進行討論,但並非用以限制本案。
舉例而言,第1圖至第3圖中的半導體結構100的製造程序將配合方法400以及第5圖~第24圖一起描述。第5圖~第24圖是根據本揭示內容部分實施例所繪示的在製造程序的不同階段中,包含第1A圖中所示的半導體結構的整合扇出型(InFO)封裝500的截面圖。儘管第5圖~第24圖係與方法400配合進行描述,但當理解第5圖~第24圖中公開的結構並不限於方法400。在其他部分實施例中,整合扇出型(InFO)封裝500包含如第2圖~第3圖所示的半導體結構。
雖然本文將所公開的方法示出和描述為一系列的步驟或事件,但是應當理解,所示出的這些步驟或事件的順序不應解釋為限制意義。例如,部分步驟可以以不同順序發生和/或與除了本文所示和/或所描述之步驟或事件以外的其他步驟或事件同時發生。另外,實施本文所描述的一個或多個態樣或實施例時,並非所有於此示出的步驟皆為必需。此外,本文中的一個或多個步驟亦可能在一個或多個分離的步驟和/或階段中執行。
請參考第4圖的方法400,在操作410中,如第5圖所示,提供載體601、黏合層602和聚合物基層603。
在部分實施例中,載體601包含玻璃、陶瓷或其他合適的材料以在器件封裝中形成各個部件期間提供結構支撐。在部分實施例中,在載體601上方設置黏合層602(例如,包含膠層、光熱轉換(light-to-heat conversion,LTHC)塗層、紫外(UV)膜等)。通過黏合層602將聚合物基層603塗覆在載體601上。在部分實施例中,聚合物基層603由聚苯並惡唑(PolyBenzOxazole,PBO)、味之素積層膜(Ajinomoto Buildup Film,ABF)、聚醯亞胺(Polyimide)、苯並環丁烯(BenzoCycloButene,BCB)、阻焊(Solder Resist,SR)膜、晶片附著膜(Die-Attach Film,DAF)等形成,但是本揭示內容不限於此。
請參考第4圖的方法400,在操作S420中,如第6圖所示,隨後,形成背側重分佈層(RDL)604。在部分實施例中,背側RDL 604包含形成在一個或多個聚合物層中的導電部件6041,例如,包含導線和/或通孔。在部分實施例中,聚合物層可以使用例如包含旋塗技術、濺射等任意合適的方法由任意合適的材料(例如,包含PI、PBO、BCB、環氧樹脂(epoxy)、矽樹脂(silicone)、丙烯酸酯(acrylates)、奈米填充酚樹脂(nano-filled pheno resin)、矽氧烷(siloxane)、含氟聚合物(a fluorinated polymer)、聚降冰片烯(polynorbornene)等)形成。
在部分實施例中,導電部件6041形成在聚合物
層中。這種導電部件6041的形成包含圖案化聚合物層(例如,使用光刻和蝕刻程序的組合)以及在圖案化的聚合物層中形成導電部件6041(例如,沉積晶種層和使用掩模層以限定導電部件6041的形狀)。設計導電部件6041以形成功能電路和用於隨後附著的晶片的輸入/輸出部件。
接下來,在操作S430中,如第7圖所示,在背側RDL 604和載體601上方形成圖案化的光阻層605。在部分實施例中,例如,光阻層605被沉積作為背側RDL 604上方的毯覆層。接下來,使用光掩模(未繪示)來曝光光阻層605的各部分,根據使用的是負性還是正性抗蝕劑來去除光阻層605中曝光或未曝光的部分。所得到的圖案化的光阻層605包含設置在載體601的週邊區域處的開口606。在部分實施例中,開口606還暴露背側RDL 604中的導電部件6041。
接下來,在操作S440中,如第8圖所示,沉積晶種層607在圖案化的光阻層605上。
接下來,在操作S450中,如第9圖所示,用導電材料608(例如,包含銅、銀、金等)填充開口606,以形成導電通孔。在部分實施例中,在鍍敷程序(例如,包含電化學鍍、化學鍍等)期間,開口606鍍敷有導電材料608。在部分實施例中,導電材料608過填充開口606,並且執行研磨和化學機械拋光(Chemical-Mechanical Planarization,CMP)程序來去除導電材料608的位於光阻層605上方的多餘部分。
接下來,在操作S460中,如第11圖所示,去除光阻層605。在部分實施例中,使用電漿灰化或濕剝離程序來去除光阻層605。在部分實施例中,在電漿灰化程序之後是在硫酸(H2SO4)中的濕浸以清洗封裝500並且去除剩餘的光阻層材料。
因此,在背側RDL 604上方形成導電通孔609。選擇性地,在部分實施例中,例如,利用導電間柱或包含銅、金或銀引線的導電引線來替換導電通孔609。在部分實施例中,導電通孔609通過開口610彼此間隔開,並且鄰近的導電通孔609之間的至少一個開口610足夠大以在其中設置一個或多個半導體晶片。
接下來,在操作S470中,如第12圖所示,驅動器晶片611A和接收器晶片611B安裝並且附著至封裝500。舉例而言,如圖所示,器件封裝500包含載體601以及具有導電部件6041的背側RDL604。在部分實施例中,例如,還包含其他互連結構,例如包含電性連接至背側RDL 604中的導電部件6041的導電通孔609。在部分實施例中,黏合層用於將驅動器晶片611A和接收器晶片611B固定至背側RDL 604。
接下來,在操作S480中,如第13圖所示,在開口610中將驅動器晶片611A和接收器晶片611B安裝至背側RDL 604之後,形成模封材料612在封裝500中。
模封材料612被分配以填充驅動器晶片611A與導電通孔609之間的間隙、鄰近的導電通孔609之間的間
隙以及接收器晶片611B與導電通孔609之間的間隙。在部分實施例中,模封材料612可以包含諸如環氧樹脂、成形底部填充物等的任何合適的材料。在部分實施例中,壓縮成形、轉移成形和液態密封成形是用於形成模封材料612的合適的方法,但是本揭示內容不限於此。舉例來說,模封材料612可為液態形式分配在驅動器晶片611A、接收器晶片611B與導電通孔609之間。隨後,執行固化程序以凝固模封材料612。在部分實施例中,模封材料612的填充溢出驅動器晶片611A、接收器晶片611B和導電通孔609,從而使得模封材料612覆蓋驅動器晶片611A、接收器晶片611B和導電通孔609的頂面。
接下來,在操作S490中,如第14圖所示,執行研磨和化學機械拋光(CMP)程序以去除模封材料612的多餘部分,並且回磨模封材料612以減小其總厚度並暴露導電通孔609。
因為所得結構包含延伸穿過模封材料612的導電通孔609,所以導電通孔609還稱為直通模封穿孔(through molding via)、內部直通穿孔(through inter via,TIV)等。在封裝500中,導電通孔609提供至背側RDL 604的電性連接。在部分實施例中,用於暴露導電通孔609的減薄程序還用於暴露導電柱6111A和導電柱6111B。
接下來,在操作S500中,如第15圖所示,在模封材料612上形成具有開口的圖案化的聚合物層613。
在部分實施例中,聚合物層613包含PI、PBO、
BCB、環氧樹脂(epoxy)、矽樹脂(silicone)、丙烯酸酯(acrylates)、奈米填充酚樹脂(nano-filled pheno resin)、矽氧烷(siloxane)、含氟聚合物(a fluorinated polymer)、聚降冰片烯(polynorbornene)等。在部分實施例中,聚合物層613選擇性地暴露於用以蝕刻聚合物層613以形成開口的蝕刻劑,例如,包含CF4、CHF3、C4F8、HF等。如圖所繪示,這些開口暴露導電柱6111A和6111B以及導電通孔609。在部分實施例中,這些開口包含一個或多個通孔和上面的金屬引線溝槽。通孔從聚合物層613的底面垂直延伸至金屬溝槽的底面,金屬溝槽延伸至聚合物層613的頂面。
在部分實施例中,如圖所繪示,開口填充有導電材料。例如,晶種層(未示出)形成在開口中,並且使用電化學鍍程序、化學鍍程序等將導電材料鍍敷在開口中。如圖所繪示,所得到的位於聚合物層613中的通孔電性連接至導電柱6111A、導電柱6111B或導電通孔609,並且下部傳輸電極106和下部接收電極110形成在聚合物層613內。在部分實施例中,圖案化聚合物層613以形成開口,並且金屬材料形成在開口內以形成下部傳輸電極106和下部接收電極110。在部分實施例中,傳輸電極106通過聚合物層613的方式與接收電極110橫向分離。下部傳輸電極106和下部接收電極110分別通過導電通孔609和背側RDL 604電性連接至地。在部分實施例中,例如,通過沉積程序的方式沉積包含銅的導電材料,隨後進行鍍敷程序和CMP程序,其程
序如先前段落所述,為簡潔起見於此不再贅述。
接下來,在操作S510中,如第16圖所示,在聚合物層613上形成波導介電材料614。在部分實施例中,波導介電材料614包含比周圍的聚合物層(例如,包含聚合物層613和616(如第21圖所示))更高的介電常數。在部分實施例中,例如,通過包含物理氣相沈積法(Physical Vapor Deposition,PVD)、CVD或PECVD的氣相沉積技術的方式將波導介電材料614形成至覆蓋聚合物層613的厚度。在部分實施例中,使用研磨和化學機械拋光(CMP)程序以除去波導介電材料614的多餘部分。
在部分實施例中,波導介電材料614包含室溫(如,25℃)液相高K聚合物,例如,包含PBO、PI等。在其他部分實施例中,波導介電材料614包含室溫或低溫(如,250℃以下)液相SiO2或旋塗玻璃(SOG),其介電常數大於或等於大約4。在其他部分實施例中,波導介電材料614包含液相SiNx或其他高K電介質。在其他部分實施例中,波導介電材料614包含低溫(如,180℃)化學氣相沉積(例如,包含常壓化學氣相沉積(APCVD)、次常壓化學氣相沉積(SACVD)、電漿促進化學氣相沉積(PECVD)、有機金屬化學氣相沉積(MOCVD)等)的SiO2(CVD-SiO2)、SiNx或SiOxNy沉積。在其他部分實施例中,波導介電材料614包含:低溫(如,210℃)高K電介質沉積,例如,包含ZrO2-Al2O3-ZrO2(ZAZ);或其他高K電介質沉積,例如,包含ZrO2、Al2O3、HfOx、
HfSiOx、ZrTiOx、TiO2、TaOx等。在其他部分實施例中,波導介電材料614包含混合原子層沉積的SrO(ALD-SrO)和化學氣相沉積的RuO2(CVD-RuO2)。例如,在其他部分實施例中,波導介電材料614包含SrTiO3(STO)介電層。
以上所述材料僅是為了說明方便起見所給出的示例。各種材料的波導介電材料614都在本揭示內容所考慮的範圍內。
接下來,在沉積之後,使用光刻和/或蝕刻程序來圖案化波導介電材料614以形成介電質波導101。舉例而言,在操作S520中,在波導介電材料614上方形成圖案化的光阻層605b。
接下來,使用光掩模(未示出)來曝光光阻層605b的各部分。然後,根據使用的是負性還是正性抗蝕劑來去除光阻層605b中曝光或未曝光的部分。如第17圖所示,所得到的圖案化的光阻層605b包含設置在傳輸電極106與接收電極110之間的部分。
接下來,在操作S530中,如第18圖所示,執行蝕刻程序以去除波導介電材料614的暴露部分。在部分實施例中,蝕刻程序包含反應離子蝕刻(RIE),但是本揭示內容不限於此。
接下來,在操作S540中,如第19圖所示,去除光阻層605b。在部分實施例中,使用電漿灰化或濕剝離程序來去除光阻層605b。在部分實施例中,在電漿灰化程序之後是在硫酸(H2SO4)中的濕浸以清洗封裝500並且去除
剩餘的光阻層材料。
接下來,在操作S550中,如第20圖所示,在聚合物層613上形成具有開口的圖案化的聚合物層615。在部分實施例中,聚合物層615包含PI、PBO、BCB、環氧樹脂(epoxy)、矽樹脂(silicone)、丙烯酸酯(acrylates)、奈米填充酚樹脂(nano-filled pheno resin)、矽氧烷(siloxane)、含氟聚合物(a fluorinated polymer)、聚降冰片烯(polynorbornene)等。在部分實施例中,聚合物層615選擇性地暴露於用以蝕刻聚合物層615以形成開口的蝕刻劑,例如,包含CF4、CHF3、C4F8、HF等。在部分實施例中,開口包含一個或多個通孔和上面的金屬引線溝槽。通孔從聚合物層615的底面垂直延伸至金屬溝槽的底面,金屬溝槽延伸至聚合物層615的頂面。
在部分實施例中,開口係由導電材料所填充。舉例而言,例如,晶種層(未示出)形成在開口中,並且使用電化學鍍程序、化學鍍程序等將導電材料鍍敷在開口中。如圖所繪示,所得到的位於聚合物層615中的通孔電性連接至導電柱6111A、導電柱6111B或導電通孔609。在部分實施例中,舉例來說,藉由沉積程序的方式沉積包含銅的導電材料,隨後進行鍍敷程序和CMP程序,其程序如先前段落所述,為簡潔起見於此不再贅述。
在部分實施例中,如第21圖所示,在聚合物層615上方形成具有導電部件的一個或多個附加的聚合物層616。在操作S560中,在聚合物層616中形成具有導電部件
的RDL。在部分實施例中,RDL包含設置在各個聚合物層之間的導電部件。如圖所繪示,在聚合物層616內形成上部傳輸電極104和上部接收電極108。在部分實施例中,圖案化聚合物層616以形成開口,並且金屬材料形成在開口內以形成上部傳輸電極104和上部接收電極108。在部分實施例中,傳輸電極104通過聚合物層616的方式與接收電極108橫向分離。
如圖所繪示,在部分實施例中,驅動器晶片611A和接收器晶片611B分別通過RDL中的導電部件電性連接至上部傳輸電極104和上部接收電極108。驅動器晶片611A通過導電柱6111A和導電通孔電性連接至上部傳輸電極104。接收器晶片611B通過導電柱6111B和導電通孔電性連接至上部接收電極108。在部分實施例中,形成在聚合物層中的RDL與背側RDL 604在組成和形成程序上基本類似,為簡潔起見於此不再贅述。
接下來,在操作S570中,如第22圖所示,形成球下金屬部(under bump metallization,UBM)618以通過聚合物層616中的RDL電性連接至下部傳輸電極106和下部接收電極110,並且在聚合物層616上方形成聚合物層617。如第23圖所示,然後形成用以輸入/輸出(I/O)焊盤的外部連接件619A和619B,例如,包含位於球下金屬部(UBM)618上的焊料球。在部分實施例中,連接件619A和619B是設置在UBM 618上的球柵陣列(ball grid array,BGA)球、可控坍塌晶片連接件(controlled
collapse chip connector,C4)凸塊等,其中UBM 618形成在RDL上方。在部分實施例中,連接件619A和619B用於將封裝500電性連接至諸如包含另一裝置晶片、中介層、封裝襯底、印刷電路板、主機板等其他封裝組件。在部分實施例中,連接件619A耦合至傳輸器接地端,並且連接件619B耦合至接收器接地端。因此,下部傳輸電極106通過導電通孔、背側RDL 604和聚合物層616以及連接件619A耦合至傳輸器接地端。下部接收電極110通過導電通孔、背側RDL 604和聚合物層616以及連接件619B耦合至接收器接地端。
接下來,從封裝500去除載體601和黏合層602。最後所得到的結構繪示於第24圖。在部分實施例中,聚合物基層603可保留在所得之封裝500中以作為絕緣和保護層。
以上步驟包含示例性操作,但是並非限定以所示出的順序循序執行該些操作。根據本揭示內容中各個實施例的精神和範圍,可以視情況添加、替換、重排和/或刪除部分操作。
在部分實施例中,一種半導體結構於此公開。半導體結構包含:介電質波導,垂直設置在第一層與第二層之間;驅動器晶片,用以在第一輸出節點處生成驅動信號;第一傳輸電極,沿著介電質波導的第一側放置並且用以接收來自第一輸出節點的驅動信號;第一接收電極,沿著介電質波導的第一側放置;以及接收器晶片,用以接收從第一接收
電極接收的信號。
此外,一種半導體結構於此公開。半導體結構包含:介電質波導,設置在第一介電材料與第二介電材料之間並且具有基本為矩形的介面;第一金屬層,沿著介電質波導的第一側設置;以及第二金屬層,沿著介電質波導的第二側設置。第二介電材料設置在模封層上,並且模封層圍繞驅動器晶片和接收器晶片。
此外,一種方法於此公開,方法包含:將驅動器晶片和接收器晶片附著在封裝中;應用模封材料以圍繞驅動器晶片和接收器晶片;在驅動器晶片和接收器晶片以及模封材料上方形成第一層;在第一層上形成介電質波導;以及在介電質波導上形成第二層。
雖然本揭示內容已以實施方式揭露如上,以使得本領域的技術人員可以更好地理解本揭示內容的各種態樣。本領域技術人員應該理解本揭示內容可用以作為基礎來設計或修飾其他步驟和結構以達到與本揭示內容所介紹實施例相同的目的和/或實現相同優點。本領域技術人員亦當理解,等效的結構並不脫離本揭示內容的精神和範圍,任何熟習此技藝者,在不脫離本揭示內容之精神和範圍內,當可作各種更動與潤飾,因此本揭示內容之保護範圍當視後附之申請專利範圍所界定者為準。
400:方法
S410~S570:步驟
Claims (10)
- 一種半導體結構,包含:一介電質波導,垂直設置在一第一層與一第二層之間;一驅動器晶片,用以在一第一輸出節點處生成一驅動信號;一第一傳輸電極,沿著該介電質波導的一第一側配置並用以接收來自該第一輸出節點的該驅動信號;一第一接收電極,沿著該介電質波導的該第一側配置;一第二接收電極,沿著該介電質波導的一第二側配置並電性耦接於一接收接地,其中該第一接收電極和該第二接收電極為鏡像圖像;以及一接收器晶片,用以自該第一接收電極接收一接收信號。
- 如請求項1所述的半導體結構,更包含:一模封材料,圍繞位於一保護層上的該驅動器晶片以及該接收器晶片,其中該第一層配置在該模封材料上;以及一第二傳輸電極,沿著該介電質波導的該第二側配置並電性耦接於一傳輸接地;其中該第一傳輸電極包含配置於該介電質波導以上的一第一金屬結構,以及該第二傳輸電極包含配置於該介電質波導以下的一第二金屬結構;其中該第一傳輸電極與該第二傳輸電極為鏡像圖像。
- 如請求項1所述的半導體結構,其中該第一接收電極包含配置於該介電質波導以上的一第一金屬結構,以及該第二接收電極包含配置於該介電質波導以下的一第二金屬結構。
- 如請求項1所述的半導體結構,其中該介電質波導包含一介電質材料,該介電質材料具有高於該第一層與該第二層之介電常數的一介電常數;其中該介電質波導包含聚醯亞胺(polyimide)、聚苯並噁唑(polybenzoxazole)、氮化矽、二氧化矽、一鈦酸鍶介電質、一氧化鋯增韌氧化鋁(ZrO2-Al2O3-ZrO2)合成介電質結構或二氧化鋯(ZrO2)、氧化鋁(Al2O3)、二氧化鉿(HfOx)、矽氧化鉿(HfSiOx)、鋯鈦氧(ZrTiOx)、二氧化鈦(TiO2)以及氧化鉭(TaOx)中的至少一者。
- 一種半導體結構,包含:一介電質波導,設置在一第一介電材料與一第二介電材料之間並且具有基本為一矩形的截面;一第一金屬層,沿著該介電質波導的一第一側設置;以及一第二金屬層,沿著該介電質波導的一第二側設置,其中該第二介電材料設置在一模封層上,並且該模封層圍繞一驅動器晶片和一接收器晶片;其中一第一接收電極配置於該第一金屬層中並耦接於該接收器晶片,一第二接收電極配置於該第二金屬層中並 耦接於一接收器接地,以及該第一接收電極與該第二接收電極為鏡像圖案。
- 如請求項5所述的半導體結構,其中一第一傳輸電極配置於該第一金屬層中,該第一傳輸電極耦接該驅動器晶片,以及一第二傳輸電極配置於該第二金屬層中,以及該第二傳輸電極耦接一傳輸接地;其中該介電質波導的一寬度在位於該第一傳輸電極之下的一過渡區域中由一第一寬度漸縮至一第二寬度,以及該第二寬度比該第一寬度窄。
- 如請求項6所述的半導體結構,更包含:複數個第一多個傳輸電極,配置於在該介電質波導上的該第一金屬層中,並耦接至該驅動器晶片的複數個輸出節點;以及複數個第二多個傳輸電極,配置於在該介電質波導下的該第二金屬層中,並耦接至一傳輸接地。
- 一種製造半導體結構的方法,包含:將一驅動器晶片和一接收器晶片附著在一封裝中;應用一模封材料以圍繞該驅動器晶片和該接收器晶片;在該驅動器晶片、該接收器晶片以及該模封材料上方形成一第一層; 在該第一層上形成該介電質波導;在該介電質波導上形成一第二層;以及形成分別沿著該介電質波導的一第一側與一第二側配置的一第一接收電極與一第二接收電極;其中該第一接收電極是被形成以耦接該接收器晶片,以及該第二接收電極是被形成以耦接一接收器接地;其中該第一接收器電極與該第二接收器電極是鏡像圖像。
- 如請求項8所述的製造半導體結構方法,更包含:形成沿該介電質波導的該第一側配置的一第一傳輸電極;形成沿該介電質波導的該第二側配置的一第二傳輸電極,該第二傳輸電極電性耦接一傳輸接地;其中該驅動器晶片包含用以提供一傳輸訊號至該第一傳輸電極的一輸出節點;其中該接收器晶片用以接收來自該第一接收電極的一經接收訊號。
- 如請求項8所述的製造半導體結構方法,更包含:圖案化該第一層以形成複數個第一多個開口;形成在該些第一多個開口內的一第一金屬材料以形成該第二傳輸電極以及該第二接收電極; 圖案化在該第一層以上的一波導層以形成一介電質波導開口;形成在該介電質波導開口內的一波導介電材料以形成該介電質波導;圖案化在該波導層以上的該第二層以形成複數個第二多個開口;以及形成在該些第二多個開口中的一第二金屬材料以形成該第一傳輸電極以及該第一接收電極。
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