TWI689925B - Single-ended undisturbed sram - Google Patents

Single-ended undisturbed sram Download PDF

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TWI689925B
TWI689925B TW107139267A TW107139267A TWI689925B TW I689925 B TWI689925 B TW I689925B TW 107139267 A TW107139267 A TW 107139267A TW 107139267 A TW107139267 A TW 107139267A TW I689925 B TWI689925 B TW I689925B
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transistor
storage node
electrically connected
write
leakage current
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TW202018713A (en
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王朝欽
侯宗佑
蔡修群
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國立中山大學
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Abstract

A single-ended undisturbed SRAM unit includes a plurality of SRAM units and a data read/write unit electrically connected with the SRAM units. Each SRAM unit comprises a transistor pair, a writing transistor, a transmission transistor, an anti-disturbance transistor and a leakage current transistor. The transistor pair electrically connected to a storage node and an inverse storage node. The writing transistor electrically connected to the storage node, the anti-disturbance transistor electrically connected to the writing transistor and the transmission transistor, and the leakage current transistor electrically connected to the storage node and a ground. Wherein, the leakage current transistor is controlled by a potential of the inverse storage node for turning on/off the electrically connection between the storage node and the ground to provide a discharge path when the leakage current transistor is on.

Description

單端讀寫無擾動式靜態隨機存取記憶體 Single-end read-write disturbance-free static random access memory

本發明是關於一種靜態隨機存取記憶體，特別是關於一種單端讀寫無擾動式靜態隨機存取記憶體。 The invention relates to a static random access memory, in particular to a single-end read-write disturbance-free static random access memory.

請參閱台灣專利申請號：106119379「單端無載式靜態隨機存取記憶體」，其揭露該SRAM單元具有一放電電晶體，且該放電電晶體電性連接SRAM單元之傳輸電晶體及防擾動電晶體，其中，當儲存節點儲存資料1，也就是儲存節點之電位為高電位時，反儲存節點為低電位，此時該放電電晶體導通，使得SRAM單元的漏電流可經由放電電晶體釋放，以避免漏電流累積於反儲存節點而影響甚至反轉該反儲存節點的電位。但在此架構下，若儲存節點儲存資料0時電位為低電位，而反儲存節點為高電位，在讀取模式下，由於寫入輔助迴圈為高電位，導致漏電流的電荷可能累積於儲存節點上，使得儲存節點的電位產生變化。 Please refer to Taiwan Patent Application No. 106119379 "Single-Ended Unloaded Static Random Access Memory", which discloses that the SRAM cell has a discharge transistor, and the discharge transistor is electrically connected to the transmission transistor of the SRAM cell and anti-disturbance Transistor, wherein when the storage node stores data 1, that is, the potential of the storage node is high, the anti-storage node is low, and the discharge transistor is turned on so that the leakage current of the SRAM cell can be discharged through the discharge transistor In order to avoid the accumulation of leakage current in the anti-storage node and affect or even reverse the potential of the anti-storage node. However, in this architecture, if the storage node stores data 0 when the potential is low and the anti-storage node is high, in the read mode, due to the high potential of the write auxiliary loop, the charge of the leakage current may accumulate in The storage node changes the potential of the storage node.

本發明的主要目的在於藉由漏電流電晶體電性連接儲存節點，使得儲存節點儲存資料0時能以漏電流電晶體提供一接地路徑，以避免漏電流電荷的累積。 The main purpose of the present invention is to electrically connect the storage node through the leakage current transistor, so that the storage node can provide a ground path with the leakage current transistor when storing data 0, so as to avoid the accumulation of leakage current charge.

本發明之一種靜態隨機存取記憶體包含複數個SRAM單元及一資料讀寫單元，各該SRAM單元具有一電晶體對、一寫入電晶體、一傳輸電晶體、一防擾動電晶體及一漏電流電晶體，該電晶體對電性連接一儲存節點及一反儲存節點，該寫入電晶體電性連接該儲存節點，該傳輸電晶體電性連接該反儲存節點，該防擾動電晶體電性連接該寫入電晶體及該傳輸電晶體，該漏電流電晶體電性連接該儲存節點及一接地端，其中該漏電流電晶體受該反儲存節點之一電位控制，以選擇性地導通或截止該儲存節點及該接地端之間的電性連接，該資料讀寫單元電性連接該防擾動電晶體。 A static random access memory of the present invention includes a plurality of SRAM cells and a data reading and writing unit, each of the SRAM cells has a transistor pair, a write transistor, a transmission transistor, an anti-disturbance transistor and a A leakage current transistor, the transistor pair is electrically connected to a storage node and an inverse storage node, the write transistor is electrically connected to the storage node, the transmission transistor is electrically connected to the anti-storage node, and the anti-disturbance transistor The write transistor and the transmission transistor are electrically connected, and the leakage current transistor is electrically connected to the storage node and a ground terminal, wherein the leakage current transistor is controlled by a potential of the anti-storage node to selectively The electrical connection between the storage node and the ground terminal is turned on or off, and the data reading and writing unit is electrically connected to the anti-disturbance transistor.

本發明藉由該漏電流電晶體提供該儲存節點一放電路徑，而可避免漏電流之電荷累積於該儲存節點，以減少整體之該靜態隨機存取記憶體可能發生資料轉態的錯誤。The present invention provides the storage node with a discharge path through the leakage current transistor, which can avoid the accumulation of the charge of the leakage current in the storage node, so as to reduce the data transition error that may occur in the entire static random access memory.

請參閱第1圖，一種靜態隨機存取記憶體100具有複數個SRAM單元110及一資料讀寫單元120，該資料讀寫單元120電性連接該些SRAM單元110。 Please refer to FIG. 1, a static random access memory 100 has a plurality of SRAM cells 110 and a data read-write unit 120. The data read-write unit 120 is electrically connected to the SRAM cells 110.

在本實施例中，各該SRAM單元110具有一電晶體對111、一寫入電 晶體112、一傳輸電晶體113、一防擾動電晶體114及一漏電流電晶體115，該資料讀寫單元120具有一位元線BL、一反位元線BLB、一反向器121及一預放電電晶體122。該電晶體對111用以鎖存資料於一儲存節點Q及一反儲存節點Qb，該寫入電晶體112電性連接該儲存節點Q及該防擾動電晶體114，該傳輸電晶體113電性連接該反儲存節點Qb，該寫入電晶體112及該傳輸電晶體113用以寫入資料至該儲存節點Q及該反儲存節點Qb，且該傳輸電晶體113還另用以讀取該反儲存節點Qb儲存之資料，該防擾動電晶體114之一端電性連接該寫入電晶體112及該傳輸電晶體113，該防擾動電晶體114之另一端電性連接該資料讀取單元120之該反位元線BLB，該防擾動電晶體114用以選擇性地導通各該SRAM單元110與該資料讀取單元120的電性連接，而能以單一個該資料讀取單元120對多個該SRAM單元110進行資料讀寫，該漏電流電晶體115電性連接該儲存節點Q，以提供漏電流一放電路徑。該位元線BL經由該反向器121耦接該反位元線BLB，以由該反向器121反向該位元線BL所讀取之反向資料，並輸出與該儲存節點Q電位相同的資料，該預放電電晶體122之兩端分別電性連接該反位元線BLB及一接地端，且該預放電電晶體122受一預放電訊號Pd控制，該預放電電晶體122導通時可讓該預放電電晶體122耦接至該接地端，以將該位元線BL放電至低電位而初始化。 In this embodiment, each of the SRAM cells 110 has a transistor pair 111 and a write circuit A crystal 112, a transmission transistor 113, an anti-disturbance transistor 114, and a leakage current transistor 115, the data reading and writing unit 120 has a bit line BL, an inverted bit line BLB, an inverter 121 and a Pre-discharge transistor 122. The transistor pair 111 is used to latch data to a storage node Q and an inverse storage node Qb, the write transistor 112 is electrically connected to the storage node Q and the anti-disturbance transistor 114, and the transmission transistor 113 is electrically Connected to the inverse storage node Qb, the write transistor 112 and the transmission transistor 113 are used to write data to the storage node Q and the inverse storage node Qb, and the transmission transistor 113 is also used to read the inverse For the data stored in the storage node Qb, one end of the anti-disturbance transistor 114 is electrically connected to the write transistor 112 and the transmission transistor 113, and the other end of the anti-disturbance transistor 114 is electrically connected to the data reading unit 120 The anti-disturbance line BLB, the anti-disturbance transistor 114 is used to selectively conduct the electrical connection between each SRAM cell 110 and the data reading unit 120, and a single one of the data reading unit 120 can be used for multiple The SRAM cell 110 reads and writes data, and the leakage current transistor 115 is electrically connected to the storage node Q to provide a leakage current-discharge path. The bit line BL is coupled to the inverted bit line BLB through the inverter 121, so that the inverted data read by the bit line BL is inverted by the inverter 121, and output to the storage node Q potential With the same data, both ends of the pre-discharge transistor 122 are electrically connected to the reverse bit line BLB and a ground terminal, and the pre-discharge transistor 122 is controlled by a pre-discharge signal Pd, and the pre-discharge transistor 122 is turned on At this time, the pre-discharge transistor 122 can be coupled to the ground terminal to discharge the bit line BL to a low potential for initialization.

在本實施例中，該電晶體對111具有一第一電晶體111a及一第二電晶體111b，該第一電晶體111a之一源極電性連接一電源電壓VDD，該第一電晶體111a之一閘極電性連接該反儲存節點Qb，該第一電晶體111a之一汲極電性連接該儲存節點Q，該第二電晶體111b之一源極電性連接該電源電壓VDD，該第二電晶體111b之一閘極電性連接該儲存節點Q，該第二電晶體111b之一汲極電性連接該反儲存節點Qb，其中，該第一電晶體111a及該第二電晶體111b皆為PMOS電 晶體，因此，當該儲存節點Q為低電位時，該第二電晶體111b導通，使得該反儲存節點Qb由該電源電壓VDD提昇至高電位，相對的，當該反儲存節點Qb為低電位時，該第一電晶體111a導通，使得該儲存節點Q可由該電源電壓VDD拉高至高電位，而可相互鎖存資料。較佳的，該第一電晶體111a及該第二電晶體111b皆為高臨界電壓(High threshold voltage)之PMOS電晶體而具有較弱電流，以利於該電晶體對111鎖存資料。 In this embodiment, the transistor pair 111 has a first transistor 111a and a second transistor 111b, one source of the first transistor 111a is electrically connected to a power supply voltage VDD, and the first transistor 111a A gate is electrically connected to the anti-storage node Qb, a drain of the first transistor 111a is electrically connected to the storage node Q, and a source of the second transistor 111b is electrically connected to the power supply voltage VDD, the A gate of the second transistor 111b is electrically connected to the storage node Q, and a drain of the second transistor 111b is electrically connected to the anti-storage node Qb, wherein the first transistor 111a and the second transistor 111b are PMOS Crystal, therefore, when the storage node Q is at a low potential, the second transistor 111b is turned on, so that the anti-storage node Qb is raised from the power supply voltage VDD to a high potential, in contrast, when the anti-storage node Qb is at a low potential The first transistor 111a is turned on, so that the storage node Q can be pulled up to a high potential from the power supply voltage VDD, and data can be latched with each other. Preferably, both the first transistor 111a and the second transistor 111b are high threshold voltage (High threshold voltage) PMOS transistors and have weaker currents to facilitate the transistor 111 to latch data.

該寫入電晶體112之一汲極電性連接該儲存節點Q，該寫入電晶體112之一源極經由一寫入輔助迴圈WAL電性連接該傳輸電晶體113及該防擾動電晶體114，其中，該寫入電晶體112之閘極接收一反寫入訊號WAB，該寫入電晶體112受到該反寫入訊號WAB的控制，而導通或截止該儲存節點Q與該防寫入輔助迴圈WAL之間的電性連接。較佳的，該寫入電晶體112為一低臨界電壓(Low threshold voltage)之NMOS電晶體而具有較大電流，以提高該SRAM單元110的存取速度。 One drain of the write transistor 112 is electrically connected to the storage node Q, and one source of the write transistor 112 is electrically connected to the transmission transistor 113 and the anti-disturbance transistor through a write auxiliary loop WAL 114, wherein the gate of the write transistor 112 receives a reverse write signal WAB, the write transistor 112 is controlled by the reverse write signal WAB, and the storage node Q and the write-protection are turned on or off The electrical connection between the auxiliary loop WAL. Preferably, the write transistor 112 is a low threshold voltage (Low threshold voltage) NMOS transistor with a large current, so as to increase the access speed of the SRAM cell 110.

該傳輸電晶體113之一汲極電性連接該反儲存節點Qb，該傳輸電晶體113之一源極電性連接該寫入電晶體112之該源極，該傳輸電晶體113之一閘極接收一寫入訊號WA，該傳輸電晶體113受到該寫入訊號WA的控制，而導通或截止該反儲存節點Qb與該防擾動電晶體114之間的電性連接。較佳的，該傳輸電晶體113為一低臨界電壓之NMOS電晶體而具有較大電流，以提高該SRAM單元110的存取速度。 One drain of the transmission transistor 113 is electrically connected to the anti-storage node Qb, one source of the transmission transistor 113 is electrically connected to the source of the write transistor 112, and one gate of the transmission transistor 113 Receiving a write signal WA, the transmission transistor 113 is controlled by the write signal WA, and the electrical connection between the anti-storage node Qb and the anti-disturbance transistor 114 is turned on or off. Preferably, the transmission transistor 113 is an NMOS transistor with a low threshold voltage and has a large current, so as to increase the access speed of the SRAM cell 110.

該防擾動電晶體114之一汲極電性連接該傳輸電晶體113之該源極及該寫入電晶體112之該源極，該防擾動電晶體114之一源極電性連接該資料讀寫單元120，該防擾動電晶體114之一閘極接收一字元線訊號WL，該傳輸電晶體 113受到該字元線訊號WL的控制，而導通或截止各該SRAM單元110及該資料讀寫單元120之間的電性連接。較佳的，該防擾動電晶體114為一低臨界電壓之NMOS電晶體而具有較大電流，以提高該SRAM單元110的存取速度。 One drain of the anti-disturbance transistor 114 is electrically connected to the source of the transmission transistor 113 and the source of the write transistor 112, and one source of the anti-disturbance transistor 114 is electrically connected to the data read In the writing unit 120, one gate of the anti-disturbance transistor 114 receives a word line signal WL, and the transmission transistor 113 is controlled by the word line signal WL, and turns on or off the electrical connection between each of the SRAM cell 110 and the data read-write unit 120. Preferably, the anti-disturbance transistor 114 is an NMOS transistor with a low threshold voltage and has a large current, so as to increase the access speed of the SRAM cell 110.

該漏電流電晶體115之一汲極電性連接該儲存節點Q，該漏電流電晶體115之一源極電性連接該接地端，該漏電流電晶體115之一閘極電性連接該反儲存節點Qb，使得該漏電流電晶體115受該反儲存節點Qb之一電位控制，以選擇性地導通或截止該儲存節點Q及該接地端之間的電性連接，其中，當該漏電流電晶體115導通時，該儲存節點Q經由該漏電流電晶體115電性連接之該接地端，而可經由該漏電流電晶體115釋放可能累積於該儲存節點Q的電荷，避免該儲存節點Q因漏電流之電荷累積而反轉其電位。若該儲存節點Q為高電位時，雖然該漏電流電晶體115截止，但亦可能產生漏電流而導致該儲存節點Q的電荷釋放，較佳的，該漏電流電晶體115為一高臨界電壓之NMOS電晶體而具有較弱電流，以避免該儲存節點Q之電荷由該漏電流電晶體115釋放。 A drain of the leakage current transistor 115 is electrically connected to the storage node Q, a source of the leakage current transistor 115 is electrically connected to the ground terminal, and a gate of the leakage current transistor 115 is electrically connected to the reverse The storage node Qb, so that the leakage current transistor 115 is controlled by a potential of the reverse storage node Qb to selectively turn on or off the electrical connection between the storage node Q and the ground terminal, wherein, when the leakage current When the transistor 115 is turned on, the storage node Q is electrically connected to the ground through the leakage current transistor 115, and the charge that may accumulate in the storage node Q can be released through the leakage current transistor 115 to avoid the storage node Q The electric potential of the leakage current reverses its potential. If the storage node Q is at a high potential, although the leakage current transistor 115 is turned off, a leakage current may be generated and the charge of the storage node Q may be discharged. Preferably, the leakage current transistor 115 is a high threshold voltage The NMOS transistor has a weak current to prevent the charge of the storage node Q from being discharged by the leakage current transistor 115.

請參閱第2圖，其為該靜態隨機存取記憶體100之各該SRAM單元110儲入資料的時序圖，其中，在寫入資料0時，該預放電訊號Pd為高電位而導通該預放電電晶體122，該字元線訊號WL及該反寫入訊號WAB皆為高電位而導通該防擾動電晶體114及該寫入電晶體112，該寫入訊號WA則為低電位而截止該傳輸電晶體113。此時，該儲存節點Q經由該寫入電晶體112、該防擾動電晶體114及該預放電電晶體122耦接至該接地端而降至低電位，以將資料0儲存於該儲存節點Q中，且該第二電晶體111b導通而將反儲存節點Qb拉高至高電位，此外，由於該傳輸電晶體113為截止，可避免該反儲存節點Qb的電荷釋放。 Please refer to FIG. 2, which is a timing diagram of data stored in each of the SRAM cells 110 of the static random access memory 100. When writing data 0, the pre-discharge signal Pd is at a high potential to turn on the pre-discharge The discharge transistor 122, the word line signal WL and the reverse write signal WAB are all at a high potential to turn on the anti-disturbance transistor 114 and the write transistor 112, and the write signal WA is at a low potential to turn off the Transmission transistor 113. At this time, the storage node Q is coupled to the ground through the write transistor 112, the anti-disturbance transistor 114, and the pre-discharge transistor 122 to a low potential to store data 0 in the storage node Q In addition, the second transistor 111b is turned on to pull the anti-storage node Qb to a high potential. In addition, since the transfer transistor 113 is turned off, the charge of the anti-storage node Qb can be prevented from being discharged.

在寫入資料1時，該預放電訊號Pd為高電位而導通該預放電電晶體 122，該字元線訊號WL及該寫入訊號WA皆為高電位而導通該防擾動電晶體114及該傳輸電晶體113，該反寫入訊號WAB則為低電位而截止該寫入電晶體112。此時，該反儲存節點Qb經由該傳輸電晶體113、該防擾動電晶體114及該預放電電晶體122耦接至該接地端而降至低電位，因此，該第一電晶體111a導通而將儲存節點Q拉高至高電位，以將資料1儲存於該儲存節點Q中，且由於該寫入電晶體112及該漏電流電晶體115為截止，而可避免該儲存節點Q的電荷釋放。 When writing data 1, the pre-discharge signal Pd is at a high potential to turn on the pre-discharge transistor 122, the word line signal WL and the write signal WA are at a high potential to turn on the anti-disturbance transistor 114 and the transmission transistor 113, the reverse write signal WAB is at a low potential and the write transistor is turned off 112. At this time, the anti-storage node Qb is coupled to the ground through the transmission transistor 113, the anti-disturbance transistor 114, and the pre-discharge transistor 122 to a low potential, therefore, the first transistor 111a is turned on The storage node Q is pulled up to a high potential to store the data 1 in the storage node Q, and since the write transistor 112 and the leakage current transistor 115 are turned off, the charge discharge of the storage node Q can be avoided.

請參閱第1及3圖，其為該靜態隨機存取記憶體100之各該SRAM單元110讀取資料的時序圖，其中，在該資料讀寫單元120讀取資料時，該預放電訊號Pd為低電位而截止該預放電電晶體122，該字元線訊號WL及該寫入訊號WA為高電位而導通該防擾動電晶體114及該傳輸電晶體113，該反寫入訊號WAB為低電位而截止該寫入電晶體112。此時，該反位元線BLB經由該防擾動電晶體114及該傳輸電晶體113電性連接至該反儲存節點Qb，而接收儲存於該反儲存節點Qb的反向資料，最後再藉由反向器121將其反向於該位元線BL上而完成資料讀取。 Please refer to FIGS. 1 and 3, which are timing diagrams of the SRAM cells 110 of the static random access memory 100 for reading data, wherein, when the data reading and writing unit 120 reads data, the pre-discharge signal Pd The pre-discharge transistor 122 is turned off for a low potential, the word line signal WL and the write signal WA are at a high potential and the anti-disturbance transistor 114 and the transmission transistor 113 are turned on, and the reverse write signal WAB is low The writing transistor 112 is turned off by the electric potential. At this time, the anti-bit line BLB is electrically connected to the anti-storage node Qb through the anti-disturbance transistor 114 and the transmission transistor 113, and receives the reverse data stored in the anti-storage node Qb, and finally The inverter 121 inverts it on the bit line BL to complete the data reading.

請再參閱第1圖，其中，當該儲存節點Q儲存資料0而為低電位時，該反儲存節點Qb為高電位，在讀取資料時，該傳輸電晶體113及該防擾動電晶體114導通，使該寫入輔助迴圈WAL為高電位，此時該漏電流電晶體115被該反儲存節點Qb導通，令該儲存節點Q經由該漏電流電晶體115耦接至該接地端，而可避免來自該寫入電晶體112及該第一電晶體111a之漏電流電荷的累積於該儲存節點Q。相對地，當該儲存節點Q儲存資料1而為高電位時，該反儲存節點Qb為低電位，在讀取資料時，該傳輸電晶體113及該防擾動電晶體114導通，該寫入輔助迴圈WAL為低電位，因此，該儲存節點Q也不會受到漏電流的影響。 Please refer to FIG. 1 again. When the storage node Q stores data 0 and is at a low potential, the anti-storage node Qb is at a high potential. When reading data, the transmission transistor 113 and the anti-disturbance transistor 114 Turn on to make the write auxiliary loop WAL high, at this time the leakage current transistor 115 is turned on by the reverse storage node Qb, so that the storage node Q is coupled to the ground via the leakage current transistor 115, and The accumulation of leakage current charge from the write transistor 112 and the first transistor 111a at the storage node Q can be avoided. In contrast, when the storage node Q stores data 1 and is at a high potential, the anti-storage node Qb is at a low potential. When reading data, the transmission transistor 113 and the anti-disturbance transistor 114 are turned on, and the write assist The loop WAL is at a low potential, so the storage node Q will not be affected by the leakage current.

本發明藉由該漏電流電晶體115提供該儲存節點Q一個放電路徑，而可避免漏電流之電荷累積於該儲存節點Q，以減少整體之該靜態隨機存取記憶體100可能發生資料轉態的錯誤。The present invention uses the leakage current transistor 115 to provide a discharge path for the storage node Q, which can prevent the charge of the leakage current from accumulating in the storage node Q, so as to reduce the possibility of data transition in the static random access memory 100 as a whole mistake.

本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。The scope of protection of the present invention shall be subject to the scope defined in the attached patent application. Any changes and modifications made by those who are familiar with this skill without departing from the spirit and scope of the present invention shall fall within the scope of protection of the present invention. .

100:靜態隨機存取記憶體100: static random access memory

110:SRAM單元110: SRAM cell

111:電晶體對111: Transistor pair

111a:第一電晶體111a: the first transistor

111b:第二電晶體111b: Second transistor

112:寫入電晶體112: Write transistor

113:傳輸電晶體113: Transmitting transistor

114:防擾動電晶體114: Anti-disturbance transistor

115:漏電流電晶體115: leakage current transistor

120:資料讀寫單元120: Data reading and writing unit

121:反向器121: Inverter

122:預放電電晶體122: pre-discharge transistor

Q:儲存節點Q: storage node

Qb:反儲存節點Qb: Anti-storage node

WA:寫入訊號WA: write signal

WAB:反寫入訊號WAB: Reverse write signal

BL:位元線BL: bit line

BLB:反位元線BLB: Inverse bit line

Pd:預放電訊號Pd: pre-discharge signal

WAL:寫入輔助迴圈WAL: write auxiliary loop

第1圖：依據本發明之一實施例，一種靜態隨機存取記憶體的電路圖。 Figure 1: A circuit diagram of a static random access memory according to an embodiment of the invention.

第2圖：依據本發明之一實施例，該靜態隨機存取記憶體寫入資料的時序圖。 Fig. 2: According to one embodiment of the present invention, a timing diagram of writing data in the static random access memory.

第3圖：依據本發明之一實施例，該靜態隨機存取記憶體讀取資料的時序圖。Fig. 3: According to one embodiment of the present invention, a timing diagram of the static random access memory for reading data.

100:靜態隨機存取記憶體 100: static random access memory

110:SRAM單元 110: SRAM cell

111:電晶體對 111: Transistor pair

111a:第一電晶體 111a: the first transistor

111b:第二電晶體 111b: Second transistor

112:寫入電晶體 112: Write transistor

113:傳輸電晶體 113: Transmitting transistor

114:防擾動電晶體 114: Anti-disturbance transistor

115:漏電流電晶體 115: leakage current transistor

120:資料讀寫單元 120: Data reading and writing unit

121:反向器 121: Inverter

122:預放電電晶體 122: pre-discharge transistor

Q:儲存節點 Q: storage node

Qb:反儲存節點 Qb: Anti-storage node

WA:寫入訊號 WA: write signal

WAB:反寫入訊號 WAB: Reverse write signal

BL:位元線 BL: bit line

BLB:反位元線 BLB: Inverse bit line

Pd:預放電訊號 Pd: pre-discharge signal

WAL:寫入輔助迴圈 WAL: write auxiliary loop

Claims (9)

一種靜態隨機存取記憶體，其包含：複數個SRAM單元，各該SRAM單元具有一電晶體對、一寫入電晶體、一傳輸電晶體、一防擾動電晶體及一漏電流電晶體，該電晶體對電性連接一儲存節點及一反儲存節點，該寫入電晶體電性連接該儲存節點，該傳輸電晶體電性連接該反儲存節點，該防擾動電晶體電性連接該寫入電晶體及該傳輸電晶體，該漏電流電晶體電性連接該儲存節點及一接地端，其中該漏電流電晶體受該反儲存節點之一電位控制，以選擇性地導通或截止該儲存節點及該接地端之間的電性連接，其中該漏電流電晶體之一汲極電性連接該儲存節點，該漏電流電晶體之一源極電性連接該接地端，該漏電流電晶體之一閘極電性連接該反儲存節點；以及一資料讀寫單元，電性連接各該SRAM單元之該防擾動電晶體。 A static random access memory includes a plurality of SRAM cells, each of which has a transistor pair, a write transistor, a transmission transistor, an anti-disturbance transistor, and a leakage current transistor, the The transistor pair is electrically connected to a storage node and an inverse storage node, the write transistor is electrically connected to the storage node, the transmission transistor is electrically connected to the anti-storage node, and the anti-disturbance transistor is electrically connected to the write Transistor and the transmission transistor, the leakage current transistor is electrically connected to the storage node and a ground terminal, wherein the leakage current transistor is controlled by a potential of the reverse storage node to selectively turn on or off the storage node And the electrical connection between the ground terminal, wherein a drain of the leakage current transistor is electrically connected to the storage node, a source of the leakage current transistor is electrically connected to the ground terminal, and the leakage current transistor A gate is electrically connected to the anti-storage node; and a data reading and writing unit is electrically connected to the anti-disturbance transistor of each of the SRAM cells. 如申請專利範圍第1項所述之靜態隨機存取記憶體，其中該漏電流電晶體為一高臨界電壓(High threshold voltage)之NMOS電晶體。 The static random access memory as described in item 1 of the patent application scope, wherein the leakage current transistor is a high threshold voltage (High threshold voltage) NMOS transistor. 如申請專利範圍第1項所述之靜態隨機存取記憶體，其中該寫入電晶體之一汲極電性連接該儲存節點，該寫入電晶體之一源極電性連接該傳輸電晶體及該防擾動電晶體，該寫入電晶體之閘極接收一反寫入訊號。 The static random access memory as described in item 1 of the patent application scope, wherein one drain of the write transistor is electrically connected to the storage node, and a source of the write transistor is electrically connected to the transmission transistor And the anti-disturbance transistor, the gate of the write transistor receives an anti-write signal. 如申請專利範圍第3項所述之靜態隨機存取記憶體，其中該寫入電晶體為一低臨界電壓(Low threshold voltage)之NMOS電晶體。 The static random access memory as described in Item 3 of the patent application scope, wherein the write transistor is a low threshold voltage (Low threshold voltage) NMOS transistor. 如申請專利範圍第3項所述之靜態隨機存取記憶體，其中該傳輸電晶體之一汲極電性連接該反儲存節點，該傳輸電晶體之一源極電性連接該寫入電晶體之該源極，該傳輸電晶體之一閘極接收一寫入訊號。 The static random access memory as described in item 3 of the patent application scope, wherein a drain of the transmission transistor is electrically connected to the anti-storage node, and a source of the transmission transistor is electrically connected to the write transistor At the source, a gate of the transmission transistor receives a write signal. 如申請專利範圍第5項所述之靜態隨機存取記憶體，其中該防擾動 電晶體之一汲極電性連接該傳輸電晶體之該源極及該寫入電晶體之該源極，該防擾動電晶體之一源極電性連接該資料讀寫單元，該防擾動電晶體之一閘極接收一字元線訊號。 Static random access memory as described in item 5 of the patent scope, where the anti-disturbance One drain of the transistor is electrically connected to the source of the transmission transistor and the source of the write transistor, one source of the anti-disturbance transistor is electrically connected to the data reading and writing unit, the anti-disturbance electric One gate of the crystal receives a word line signal. 如申請專利範圍第1項所述之靜態隨機存取記憶體，其中該傳輸電晶體及該防擾動電晶體皆為一低臨界電壓之NMOS電晶體。 The static random access memory as described in item 1 of the scope of the patent application, wherein the transmission transistor and the anti-disturbance transistor are both low-voltage NMOS transistors. 如申請專利範圍第1項所述之靜態隨機存取記憶體，其中該電晶體對具有一第一電晶體及一第二電晶體，該第一電晶體之一源極電性連接一電源電壓，該第一電晶體之一閘極電性連接該反儲存節點，該第一電晶體之一汲極電性連接該儲存節點，該第二電晶體之一源極電性連接該電源電壓，該第二電晶體之一閘極電性連接該儲存節點，該第二電晶體之一汲極電性連接該反儲存節點。 The static random access memory as described in item 1 of the patent application range, wherein the transistor pair has a first transistor and a second transistor, and a source of the first transistor is electrically connected to a power supply voltage , A gate of the first transistor is electrically connected to the inverse storage node, a drain of the first transistor is electrically connected to the storage node, and a source of the second transistor is electrically connected to the power supply voltage, A gate of the second transistor is electrically connected to the storage node, and a drain of the second transistor is electrically connected to the anti-storage node. 如申請專利範圍第8項所述之靜態隨機存取記憶體，其中該第一電晶體及該第二電晶體為高臨界電壓之PMOS電晶體。 The static random access memory as described in item 8 of the patent application scope, wherein the first transistor and the second transistor are high critical voltage PMOS transistors.
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