TWI630611B - Single-ended load-less static random access memory - Google Patents

Abstract

A single-ended unloaded SRAM memory includes a plurality of SRAM cells and a data read/write unit, each SRAM cell having a transistor pair, a write transistor, a transmission transistor, and an anti-disturbance transistor. And a discharge transistor, the transistor is electrically connected to a storage node and an anti-storage node, the transmission transistor is electrically connected to the anti-storage node and a discharge node, and the anti-disturbing transistor is electrically connected to the discharge node, The discharge transistor is electrically connected to the discharge node and a ground terminal, wherein the discharge transistor is controlled by a voltage of one of the anti-storage nodes, and a discharge path of a leakage current is provided when the anti-storage node stores the data 0. Avoid storing data that is affected by leakage current.

Description

Single-ended unloaded static random access memory

The present invention relates to a static random access memory, and more particularly to a single-ended unloaded static random access memory.

Please refer to FIG. 1 , which is a structural diagram of a single-ended unloaded SRAM 200 of the Republic of China Patent No. I482154. Each of the SRAM cells 210 of the single-ended unloaded SRAM 200 includes 5 transistors 211, 212, 213, 214, 215, wherein the transistors 211, 212 are two P-type transistors arranged back to back, which are used to latch the voltage of the node Q and the node Qb, that is, the SRAM The stored data, the transistors 213, 214, 215 are used to write data to or read data from the SRAM unit 210.

Referring to FIG. 2, a timing diagram of each control signal when the SRAM unit 210 of the single-ended unloaded SRAM memory 200 writes data, wherein when the SRAM unit 210 writes 0, the pre- The discharge signal Pd is at a high potential to turn on the transistor 221 and turn on the discharge path of the inverted bit line BLB, the word line signal WL is at a high potential to turn on the transistor 215, and the write signal WA is at a low potential to turn off the transistor 214 and reverse The write signal WAB is at a high potential to turn on the transistor 213. Since the transistors 213 and 215 are turned on, the node Q is discharged to a low potential via the write assist loop WAL and the transistor 215 and the inverted bit line BLB, and conducts the transistor 212. The node Qb is raised to a high potential to latch the data of the node Q. When the SRAM cell 210 is written to 1, the pre-discharge signal Pd is at a high potential to turn on the transistor 221 and turn on the discharge path of the inverted bit line BLB, and the word line signal WL is at a high potential to turn on the transistor 215 and write the signal. WA is at a high potential to turn on the transistor 214 and the reverse write signal WAB is at a low potential to turn off the transistor 213. Since the transistors 214, 215 are turned on, the node Qb is discharged to a low potential via the transistors 214, 215 and the inverted bit line BLB. And the conductive crystal 211 causes the node Q to be connected to the power supply voltage VDD to rise to a high potential to latch the data of the node Q.

Please refer to FIG. 3 , which is a timing diagram of each control signal when the SRAM unit 210 of the single-ended unloaded SRAM 200 reads data. When the SRAM unit 210 reads data, the pre-discharge signal Pd The transistor 221 is turned off and the discharge path of the inverted bit line BLB is turned off to prevent the discharge current of the reverse bit line BLB from destroying the data stored in the SRAM cell 210, and the word line signal WL is high. The 215 is turned on, the write signal WA is at a high potential to turn on the transistor 214, and the reverse write signal WAB is at a low potential to turn off the transistor 213. Therefore, the data stored in the node Qb can be transferred to the inverted bit line via the transistors 214 and 218. BLB, finally, the data is transferred to the bit line BL via the inverter 222 to complete the reading.

Referring to FIG. 4 again, when the node Q of the SRAM cell 210 stores the data 1 and the node Qb is low, the leakage current generated by the SRAM cell 210 is as indicated by the arrow in FIG. 4, and since the single-ended is not The plurality of SRAM cells 210 of the SRAM 200 are shared by the single data read/write unit 220. Therefore, the pre-discharge signal is in the standby state of the single-ended unloaded SRAM 200. Pd is a high potential to turn on the transistor 221 and turn on the discharge path of the inverted bit line BLB, so that the leakage current generated by each of the SRAM cells 210 can be discharged via the inverted bit line BLB. However, it can be seen from the timing chart of reading the data in FIG. 3 that when the SRAM unit 210 reads the data, the pre-discharge signal Pd is at a low potential to turn off the transistor 221 and cut off the discharge path of the inverse bit line BLB. The continuous reading of the data of the SRAM cell 210 in the same row will cause the remaining leakage current of the SRAM cell 210 to be discharged through the reverse bit line BLB, which will cause the stored data to be affected by the leakage current.

The main purpose of the present invention is to provide a discharge circuit for each of the SRAM cells by adding a discharge transistor to each of the SRAM cells. When the anti-storage node is at a low potential, the discharge transistor is turned on to provide a discharge path for each of the SRAM cells. The data stored in the SRAM cell is affected by the leakage current.

A single-ended unloaded SRAM memory of the present invention comprises a plurality of SRAM cells and a data read/write unit, each SRAM cell having a transistor pair, a write transistor, a transmission transistor, and an anti-block. a disturbing transistor and a discharge transistor, the transistor is electrically connected to a storage node and an anti-storage node, the transmission transistor is electrically connected to the anti-storage node and a discharge node, and the anti-disturbing transistor is electrically connected to the a discharge node electrically connected to the discharge node and a ground, wherein the discharge transistor is controlled by a voltage of the reverse storage node to selectively turn on or off between the discharge node and the ground Electrically connected, the data reading and writing unit is electrically connected to the anti-disturbing transistor.

The single-ended unloaded crystalline random access memory of the present invention allows the SRAM cell to discharge through the discharge transistor when the pre-discharge transistor is turned off to avoid leakage current accumulation and affect the storage of the SRAM cell. Information.

Referring to FIG. 5, a single-ended unloaded SRAM 100 includes a plurality of SRAM cells 110 and a data read/write unit 120. The SRAM cells 110 use a data together. Read and write unit 120. The data read/write unit 120 has a pre-discharge transistor 121, an inverter 122, a reverse bit line BLB, and a bit line BL. The bit line BLB is electrically connected to the SRAMs, and the reverse The bit line BLB is electrically connected to a ground via the pre-discharge transistor 121. The pre-discharge transistor 121 is controlled by a pre-discharge signal Pd to selectively turn on or off the bit line BLB and the ground. The electrical connection between the bit lines BL is coupled to the inverted bit line BLB via the inverter 122. In this embodiment, the pre-discharge transistor 121 is an N-type transistor. When the pre-discharge signal Pd is at a high potential, the pre-discharge transistor 121 is turned on, so that the inverted bit line BLB is electrically connected to the The ground terminal, and vice versa, when the pre-discharge signal Pd is low, the pre-discharge transistor 121 is turned off, and the inverted bit line BLB is electrically connected to the inverter 122.

Referring to FIG. 5, each of the SRAM cells 110 has a transistor pair 111, a write transistor 112, a transmission transistor 113, an anti-disturbance transistor 114, and a discharge transistor 115. The write transistor 112 and the transfer transistor 113 are used to increase the magnitude of the drive current of the write data, and the write transistor 112 and the transfer transistor 113 form a write assist loop WAL. The anti-disturbing transistor 114 is used to control the word line.

The transistor pair 111 has a first P-type transistor 116 and a second P-type transistor 117, wherein a source of the first P-type transistor 116 is electrically connected to a power supply voltage VDD, the first P One of the gates of the transistor 116 is electrically connected to the anti-storage node Qb and is controlled by the voltage of the anti-storage node Qb. One of the first P-type transistors 116 is electrically connected to a storage node Q, and the second One source of the P-type transistor 117 is electrically connected to the power supply voltage VDD, and one gate of the second P-type transistor 117 is electrically connected to the storage node Q and controlled by the voltage of the storage node Q. The second P One of the type of transistors 117 is electrically connected to the anti-storage node Qb. Preferably, the first P-type transistor 116 and the second P-type transistor 117 are P-type transistors with a high-threshold voltage to strengthen the storage node Q and the anti-storage node Qb. The data is latched and the leakage current is reduced.

One of the gates of the write transistor 112 receives a write-back signal WAB and is controlled by the write-back signal WAB, wherein one of the write transistors 112 is electrically connected to the storage node Q, and the write One source of the transistor 112 is electrically connected to a discharge node N via the write assist loop WAL. Preferably, the write transistor 112 is a low-threshold voltage N-type transistor to increase the magnitude of the drive current of the write data.

One of the gates of the transmission transistor 113 receives a write signal WA and is controlled by the write signal WA. One of the transmission transistors 113 is electrically connected to the anti-storage node Qb. One source of the transmission transistor 113 The discharge node N is electrically connected to the discharge node N. Preferably, the transmission transistor 113 is a low-threshold voltage N-type transistor to increase the driving current of the written data.

One of the gates of the anti-disturbance transistor 114 receives a word line signal WL and is controlled by the word signal WL. One of the anti-disturbance transistors 114 is electrically connected to the discharge node N. The anti-disturbance transistor 114 One of the sources is electrically connected to the inverted bit line BLB of the data read/write unit 120 and the pre-discharge transistor 121 to determine whether each of the SRAM units 110 is connected to the data read/write unit 120.

One source of the discharge transistor 115 is electrically connected to the discharge node N, the source of the write transistor 112, the source of the transfer transistor 113, and the drain of the anti-disturbance transistor 114. One of the discharge transistors 115 is electrically connected to the anti-storage node Qb, and one of the discharge transistors 115 is electrically connected to the ground terminal G, wherein the discharge transistor 115 is controlled by a voltage of the anti-storage node Qb. To selectively turn on or off the electrical connection between the discharge node N and the ground. Preferably, the discharge transistor 115 is a low-threshold voltage P-type transistor to provide a discharge path of leakage current.

The timing and control method of each control signal of the write/read data of the single-ended unloaded SRAM 100 of the present invention is the same as the second and third figures of the prior art, so the single end of the present invention The circuit operation of the write/read of the unloaded SRAM 100 will not be described again.

Referring to FIG. 6, when the single-ended unloaded SRAM 100 reads data of one of the SRAM cells 110, the pre-discharge transistor 121 is turned off. At this time, the anti-storage node Qb stores The SRAM cell 110 of the data 0 cannot release its leakage current through the inverted bit line BLB and the pre-discharge transistor 121, but since the anti-storage node Qb is at a low potential, the discharge transistor 115 is turned on to make the discharge node N Connected to the ground terminal, the leakage current of the SRAM cell 110 can be released via the discharge transistor 115, and the accumulation of leakage current can be avoided to affect the potential of the anti-storage node Qb.

The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .

100‧‧‧ Single-ended unloaded SRAM
110‧‧‧SRAM unit
111‧‧‧Opto optic pair
112‧‧‧Write transistor
113‧‧‧Transmission transistor
114‧‧‧Anti-disturbing electromagnet
115‧‧‧discharge transistor
116‧‧‧First P-type transistor
117‧‧‧Second P-type transistor
120‧‧‧data reading and writing unit
121‧‧‧Pre-discharge transistor
122‧‧‧Inverter
Q‧‧‧ Storage node
Qb‧‧‧Anti-storage node
N‧‧‧discharge node
200‧‧‧ single-ended unloaded static random access memory
210‧‧‧SRAM unit
211-215‧‧‧Optoelectronics
220‧‧‧data reading and writing unit
221‧‧‧Optoelectronics
222‧‧‧Inverter
WAB‧‧‧anti-write signal
WA‧‧‧ write signal
WL‧‧‧ character line signal
Pd‧‧‧Pre-discharge signal
BLB‧‧‧ anti-bit line
BL‧‧‧ bit line
WAL‧‧‧Write auxiliary loop
VDD‧‧‧Power supply voltage

Figure 1: Circuit diagram of a single-ended unloaded SRAM in the prior art. Figure 2: Timing diagram of each control signal when the single-ended unloaded SRAM writes data in the prior art. Figure 3: Timing diagram of each control signal when the single-ended unloaded SRAM reads data in the prior art. Figure 4: Schematic diagram of the leakage current of the single-ended unloaded SRAM in the prior art. Figure 5 is a circuit diagram of a single-ended unloaded SRAM in accordance with an embodiment of the present invention. Figure 6 is a schematic diagram showing leakage current of the single-ended unloaded SRAM according to an embodiment of the present invention.

Claims (10)

A single-ended unloaded static random access memory, comprising: a plurality of SRAM cells, each of the SRAM cells having a transistor pair, a write transistor, a transmission transistor, an anti-disturbance transistor, and a discharge a transistor, the transistor is electrically connected to a storage node and an anti-storage node, the transmission transistor is electrically connected to the anti-storage node and a discharge node, and the anti-disturbing transistor is electrically connected to the discharge node, and the discharge device is electrically connected The crystal is electrically connected to the discharge node and a ground end, wherein the discharge transistor is controlled by a voltage of the anti-storage node to selectively turn on or off an electrical connection between the discharge node and the ground; and The data reading and writing unit is electrically connected to the anti-disturbing transistor. The single-ended unloaded SRAM according to claim 1, wherein one of the discharge transistors is electrically connected to the discharge node, and one of the discharge transistors is electrically connected to the gate. The anti-storage node, one of the discharge transistors is electrically connected to the ground. The single-ended unloaded SRAM according to claim 2, wherein the discharge transistor is a low-threshold voltage P-type transistor. The single-ended unloaded static random access memory according to claim 1, wherein the transistor pair has a first P-type transistor and a second P-type transistor, the first P-type battery One source of the crystal is electrically connected to a power supply voltage, and one of the first P-type transistors is electrically connected to the anti-storage node, and one of the first P-type transistors is electrically connected to the storage node. One source of the second P-type transistor is electrically connected to the power supply voltage, and one of the gates of the second P-type transistor is electrically connected to the storage node, and one of the second P-type transistors is electrically connected to the gate Anti-storage node. The single-ended unloaded SRAM according to claim 4, wherein the first P-type transistor and the second P-type transistor are high-threshold voltage P Type transistor. The single-ended unloaded SRAM according to claim 2, wherein one of the gates of the write transistor receives an inverted write signal, and one of the write transistors is electrically Connected to the storage node, one source of the write transistor is electrically connected to the discharge node and the source of the discharge transistor. The single-ended unloaded SRAM according to claim 6, wherein the write transistor is a low-threshold voltage N-type transistor. The single-ended unloaded SRAM according to claim 2, wherein one of the gates of the transmission transistor receives a write signal, and one of the transmission transistors is electrically connected to the opposite a storage node, one source of the transmission transistor is electrically connected to the discharge node and the source of the discharge transistor. The single-ended unloaded SRAM according to claim 8, wherein the transmission transistor is a low-threshold voltage N-type transistor. The single-ended unloaded SRAM according to claim 2, wherein one of the gates of the anti-disturbance transistor receives a word line signal, and one of the anti-disturbing transistors is electrically Connecting the discharge node and the source of the discharge transistor, one source of the anti-disturbance transistor is electrically connected to the data read/write unit.