TWI700695B - Static random access memory - Google Patents

Abstract

A static random access memory includes a power gating circuit, an SRAM unit, and a data reading and writing unit. When the SRAM is in a reading and writing mode, the power gating circuit transmits a supply voltage to the SRAM unit. When the SRAM is in a standby mode, the power gating circuit transmits a step-down voltage to the SRAM unit. Because the SRAM could receive the step-down voltage which is lower than the supply voltage in the standby mode through the power gating circuit, the SRAM memory could greatly reduce the power consumption.

Description

Static random access memory

The present invention relates to a static random access memory, in particular to a static random access memory with power gating circuit.

Please refer to Figure 6 of the Republic of China Patent Publication No. I630611 "Single-ended Unloaded Static Random Access Memory". The single-ended unloaded static random access memory 100 includes a plurality of SRAM cells 110 and one Data reading and writing unit 120, each SRAM unit 110 has a transistor pair 111, a write transistor 112, a transmission transistor 113, an anti-disturbance transistor 114, and a discharge transistor 115, the transistor pair 111 Is electrically connected to a storage node Q and an anti-storage node Qb, the transmission transistor 113 is electrically connected to the anti-storage node Qb and a discharge node N, the anti-disturbance transistor 114 is electrically connected to the discharge node N, the discharge transistor 115 is electrically connected to the discharge node N and a ground terminal. The discharge transistor 115 is controlled by the voltage of the anti-storage node Qb, and can provide a leakage current discharge path when the anti-storage node Qb stores data 0. Avoid the stored data from being affected by leakage current. The conventional single-ended unloaded static random access memory 100 uses the gate-drain interconnected transistor pair 111 to latch data; through the write transistor 112, the transmission transistor 113 and The anti-disturbance transistor 114 performs data access; and the discharge transistor 115 provides a discharge path to prevent the data stored in the storage node Q and the anti-storage node Qb from being generated due to the accumulation of leakage current in the anti-storage node Qb Variety. However, because the conventional single-ended unloaded static random access memory receives VDD during data access and standby to maintain normal operation, the power consumption is relatively high.

The main purpose of the present invention is to change the voltage received by the SRAM cell in the access mode and the standby mode by the power gating circuit, so as to effectively reduce the power consumption of the static random access memory in the standby mode.

A static random access memory of the present invention includes a power gating circuit, an SRAM unit, and a data reading and writing unit. The power gating circuit has at least one first loop and at least one second loop, the first loop and The second loop receives a power supply voltage, the first loop has a first switching transistor, and the first switching transistor is controlled by a first switching signal, the first loop is used to output the power supply voltage, and the second loop The loop has a second switching transistor, and the second switching transistor is controlled by a second switching signal. The second loop is used to step down the power supply voltage to output a step-down voltage. The SRAM cell is electrically connected to the The first loop and the second loop of the power gating circuit, wherein when the SRAM cell is in an access mode, the first loop of the power gating circuit is turned on, so that the SRAM cell in the access mode receives When the power supply voltage and the SRAM unit are in a standby mode, the second loop of the power gating circuit is turned on, so that the SRAM unit in the standby mode receives the step-down voltage, and the data read/write unit is electrically connected to the SRAM unit.

In the present invention, the power gating circuit allows the SRAM cell to use the step-down voltage lower than the power supply voltage in the standby mode, which can greatly reduce power consumption and improve the efficiency of the static random access memory.

Please refer to Figure 1, which is an embodiment of the present invention, a functional block diagram of a static random access memory 100. The static random access memory 100 includes a power gating circuit 110, a plurality of SRAM cells 120, and A data reading and writing unit 130. The SRAM cells 120 are memory cells in the same column of the static random access memory 100 and are electrically connected to the same power gating circuit 110. The power gating circuit 110 uses To provide power to the SRAM cells 120, the data read/write unit 130 is electrically connected to the SRAM cells 120 for data access. The static random access memory 100 may also have memory cells and power gating circuits in other columns, which are not shown in the drawing.

Referring to Figure 2, the power gating circuit 110 has at least one first loop L1 and at least one second loop L2. The first loop L1 and the second loop L2 receive a power supply voltage VDD, and the first loop L1 uses To output the power supply voltage VDD, the second loop L2 is used to step down the power supply voltage VDD to output a step-down voltage. In this embodiment, the first loop L1 has a first switching transistor 111, the first switching transistor 111 receives the power supply voltage VDD, and the first switching transistor 111 is controlled by a first switching signal to determine Whether to output the power supply voltage VDD, in this embodiment, the first switch control signal is an inverted write signal WAB.

The second loop L2 has a second switching transistor 112 and a step-down transistor 113. The step-down transistor 113 receives the power supply voltage VDD and generates a voltage drop to output a step-down voltage. The second switch transistor 112 is electrically connected to the step-down transistor 113 to receive the step-down voltage, and the second switching transistor 112 is controlled by a second switch signal to determine whether to output the step-down voltage. In this embodiment, the second control signal is a write signal WA, and the reverse write signal WAB and the write signal WA are mutually inverse signals. Therefore, when the first switching transistor 111 is turned on , The second switching transistor 112 is turned off, and when the first switching transistor 111 is turned off, the second switching transistor 112 is turned on, so that the power gating circuit 110 can selectively output the power supply voltage VDD or the drop Voltage is applied to the SRAM cell 120.

Please refer to FIG. 2 again. Preferably, the first switching transistor 111, the second switching transistor 112, and the step-down transistor 113 are all ultra-low threshold voltage PMOS transistors (Ultra-Low threshold voltage PMOS). ), it has a larger drive current and a better response speed. A source of the first switching transistor 111 receives the power supply voltage VDD, a gate of the first switching transistor 111 receives the reverse write signal WAB, and a drain of the first switching transistor 111 is electrically connected In the SRAM unit 120, the first switching transistor 111 is controlled by the potential of the write-inverse signal WAB to determine whether to output the power supply voltage VDD. A source of the step-down transistor 113 receives the power supply voltage VDD, a gate and a drain of the step-down transistor 113 are connected to each other and electrically connected to a source of the second switching transistor 112, so that the The step-down transistor 113 can be equivalent to a diode to perform a voltage drop to output the step-down voltage. One of the gates of the two switching transistors 112 receives the write signal WA, and one of the second switching transistors 112 The drain is electrically connected to the SRAM cell 120, so that the second switching transistor 112 is controlled by the potential of the write signal WA to determine whether to output the step-down voltage.

Referring to FIG. 2, each of the SRAM cells 120 is electrically connected to the first loop L1 and the second loop L2 of the power gating circuit 110 to selectively receive the power supply voltage VDD or the step-down voltage. The SRAM cell 120 has a transistor pair 121, a transmission transistor 122, a write transistor 123, an anti-disturbance transistor 124 and a discharge transistor 125. The transistor pair 121 is electrically connected to the power gating circuit 110, a storage node Q and an anti-storage node Qb for latching data of the storage node Q and the anti-storage node Qb. The transmission transistor 122 is electrically connected to the anti-storage node Qb and a transmission node Wn to determine whether the anti-storage node Qb and the transmission node Wn are turned on or off. The write transistor 123 is electrically connected to the power gating circuit 110 and the transmission node Wn to determine whether the power gating circuit 110 and the transmission node Wn are turned on or off. The anti-disturbance transistor 124 is electrically connected to the transmission node Wn and the data reading and writing unit 130 to determine whether the transmission node Wn and the data reading and writing unit 130 are turned on or off. The discharge transistor 125 is electrically connected to the storage node Q, the anti-storage node Qb, and a ground terminal, and the electric potential of the anti-storage node Qb controls the on or off between the storage node Q and the ground terminal.

The transistor pair 121 has a first P-type transistor 121a and a second P-type transistor 121b. Preferably, the first P-type transistor 121a and the second P-type transistor 121b are both high thresholds The P-type transistor (High threshold voltage PMOS) has a smaller drive current to avoid the influence of leakage current and has a better ability to latch data. A source of the first P-type transistor 121a is electrically connected to the power gating circuit 110 to receive the power supply voltage VDD of the first loop L1 or the step-down voltage of the second loop L2, the first P-type A gate of the transistor 121a is electrically connected to the anti-storage node Qb, and a drain of the first P-type transistor 121a is electrically connected to the storage node Q. A source of the second P-type transistor 121b is electrically connected to the power gating circuit 110 to receive the power supply voltage VDD of the first loop L1 or the step-down voltage of the second loop L2, the second P-type transistor A gate of the transistor 121b is electrically connected to the storage node Q, and a drain of the second P-type transistor 121b is electrically connected to the anti-storage node Qb.

The transmission transistor 122 is an ultra-low threshold voltage NMOS (Ultra-Low threshold voltage NMOS), which has a larger drive current and a better response speed. A drain of the transmission transistor 122 is electrically connected to the inverter. Storage node Qb, a gate of the transmission transistor 122 receives the write signal WA, a source of the transmission transistor 122 is electrically connected to the transmission node Wn, and the transmission transistor 122 receives the potential of the write signal WA The control determines whether the anti-storage node Qb and the transmission node Wn are turned on or off.

The write transistor 123 is a high threshold voltage PMOS (High threshold voltage PMOS) with a small drive current to avoid the influence of leakage current. A source of the write transistor 123 is electrically connected to the power gate. The circuit 110 receives the power supply voltage VDD of the first loop L1 or the step-down voltage of the second loop L2, a drain of the write transistor 123 is electrically connected to the transmission node Wn, and the write transistor 123 A gate receives a write zero signal WLO, and the write transistor 123 is controlled by the potential of the write zero signal WLO to determine whether the power gating circuit 110 and the transmission node Wn are turned on or off.

The anti-disturbance transistor 124 is an ultra-low threshold voltage NMOS (Ultra-Low threshold voltage NMOS), which has a larger driving current and a better response speed. One of the drain electrodes of the anti-disturbance transistor 124 is electrically connected At the transmission node Wn, a gate of the anti-disturbance transistor 124 receives a word line signal WL, a source of the anti-disturbance transistor 124 is electrically connected to the data read/write unit 130, and the anti-disturbance transistor 124 receives The control of the potential of the word line signal WL determines whether the transmission node Wn and the data read/write unit 130 are turned on or off.

The discharge transistor 125 is a high threshold voltage NMOS (High threshold voltage NMOS) and has a small drive current to avoid the influence of leakage current. A drain of the discharge transistor 125 is electrically connected to the storage node Q, and A gate of the discharge transistor 125 is electrically connected to the inverse storage node Qb, a source of the discharge transistor 125 is electrically connected to the ground terminal, and the discharge transistor 125 is controlled by the potential of the inverse storage node Qb to determine the The conduction or cutoff between the storage node Q and the ground terminal.

The data read/write unit 130 has a bit line BL, an inverted bit line BLB, an inverter 131, and a pre-discharge transistor 132. The inverted bit line BLB is electrically connected to the anti-disturbance transistor 124 For the source, the input terminal of the inverter 131 is electrically connected to the inverted bit line BLB, and the output terminal of the inverter 131 is electrically connected to the bit line BL. The pre-discharge transistor 132 is an ultra-low threshold voltage NMOS (Ultra-Low threshold voltage NMOS), which has a larger driving current and a better response speed. One of the drain electrodes of the pre-discharge transistor 132 is electrically connected The inverted bit line BLB, a gate of the pre-discharge transistor 132 receives a pre-discharge signal Pd, a source of the pre-discharge transistor 132 is electrically connected to the ground terminal, and the pre-discharge transistor 132 receives the pre-discharge signal Pd. The control of the potential of the discharge signal Pd determines the conduction or cut-off between the inverted bit line BLB and the ground terminal, so as to discharge the inverted bit line BLB to a low potential. In addition, through the anti-disturbance transistor 124 of each SRAM cell 120 to control the conduction between the data reading unit 130 and each SRAM cell 120, it is possible to achieve a single data reading unit 130 for multiple The SRAM unit 120 performs data reading and writing.

Please refer to Figure 3 for the level of the control signal of the SRAM cell 120 in each mode. Please refer to Figure 2. The write signal WA is only low in standby mode and high in other modes. . In the standby mode, the write signal WA is at a low level to turn on the second loop L2, and the write-inverse signal WAB is at a high potential to turn off the first loop L1, so that the SRAM cells 120 are in the standby mode The power consumption during standby can be greatly reduced by receiving the step-down voltage. In other modes, the write-inverse signal WAB is at a low potential to turn on the first loop L1, and the write signal WA is at a high potential to turn off the second loop L2, so that the SRAM cell 120 is in writing and reading In the mode, the power supply voltage VDD is received and it works normally.

Please refer to Figures 2 and 3. In the write 0 mode, the word line signal WL and the write zero signal WLO are at a low level, and the write signal WA and the pre-discharge signal Pd are at a high level. At this time, The anti-disturbance transistor 124 is turned off, the first switching transistor 111, the write transistor 123, the transmission transistor 122, and the pre-discharge transistor 132 are turned on, and the power supply voltage VDD of the first loop L1 passes through the write The input transistor 123 and the transmission transistor 122 are transmitted to the anti-storage node Qb, so that the anti-storage node Qb is pulled to a high potential, and then the discharge transistor 125 is turned on, so that the storage node Q is discharged to low through the discharge transistor 125 Potential to complete writing 0.

Please refer to Figures 2 and 3. In the write 1 mode, the word line signal WL, the write signal WA, the write zero signal WLO, and the pre-discharge signal Pd are all high. At this time, the write The input transistor 123 is turned off, the first switching transistor 111, the transmission transistor 122, the anti-disturbance transistor 124 and the pre-discharge transistor 132 are turned on, and the anti-storage node Qb passes through the transmission transistor 122 and the anti-disturbance transistor 132. The transistor 124 and the pre-discharge transistor 132 are connected to the ground terminal and discharged to a low potential, thereby turning on the first P-type transistor 121a of the transistor pair 121 and turning off the discharge transistor 125, so that the first loop The power supply voltage VDD of L1 charges the storage node Q to a high potential via the first P-type transistor 121a to complete writing 1.

The SRAM cell 120 achieves the writing of data to the storage node Q only by controlling the potential of the anti-storage node Qb, so that the static random access memory 100 receiving the step-down voltage can maintain good static noise Margin (SNM).

Please refer to Figures 2 and 3. In the read mode, the word line signal WL, the write signal WA, and the write zero signal WLO are high, and the pre-discharge signal Pd is low. At this time, the The write transistor 123 and the pre-discharge transistor 132 are turned off, the first switching transistor 111, the transmission transistor 122, and the anti-disturbance transistor 124 are turned on, and the anti-storage node Qb passes through the transmission transistor 122 and the anti-disturbance transistor. The perturbation transistor 124 is connected to the inverted bit line BLB, so that the potential of the inverted bit line BLB will be the same as the inverted storage node Qb, and then the inverter 131 reverses the potential of the inverted bit line BLB to the The bit line BL makes the potential of the bit line BL the same as the potential of the storage node Q to complete data reading.

In the present invention, the power gating circuit 110 allows the SRAM cell 120 to use the step-down voltage lower than the power supply voltage VDD in the standby mode, which can greatly reduce power consumption and improve the performance of the static random access memory 100 effectiveness.

The scope of protection of the present invention shall be subject to the scope of the attached patent application. Anyone who is familiar with the art and makes any changes and modifications without departing from the spirit and scope of the present invention shall fall within the scope of protection of the present invention. .

100: Static random access memory

110: power gating circuit

111: The first switching transistor

112: second switching transistor

113: step-down crystal

120: VSRAM unit

121: Transistor Pair

121a: The first P-type transistor

121b: second P-type transistor

122: Transmission Transistor

123: write transistor

124: Anti-disturbance transistor

125: discharge transistor

130: data reading and writing unit

131: Inverter

132: pre-discharge transistor

L1: first loop

L2: second loop

VDD: power supply voltage

WAB: reverse write signal

WA: write signal

Q: Storage node

Qb: Anti-storage node

Wn: Transmission node

WLO: write zero signal

WL: character line signal

BLB: Anti-bit line

BL: bit line

Pd: pre-discharge signal

Figure 1: A functional block diagram of a static random access memory according to an embodiment of the invention. Figure 2: Circuit diagram of the static random access memory according to an embodiment of the present invention. Figure 3: According to an embodiment of the present invention, the magnitude of the control signal potential of the static random access memory in each mode.

100: Static random access memory

110: power gating circuit

120: SRAM cell

130: data reading and writing unit

Claims (9)

A static random access memory, comprising: a power gating circuit having at least one first loop and at least one second loop, the first loop and the second loop receiving a power supply voltage, the first loop having a A first switching transistor, and the first switching transistor is controlled by a first switching signal, the first loop is used to output the power supply voltage, the second loop has a second switching transistor, and the second switching transistor The crystal is controlled by a second switch signal, and the second loop is used to step down the power supply voltage to output a step-down voltage; an SRAM unit is electrically connected to the first loop and the second loop of the power gating circuit , Wherein, when the SRAM cell is in an access mode, the first loop of the power gating circuit is turned on, so that the SRAM cell in the access mode receives the power voltage. When the SRAM cell is in a standby mode, the The second loop of the power gating circuit is turned on so that the SRAM cell in the standby mode receives the step-down voltage; and a data reading and writing unit is electrically connected to the SRAM cell; wherein the SRAM cell has a pair of transistors, A transmission transistor, a write transistor, an anti-disturbance transistor, and a discharge transistor. The pair of transistors are electrically connected to the power gating circuit, a storage node and an anti-storage node. The transmission transistor is electrically connected The anti-storage node and a transmission node are connected, the write transistor is electrically connected to the power gating circuit and the transmission node, the anti-disturbance transistor is electrically connected to the transmission node and the data read/write unit, and the discharge transistor The storage node, the anti-storage node and a ground terminal are electrically connected. For the static random access memory described in claim 1, wherein the first switch control signal is an inverted write signal, a source of the first switching transistor receives the power supply voltage, and the first switch A gate of the transistor receives the reverse write signal, and a drain of the first switching transistor is electrically connected Connect the SRAM cell. For the static random access memory described in item 2 of the scope of patent application, wherein the second control signal is a write signal, the second loop has a step-down crystal, and a source of the step-down crystal receives The power supply voltage, a gate and a drain of the step-down transistor are connected to each other and electrically connected to a source of the second switching transistor, one of the two switching transistors receives the write signal, the A drain of the second switching transistor is electrically connected to the SRAM cell. For the static random access memory described in item 3 of the scope of patent application, the first switching transistor, the second switching transistor and the step-down transistor are all ultra-low threshold P-type transistors (Ultra- Low threshold voltage PMOS). The static random access memory described in claim 1, wherein the transistor pair has a first P-type transistor and a second P-type transistor, and a source of the first P-type transistor Is electrically connected to the power gating circuit, a gate of the first P-type transistor is electrically connected to the inverse storage node, a drain of the first P-type transistor is electrically connected to the storage node, and the second P A source of the second P-type transistor is electrically connected to the power gating circuit, a gate of the second P-type transistor is electrically connected to the storage node, and a drain of the second P-type transistor is electrically connected to the anti-storage node . The static random access memory described in the first item of the scope of patent application, wherein a source of the write transistor is electrically connected to the power gating circuit, and a drain of the write transistor is electrically connected to a transmission node , A gate of the write transistor receives a write zero signal. The static random access memory described in claim 1, wherein a drain of the discharge transistor is electrically connected to the storage node, a gate of the discharge transistor is electrically connected to the anti-storage node, the A source of the discharge transistor is electrically connected to the ground terminal. The static random access memory described in item 1 of the scope of patent application, wherein the transmission circuit A drain of the crystal is electrically connected to the inverse storage node, a gate of the transmission transistor receives a write signal, and a source of the transmission transistor is electrically connected to the transmission node. For the static random access memory described in item 1 of the scope of patent application, wherein a drain of the anti-disturbance transistor is electrically connected to the transmission node, and a gate of the anti-disturbance transistor receives a word line signal, A source of the anti-disturbance transistor is electrically connected to the data reading and writing unit.

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