CN102136297A - Storage unit capable of controlling bit line oscillation amplitude for register file - Google Patents
Storage unit capable of controlling bit line oscillation amplitude for register file Download PDFInfo
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- CN102136297A CN102136297A CN2011100835252A CN201110083525A CN102136297A CN 102136297 A CN102136297 A CN 102136297A CN 2011100835252 A CN2011100835252 A CN 2011100835252A CN 201110083525 A CN201110083525 A CN 201110083525A CN 102136297 A CN102136297 A CN 102136297A
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Abstract
The invention belongs to the technical field of the design of the storage unit of an integrated circuit, and in particular relates to a storage unit capable of controlling the bit line oscillation amplitude for a register file. The storage unit comprises two phase inverters, two write transistors, two read transistors, two read insulating tubes and two mode control transistors in a cross mode, wherein the two phase inverters are coupled between a power supply and the ground. When a mod signal is under a power supply voltage, a pseudo earth wire voltage approaches to a power ground; and when the mod signal is on the power ground, the pseudo earth wire voltage is a certain middle-point voltage. The storage unit can limit the oscillation amplitude of a readbit line to lower the power consumption of a register file; and under a certain special condition, bit line full swing is required to adapt to requirements. The control unit provided by the invention can conveniently realize conversion between the full oscillation amplitude and the low oscillation amplitude of the bit line.
Description
Technical field
The invention belongs to the integrated circuit memory cells design field, be specifically related to a kind of register file and reach static storage cell at random.
Background technology
Register file is a first order storage unit in the processor, and it will quadrature little, and speed is fast, and power consumption is little.The function and the power consumption of the speed of register file play decisive role to performance of processors.Along with the development of technology, the frequency of operation of processor is more and more higher, and this frequency of operation and power consumption to register file has proposed great requirement.
Fig. 1 has showed 8 traditional pipe register file stores unit 110.PMOS pipe 100 and NMOS pipe 102 constitute a phase inverter that is coupled between supply voltage and the ground, and its grid end links to each other at node 109 places, and drain terminal node 108 places link to each other; Same, PMOS pipe 101 and NMOS pipe 103 also constitute a phase inverter that is coupled between supply voltage and the ground, and its grid end links to each other at node 108 places, and drain terminal node 109 places link to each other.These four transistors have constituted the phase inverter of a pile coupling, and it has two memory nodes: true memory node 109 and complementary storage node 108.Write circuit is made of NMOS pipe 106 and 107, and their grid end is linked on the write word line WWL jointly, and the drain terminal of transistor 107 is linked true write bit line WBL, and the source end is linked on the true memory node; The drain terminal of transistor 107 is linked complementary write bit line WBLB, and the source end is linked on the complementary storage node.During write operation, word line WWL gate transistor 106 and 107 writes memory node 109 and 108 with the data among WBL and the WBLB.Reading circuit is made of NMOS pipe 104 and 105, and their grid end is linked on the readout word line RWL jointly, and the drain terminal of transistor 105 is linked true sense bit line RBL, and the source end is linked on the true memory node; The drain terminal of transistor 104 is linked complementary write bit line RBLB, and the source end is linked on the complementary storage node.During read operation, word line RWL gate transistor 105 and 104 passes to the data on true memory node and the complementary storage node on true sense bit line RBL and the complementary sense bit line RBLB.As seen, one of shortcoming of this storage unit is that write operation is identical with read operation, and when promptly read operation began, the value on true sense bit line RBL and the complementary sense bit line RBLB can be destroyed the value on true storage and the complementary storage node, cause read a character with two or more ways of pronunciation bad.
Fig. 2 has showed to have and has prevented to read a character with two or more ways of pronunciation 10 bad pipe register file stores unit 210.Compare to have added with 8 traditional transistor memory units and read isolated tube 207 and 208.Read isolated tube 208 and be nmos pass transistor, its grid end connects true memory node 201, and its source end links to each other with ground, and the source end of reading transistor 209 links to each other with the grid end of reading isolated tube 208 now, forms puppet and reads memory node 204.Read isolated tube 207 and be nmos pass transistor, its grid end connects complementary storage node 202, and its source end links to each other with ground, and the source end of reading transistor 206 links to each other with the grid end of reading isolated tube 207 now, forms pseudo-complementation and reads memory node 203.During read operation, word line RWL gate transistor 206 and 209, sense bit line RBL and complementary sense bit line optionally discharge according to the data that puppet is read on memory node 204 and the pseudo-complementary storage node 203 because sense bit line and memory node are isolated, can not find out read a character with two or more ways of pronunciation bad.Yet directly link to each other with 208 owing to read isolated tube 207,, cause bigger power consumption penalty so the sense bit line velocity of discharge is very fast, even reaches the rail-to-rail amplitude of oscillation with ground.So need a kind of method that reduces bit line discharges speed, to reduce power consumption.
Summary of the invention
The object of the present invention is to provide a kind of can be at varying environment, different application situation, register file can have been given play to the storage unit in the accumulator system of different performances.
Storage unit in the accumulator system that the present invention proposes is a kind of register memory cell of the may command amplitude of oscillation, comprising:
First and second phase inverters, described first and second phase inverters are connected between supply voltage and the power supply ground through cross-couplings, form the storage unit core circuit, have true memory node and complementary storage node;
First write transistor, its grid end is connected on the write word line, and the source end is connected on the true memory node, and drain terminal is connected on first write bit line;
Second write transistor, its grid end is connected on the write word line, and the source end is connected on the complementary storage node, and drain terminal is connected on second write bit line;
First reads isolated tube, and its grid end is connected on the true memory node, is used to isolate pseudo-memory node and true memory node, and forms the first pseudo-ground wire; The source end is connected on the first pseudo-ground wire, and drain terminal is connected on the first pseudo-memory node;
First reading transistor, its grid end is connected on the readout word line, is used to connect the pseudo-memory node and first sense bit line; The source end connects pseudo-memory node, and drain terminal connects first sense bit line; The described first pseudo-ground wire is configured and is coupled to power ground, or is configured by pattern control line control and is coupled to power ground; This first pseudo-ground wire can be shared by a column unit;
The second reading isolated tube, its grid end is connected on the complementary storage node, is used to isolate pseudo-complementary storage node and complementary storage node, and forms the second pseudo-ground wire; The source end is connected on the second pseudo-ground wire, and drain terminal is connected on the second pseudo-memory node;
The second reading transistor, its grid end is connected on the readout word line, is used to connect pseudo-complementary storage node and second reading bit line; The source end is connected on the second pseudo-memory node, and drain terminal is connected on the second reading bit line; The described second pseudo-ground wire is configured and is coupled to power ground, or is configured by pattern control line control and is coupled to power ground; This second pseudo-ground wire can be shared by a column unit.
The register memory cell of the may command amplitude of oscillation provided by the invention can limit the amplitude of oscillation of sense bit line, reduces the power consumption of register file; On the other hand, at some in particular cases, need the bit line full swing to adapt to requirement, control module provided by the invention can be realized the full swing of bit line and the conversion between the low amplitude of oscillation very easily.
Description of drawings
Fig. 1 is the synoptic diagram of traditional 8 transistor cells.
Fig. 2 is the synoptic diagram that can prevent to read a character with two or more ways of pronunciation 10 bad pipe register file stores unit.
Fig. 3 is the synoptic diagram that can reduce the single register file stores unit of the bit line amplitude of oscillation.
Fig. 4 is the synoptic diagram that can reduce the register file stores cell array of the bit line amplitude of oscillation.
Fig. 5 is the synoptic diagram that can regulate the single register file stores unit of the bit line amplitude of oscillation.
Fig. 6 is the synoptic diagram that can regulate the register file stores cell array of the bit line amplitude of oscillation.
Embodiment
The invention describes a kind of register file stores unit that can reduce and regulate the sense bit line amplitude of oscillation.Various example of the present invention and design philosophy have wherein below been set forth.
The expression that Fig. 3 is exemplary the present invention's first example 9 the pipe register memory cells 311.This unit comprises pull-up device 300 and 301, pull-down 302 and 303, and writing controller spare 304 and 305, Read Controller spare 308 is read isolating device 309, reads pull-down 310.Pull-up device 300 is the PMOS transistor, its source end links to each other with supply voltage VDD, pull-down 302 is a nmos pass transistor, its source end links to each other with power supply ground GND, its drain terminal links to each other at node 313 places with 300 the drain terminal of pulling up transistor, and the grid end of pull-up device 300 and pull-down 302 links to each other at node 312 places.Pull-up device 301 is the PMOS transistor, its source end links to each other with supply voltage VDD, pull-down 303 is a nmos pass transistor, its source class links to each other with power supply ground GND, its drain terminal links to each other at node 312 places with 301 the drain terminal of pulling up transistor, and the grid end of pull-up device 301 and pull-down 303 links to each other at node 313 places.Such four transistors 300,301,302,303 have formed the phase inverter of a pair of coupling, form 2 memory nodes: true memory node 312 and complementary storage node 313.
Writing controller spare 304 and 305 is a nmos pass transistor, and their grid end is connected on the write word line WWL jointly; The source end of writing controller spare 304 is linked on the complementary storage node 313, and drain terminal is linked on the complementary write bit line WBLB; The source end of writing controller spare 305 connects on the true memory node 312, and the source end is linked on the true write bit line WBL.During write operation, write word line WWL by apply opposite signal on true write bit line WBL and the complementary write bit line of WBLB, writes memory node 312 and 313 with data with writing controller spare 304 and 305 gatings.
Read Controller spare 308 is a nmos pass transistor, and its grid end is connected on the readout word line RWL, and drain terminal is linked on the true sense bit line BLB.Read isolated tube 309 and be nmos pass transistor, its grid end is connected on the true memory node 312, and drain terminal links to each other on pseudo-memory node 314 with the source end of Read Controller spare 308, and the source end is connected on the pseudo-ground wire node 315.Reading pull-down is the NMOS pipe, and its grid end and drain terminal are connected on the pseudo-ground wire node 315 jointly, and the source end links to each other with ground, and this device forms a current-limiting resistance, the velocity of discharge that the restriction bit line powers on and flows.The amplitude of oscillation of bit line just reduces greatly like this, thereby has greatly reduced power consumption.
The expression that Fig. 4 is exemplary the present invention's second example register memory cell array 423.It is made of two storage unit 421 and 422 and pull-down 420.The grid end of pull-down 420 and drain terminal are connected on the pseudo-ground wire node 424 jointly, and the source end is connected on the ground.Compare with first example, its characteristics are: every array storage unit is shared a pull-down 420.During write operation, word line WWL1 gate transistor 404 and 405 then according to the level on WBL and the WBLB, writes memory node 400 and 401 with data; Perhaps word line WWL2 gate transistor 414 and 415 then according to the level on WBL and the WBLB, writes memory node 410 and 411 with data.During read operation, word line RWL1 gate transistor 408 or word line RWL2 gate transistor 418, according to the value on pseudo-memory node 425 or 426, pairs of bit line RBL discharges then.Owing to have only a storage unit 421 or storage unit 422 conductings at every turn, read pull-down 420 and can't have a significant impact the velocity of discharge so share one.Can under the situation of saving area, reach the effect identical like this with first example.
The expression that Fig. 5 is exemplary the present invention's the 3rd example 11 the pipe register memory cells 513.This unit comprises pull-up device 500 and 501, pull-down 502 and 503, and writing controller spare 504 and 505, Read Controller spare 509 is read isolating device 508, reads pull-down 512 and reads drop-down control device 511 and 510.Pull-up device 500 is the PMOS transistor, its source end links to each other with supply voltage VDD, pull-down 502 is a nmos pass transistor, its source end links to each other with power supply ground GND, its drain terminal links to each other at node 515 places with 500 the drain terminal of pulling up transistor, and the grid end of pull-up device 500 and pull-down 502 links to each other at node 516 places.Pull-up device 501 is the PMOS transistor, its source end links to each other with supply voltage VDD, pull-down 503 is a nmos pass transistor, its source class links to each other with power supply ground GND, its drain terminal links to each other at node 516 places with 501 the drain terminal of pulling up transistor, and the grid end of pull-up device 501 and pull-down 503 links to each other at node 515 places.Such four transistors 500,501,502,503 have formed the phase inverter of a pair of coupling, form 2 memory nodes: true memory node 516 and complementary storage node 515.
Writing controller spare 504 and 505 is a nmos pass transistor, and their grid end is connected on the write word line WWL jointly; The source end of writing controller spare 504 is linked on the complementary storage node 515, and drain terminal is linked on the complementary write bit line WBLB; The source end of writing controller spare 505 connects on the true memory node 516, and the source end is linked on the true write bit line WBL.During write operation, write word line WWL by apply opposite signal on true write bit line WBL and the complementary write bit line of WBLB, writes memory node 515 and 516 with data with writing controller spare 504 and 505 gatings.
Read Controller spare 509 is a nmos pass transistor, and its grid end is connected on the readout word line RWL, and drain terminal is linked on the true sense bit line BLB.Read isolated tube 508 and be nmos pass transistor, its grid end is connected on the true memory node 516, and drain terminal links to each other on pseudo-memory node 517 with 308 source end, and the source end is connected on the pseudo-ground wire node 514.Reading pull-down is the NMOS pipe, and its drain terminal is connected on the pseudo-ground wire node 514, and the source end links to each other with ground, and grid terminate on the Control Node 518.Read Controller spare is made of NMOS pipe 511 and PMOS pipe 510, and their grid end is connected on the control signal wire mod jointly, and drain terminal is connected on the Control Node 518 jointly.The source end of PMOS pipe 510 is connected on the supply voltage, and the source end of NMOS pipe 511 is connected on the pseudo-ground wire node 514.When the Mod signal wire is supply voltage, nmos pass transistor 511 conductings, PMOS transistor 510 turn-offs, node 514 and node 518 short circuits, this situation and first example class are seemingly; The mod signal wire is when ground, and nmos pass transistor 511 turn-offs, 510 conductings of PMOS transistor, and at this moment, node 518 and supply voltage short circuit make pull-down transistor 512 conductings, pseudo-ground wire node 514 and ground short circuit, this situation is with similar as the conventional situation of Fig. 2.When read operation began, readout word line RWL was to allomeric pipe 509, and sense bit line RBL carries out the discharge of friction speed according to the value on pseudo-memory node 517 and the mod signal wire, reaches different effects.
The expression that Fig. 6 is exemplary the present invention's the 4th example register memory cell array 632.It has two storage unit 630 and 631 and pull-down circuits 633 to constitute.Compare with first example, its characteristics are: every array storage unit is shared a pull-down circuit 633.Read pull-down circuit 633 by reading pull-down NMOS transistor 621 and reading to control PMOS transistor 618 and nmos pass transistor 620 constitutes.During write operation, write word line WWL1 gate transistor 604 and 605 according to the level on WBL and the WBLB, writes memory node 600 and 601 with data; Perhaps write word line WWL2 gate transistor 614 and 615 then according to the level on WBL and the WBLB, writes memory node 610 and 611 with data.During read operation, readout word line RWL1 gate transistor 609 or readout word line RWL2 gate transistor 619 then according to value on pseudo-memory node 626 or 627 and the value on the mod signal wire, carry out in various degree discharge to sense bit line RBL.Owing to have only a storage unit 630 or 631 conductings, can't have a significant impact the velocity of discharge at every turn so share a pull-down circuit.Can under the situation of saving area, reach the effect identical like this with the 3rd example.
Claims (5)
1. register file stores unit is characterized in that comprising:
First and second phase inverters, described first and second phase inverters are connected between supply voltage and the power supply ground through cross-couplings, form the storage unit core circuit, have true memory node and complementary storage node;
First write transistor, its grid end is connected on the write word line, and the source end is connected on the true memory node, and drain terminal is connected on first write bit line;
Second write transistor, its grid end is connected on the write word line, and the source end is connected on the complementary storage node, and drain terminal is connected on second write bit line;
First reads isolated tube, and its grid end is connected on the true memory node, is used to isolate pseudo-memory node and true memory node, and forms the first pseudo-ground wire; The source end is connected on the first pseudo-ground wire, and drain terminal is connected on the first pseudo-memory node;
First reading transistor, its grid end is connected on the readout word line, is used to connect the pseudo-memory node and first sense bit line; The source end connects pseudo-memory node, and drain terminal connects first sense bit line;
The second reading isolated tube, its grid end is connected on the complementary storage node, is used to isolate pseudo-complementary storage node and complementary storage node, and forms the second pseudo-ground wire; The source end is connected on the second pseudo-ground wire, and drain terminal is connected on the second pseudo-memory node;
The second reading transistor, its grid end is connected on the readout word line, is used to connect pseudo-complementary storage node and second reading bit line; The source end is connected on the second pseudo-memory node, and drain terminal is connected on the second reading bit line.
2. register file stores according to claim 1 unit is characterized in that: the described first pseudo-ground wire is configured and is coupled to power ground, or is configured by pattern control line control and is coupled to power ground.
3. register file stores according to claim 2 unit is characterized in that: the described first pseudo-ground wire is shared by an array storage unit.
4. register file stores according to claim 1 unit is characterized in that: the described second pseudo-ground wire is configured and is coupled to power ground, or is configured by pattern control line control and is coupled to power ground.
5. register file stores according to claim 4 unit is characterized in that: the described second pseudo-ground wire is shared by an array storage unit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011100835252A CN102136297A (en) | 2011-04-02 | 2011-04-02 | Storage unit capable of controlling bit line oscillation amplitude for register file |
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| CN2011100835252A CN102136297A (en) | 2011-04-02 | 2011-04-02 | Storage unit capable of controlling bit line oscillation amplitude for register file |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102710251A (en) * | 2012-05-28 | 2012-10-03 | 宁波大学 | Physical unclonable functions (PUF) circuit unit |
| CN103500583A (en) * | 2013-09-11 | 2014-01-08 | 复旦大学 | Reading bit line electric leakage resistant storage unit applicable to writing strengthening of low-voltage register file |
| CN103578529A (en) * | 2013-10-21 | 2014-02-12 | 复旦大学 | Subthreshold storage unit for changing power supply according to write data |
| CN103578531A (en) * | 2013-10-21 | 2014-02-12 | 复旦大学 | Negative bit line voltage generation circuit |
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| US20030090928A1 (en) * | 2001-11-09 | 2003-05-15 | Takashi Takemura | Semiconductor memory device |
| US20070297263A1 (en) * | 2003-06-05 | 2007-12-27 | Renesas Technology Corp. | Semiconductor memory device capable of controlling potential level of power supply line and/or ground line |
| US20090303820A1 (en) * | 2008-06-09 | 2009-12-10 | Igor Arsovski | Apparatus and method for low power sensing in a multi-port sram using pre-discharged bit lines |
| US20100142258A1 (en) * | 2008-12-05 | 2010-06-10 | Tsai Tsung-Heng | Ten-transistor static random access memory architecture |
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2011
- 2011-04-02 CN CN2011100835252A patent/CN102136297A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20030090928A1 (en) * | 2001-11-09 | 2003-05-15 | Takashi Takemura | Semiconductor memory device |
| US20070297263A1 (en) * | 2003-06-05 | 2007-12-27 | Renesas Technology Corp. | Semiconductor memory device capable of controlling potential level of power supply line and/or ground line |
| US20090303820A1 (en) * | 2008-06-09 | 2009-12-10 | Igor Arsovski | Apparatus and method for low power sensing in a multi-port sram using pre-discharged bit lines |
| US20100142258A1 (en) * | 2008-12-05 | 2010-06-10 | Tsai Tsung-Heng | Ten-transistor static random access memory architecture |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102710251A (en) * | 2012-05-28 | 2012-10-03 | 宁波大学 | Physical unclonable functions (PUF) circuit unit |
| CN103500583A (en) * | 2013-09-11 | 2014-01-08 | 复旦大学 | Reading bit line electric leakage resistant storage unit applicable to writing strengthening of low-voltage register file |
| CN103500583B (en) * | 2013-09-11 | 2016-05-25 | 复旦大学 | For the anti-sense bit line electric leakage memory cell of writing reinforcement of low-voltage register file |
| CN103578529A (en) * | 2013-10-21 | 2014-02-12 | 复旦大学 | Subthreshold storage unit for changing power supply according to write data |
| CN103578531A (en) * | 2013-10-21 | 2014-02-12 | 复旦大学 | Negative bit line voltage generation circuit |
| CN103578529B (en) * | 2013-10-21 | 2016-08-03 | 复旦大学 | A kind of basis is write data and is changed the sub-threshold memory cell that power supply is powered |
| CN103578531B (en) * | 2013-10-21 | 2016-09-28 | 复旦大学 | A kind of negative bit line voltage generation circuit |
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Application publication date: 20110727 |