CN103578531B - A kind of negative bit line voltage generation circuit - Google Patents
A kind of negative bit line voltage generation circuit Download PDFInfo
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- CN103578531B CN103578531B CN201310494138.7A CN201310494138A CN103578531B CN 103578531 B CN103578531 B CN 103578531B CN 201310494138 A CN201310494138 A CN 201310494138A CN 103578531 B CN103578531 B CN 103578531B
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Abstract
The invention belongs to integrated circuit storage design field, be specially the negative bit line voltage generation circuit of one.Its structure includes a coupling electric capacity, and a level being responsible for after coupling retracts the lower trombone slide of " 0 ", a preliminary filling pipe being responsible for charging drop-down tube grid and a discharge tube being responsible for electric discharge, and two pairs of phase inverters.One of them phase inverter is low deflection phase inverter, for producing the high level of moment to low level saltus step；Another is then pulled down the output phase inverter of management and control for pin ground, for data output.Present configuration is simple, it is possible to effective generation bears bit-line voltage.
Description
Technical field
The invention belongs to IC design field, be specifically related to a kind of register file (Register File) or SRAM (Static Random Access
Memory, SRAM) negative bit line voltage generation circuit.
Background technology
SRAM is normally occupied a large amount of areas of chip, and especially with the progress of Technology, its shared ratio is increasing.Predicting according to american semiconductor technology blueprint (ITRS), by 2014, SRAM was up to more than 90% in the ratio shared by SOC(system on a chip) (SoC).Therefore, the main performance of chip, including area, speed and power consumption, all dominated by SRAM.
But, along with not mating of the progress of Technology, process deviation and device parameters more comes seriously, SRAM uses the transistor of minimum dimension because of it, thus very sensitive to these technique change so that and it is easy to produce reading and writing functionality errors.Therefore, the stability of the reading and writing operation improving SRAM is increasingly paid close attention to by designers.
2006, H. Pilo was at meeting " Symposium on VLSI
Technology " in deliver " An SRAM design in 65-nm
and 45-nm technology nodes featuring read and write-assist circuits to expand
Operating voltage ", it is proposed that the method on a kind of dummy unit ground, effectively improve the stability of SRAM read operation.2008, Y. H. Chen was at meeting " Symposium on VLSI
Technology " in deliver " A 0.6-V 45-nm adaptive
dual-rail SRAM compiler circuit design for lower VDDmin
VLSIs ", it is proposed that a kind of adaptive double track voltage strategy so that even if SRAM also can read and write operation under the running voltage of 0.6V.2009, O. Hirabayashi was at " IEEE International
Solid-State Circuits Conference (ISSCC) " deliver " process-variation-tolerant in meeting
dual-power-supply SRAM with 0.179-mm2 cell in 40-nm CMOS using
Level-programmable wordline driver ", it is proposed that a kind of bootstrapping or certainly fall word line voltage strategy, substantially increase the reading and writing operation tolerance limit of SRAM.2011, S. Mukhopadhyay delivered " SRAM write-ability in magazine " Transaction on VLSI "
Improvement with transient negative bitline voltage ", it is proposed that a kind of negative bit-line voltage householder method, effectively improve the read operation stability of SRAM.The stability problem operated for the reading and writing of SRAM, present invention also proposes a kind of negative bit-line voltage strategy to improve its operation tolerance limit.Unlike the negative bit-line voltage strategy used from S. Mukhopadhyay, the negative bit line of the present invention produces circuit and is not only suitable for the SRAM of difference, also is adapted for the SRAM of Single-end output equally.
Summary of the invention
It is an object of the invention to provide a kind of simple in construction, it is possible to the effective negative bit line voltage generation circuit producing negative bit-line voltage.
The negative bit line voltage generation circuit that the present invention provides, including:
One output phase inverter, its input, as the input of whole circuit, exports the output as whole circuit, but one end of the ground pin of its pulldown network and the drain electrode of a lower trombone slide NMOS tube and coupling electric capacity is connected.The source ground of lower trombone slide NMOS tube, and the drain electrode of grid and a preliminary filling PMOS and an electric discharge NMOS tube is connected.Wherein, the source electrode of preliminary filling PMOS is connected with power supply, and grid connects with input；The grid of electric discharge NMOS tube is connected with input, and source electrode but connects with the output of a low deflection phase inverter and the other end of coupling electric capacity.And the low input of deflection phase inverter is connected with the input of whole circuit.
The negative bit line voltage generation circuit that the present invention provides, simple in construction, it is possible to effective generation bears bit-line voltage.
Accompanying drawing explanation
Fig. 1 is the electrical block diagram of the present invention.
Fig. 2 is the operation chart that the present invention produces negative bit-line voltage.
Detailed description of the invention
The present invention describes a kind of negative bit line voltage generation circuit, the present invention is expanded on further below by way of example.
Fig. 1 show the negative bit line voltage generation circuit structure that the present invention realizes.PMOS M0, NMOS tube M1 constitutes output phase inverter, and input is Input, and output is Bitline, and the ground pin of NMOS tube M1 and the drain electrode of pull-down NMOS pipe M4 and coupling electric capacity C are connected, and their common node is 601.The source electrode of pull-down NMOS pipe M4 with ground connect, grid then with preliminary filling PMOS M3 and discharge NMOS tube M2 drain electrode connect, their common node is 603.Wherein, preliminary filling PMOS M3 is all connected with input Input with the grid of electric discharge NMOS tube M2, and the source electrode of preliminary filling PMOS M3 is connected with power supply, the source electrode of electric discharge NMOS tube M2 but connects with output and the coupling electric capacity C of deflection phase inverter INV, and their common node is 602.The input of deflection phase inverter is connected with Input.
Fig. 2 represents the operation signal of the negative bit line voltage generation circuit that the present invention realizes.Circuit input Input is initially located in low level state, and M1 turns off, and Bitline preliminary filling is high level by M0.Now, M3 is in opening, and M2 turns off, and node 603 is opened by preliminary filling to high level, M4, node 601 is pulled down to low level, and node 602 is then pulled up as high level by deflection phase inverter.When Input has one " 0 " to arrive the saltus step of " 1 ", and first M0 and M3 turns off, and M1 and M2 opens, and bit line Bitline is discharged by M1 and M4.Then, existence due to high deflection phase inverter, node 602 has one quick " 1 " to arrive the saltus step of " 0 ", and this quick saltus step is coupled electric capacity C and is coupled to node 601, makes node produce one " 0 " saltus step to negative voltage, and now, owing to M2 opens, node 603 can be pulled down to low level, turns off M4, so make node 601 can keep this negative voltage, be then transferred to Bitline by M1.When Input is from " 1 " rebound " 0 ", Bitline is high level by preliminary filling again, and other node also returns to initial state.
Claims (2)
1. a negative bit line voltage generation circuit, it is characterised in that including:
The output phase inverter that one PMOS and NMOS tube are constituted, its input Input is as the input of whole circuit, and output Bitline is as the output of whole circuit；One end of the ground pin of the pulldown network of NMOS tube and the drain electrode of a pull-down NMOS pipe and coupling electric capacity is connected, and they have a common node；The source ground of pull-down NMOS pipe, and the drain electrode of grid and a preliminary filling PMOS and an electric discharge NMOS tube is connected, they have a common node；Wherein, preliminary filling PMOS is all connected with input Input with the grid of electric discharge NMOS tube, and the source electrode of preliminary filling PMOS is connected with power supply, and the other end of the source electrode of electric discharge NMOS tube and the output of a low deflection phase inverter and coupling electric capacity connects, and they have a common node；The input of low deflection phase inverter is connected with the input Input of whole circuit.
Negative bit line voltage generation circuit the most according to claim 1, it is characterised in that: when input from low transition be high level time, output produce a negative value；When inputting rebound low level, output produces a normal high level voltage value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310494138.7A CN103578531B (en) | 2013-10-21 | 2013-10-21 | A kind of negative bit line voltage generation circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310494138.7A CN103578531B (en) | 2013-10-21 | 2013-10-21 | A kind of negative bit line voltage generation circuit |
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| CN103578531A CN103578531A (en) | 2014-02-12 |
| CN103578531B true CN103578531B (en) | 2016-09-28 |
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| CN201310494138.7A Active CN103578531B (en) | 2013-10-21 | 2013-10-21 | A kind of negative bit line voltage generation circuit |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1716448A (en) * | 2005-06-02 | 2006-01-04 | 复旦大学 | High speed low power consumption current sensitive amplifier |
| CN102136297A (en) * | 2011-04-02 | 2011-07-27 | 复旦大学 | Storage unit capable of controlling bit line oscillation amplitude for register file |
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2013
- 2013-10-21 CN CN201310494138.7A patent/CN103578531B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1716448A (en) * | 2005-06-02 | 2006-01-04 | 复旦大学 | High speed low power consumption current sensitive amplifier |
| CN102136297A (en) * | 2011-04-02 | 2011-07-27 | 复旦大学 | Storage unit capable of controlling bit line oscillation amplitude for register file |
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| CN103578531A (en) | 2014-02-12 |
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