TWI482154B - Single-ended load-free static random access memory - Google Patents
Single-ended load-free static random access memory Download PDFInfo
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- TWI482154B TWI482154B TW101144358A TW101144358A TWI482154B TW I482154 B TWI482154 B TW I482154B TW 101144358 A TW101144358 A TW 101144358A TW 101144358 A TW101144358 A TW 101144358A TW I482154 B TWI482154 B TW I482154B
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Description
本發明係有關於一種靜態隨機存取記憶體，特別係有關於一種可隔絕雜訊干擾之單端無載式靜態隨機存取記憶體單元。
The present invention relates to a static random access memory, and more particularly to a single-ended unloaded static random access memory cell capable of isolating noise interference.
請參閱第4圖，習知無載式靜態隨機存取記憶體200為雙端無載式架構，其具有一PMOS電晶體對210、一電性連接該PMOS電晶體對210之第一NMOS電晶體220及一電性連接該PMOS電晶體對210之第二NMOS電晶體230，該第一NMOS電晶體220之一端係電性連接一反位元線L1，且該第二NMOS電晶體230之一端係電性連接一位元線L2，由於NMOS電晶體直接電性連接於該反位元線L1與該位元線L2，因此習知無載式靜態隨機存取記憶體200極易受到該反位元線L1與該位元線L2之雜訊干擾而導致雜訊邊際(noise margin)降低。
Referring to FIG. 4, the conventional unloaded SRAM 200 is a double-ended unloaded architecture having a PMOS transistor pair 210 and a first NMOS device electrically connected to the PMOS transistor pair 210. The second NMOS transistor 230 is electrically connected to the second NMOS transistor 230 of the PMOS transistor pair 210. One end of the first NMOS transistor 220 is electrically connected to a reverse bit line L1, and the second NMOS transistor 230 is electrically connected. One end is electrically connected to one bit line L2. Since the NMOS transistor is directly electrically connected to the bit line L1 and the bit line L2, the conventional unloaded SRAM 200 is highly susceptible to the The noise interference between the anti-bit line L1 and the bit line L2 causes a noise margin to decrease.
本發明之主要目的係在於提供一種單端無載式靜態隨機存取記憶體，其包含至少一靜態隨機存取記憶體單元、一預放電電路、一反位元線及一位元線，該靜態隨機存取記憶體單元具有一第一電晶體、一第二電晶體、一第三電晶體、一第四電晶體及一防擾動電晶體，該第一電晶體之一第一端電性連接該第二電晶體之一第四端及該第四電晶體之一第七端，該第二電晶體之一第三端電性連接該第一電晶體之一第二端及該第三電晶體之一第五端，該第三電晶體之一第六端電性連接該第四電晶體之一第八端及該防擾動電晶體之一第九端，該反位元線電性連接該防擾動電晶體之一第十端及該預放電電路，該位元線電性連接該反位元線，單端式無載靜態隨機存取記憶體在寫入資料時，該第三電晶體及該第四電晶體所構成之迴圈電路能有效阻隔該反位元線於接地時對該靜態隨機存取記憶體單元所造成之雜訊干擾，此外，該防擾動電晶體能阻隔該反位元線對該靜態隨機存取記憶體單元所產生之擾動。
The main purpose of the present invention is to provide a single-ended unloaded SRAM comprising at least one SRAM cell, a pre-discharge circuit, an inverted bit line and a bit line. The SRAM cell has a first transistor, a second transistor, a third transistor, a fourth transistor, and an anti-disturbance transistor, and the first end of the first transistor is electrically Connecting a fourth end of the second transistor and a seventh end of the fourth transistor, wherein the third end of the second transistor is electrically connected to the second end of the first transistor and the third end a fifth end of the third transistor, the sixth end of the third transistor is electrically connected to one of the eighth ends of the fourth transistor and one of the ninth ends of the anti-disturbance transistor, the bit line electrical Connecting a tenth end of the anti-disturbance transistor and the pre-discharge circuit, the bit line is electrically connected to the anti-bit line, and the third-end unloaded SRAM is third when writing data The loop circuit formed by the transistor and the fourth transistor can effectively block the reverse bit line when grounded The static random access memory cell caused by the noise interference, in addition, the transistor tamperproof bit line can be separated from the reaction unit of the random access memory disturbances arising from static.
請參閱第1圖，其係本發明之一較佳實施例，一種單端無載式靜態隨機存取記憶體100，其包含複數個靜態隨機存取記憶體單元110、一預放電電路120、一反相器130、一反位元線BLB及一位元線BL，各該靜態隨機存取記憶體單元110具有一第一電晶體111、一第二電晶體112、一第三電晶體113、一第四電晶體114及一防擾動電晶體115，該第一電晶體111之一第一端111a電性連接該第二電晶體112之一第四端112b及該第四電晶體114之一第七端114a，該第二電晶體112之一第三端112a電性連接該第一電晶體111之一第二端111b及該第三電晶體113之一第五端113a，該第三電晶體113之一第六端113b電性連接該第四電晶體114之一第八端114b及該防擾動電晶體115之一第九端115a，該反位元線BLB電性連接該些靜態隨機存取記憶體單元110之該防擾動電晶體115之一第十端115b、該預放電電路120及該反相器130，且該位元線BL電性連接該反相器130，在本實施例中，該第一端111a、該第四端112b及該第七端114a係共接至一第一節點Qb
，且該第三端112a、該第二端111b及該第五端113a係共接至一第二節點Q。
請再參閱第1圖，各該靜態隨機存取記憶體單元110之該第一電晶體111及該第二電晶體112為具有高臨界電壓特性之PMOS電晶體對，該防擾動電晶體115為具有低臨界電壓特性之NMOS電晶體，且該第三電晶體113及該第四電晶體114為具有低臨界電壓特性之NMOS電晶體，該預放電電路120可為一NMOS電晶體，PMOS電晶體對係用於閂鎖資料，而該第三電晶體113及該第四電晶體114係用以傳輸資料，在本實施例中，該第一電晶體111之該第一端111a及該第二電晶體112之該第三端112a為閘極端，該第一電晶體111之該第二端111b、該第二電晶體112之該第四端112b、該第三電晶體113之該第五端113a、該第四電晶體114之該第七端114a及該防擾動電晶體115之該第九端115a為汲極端，且該第六端113b、該第四電晶體114之該第八端114b及該防擾動電晶體115之該第十端115b為源極端，此外，該反相器130具有一PMOS電晶體131及一NMOS電晶體132，該PMOS電晶體131之一閘極端131a、該NMOS電晶體132之一閘極端132a及該防擾動電晶體115之該第十端115b共接於該反位元線BLB，且該PMOS電晶體131之一汲極端131b及該NMOS電晶體132之一汲極端132b共接於該位元線BL。
關於本發明之作動敘述如下，請參閱第2圖，其係該單端無載式靜態隨機存取記憶體100之讀取資料(Read Access)時序圖，當輸入記憶體之位址為有效位址(ADDRi)時，該第三電晶體113之一閘極端WEB為低電位，該第四電晶體114之一閘極端WE及該防擾動電晶體115之一閘極端WL為高電位，故該第三電晶體113為關閉狀態，該第四電晶體114及該防擾動電晶體115為開啟狀態，並藉由關閉該預放電電路120，使該反位元線BLB為一浮接(floating)狀態，此時該第一節點Qb
之儲存值將經由該第四電晶體114及該防擾動電晶體115傳送至該反位元線BLB，再經由該反相器130輸送至該位元線BL，由於該第三電晶體113處於關閉狀態，因此可確保該第二節點Q之儲存值不會受到該反位元線BLB之擾動，習知靜態隨機存取記憶體在進行讀取及寫入資料時，很容易受到位元線的雜訊影響而導致其雜訊邊際(noise margin)降低，本發明藉由該反相器130隔絕該位元線BL的雜訊，因此該些靜態隨機存取記憶體單元110在讀取資料時不會受到該位元線BL之雜訊影響。
請參閱第3圖，其係該單端無載式靜態隨機存取記憶體100之寫入資料(Write Access)時序圖，當欲使該第二節點Q之寫入邏輯為1時，該第三電晶體113之一閘極端WEB為低電位，該第四電晶體114之一閘極端WE及該防擾動電晶體115之一閘極端WL為高電位，故該第三電晶體113為關閉狀態，該第四電晶體114及該防擾動電晶體115為開啟狀態，且該預放電電路120係開啟而使該反位元線BLB呈現一接地狀態，此時該第一節點Qb
之準位可經由該第四電晶體114、該防擾動電晶體115及該反位元線BLB放電至低電位，當該第一節點Qb
之準位為低電位時，可藉由啟動該第一電晶體111而使該第二節點Q為高準位，另外，當欲使該第二節點Q之寫入邏輯為0時，該第四電晶體114之一閘極端WE為低電位，該第三電晶體113之一閘極端WEB及該防擾動電晶體115之一閘極端WL為高電位，故該第四電晶體114為關閉狀態，該第三電晶體113及該防擾動電晶體115為開啟狀態，由於該第三電晶體113之該第六端113b電性連接至該第四電晶體114之該第八端114b而構成一迴圈電路，故此時該第二節點Q之準位可經由該第三電晶體113、該防擾動電晶體115及該反位元線BLB放電至低電位，該迴圈電路可有效阻隔該反位元線BLB於接地時對該些靜態隨機存取記憶體單元110所造成之共模雜訊(common mode noise)干擾，此外，該防擾動電晶體115能阻隔來自該反位元線BLB對該些靜態隨機存取記憶體單元110所產生之擾動。
本發明之該靜態隨機存取記憶體單元110於讀取資料時可藉由該反相器130阻絕該位元線BL對該靜態隨機存取記憶體單元110所產生之擾動，於寫入資料時可藉由該第三電晶體113及該第四電晶體114所構成之迴圈電路阻隔該反位元線BLB對該些靜態隨機存取記憶體單元110所造成之共模雜訊，此外，該防擾動電晶體115能阻隔該反位元線BLB對該些靜態隨機存取記憶體單元110所產生之擾動，由於該些靜態隨機存取記憶體單元110抗雜訊能力有效增加，能操作於低電壓而不受雜訊干擾，故能降低該些靜態隨機存取記憶體單元110之功率消耗，另外，由於該單端無載式靜態隨機存取記憶體100僅使用五顆MOS電晶體，因此所使用之記憶體面積及成本可大幅下降。
本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。
Referring to FIG. 1 , a single-ended unloaded SRAM 100 includes a plurality of SRAM cells 110 , a pre-discharge circuit 120 , and a preferred embodiment of the present invention. An inverter 130, a reverse bit line BLB and a bit line BL, each of the SRAM cells 110 has a first transistor 111, a second transistor 112, and a third transistor 113. a fourth transistor 114 and an anti-disturbing transistor 115. The first end 111a of the first transistor 111 is electrically connected to the fourth end 112b of the second transistor 112 and the fourth transistor 114. a third end 114a, the third end 112a of the second transistor 112 is electrically connected to the second end 111b of the first transistor 111 and the fifth end 113a of the third transistor 113, the third The sixth end 113b of the transistor 113 is electrically connected to one of the eighth end 114b of the fourth transistor 114 and the ninth end 115a of the anti-disturbance transistor 115. The inverted bit line BLB is electrically connected to the static a tenth end 115b of the anti-disturbance transistor 115 of the random access memory unit 110, the pre-discharge circuit 120, and the inverter 130, The first bit 111a, the fourth end 112b, and the seventh end 114a are connected to a first node Q b , and the first end 111 a , the fourth end 112 b , and the seventh end 114 a are connected to a first node Q b , and The third end 112a, the second end 111b and the fifth end 113a are connected to a second node Q.
Referring to FIG. 1 again, the first transistor 111 and the second transistor 112 of each of the SRAM cells 110 are PMOS transistor pairs having high threshold voltage characteristics, and the anti-disturbance transistor 115 is An NMOS transistor having a low threshold voltage characteristic, and the third transistor 113 and the fourth transistor 114 are NMOS transistors having a low threshold voltage characteristic, and the pre-discharge circuit 120 can be an NMOS transistor, a PMOS transistor The pair is used for latching data, and the third transistor 113 and the fourth transistor 114 are used for transmitting data. In this embodiment, the first end 111a and the second of the first transistor 111 are The third end 112a of the transistor 112 is a gate terminal, the second end 111b of the first transistor 111, the fourth end 112b of the second transistor 112, and the fifth end of the third transistor 113 The seventh end 114a of the fourth transistor 114 and the ninth end 115a of the anti-disturbance transistor 115 are 汲 extremes, and the sixth end 113b and the eighth end 114b of the fourth transistor 114 And the tenth end 115b of the anti-disturbance transistor 115 is a source terminal, and further, the inverter 130 has a PMO The S transistor 131 and an NMOS transistor 132, the gate terminal 131a of the PMOS transistor 131, the gate terminal 132a of the NMOS transistor 132, and the tenth terminal 115b of the anti-disturbance transistor 115 are connected to the opposite end. The bit line BLB, and one of the PMOS transistors 131 and the one of the NMOS transistors 132 are connected to the bit line BL.
The operation of the present invention is described below. Please refer to FIG. 2, which is a read access timing diagram of the single-ended unloaded SRAM 100. When the address of the input memory is a valid bit. At the address (ADDRi), one gate terminal WEB of the third transistor 113 is at a low potential, and one gate terminal WE of the fourth transistor 114 and one gate terminal WL of the anti-disturbance transistor 115 are at a high potential, so The third transistor 113 is in a closed state, the fourth transistor 114 and the anti-disturbing transistor 115 are in an on state, and the epipolar line BLB is floated by turning off the pre-discharge circuit 120. a state in which the stored value of the first node Q b is transmitted to the inverted bit line BLB via the fourth transistor 114 and the anti-disturbing transistor 115, and then sent to the bit line via the inverter 130. BL, since the third transistor 113 is in a closed state, it can be ensured that the stored value of the second node Q is not disturbed by the inverse bit line BLB, and the conventional static random access memory is reading and writing. When entering data, it is easy to be affected by the noise of the bit line and cause its noise margin (nois In the present invention, the inverter 130 isolates the noise of the bit line BL, so the static random access memory cells 110 are not affected by the bit line BL when reading data. News impact.
Please refer to FIG. 3 , which is a write access timing diagram of the single-ended unloaded SRAM 100. When the write logic of the second node Q is to be 1, the One gate terminal WEB of the three transistor 113 is at a low potential, and one gate terminal WE of the fourth transistor 114 and one gate terminal WL of the anti-disturbance transistor 115 are at a high potential, so the third transistor 113 is turned off. The fourth transistor 114 and the anti-disturbing transistor 115 are in an on state, and the pre-discharge circuit 120 is turned on to cause the inverted bit line BLB to assume a ground state. At this time, the first node Q b is at the level. The fourth transistor 114, the anti-disturbing transistor 115, and the inverted bit line BLB can be discharged to a low potential. When the level of the first node Q b is low, the first power can be activated. The crystal 111 causes the second node Q to be at a high level. In addition, when the write logic of the second node Q is to be 0, the gate terminal WE of the fourth transistor 114 is low, and the third One gate terminal WEB of the transistor 113 and one gate terminal WL of the anti-disturbance transistor 115 are at a high potential, so the fourth transistor 114 is turned off. In a state, the third transistor 113 and the anti-disturbing transistor 115 are in an open state, and the sixth end 113b of the third transistor 113 is electrically connected to the eighth end 114b of the fourth transistor 114. a loop circuit, so that the level of the second node Q can be discharged to a low potential via the third transistor 113, the anti-disturbing transistor 115 and the inverted bit line BLB, and the loop circuit can effectively block the The anti-bit line BLB interferes with the common mode noise caused by the static random access memory cells 110 when grounded. In addition, the anti-disturbing transistor 115 can block the BLB from the inverted bit line. Disturbances generated by the SRAM cells 110.
The SRAM cell 110 of the present invention can block the disturbance generated by the bit line BL on the SRAM cell 110 when the data is read, and write the data to the static random access memory unit 110. The loop circuit formed by the third transistor 113 and the fourth transistor 114 blocks the common mode noise caused by the inverted bit line BLB to the static random access memory cells 110. The anti-disturbing transistor 115 can block the interference generated by the anti-bit line BLB on the SRAM cells 110, and the anti-noise capability of the SRAM cells 110 can be effectively increased. Operating at a low voltage without interference of noise, the power consumption of the SRAM cells 110 can be reduced. In addition, since the single-ended unloaded SRAM 100 uses only five MOS devices. Crystals, so the memory area and cost used can be greatly reduced.
The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .
100．．．單端無載式靜態隨機存取記憶體100. . . Single-ended unloaded static random access memory
110．．．靜態隨機存取記憶體單元110. . . Static random access memory unit
111．．．第一電晶體111. . . First transistor
111a．．．第一端111a. . . First end
111b．．．第二端111b. . . Second end
112．．．第二電晶體112. . . Second transistor
112a．．．第三端112a. . . Third end
112b．．．第四端112b. . . Fourth end
113．．．第三電晶體113. . . Third transistor
113a．．．第五端113a. . . Fifth end
113b．．．第六端113b. . . Sixth end
114．．．第四電晶體114. . . Fourth transistor
114a．．．第七端114a. . . Seventh end
114b．．．第八端114b. . . Eighth end
115．．．防擾動電晶體115. . . Anti-disturbance transistor
115a．．．第九端115a. . . Ninth end
115b．．．第十端115b. . . Tenth end
120．．．預放電電路120. . . Pre-discharge circuit
130．．．反相器130. . . inverter
131．．．PMOS電晶體131. . . PMOS transistor
131a．．．閘極端131a. . . Gate extreme
131b．．．汲極端131b. . . Extreme
132．．．NMOS電晶體132. . . NMOS transistor
132a．．．閘極端132a. . . Gate extreme
132b．．．汲極端132b. . . Extreme
200．．．靜態隨機存取記憶體200. . . Static random access memory
210．．．PMOS電晶體對210. . . PMOS transistor pair
220．．．第一NMOS電晶體220. . . First NMOS transistor
230．．．第二NMOS電晶體230. . . Second NMOS transistor
BLB．．．反位元線BLB. . . Inverse bit line
BL．．．位元線BL. . . Bit line
Qb ．．．第一節點Q b . . . First node
Q．．．第二節點Q. . . Second node
L1．．．反位元線L1. . . Inverse bit line
L2．．．位元線L2. . . Bit line
第1圖：依據本發明之一較佳實施例，一種單端無載式靜態隨機存取記憶體之電路圖。
第2圖：依據本發明之一較佳實施例，該單端無載式靜態隨機存取記憶體之讀取時序圖。
第3圖：依據本發明之一較佳實施例，該單端無載式靜態隨機存取記憶體之寫入時序圖。
第4圖：習知靜態隨機存取記憶體之電路圖。
1 is a circuit diagram of a single-ended unloaded SRAM in accordance with a preferred embodiment of the present invention.
2 is a timing chart of reading of the single-ended unloaded SRAM according to a preferred embodiment of the present invention.
Figure 3 is a timing chart of the writing of the single-ended unloaded SRAM according to a preferred embodiment of the present invention.
Figure 4: Circuit diagram of a conventional static random access memory.
100．．．單端無載式靜態隨機存取記憶體100. . . Single-ended unloaded static random access memory
110．．．靜態隨機存取記憶體單元110. . . Static random access memory unit
111．．．第一電晶體111. . . First transistor
111a．．．第一端111a. . . First end
111b．．．第二端111b. . . Second end
112．．．第二電晶體112. . . Second transistor
112a．．．第三端112a. . . Third end
112b．．．第四端112b. . . Fourth end
113．．．第三電晶體113. . . Third transistor
113a．．．第五端113a. . . Fifth end
113b．．．第六端113b. . . Sixth end
114．．．第四電晶體114. . . Fourth transistor
114a．．．第七端114a. . . Seventh end
114b．．．第八端114b. . . Eighth end
115．．．防擾動電晶體115. . . Anti-disturbance transistor
115a．．．第九端115a. . . Ninth end
115b．．．第十端115b. . . Tenth end
120．．．預放電電路120. . . Pre-discharge circuit
130．．．反相器130. . . inverter
131．．．PMOS電晶體131. . . PMOS transistor
131a．．．閘極端131a. . . Gate extreme
131b．．．汲極端131b. . . Extreme
132．．．NMOS電晶體132. . . NMOS transistor
132a．．．閘極端132a. . . Gate extreme
132b．．．汲極端132b. . . Extreme
BLB．．．反位元線BLB. . . Inverse bit line
BL．．．位元線BL. . . Bit line
Qb ．．．第一節點Q b . . . First node
Q．．．第二節點Q. . . Second node
Claims (7)
至少一靜態隨機存取記憶體單元，其具有一第一電晶體、一第二電晶體、一第三電晶體、一第四電晶體及一防擾動電晶體，該第一電晶體之一第一端電性連接該第二電晶體之一第四端及該第四電晶體之一第七端，該第二電晶體之一第三端電性連接該第一電晶體之一第二端及該第三電晶體之一第五端，該第三電晶體之一第六端電性連接該第四電晶體之一第八端及該防擾動電晶體之一第九端；
一預放電電路；
一反位元線，其電性連接該防擾動電晶體之一第十端及該預放電電路，該第三電晶體及該第四電晶體所構成之迴圈電路能阻隔該反位元線對該靜態隨機存取記憶體單元所造成之雜訊，且該防擾動電晶體能阻隔該反位元線對該靜態隨機存取記憶體單元所產生之擾動；以及
一位元線，其電性連接該反位元線。A single-ended unloaded static random access memory, comprising:
At least one static random access memory cell having a first transistor, a second transistor, a third transistor, a fourth transistor, and an anti-disturbing transistor, the first transistor One end of the second transistor is electrically connected to the fourth end of the second transistor, and the third end of the second transistor is electrically connected to the second end of the first transistor. And a fifth end of the third transistor, the sixth end of the third transistor is electrically connected to one of the eighth ends of the fourth transistor and one of the ninth ends of the anti-disturbance transistor;
a pre-discharge circuit;
An anti-bit line electrically connected to one of the tenth end of the anti-disturbing transistor and the pre-discharge circuit, wherein the third transistor and the fourth transistor form a loop circuit capable of blocking the bit line The noise caused by the SRAM cell, and the anti-disturbing transistor can block the interference generated by the inverse bit line to the SRAM cell; and one bit line, the electric Sexually connect the inverse bit line.
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| TW101144358A TWI482154B (en) | 2012-11-27 | 2012-11-27 | Single-ended load-free static random access memory |
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| TWI689925B (en) * | 2018-11-06 | 2020-04-01 | 國立中山大學 | Single-ended undisturbed sram |
| TWI757190B (en) * | 2021-05-25 | 2022-03-01 | 國立中山大學 | Static random access memory |
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| TWI757190B (en) * | 2021-05-25 | 2022-03-01 | 國立中山大學 | Static random access memory |
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| TW201421473A (en) | 2014-06-01 |
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