TWI688121B - Light emitting diode structure - Google Patents

Light emitting diode structure Download PDF

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TWI688121B
TWI688121B TW107129676A TW107129676A TWI688121B TW I688121 B TWI688121 B TW I688121B TW 107129676 A TW107129676 A TW 107129676A TW 107129676 A TW107129676 A TW 107129676A TW I688121 B TWI688121 B TW I688121B
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layer
width
emitting diode
light
maximum
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TW107129676A
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TW202010152A (en
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郭修邑
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隆達電子股份有限公司
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Priority to TW107129676A priority Critical patent/TWI688121B/en
Priority to CN201910500322.5A priority patent/CN110858617B/en
Priority to JP2019139900A priority patent/JP2020031210A/en
Priority to US16/541,132 priority patent/US10944034B2/en
Publication of TW202010152A publication Critical patent/TW202010152A/en
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Publication of TWI688121B publication Critical patent/TWI688121B/en
Priority to JP2020175273A priority patent/JP7183235B2/en
Priority to US17/134,549 priority patent/US11430935B2/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22Roughened surfaces, e.g. at the interface between epitaxial layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40Materials therefor
    • H01L33/42Transparent materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52Encapsulations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58Optical field-shaping elements
    • H01L33/60Reflective elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008Processes
    • H01L2933/0033Processes relating to semiconductor body packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483Containers
    • H01L33/486Containers adapted for surface mounting

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  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

A light emitting diode includes a base layer, an electric contact layer, a semiconductor stack, and an insulation layer. The base layer has a maximum first width. The electric contact layer has a maximum second width and is disposed on the dielectric layer. The semiconductor stack has a maximum third width and is disposed on the electric contact layer. The semiconductor stack includes a first type semiconductor layer, a light emitting layer, and a second type semiconductor layer stacked in sequence, wherein a width of the first type semiconductor layer, the light emitting layer, and the second type semiconductor layer substantially smaller than or equal to the maximum third width. The insulation layer covers at least one sidewall of the base layer, one sidewall of the electric contact layer, and one sidewall of the semiconductor stack. The maximum second width is greater than the maximum third width, and the maximum second width is less than or equal to the maximum first width.

Description

發光二極體結構 Light emitting diode structure

本發明是有關一種發光二極體結構。 The invention relates to a light-emitting diode structure.

微發光二極體(micro light emitting diode,micro LED)是將傳統發光二極體的尺寸降至微米(μm)等級,且目標良率需達到99%以上。然而,微發光二極體製程目前面臨相當多的技術挑戰,其中巨量轉移(Mass Transfer)技術是最困難的關鍵製程。此外,更包括設備的精密度、轉移良率、轉移時間、對位問題、可重工性(rework property)及加工成本等諸多技術難題亟需解決。 The micro light emitting diode (micro LED) is to reduce the size of the traditional light emitting diode to the micrometer (μm) level, and the target yield must reach more than 99%. However, the micro-luminescence diode process currently faces quite a few technical challenges, among which Mass Transfer technology is the most difficult key process. In addition, many technical problems, including precision of equipment, transfer yield, transfer time, alignment problems, rework property and processing cost, need to be solved urgently.

舉例來說,目前用來製造微發光二極體的技術是由製程定義出微發光二極體結構後,將此微發光二極體結構接合至第一暫時基板,並透過雷射剝離(laser lift-off,LLO)技術將藍寶石(Sapphire)基板移除,再使用接合材料將此微發光二極體結構接合到第二暫時基板。接著,移除第一暫時基板並製作支架結構後,蝕刻接合材料,最後移轉微發光二極體結構中的磊晶結構。上述過程中需經過兩次暫時基板的接合及兩次移除暫時基板的製 程,除了良率損失不好控制外,磊晶結構在應力釋放後,微發光二極體之間的間距也會和原先設計的不同,造成移轉時的對位問題。 For example, the current technology used to manufacture micro-luminescent diodes is to define the micro-luminescent diode structure from the manufacturing process, and then join the micro-luminescent diode structure to the first temporary substrate, and peel it through the laser (laser Lift-off (LLO) technology removes the sapphire substrate, and then uses the bonding material to bond the micro-luminescent diode structure to the second temporary substrate. Next, after removing the first temporary substrate and fabricating the support structure, the bonding material is etched, and finally the epitaxial structure in the micro-light emitting diode structure is transferred. In the above process, two temporary substrate joints and two temporary substrate removal processes are required Cheng, in addition to poor yield loss control, after the stress of the epitaxial structure is released, the spacing between the microluminescent diodes will also be different from the original design, causing alignment problems during transfer.

本發明之一態樣係提供一種發光二極體結構,其包含基底層、電性接觸層、半導體疊層以及絕緣層。基底層具有最大第一寬度。電性接觸層具有最大第二寬度並設置於基底層上。半導體疊層具有最大第三寬度並設置於電性接觸層上。半導體疊層包括第一型半導體層、發光層及第二型半導體層依序堆疊,其中第一型半導體層、發光層及第二型半導體層的寬度實質上皆小於或等於最大第三寬度。絕緣層至少覆蓋基底層之一側壁、電性接觸層之一側壁及半導體疊層之一側壁。最大第二寬度大於最大第三寬度,且最大第二寬度小於或等於最大第一寬度。 One aspect of the present invention provides a light-emitting diode structure that includes a base layer, an electrical contact layer, a semiconductor stack, and an insulating layer. The base layer has the largest first width. The electrical contact layer has a maximum second width and is disposed on the base layer. The semiconductor stack has a maximum third width and is disposed on the electrical contact layer. The semiconductor stack includes a first-type semiconductor layer, a light-emitting layer, and a second-type semiconductor layer that are sequentially stacked, wherein the widths of the first-type semiconductor layer, the light-emitting layer, and the second-type semiconductor layer are substantially less than or equal to the maximum third width. The insulating layer covers at least one side wall of the base layer, one side wall of the electrical contact layer and one side wall of the semiconductor stack. The maximum second width is greater than the maximum third width, and the maximum second width is less than or equal to the maximum first width.

根據本發明某些實施方式,電性接觸層為單層。最大第二寬度實質上等於最大第一寬度。 According to some embodiments of the present invention, the electrical contact layer is a single layer. The maximum second width is substantially equal to the maximum first width.

根據本發明某些實施方式,電性接觸層包括一歐姆接觸層及一第一金屬層。歐姆接觸層具有最大第四寬度並設置於半導體疊層與基底層之間,且第一金屬層具有最大第五寬度並設置於歐姆接觸層與基底層之間。最大第四寬度小於或實質上等於最大第一寬度,且最大第五寬度實質上等於最大第一寬度。 According to some embodiments of the present invention, the electrical contact layer includes an ohmic contact layer and a first metal layer. The ohmic contact layer has a maximum fourth width and is disposed between the semiconductor stack and the base layer, and the first metal layer has a maximum fifth width and is disposed between the ohmic contact layer and the base layer. The maximum fourth width is less than or substantially equal to the maximum first width, and the maximum fifth width is substantially equal to the maximum first width.

根據本發明某些實施方式,最大第四寬度實質 上等於最大第三寬度。 According to some embodiments of the invention, the maximum fourth width is substantially Upper is equal to the maximum third width.

根據本發明某些實施方式,此發光二極體結構更包含一電極層設置於半導體疊層上。 According to some embodiments of the present invention, the light emitting diode structure further includes an electrode layer disposed on the semiconductor stack.

根據本發明某些實施方式,電極層可被發光層所發出的光穿透。 According to some embodiments of the present invention, the electrode layer may be penetrated by light emitted by the light emitting layer.

根據本發明某些實施方式,電極層為第二金屬層。 According to some embodiments of the present invention, the electrode layer is a second metal layer.

根據本發明某些實施方式,基底層包含介電材料或金屬材料。 According to some embodiments of the present invention, the base layer includes a dielectric material or a metal material.

根據本發明某些實施方式,基底層包含一分散式布拉格反射鏡(Distributed Bragg Reflector),且該絕緣層至少覆蓋該分散式布拉格反射鏡之一側壁。 According to some embodiments of the present invention, the base layer includes a distributed Bragg reflector (Distributed Bragg Reflector), and the insulating layer covers at least one side wall of the distributed Bragg reflector.

根據本發明某些實施方式,當基底層包含分散式布拉格反射鏡時,電性接觸層可被發光層所發出的光穿透。 According to some embodiments of the present invention, when the base layer includes a decentralized Bragg reflector, the electrical contact layer may be penetrated by light emitted by the light emitting layer.

本發明另一態樣係提供一種發光二極體結構,其包含半導體疊層、絕緣層、第一導電墊、第二導電墊以及支撐區域。半導體疊層由上而下依序包括第一型半導體層、發光層及第二型半導體層,其中第二型半導體層包含第一部分和第二部分,且第一部分位於第二部分上。第二部分的最大寬度大於第一部分的最大寬度。絕緣層覆蓋半導體疊層的側壁以及第二部分的上表面,且絕緣層具有第一開口及第二開口分別位於第一型半導體層及第二部分上。第一導電墊藉由第一開口電性連接至第一型半導體 層。第二導電墊藉由第二開口電性連接至第二部分。支撐區域位於絕緣層上方且位於第一導電墊與第二導電墊之間。 Another aspect of the present invention provides a light emitting diode structure that includes a semiconductor stack, an insulating layer, a first conductive pad, a second conductive pad, and a support region. The semiconductor stack includes a first type semiconductor layer, a light emitting layer, and a second type semiconductor layer in order from top to bottom, wherein the second type semiconductor layer includes a first portion and a second portion, and the first portion is located on the second portion. The maximum width of the second part is greater than the maximum width of the first part. The insulating layer covers the side wall of the semiconductor stack and the upper surface of the second portion, and the insulating layer has a first opening and a second opening on the first type semiconductor layer and the second portion, respectively. The first conductive pad is electrically connected to the first type semiconductor through the first opening Floor. The second conductive pad is electrically connected to the second part through the second opening. The supporting area is located above the insulating layer and between the first conductive pad and the second conductive pad.

根據本發明某些實施方式,上述發光二極體結構更包含一固晶基板,其電性對接第一導電墊和第二導電墊。 According to some embodiments of the present invention, the light-emitting diode structure further includes a solid crystal substrate electrically connected to the first conductive pad and the second conductive pad.

根據本發明某些實施方式,上述發光二極體結構更包含第一黏著層以及第二黏著層。第一黏著層位於第一導電墊與固晶基板之間,而第二黏著層位於第二導電墊與固晶基板之間,第一黏著層與第二黏著層之間電性絕緣。 According to some embodiments of the present invention, the light emitting diode structure further includes a first adhesive layer and a second adhesive layer. The first adhesive layer is located between the first conductive pad and the solid crystal substrate, and the second adhesive layer is located between the second conductive pad and the solid crystal substrate, and the first adhesive layer and the second adhesive layer are electrically insulated.

根據本發明某些實施方式,此發光二極體結構更包含一電極層設置於第一型半導體層與第一導電墊之間。 According to some embodiments of the present invention, the light emitting diode structure further includes an electrode layer disposed between the first type semiconductor layer and the first conductive pad.

根據本發明某些實施方式,上述發光二極體結構更包含一導電塊設置於第二開口中,且第二導電墊覆蓋導電塊的頂表面及側壁。 According to some embodiments of the present invention, the light-emitting diode structure further includes a conductive block disposed in the second opening, and the second conductive pad covers the top surface and the side wall of the conductive block.

根據本發明某些實施方式,位於第二型半導體層之第一部分上之絕緣層的頂表面與導電塊的頂表面實質上齊平。 According to some embodiments of the present invention, the top surface of the insulating layer on the first portion of the second type semiconductor layer is substantially flush with the top surface of the conductive block.

根據本發明某些實施方式,第一導電墊延伸覆蓋絕緣層的一部分。 According to some embodiments of the present invention, the first conductive pad extends to cover a portion of the insulating layer.

根據本發明某些實施方式,第一導電墊的頂表面與第二導電墊的頂表面實質上齊平。 According to some embodiments of the present invention, the top surface of the first conductive pad is substantially flush with the top surface of the second conductive pad.

根據本發明某些實施方式,第二型半導體層具 有暴露在外之一表面,且該表面具有一粗糙紋理。 According to some embodiments of the present invention, the second type semiconductor layer has There is a surface exposed outside, and the surface has a rough texture.

10、20、30‧‧‧發光二極體結構 10, 20, 30 ‧‧‧ LED structure

40、50、60‧‧‧前驅結構 40, 50, 60 ‧‧‧ precursor structure

110‧‧‧基底層 110‧‧‧ Basement

120‧‧‧電性接觸層 120‧‧‧Electrical contact layer

122‧‧‧第一金屬層 122‧‧‧First metal layer

124‧‧‧歐姆接觸層 124‧‧‧ohm contact layer

130‧‧‧半導體疊層 130‧‧‧semiconductor stack

132‧‧‧第一型半導體層 132‧‧‧Type 1 semiconductor layer

134‧‧‧發光層 134‧‧‧luminous layer

136‧‧‧第二型半導體層 136‧‧‧Type 2 semiconductor layer

136a‧‧‧第一部分 136a‧‧‧Part I

136b‧‧‧第二部分 136b‧‧‧Part II

140‧‧‧絕緣層 140‧‧‧Insulation

140a‧‧‧第一開口 140a‧‧‧First opening

140b‧‧‧第二開口 140b‧‧‧Second opening

140t‧‧‧頂表面 140t‧‧‧Top surface

150‧‧‧電極層 150‧‧‧electrode layer

160‧‧‧黏著層 160‧‧‧adhesive layer

162‧‧‧第一黏著層 162‧‧‧The first adhesive layer

164‧‧‧第二黏著層 164‧‧‧Second adhesive layer

170‧‧‧固晶基板 170‧‧‧Solid crystal substrate

180‧‧‧導電塊 180‧‧‧conductive block

180t‧‧‧頂表面 180t‧‧‧Top surface

180s‧‧‧側壁 180s‧‧‧Side wall

192‧‧‧第一導電墊 192‧‧‧First conductive pad

192t‧‧‧頂表面 192t‧‧‧Top surface

194‧‧‧第二導電墊 194‧‧‧Second conductive pad

194t‧‧‧頂表面 194t‧‧‧Top surface

310‧‧‧生長基板 310‧‧‧Growth substrate

320‧‧‧磊晶疊層 320‧‧‧ Epilayer

320’‧‧‧半導體疊層 320’‧‧‧ semiconductor stack

320”‧‧‧剩餘的半導體疊層 320”‧‧‧ remaining semiconductor stack

326‧‧‧第二型半導體層 326‧‧‧Second type semiconductor layer

326’‧‧‧剩餘的第二型半導體層 326’‧‧‧ remaining second type semiconductor layer

326a‧‧‧第一部分 326a‧‧‧Part I

326a’‧‧‧剩餘的第一部分 326a’‧‧‧The remaining first part

326b‧‧‧第二部分 326b‧‧‧Part II

326b’‧‧‧剩餘的第二部分 326b’‧‧‧The remaining second part

326s‧‧‧表面 326s‧‧‧surface

322‧‧‧第一型半導體層 322‧‧‧Type 1 semiconductor layer

324‧‧‧發光層 324‧‧‧luminous layer

328‧‧‧未摻雜半導體層 328‧‧‧ undoped semiconductor layer

330‧‧‧歐姆接觸層 330‧‧‧ohm contact layer

330’‧‧‧剩餘的歐姆接觸層 330’‧‧‧ remaining ohmic contact layer

330’a‧‧‧暴露的部分 330’a‧‧‧ exposed part

332‧‧‧金屬層 332‧‧‧Metal layer

332’‧‧‧剩餘的金屬層 332’‧‧‧ remaining metal layer

332’a‧‧‧暴露的部分 332’a‧‧‧ exposed part

340a、340b‧‧‧基底層 340a, 340b ‧‧‧ base layer

340a’、340b’‧‧‧剩餘的基底層 340a’, 340b’‧‧‧ remaining base layer

350‧‧‧犧牲層 350‧‧‧Sacrifice

350R‧‧‧開口 350R‧‧‧Opening

350a‧‧‧犧牲層頂表面的一部分 350a‧‧‧Part of the top surface of the sacrificial layer

350P‧‧‧暴露的部分 350P‧‧‧Exposed part

352‧‧‧開口 352‧‧‧ opening

360‧‧‧承載基板 360‧‧‧Bearing substrate

370‧‧‧電極層 370‧‧‧electrode layer

370’‧‧‧剩餘的電極層 370’‧‧‧ remaining electrode layer

380‧‧‧絕緣層 380‧‧‧Insulation

380a‧‧‧第一部分 380a‧‧‧Part 1

380b‧‧‧第二部分 380b‧‧‧Part II

380t‧‧‧頂表面 380t‧‧‧Top surface

380R1‧‧‧第一開口 380R1‧‧‧First opening

380R2‧‧‧第二開口 380R2‧‧‧Second opening

382‧‧‧支撐架 382‧‧‧Support frame

382P‧‧‧轉折位置處 382P‧‧‧turning position

390‧‧‧導電塊 390‧‧‧Conducting block

390t‧‧‧頂表面 390t‧‧‧Top surface

390s‧‧‧側壁 390s‧‧‧Side wall

410‧‧‧支撐層 410‧‧‧support layer

412‧‧‧支撐架 412‧‧‧Support frame

420‧‧‧黏著層 420‧‧‧ adhesive layer

432‧‧‧第一導電墊 432‧‧‧The first conductive pad

434‧‧‧第二導電墊 434‧‧‧Second conductive pad

SP‧‧‧支撐區域 SP‧‧‧Support area

A-A’、B-B’‧‧‧線段 Line segment A-A’, B-B’‧‧‧

W1、W2、W3、W4、W5‧‧‧最大寬度 W1, W2, W3, W4, W5 ‧‧‧ maximum width

為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之詳細說明如下:第1A及1B圖繪示根據本發明多個實施方式之發光二極體結構的剖面示意圖。 In order to make the above and other objects, features, advantages and examples of the present invention more obvious and understandable, the drawings are described in detail as follows: FIGS. 1A and 1B illustrate light emitting diodes according to various embodiments of the present invention A schematic cross-sectional view of the structure.

第2圖繪示根據本發明另一實施方式之發光二極體結構的剖面示意圖。 FIG. 2 is a schematic cross-sectional view of a light emitting diode structure according to another embodiment of the invention.

第3圖繪示根據本發明又一實施方式之發光二極體結構的剖面示意圖。 FIG. 3 is a schematic cross-sectional view of a light emitting diode structure according to another embodiment of the invention.

第4圖至第11B圖繪示根據本發明一實施方式之製造發光二極體結構於各階段的剖面示意圖。 4 to 11B are schematic cross-sectional views at various stages of manufacturing a light-emitting diode structure according to an embodiment of the present invention.

第12圖繪示根據本發明一實施方式之發光二極體結構於其中一製造階段的上視圖。 FIG. 12 is a top view of a light-emitting diode structure according to an embodiment of the invention at one of the manufacturing stages.

第13圖至第15圖繪示發光二極體結構於多個製造階段中根據第12圖線段A-A’的剖面示意圖。 13 to 15 are schematic cross-sectional views of the light-emitting diode structure according to the line segment A-A' of FIG. 12 in multiple manufacturing stages.

第16A圖和第16B圖繪示發光二極體結構於其中一製造階段中根據第12圖線段B-B’的剖面示意圖。 16A and 16B are schematic cross-sectional views of the light-emitting diode structure according to the line segment B-B' of FIG. 12 in one of the manufacturing stages.

第17圖至第25圖繪示根據本發明另一實施方式之製造發光二極體結構於各階段的剖面示意圖。 17 to 25 are schematic cross-sectional views at various stages of manufacturing a light-emitting diode structure according to another embodiment of the present invention.

第26圖至第34圖繪示根據本發明另一實施方式之製造發光二極體結構於各階段的剖面示意圖。 26 to 34 are schematic cross-sectional views at various stages of manufacturing a light-emitting diode structure according to another embodiment of the present invention.

第35圖繪示根據本發明另一實施方式之發光二極體結 構於其中一製造階段的上視圖。 FIG. 35 shows a light emitting diode junction according to another embodiment of the invention Constructed in a top view of one of the manufacturing stages.

第36圖至第38A圖繪示發光二極體結構於多個製造階段中根據第35圖線段A-A’的剖面示意圖。 FIGS. 36 to 38A are schematic cross-sectional views of the light-emitting diode structure according to the line segment A-A' of FIG. 35 in multiple manufacturing stages.

第38B圖繪示發光二極體結構於其中一製造階段中根據第35圖線段B-B’的剖面示意圖。 FIG. 38B is a schematic cross-sectional view of the light-emitting diode structure according to the line B-B' of FIG. 35 in one of the manufacturing stages.

第39圖至第50圖繪示根據本發明又一實施方式之製造發光二極體結構於各階段的剖面示意圖。 39 to 50 are schematic cross-sectional views at various stages of manufacturing a light-emitting diode structure according to yet another embodiment of the present invention.

為了使本揭示內容的敘述更加詳盡與完備,下文針對了本發明的實施態樣與具體實施例提出了說明性的描述;但這並非實施或運用本發明具體實施例的唯一形式。以下所揭露的各實施例,在有益的情形下可相互組合或取代,也可在一實施例中附加其他的實施例,而無須進一步的記載或說明。 In order to make the description of this disclosure more detailed and complete, the following provides an illustrative description of the implementation form and specific embodiments of the present invention; however, this is not the only form for implementing or using specific embodiments of the present invention. The embodiments disclosed below can be combined or replaced with each other under beneficial circumstances, and other embodiments can be added to an embodiment without further description or description.

在以下描述中,將詳細敘述許多特定細節以使讀者能夠充分理解以下的實施例。然而,可在無此等特定細節之情況下實踐本發明之實施例。在其他情況下,為簡化圖式,熟知的結構與裝置僅示意性地繪示於圖中。 In the following description, many specific details will be described in detail to enable the reader to fully understand the following embodiments. However, embodiments of the invention may be practiced without these specific details. In other cases, to simplify the drawings, well-known structures and devices are only schematically shown in the drawings.

第1A和1B圖繪示根據本發明多個實施方式之發光二極體結構10的剖面示意圖。請先參閱第1A圖和第1B圖。本發明之發光二極體結構10包含基底層110、電性接觸層120、半導體疊層130以及絕緣層140。 1A and 1B are schematic cross-sectional views of a light emitting diode structure 10 according to various embodiments of the present invention. Please refer to Figure 1A and Figure 1B first. The light emitting diode structure 10 of the present invention includes a base layer 110, an electrical contact layer 120, a semiconductor stack 130, and an insulating layer 140.

如第1A圖和第1B圖所示,具體而言,基底層 110具有最大第一寬度W1。詳細的說,在實際操作上,基底層110可以具有梯形輪廓。在多個實施例中,基底層110可包含介電材料或金屬材料。舉例來說,介電材料包含二氧化矽(Silicon Dioxide,SiO2)、氮化矽(Silicon Nitride,Si3N4)、二氧化鈦(TiO2)、五氧化二鉭(Ta2O5)或上述之任意組合;金屬材料包含金、鋁、銅、鎳等。 As shown in FIGS. 1A and 1B, specifically, the base layer 110 has a maximum first width W1. In detail, in actual operation, the base layer 110 may have a trapezoidal profile. In various embodiments, the base layer 110 may include a dielectric material or a metal material. For example, the dielectric material includes silicon dioxide (Silicon Dioxide, SiO 2 ), silicon nitride (Silicon Nitride, Si 3 N 4 ), titanium dioxide (TiO 2 ), tantalum pentoxide (Ta 2 O 5 ), or the above Any combination; metal materials include gold, aluminum, copper, nickel, etc.

如第1A圖和第1B圖所示,電性接觸層120具有最大第二寬度W2並設置於基底層110上。詳細的說,在實際操作上,電性接觸層120可以具有梯形輪廓。值得注意的是,最大第二寬度W2小於或等於最大第一寬度W1。半導體疊層130具有最大第三寬度W3並設置於電性接觸層120上。在實際操作上,半導體疊層130可以具有梯形輪廓。更詳細的說,半導體疊層130包括第一型半導體層132、發光層134及第二型半導體層136依序堆疊在電性接觸層120上。在實際操作上,第一型半導體層132、發光層134及第二型半導體層136可以各自具有梯形輪廓。可以理解的是,第一型半導體層132、發光層134及第二型半導體層136各自的寬度實質上皆等於或小於最大第三寬度W3。值得注意的是,最大第二寬度W2大於最大第三寬度W3。 As shown in FIGS. 1A and 1B, the electrical contact layer 120 has a maximum second width W2 and is disposed on the base layer 110. In detail, in actual operation, the electrical contact layer 120 may have a trapezoidal profile. It is worth noting that the maximum second width W2 is less than or equal to the maximum first width W1. The semiconductor stack 130 has a maximum third width W3 and is disposed on the electrical contact layer 120. In practical operation, the semiconductor stack 130 may have a trapezoidal profile. In more detail, the semiconductor stack 130 includes a first-type semiconductor layer 132, a light-emitting layer 134, and a second-type semiconductor layer 136 that are sequentially stacked on the electrical contact layer 120. In actual operation, the first-type semiconductor layer 132, the light-emitting layer 134, and the second-type semiconductor layer 136 may each have a trapezoidal profile. It can be understood that the widths of the first-type semiconductor layer 132, the light-emitting layer 134, and the second-type semiconductor layer 136 are substantially equal to or less than the maximum third width W3. It is worth noting that the maximum second width W2 is greater than the maximum third width W3.

在多個實施例中,第一型半導體層132可為P型III-V族半導體層。舉例來說,III-V族半導體層可包含如砷化鎵(GaAs)、氮化鎵(GaN)、磷化鎵(GaP)、砷化銦(InAs)、氮化鋁(AlN)、氮化銦(InN)、磷化銦(InP)等二元磊晶材料,或如磷化鎵砷(GaAsP)、砷化鋁鎵 (AlGaAs)、磷化銦鎵(InGaP)、氮化銦鎵(InGaN)、磷鎵化鋁銦(AlInGaP)、磷砷化銦鎵(InGaAsP)等三元或四元磊晶材料。因此,P型III-V族半導體層可以為上述III-V族半導體層經IIA族元素(例如鈹、鎂、鈣或鍶等)摻雜後而形成。 In various embodiments, the first-type semiconductor layer 132 may be a P-type III-V group semiconductor layer. For example, the III-V semiconductor layer may include, for example, gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), indium arsenide (InAs), aluminum nitride (AlN), nitride Binary epitaxial materials such as indium (InN), indium phosphide (InP), or such as gallium arsenide phosphide (GaAsP), aluminum gallium arsenide (AlGaAs), Indium Gallium Phosphide (InGaP), Indium Gallium Nitride (InGaN), Indium Aluminum Gallium Phosphide (AlInGaP), Indium Gallium Phosphide Arsenide (InGaAsP) and other ternary or quaternary epitaxial materials. Therefore, the P-type group III-V semiconductor layer may be formed by doping the group III-V semiconductor layer with a group IIA element (such as beryllium, magnesium, calcium, or strontium).

在多個實施例中,發光層134可包含多層量子井(multiple quantum well,MQW)、單一量子井(single-quantum well,SQW)、同質接面(homojunction)、異質接面(heterojunction)或其它類似的結構。 In various embodiments, the light-emitting layer 134 may include multiple quantum wells (MQW), single-quantum wells (SQW), homojunctions, heterojunctions, or other heterojunctions. Similar structure.

在多個實施例中,第二型半導體層136可為N型III-V族半導體層。舉例來說,III-V族半導體層可包含如砷化鎵(GaAs)、氮化鎵(GaN)、磷化鎵(GaP)、砷化銦(InAs)等二元磊晶材料,或如磷化鎵砷(GaAsP)、砷化鋁鎵(AlGaAs)、磷化銦鎵(InGaP)、氮化銦鎵(InGaN)、磷鎵化鋁銦(AlInGaP)、磷砷化銦鎵(InGaAsP)等三元或四元磊晶材料。因此,N型III-V族半導體層可以為上述III-V族半導體層經IVA族元素(例如矽等)摻雜後而形成。 In various embodiments, the second-type semiconductor layer 136 may be an N-type group III-V semiconductor layer. For example, the III-V semiconductor layer may include binary epitaxial materials such as gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), indium arsenide (InAs), or such as phosphorous Gallium arsenide (GaAsP), aluminum gallium arsenide (AlGaAs), indium gallium phosphide (InGaP), indium gallium nitride (InGaN), aluminum indium gallium phosphide (AlInGaP), indium gallium arsenide (InGaAsP), etc. Yuan or quaternary epitaxial material. Therefore, the N-type group III-V semiconductor layer may be formed by doping the above group III-V semiconductor layer with a group IVA element (such as silicon).

如第1A圖和第1B圖所示,在本實施方式中,電性接觸層120包括歐姆接觸層124及第一金屬層122。歐姆接觸層124具有最大第四寬度W4並設置於半導體疊層130與基底層110之間,且第一金屬層122具有最大第五寬度W5並設置於歐姆接觸層124與基底層110之間。更詳細的說,在實際操作上,歐姆接觸層124及第一金屬層122可以 各自具有梯形輪廓。應注意,最大第四寬度W4小於或實質上等於最大第一寬度W1,且最大第五寬度W5實質上等於最大第一寬度W1。在一些實施例中,歐姆接觸層124可包含透光導電材料或不透光導電材料。舉例來說,透光導電材料可包含氧化銦錫(Indium tin oxide,ITO)、氧化銦鋅(IZO)、氧化鋁鋅(AZO)或具有透光導電效果的材料;且不透光導電材料可包含鎳(Ni)、銀(Ag)、鎳金(Ni/Au)合金或上述之組合。在一些實施例中,第一金屬層122包含鈦(Ti)、鎳(Ni)、鋁(Al)、金(Au)、鉑(Pt)、鉻(Cr)、銀(Ag)、銅(Cu)或其合金。應注意,當歐姆接觸層124包含透光導電材料時,第一金屬層122可將上述被歐姆接觸層124穿透的光反射回去,使得光被導引為向上發射,進而增加出光效率。 As shown in FIGS. 1A and 1B, in this embodiment, the electrical contact layer 120 includes an ohmic contact layer 124 and a first metal layer 122. The ohmic contact layer 124 has a maximum fourth width W4 and is disposed between the semiconductor stack 130 and the base layer 110, and the first metal layer 122 has a maximum fifth width W5 and is disposed between the ohmic contact layer 124 and the base layer 110. In more detail, in actual operation, the ohmic contact layer 124 and the first metal layer 122 can Each has a trapezoidal profile. It should be noted that the maximum fourth width W4 is less than or substantially equal to the maximum first width W1, and the maximum fifth width W5 is substantially equal to the maximum first width W1. In some embodiments, the ohmic contact layer 124 may include a light-transmitting conductive material or an opaque conductive material. For example, the light-transmitting conductive material may include indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), or a material having a light-transmitting conductive effect; and the light-transmitting conductive material may Including nickel (Ni), silver (Ag), nickel-gold (Ni/Au) alloy or a combination of the above. In some embodiments, the first metal layer 122 includes titanium (Ti), nickel (Ni), aluminum (Al), gold (Au), platinum (Pt), chromium (Cr), silver (Ag), copper (Cu) ) Or its alloys. It should be noted that when the ohmic contact layer 124 includes a light-transmitting conductive material, the first metal layer 122 can reflect the light penetrated by the ohmic contact layer 124 back, so that the light is guided to emit upward, thereby increasing the light extraction efficiency.

在某些實施方式中,電性接觸層120為單層。具體的說,單層的電性接觸層120可包含透光導電材料或不透光導電材料。舉例來說,透光導電材料可包含氧化銦錫(Indium tin oxide,ITO)、氧化銦鋅(IZO)、氧化鋁鋅(AZO)或具有透光導電效果的材料;且不透光導電材料可包含鎳(Ni)、銀(Ag)、鎳金(Ni/Au)合金或上述之組合。此外,無論是多層或單層的電性接觸層120都具有良好的導電性,故可減少與第一型半導體層132的表面電阻,進而降低發光二極體結構10之驅動電壓,並可降低電性接觸層120在製程上之困難度。 In some embodiments, the electrical contact layer 120 is a single layer. Specifically, the single-layer electrical contact layer 120 may include a light-transmitting conductive material or an opaque conductive material. For example, the light-transmitting conductive material may include indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), or a material having a light-transmitting conductive effect; and the light-transmitting conductive material may Including nickel (Ni), silver (Ag), nickel-gold (Ni/Au) alloy or a combination of the above. In addition, both the multi-layer and the single-layer electrical contact layer 120 have good conductivity, so the surface resistance of the first type semiconductor layer 132 can be reduced, thereby reducing the driving voltage of the light emitting diode structure 10 and reducing The difficulty of the electrical contact layer 120 in the manufacturing process.

請繼續參閱第1A圖和第1B圖,絕緣層140至少 覆蓋基底層110之一側壁、電性接觸層120之一側壁及半導體疊層130之一側壁。在多個實施方式中,絕緣層140所使用的材料可以是氧化矽、氮化矽、氮氧化矽、環氧樹脂(epoxy)或其它合適之絕緣材料。 Please continue to refer to FIGS. 1A and 1B, the insulating layer 140 is at least Covering a sidewall of the base layer 110, a sidewall of the electrical contact layer 120, and a sidewall of the semiconductor stack 130. In various embodiments, the material used for the insulating layer 140 may be silicon oxide, silicon nitride, silicon oxynitride, epoxy, or other suitable insulating materials.

如第1A圖和第1B圖所示,在一實施方式中,發光二極體結構10還可包含電極層150設置半導體疊層130上,且電極層150的一部分暴露在絕緣層140之外。在一實施例中,絕緣層140至少覆蓋電極層150之一側壁。在某些實施例中,絕緣層140可覆蓋電極層150之一側壁及電極層150之頂表面的一部分。此外,在其他實施例中,絕緣層140僅覆蓋半導體疊層130一部分的上表面,因而形成一開口。此絕緣層140的開口暴露出半導體疊層130的其餘上表面。電極層150可設置在絕緣層140的開口中,並接觸半導體疊層130。或者,電極層150還可以覆蓋絕緣層140頂表面的一部分。暴露在絕緣層140之外的電極層150的所述部分則作為電性接觸的載台。 As shown in FIGS. 1A and 1B, in one embodiment, the light emitting diode structure 10 may further include an electrode layer 150 disposed on the semiconductor stack 130, and a portion of the electrode layer 150 is exposed outside the insulating layer 140. In one embodiment, the insulating layer 140 covers at least one side wall of the electrode layer 150. In some embodiments, the insulating layer 140 may cover a side wall of the electrode layer 150 and a portion of the top surface of the electrode layer 150. In addition, in other embodiments, the insulating layer 140 covers only a part of the upper surface of the semiconductor stack 130, thus forming an opening. The opening of the insulating layer 140 exposes the remaining upper surface of the semiconductor stack 130. The electrode layer 150 may be disposed in the opening of the insulating layer 140 and contact the semiconductor stack 130. Alternatively, the electrode layer 150 may also cover a part of the top surface of the insulating layer 140. The portion of the electrode layer 150 exposed outside the insulating layer 140 serves as a stage for electrical contact.

在一實施方式中,電極層150可被發光層134所發出的光穿透。因此,可以理解的是,電極層150包含透光導電材料,舉例來說,透光導電材料可包含氧化銦錫(Indium tin oxide,ITO)、氧化銦鋅(IZO)、氧化鋁鋅(AZO)或具有透光導電效果的材料。此外,由於上述透光導電材料具有良好的導電性,故可減少與第二型半導體層136的表面電阻,進而降低發光二極體結構10之驅動電壓,並可降低電極層150在製程上之困難度。在電極層150包含 透光導電材料的實施方式中,電極層150的寬度通常等於半導體疊層130的最大第三寬度W3,以使製造過程變得更為簡易。 In one embodiment, the electrode layer 150 can be penetrated by the light emitted by the light emitting layer 134. Therefore, it can be understood that the electrode layer 150 includes a light-transmitting conductive material. For example, the light-transmitting conductive material may include indium tin oxide (ITO), indium zinc oxide (IZO), and aluminum zinc oxide (AZO). Or materials with light-transmitting and conductive effects. In addition, since the light-transmitting conductive material has good conductivity, the surface resistance of the second-type semiconductor layer 136 can be reduced, thereby reducing the driving voltage of the light emitting diode structure 10, and reducing the electrode layer 150 in the manufacturing process Difficulty. The electrode layer 150 contains In the embodiment of the light-transmitting conductive material, the width of the electrode layer 150 is generally equal to the maximum third width W3 of the semiconductor stack 130 to make the manufacturing process easier.

在另一實施方式中,電極層150還可以包含不透光的金屬材料,舉例來說,不透光的金屬材料包含鉻(Cr)、鍺金(GeAu)、金(Au)、鈦(Ti)、鋁(Al)或與其類似之不透光的金屬材料。在電極層150包含不透光的金屬材料的實施方式中,為了不影響發光二極體的出光效率,電極層150的寬度通常小於半導體疊層130的最大第三寬度W3。舉例來說,電極層150的寬度大小只要能提供外接導線足夠的接合面積即可。 In another embodiment, the electrode layer 150 may further include an opaque metal material. For example, the opaque metal material includes chromium (Cr), germanium gold (GeAu), gold (Au), and titanium (Ti ), aluminum (Al) or similar opaque metal materials. In the embodiment in which the electrode layer 150 includes an opaque metal material, in order not to affect the light extraction efficiency of the light emitting diode, the width of the electrode layer 150 is generally smaller than the maximum third width W3 of the semiconductor stack 130. For example, the width of the electrode layer 150 only needs to provide a sufficient bonding area for the external wires.

如第1A圖和第1B圖所示,在一實施方式中,發光二極體結構10還可包含固晶基板170。具體的說,基底層110、電性接觸層120、半導體疊層130及絕緣層140皆設置於固晶基板170上。在本發明之某些實施方式中,固晶基板170可以為硬式印刷電路板、高熱導係數鋁基板、玻璃基板、陶瓷基板、軟式印刷電路板、金屬複合材料板、發光基板或具有諸如電晶體或積體電路(ICs)之功能元件的半導體基板。在一實施方式中,發光二極體結構10更可以包含黏著層160夾置於固晶基板170與基底層110之間,以提高發光二極體結構10與固晶基板170之間的結合力。在本發明之某些實施例中,黏著層160的材料可包含絕緣膠、導電膠和/或金屬。舉例來說,黏著層160的材料可為絕緣膠,例如環氧樹脂或矽膠;黏著層160的材料可為導電膠,例如 混合銀粉之環氧樹脂;黏著層160的材料可為金屬,例如銅、鋁、錫、金、銦和/或銀,但不以此為限。 As shown in FIGS. 1A and 1B, in one embodiment, the light emitting diode structure 10 may further include a solid crystal substrate 170. Specifically, the base layer 110, the electrical contact layer 120, the semiconductor stack 130, and the insulating layer 140 are all disposed on the solid crystal substrate 170. In some embodiments of the present invention, the solid crystal substrate 170 may be a rigid printed circuit board, a high thermal conductivity aluminum substrate, a glass substrate, a ceramic substrate, a flexible printed circuit board, a metal composite material board, a light emitting substrate, or a substrate such as a transistor Or a semiconductor substrate of functional elements of integrated circuits (ICs). In one embodiment, the light emitting diode structure 10 may further include an adhesive layer 160 sandwiched between the solid crystal substrate 170 and the base layer 110 to improve the bonding force between the light emitting diode structure 10 and the solid crystal substrate 170 . In some embodiments of the present invention, the material of the adhesive layer 160 may include insulating glue, conductive glue, and/or metal. For example, the material of the adhesive layer 160 may be an insulating adhesive, such as epoxy resin or silicone; the material of the adhesive layer 160 may be a conductive adhesive, such as Epoxy resin mixed with silver powder; the material of the adhesive layer 160 may be metal, such as copper, aluminum, tin, gold, indium, and/or silver, but not limited thereto.

下文將依序介紹第1A圖及第1B圖的各種實施例,且主要針對各實施方式之相異處進行說明,而不再對重覆部分進行贅述。請先參閱第1A圖,在本實施例中,發光二極體結構10的電性接觸層120包含歐姆接觸層124及第一金屬層122,且第一金屬層122夾置於歐姆接觸層124與基底層110之間。半導體疊層130中的第一型半導體層132和第二型半導體層136分別是P型和N型的III-V族半導體層(例如,包含GaN)。位於半導體疊層130上的電極層150包含透光導電材料(例如,ITO)。於本實施例中,基底層110的最大第一寬度W1實質上等於電性接觸層120的最大第二寬度W2,其中歐姆接觸層124的最大第四寬度W4實質上等於第一金屬層122的最大第五寬度W5,且電性接觸層120的最大第二寬度W2大於半導體疊層130的最大第三寬度W3。 In the following, various examples of FIG. 1A and FIG. 1B will be introduced in order, and the differences between the various embodiments will be mainly described, and the repeated parts will not be repeated. Please refer to FIG. 1A first. In this embodiment, the electrical contact layer 120 of the light emitting diode structure 10 includes an ohmic contact layer 124 and a first metal layer 122, and the first metal layer 122 is sandwiched between the ohmic contact layer 124 With the base layer 110. The first-type semiconductor layer 132 and the second-type semiconductor layer 136 in the semiconductor stack 130 are P-type and N-type group III-V semiconductor layers (for example, containing GaN). The electrode layer 150 on the semiconductor stack 130 includes a light-transmitting conductive material (for example, ITO). In this embodiment, the maximum first width W1 of the base layer 110 is substantially equal to the maximum second width W2 of the electrical contact layer 120, wherein the maximum fourth width W4 of the ohmic contact layer 124 is substantially equal to the first metal layer 122 The maximum fifth width W5, and the maximum second width W2 of the electrical contact layer 120 are greater than the maximum third width W3 of the semiconductor stack 130.

請參閱第1B圖。第1B圖所繪示之發光二極體結構10與第1A圖所繪示之發光二極體結構10的不同之處在於:基底層110的最大第一寬度W1實質上等於第一金屬層122的最大第五寬度W5,半導體疊層130的最大第三寬度W3實質上等於歐姆接觸層124的最大第四寬度W4,且第一金屬層122的最大第五寬度W5大於半導體疊層130的最大第三寬度W3。 Please refer to Figure 1B. The difference between the light-emitting diode structure 10 shown in FIG. 1B and the light-emitting diode structure 10 shown in FIG. 1A is that the maximum first width W1 of the base layer 110 is substantially equal to the first metal layer 122 The maximum fifth width W5, the maximum third width W3 of the semiconductor stack 130 is substantially equal to the maximum fourth width W4 of the ohmic contact layer 124, and the maximum fifth width W5 of the first metal layer 122 is greater than the maximum of the semiconductor stack 130 The third width W3.

第2圖繪示根據本發明另一實施方式之發光二 極體結構的剖面示意圖。為了便於比較與上述各實施方式之相異處並簡化說明,在下文之各實施例中使用相同的符號標注相同的元件,且主要針對各實施方式之相異處進行說明,而不再對重覆部分進行贅述。 FIG. 2 illustrates a second light emitting device according to another embodiment of the present invention A schematic cross-sectional view of the polar body structure. In order to facilitate the comparison with the differences between the above embodiments and simplify the description, the same symbols are used in the following examples to mark the same elements, and the differences between the embodiments are mainly described, and no emphasis will be given. Repeat the details.

第2圖所繪示之發光二極體結構20與第1A圖所繪示之發光二極體結構10的不同之處在於:發光二極體結構20的基底層110係包含分散式布拉格反射鏡(Distributed Bragg Reflector,DBR)。電性接觸層120為包含透光導電材料的單層,舉例來說,透光導電材料包含氧化銦錫(Indium tin oxide,ITO)、氧化銦鋅(IZO)、氧化鋁鋅(AZO)或具有透光導電效果的材料。由於透光導電材料具有良好的導電性,故可減少與第一型半導體層132的表面電阻,進而降低發光二極體結構20之驅動電壓,並可降低電性接觸層120在製程上之困難度。電性接觸層120具有最大第二寬度W2。具體的說,分散式布拉格反射鏡可由兩種具有不同折射率之同質或異質材料之薄膜相互堆疊所構成,並可將半導體疊層130中之發光層134所發出之光線反射並朝向遠離固晶基板170之方向出光,以提高發光二極體結構20之發光效率。值得注意的是,最大第二寬度W2大於最大第三寬度W3。 The difference between the light-emitting diode structure 20 shown in FIG. 2 and the light-emitting diode structure 10 shown in FIG. 1A is that the base layer 110 of the light-emitting diode structure 20 includes a distributed Bragg reflector (Distributed Bragg Reflector, DBR). The electrical contact layer 120 is a single layer containing a light-transmitting conductive material. For example, the light-transmitting conductive material includes indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), or Light-transmitting conductive material. Since the light-transmitting conductive material has good conductivity, it can reduce the surface resistance of the first type semiconductor layer 132, thereby reducing the driving voltage of the light emitting diode structure 20, and can reduce the difficulty of the electrical contact layer 120 in the manufacturing process degree. The electrical contact layer 120 has a maximum second width W2. Specifically, the decentralized Bragg reflector can be formed by stacking two thin films of homogeneous or heterogeneous materials with different refractive indexes, and can reflect the light emitted by the light emitting layer 134 in the semiconductor stack 130 and face away from the solid crystal The light is emitted in the direction of the substrate 170 to improve the light emitting efficiency of the light emitting diode structure 20. It is worth noting that the maximum second width W2 is greater than the maximum third width W3.

第3圖繪示根據本發明又一實施方式之發光二極體結構的剖面示意圖。為了便於比較與上述各實施方式之相異處並簡化說明,在下文之各實施例中使用相同的符號標注相同的元件,且主要針對各實施方式之相異處進行 說明,而不再對重覆部分進行贅述。 FIG. 3 is a schematic cross-sectional view of a light emitting diode structure according to another embodiment of the invention. In order to facilitate the comparison with the differences between the above-mentioned embodiments and simplify the description, the same symbols are used in the following examples to mark the same elements, and mainly for the differences between the embodiments Explanation, without repeating the repeated part.

如第3圖所示,發光二極體結構30包含半導體疊層130、絕緣層140、第一導電墊192、第二導電墊194以及支撐區域SP。具體的說,半導體疊層130由上而下依序包括第一型半導體層132、發光層134及第二型半導體層136,其中第二型半導體層136包含第一部分136a和第二部分136b,且第一部分136a位於第二部分136b上。在一實施例中,第一型半導體層132的寬度、發光層134的寬度和第二型半導體層136之第一部分136a的寬度實質上可以相同。應注意,第二型半導體層136的第二部分136b的寬度大於其第一部分136a的寬度,換句話說,第二型半導體層136具有階梯狀的剖面輪廓。絕緣層140覆蓋半導體疊層130的側壁以及第二部分136b的上表面。值得注意的是,絕緣層140具有第一開口140a以及第二開口140b分別位於第一型半導體層132及第二型半導體層136的第二部分136b上。第一導電墊192藉由第一開口140a電性連接至第一型半導體層132,而第二導電墊194藉由第二開口140b電性連接至第二型半導體層136的第二部分136b。在一些實施例中,第一導電墊192延伸覆蓋絕緣層140頂表面140t的一部分。在一實施例中,第一導電墊192的頂表面192t與第二導電墊194的頂表面194t實質上齊平。支撐區域SP位於絕緣層140上方且位於第一導電墊192與第二導電墊194之間。 As shown in FIG. 3, the light emitting diode structure 30 includes a semiconductor stack 130, an insulating layer 140, a first conductive pad 192, a second conductive pad 194, and a support region SP. Specifically, the semiconductor stack 130 includes a first type semiconductor layer 132, a light emitting layer 134, and a second type semiconductor layer 136 in order from top to bottom, wherein the second type semiconductor layer 136 includes a first portion 136a and a second portion 136b, And the first part 136a is located on the second part 136b. In an embodiment, the width of the first type semiconductor layer 132, the width of the light emitting layer 134, and the width of the first portion 136a of the second type semiconductor layer 136 may be substantially the same. It should be noted that the width of the second portion 136b of the second type semiconductor layer 136 is greater than the width of the first portion 136a thereof, in other words, the second type semiconductor layer 136 has a stepped cross-sectional profile. The insulating layer 140 covers the sidewall of the semiconductor stack 130 and the upper surface of the second portion 136b. It is worth noting that the insulating layer 140 has a first opening 140a and a second opening 140b located on the second portion 136b of the first type semiconductor layer 132 and the second type semiconductor layer 136, respectively. The first conductive pad 192 is electrically connected to the first type semiconductor layer 132 through the first opening 140a, and the second conductive pad 194 is electrically connected to the second portion 136b of the second type semiconductor layer 136 through the second opening 140b. In some embodiments, the first conductive pad 192 extends to cover a portion of the top surface 140t of the insulating layer 140. In one embodiment, the top surface 192t of the first conductive pad 192 and the top surface 194t of the second conductive pad 194 are substantially flush. The support area SP is located above the insulating layer 140 and between the first conductive pad 192 and the second conductive pad 194.

請繼續參閱第3圖,在一實施例中,發光二極 體結構30更包含一電極層150設置於第一型半導體層132與第一導電墊192之間。在一實施例中,發光二極體結構30更包含一固晶基板170。發光二極體結構30的第一導電墊192和第二導電墊194電性對接至固晶基板170上。也就是說,發光二極體結構30的第一導電墊192和第二導電墊194是透過覆晶(flip-chip)的方式電性連接至固晶基板170上。在某些實施例中,發光二極體結構30可更包含第一黏著層162以及第二黏著層164。詳細的說,第一黏著層162位於第一導電墊192與固晶基板170之間,而第二黏著層164位於第二導電墊194與固晶基板170之間。值得注意的是,第一黏著層162與第二黏著層164之間為電性絕緣,以避免第一導電墊192與第二導電墊194之間發生短路的問題。在多個實例中,第一黏著層162和第二黏著層164皆為透明導電的黏著層,舉例來說,透明導電的黏著層包含混合銀粉之環氧樹脂或異方性導電膠(Anisotropic Conductive Film,ACF)。 Please continue to refer to Figure 3, in one embodiment, the light-emitting diode The body structure 30 further includes an electrode layer 150 disposed between the first type semiconductor layer 132 and the first conductive pad 192. In one embodiment, the light emitting diode structure 30 further includes a solid crystal substrate 170. The first conductive pad 192 and the second conductive pad 194 of the light emitting diode structure 30 are electrically connected to the solid crystal substrate 170. In other words, the first conductive pad 192 and the second conductive pad 194 of the light emitting diode structure 30 are electrically connected to the solid crystal substrate 170 by flip-chip. In some embodiments, the light emitting diode structure 30 may further include a first adhesive layer 162 and a second adhesive layer 164. In detail, the first adhesive layer 162 is located between the first conductive pad 192 and the solid crystal substrate 170, and the second adhesive layer 164 is located between the second conductive pad 194 and the solid crystal substrate 170. It is worth noting that the first adhesive layer 162 and the second adhesive layer 164 are electrically insulated to avoid the problem of a short circuit between the first conductive pad 192 and the second conductive pad 194. In many examples, both the first adhesive layer 162 and the second adhesive layer 164 are transparent conductive adhesive layers. For example, the transparent conductive adhesive layer includes silver powder mixed epoxy resin or anisotropic conductive adhesive Film, ACF).

請繼續參閱第3圖,在一些實施例中,發光二極體結構30更包含一導電塊180,其設置於第二開口140b中,且第二導電墊194覆蓋導電塊180的頂表面180t及側壁180s。在一實施例中,位於電極層150上之絕緣層140的頂表面140t與導電塊180之頂表面180t實質上齊平。 Please continue to refer to FIG. 3. In some embodiments, the light emitting diode structure 30 further includes a conductive block 180 disposed in the second opening 140b, and the second conductive pad 194 covers the top surface 180t of the conductive block 180 and The side wall is 180s. In one embodiment, the top surface 140t of the insulating layer 140 on the electrode layer 150 is substantially flush with the top surface 180t of the conductive block 180.

本發明的另一態樣是提供一種發光二極體結構10的製造方法。第4圖至第16B圖繪示根據本發明一實施方式之製造發光二極體結構10於各階段的剖面示意圖。 Another aspect of the present invention is to provide a method for manufacturing the light emitting diode structure 10. 4 to 16B are schematic cross-sectional views at various stages of manufacturing the light-emitting diode structure 10 according to an embodiment of the present invention.

如第4圖所示,首先,提供一前驅結構40。此前驅結構40由上至下依序包含電極層370、半導體疊層320'、歐姆接觸層330、金屬層332、基底層340a、犧牲層350以及承載基板360。 As shown in FIG. 4, first, a precursor structure 40 is provided. The precursor structure 40 includes an electrode layer 370, a semiconductor stack 320', an ohmic contact layer 330, a metal layer 332, a base layer 340a, a sacrificial layer 350, and a carrier substrate 360 in order from top to bottom.

第5至第9圖為本發明一實施方式用以完成上述前驅結構的各製造階段的剖面示意圖。請先參照第5圖,形成磊晶疊層320於生長基板310上。在一實施方式中,磊晶疊層320可藉由磊晶生長技術形成在生長基板310上。在一實施例中,生長基板310可為藍寶石(Sapphire)基板或其他適合的基板。在多個實施方式中,磊晶疊層320包含未摻雜半導體層328、第二型半導體層326、發光層324和第一型半導體層322依序堆疊於生長基板310上。在一些實施例中,未摻雜半導體層328為未摻雜III-V族半導體層。舉例來說,未摻雜III-V族半導體層可包含如砷化鎵(GaAs)、氮化鎵(GaN)、磷化鎵(GaP)、砷化銦(InAs)、氮化鋁(AlN)、氮化銦(InN)、磷化銦(InP)等二元磊晶材料,或如磷化鎵砷(GaAsP)、砷化鋁鎵(AlGaAs)、磷化銦鎵(InGaP)、氮化銦鎵(InGaN)、磷鎵化鋁銦(AlInGaP)、磷砷化銦鎵(InGaAsP)等三元或四元磊晶材料。在一些實施例中,第二型半導體層326為N型III-V族半導體層,且第一型半導體層322為P型III-V族半導體層。可以理解的是,N型III-V族半導體層可以為上述未摻雜III-V族半導體層經IVA族元素(例如矽等)摻雜後而形成,且P型III-V族半導體層可以為上述未摻雜III-V族半導體層經IIA族元素(例如鈹、鎂、 鈣或鍶等)摻雜後而形成。在多個實施例中,發光層324可包含多層量子井(multiple quantum well,MQW)、單一量子井(single-quantum well,SQW)、同質接面(homojunction)、異質接面(heterojunction)或其它類似的結構。 5 to 9 are schematic cross-sectional views of an embodiment of the present invention used to complete the aforementioned precursor structure at various manufacturing stages. Please refer to FIG. 5 first to form an epitaxial stack 320 on the growth substrate 310. In one embodiment, the epitaxial stack 320 may be formed on the growth substrate 310 by epitaxial growth technology. In an embodiment, the growth substrate 310 may be a sapphire substrate or other suitable substrates. In various embodiments, the epitaxial stack 320 includes an undoped semiconductor layer 328, a second type semiconductor layer 326, a light emitting layer 324, and a first type semiconductor layer 322 sequentially stacked on the growth substrate 310. In some embodiments, the undoped semiconductor layer 328 is an undoped III-V semiconductor layer. For example, the undoped III-V semiconductor layer may include gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), indium arsenide (InAs), aluminum nitride (AlN) , Indium nitride (InN), indium phosphide (InP) and other binary epitaxial materials, or such as gallium arsenide phosphide (GaAsP), aluminum gallium arsenide (AlGaAs), indium gallium phosphide (InGaP), indium nitride Ternary or quaternary epitaxial materials such as gallium (InGaN), aluminum indium phosphorous gallium (AlInGaP), indium gallium phosphorous arsenide (InGaAsP), etc. In some embodiments, the second type semiconductor layer 326 is an N-type group III-V semiconductor layer, and the first type semiconductor layer 322 is a P-type group III-V semiconductor layer. It can be understood that the N-type group III-V semiconductor layer may be formed by doping the undoped group III-V semiconductor layer with an IVA element (such as silicon, etc.), and the P-type group III-V semiconductor layer may be It is the undoped III-V semiconductor layer through the group IIA element (such as beryllium, magnesium, Calcium or strontium are formed after doping. In various embodiments, the light-emitting layer 324 may include multiple quantum wells (MQW), single-quantum wells (SQW), homojunctions, heterojunctions, or other heterojunctions. Similar structure.

請繼續參閱第5圖,由下而上依序形成歐姆接觸層330、金屬層332以及基底層340a於磊晶疊層320上。在本實施例中,歐姆接觸層330可包含透光導電材料或不透光導電材料。舉例來說,透光導電材料可包含氧化銦錫(Indium tin oxide,ITO)、氧化銦鋅(IZO)、氧化鋁鋅(AZO)或具有透光導電效果的材料;且不透光導電材料可包含鎳(Ni)、銀(Ag)、鎳金(Ni/Au)合金或上述之組合。有關金屬層332的材料如前文第一金屬層122所述,在此不再贅述。在本實施方式中,基底層340a可包含介電材料或金屬材料。舉例來說,介電材料包含二氧化矽(Silicon Dioxide,SiO2)、氮化矽(Silicon Nitride,Si3N4)、二氧化鈦(TiO2)、五氧化二鉭(Ta2O5)或上述之任意組合;且金屬材料包含金、鋁、銅、鎳等。 Please continue to refer to FIG. 5, the ohmic contact layer 330, the metal layer 332 and the base layer 340 a are sequentially formed on the epitaxial stack 320 from bottom to top. In this embodiment, the ohmic contact layer 330 may include a light-transmitting conductive material or an opaque conductive material. For example, the light-transmitting conductive material may include indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), or a material having a light-transmitting conductive effect; and the light-transmitting conductive material may Including nickel (Ni), silver (Ag), nickel-gold (Ni/Au) alloy or a combination of the above. The material of the metal layer 332 is as described above in the first metal layer 122, and will not be repeated here. In this embodiment, the base layer 340a may include a dielectric material or a metal material. For example, the dielectric material includes silicon dioxide (Silicon Dioxide, SiO 2 ), silicon nitride (Silicon Nitride, Si 3 N 4 ), titanium dioxide (TiO 2 ), tantalum pentoxide (Ta 2 O 5 ), or the above Any combination; and the metal materials include gold, aluminum, copper, nickel, etc.

請參閱第6圖,形成犧牲層350於基底層340a上。在多個實施例中,犧牲層350包含苯并環丁烯(Benzocyclobutene,BCB)或聚醯亞胺(polyimide,PI)。 Referring to FIG. 6, a sacrificial layer 350 is formed on the base layer 340a. In various embodiments, the sacrificial layer 350 includes Benzocyclobutene (BCB) or polyimide (PI).

然後,請參閱第7圖,形成承載基板360於犧牲層350上。在多個實施例中,承載基板360可為矽基板或其他合適的基板。須說明的是,在犧牲層350上形成承載基板 360之後,將如第7圖所繪示之結構翻轉使生長基板310位於頂部且承載基板360位於底部。 Then, referring to FIG. 7, a carrier substrate 360 is formed on the sacrificial layer 350. In various embodiments, the carrier substrate 360 may be a silicon substrate or other suitable substrates. It should be noted that a carrier substrate is formed on the sacrificial layer 350 After 360, the structure as shown in FIG. 7 is turned so that the growth substrate 310 is at the top and the carrier substrate 360 is at the bottom.

請參閱第8圖,移除生長基板310。在一些實施方式中,可利用雷射剝離(laser lift-off,LLO)、研磨(grinding)或蝕刻(etching)等方式將生長基板310移除。具體的說,將生長基板310移除以暴露出磊晶疊層320的未摻雜半導體層328。 Please refer to FIG. 8 to remove the growth substrate 310. In some embodiments, the growth substrate 310 may be removed by laser lift-off (LLO), grinding, or etching. Specifically, the growth substrate 310 is removed to expose the undoped semiconductor layer 328 of the epitaxial stack 320.

請參閱第9圖,隨後,移除磊晶疊層320的一部分,以形成半導體疊層320’。更詳細的說,由於磊晶疊層320中的未摻雜半導體層328是不具有導電功能,因此,在此步驟中係完全移除磊晶疊層320中的未摻雜半導體層328,並暴露出第二型半導體層326。於此步驟後,半導體疊層320’(亦即剩餘的磊晶疊層)由上而下包含第二型半導體層326、發光層324和第一型半導體層322依序堆疊於歐姆接觸層330上。 Please refer to FIG. 9, and then, a part of the epitaxial stack 320 is removed to form a semiconductor stack 320'. In more detail, since the undoped semiconductor layer 328 in the epitaxial stack 320 does not have a conductive function, in this step, the undoped semiconductor layer 328 in the epitaxial stack 320 is completely removed, and The second type semiconductor layer 326 is exposed. After this step, the semiconductor stack 320' (that is, the remaining epitaxial stack) includes the second type semiconductor layer 326, the light emitting layer 324, and the first type semiconductor layer 322 sequentially stacked on the ohmic contact layer 330 from top to bottom on.

然後,形成電極層370於半導體疊層320’上,以完成如第4圖所示之前驅結構40。在一實施方式中,電極層370包含透光導電材料,舉例來說,透光導電材料包含氧化銦錫(Indium tin oxide,ITO)、氧化銦鋅(IZO)、氧化鋁鋅(AZO)或具有透光導電效果的材料。此外,由於上述透光導電材料具有良好的導電性,故可減少與第二型半導體層326的表面電阻,進而降低發光二極體之驅動電壓,並可降低電極層370在製程上之困難度。在另一實施方式中,電極層370還可以包含不透光的金屬材料,舉例來說,不透 光的金屬材料包含鉻(Cr)、鍺金(GeAu)、金(Au)、鈦(Ti)、鋁(Al)或與其類似之不透光的金屬材料。 Then, an electrode layer 370 is formed on the semiconductor stack 320' to complete the precursor structure 40 as shown in FIG. In one embodiment, the electrode layer 370 includes a light-transmitting conductive material. For example, the light-transmitting conductive material includes indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), or Light-transmitting conductive material. In addition, since the light-transmitting conductive material has good conductivity, it can reduce the surface resistance of the second type semiconductor layer 326, thereby reducing the driving voltage of the light emitting diode, and can reduce the difficulty of the electrode layer 370 in the manufacturing process . In another embodiment, the electrode layer 370 may further include an opaque metal material, for example, opaque Light metallic materials include chromium (Cr), germanium gold (GeAu), gold (Au), titanium (Ti), aluminum (Al), or similar opaque metal materials.

接著,移除前驅結構40之部分的電極層370、部分的半導體疊層320’、部分的歐姆接觸層330、部分的金屬層332和部分的基底層340a以暴露出犧牲層350。第10A圖至第11B圖為本發明一實施方式用以實現此步驟的剖面示意圖。在這個步驟中,包含了兩次的移除製程。如第10A圖所示,在一實施方式中,第一次移除製程可利用微影蝕刻製程來移除部分的電極層370以及部分的半導體疊層320’,並暴露出歐姆接觸層330。在這個實施方式中,剩餘的半導體疊層320”與剩餘的電極層370’具有實質上相同的寬度。如第10B圖所示,在另一實施方式中,第一次移除製程可利用微影蝕刻製程來移除部分的電極層370、部分的半導體疊層320’以及部分的歐姆接觸層330,並暴露出金屬層332。在這個實施方式中,剩餘的半導體疊層320”、剩餘的電極層370’和剩餘的歐姆接觸層330’具有實質上相同的寬度。須注意的是,在電極層370包含透光導電材料的實施方式中,蝕刻後剩餘的半導體疊層320”的寬度實質上等於剩餘的電極層370’的寬度。在電極層370包含不透光的金屬材料的實施方式中,為了不影響發光二極體的出光效率,蝕刻後剩餘的電極層370’的寬度通常小於剩餘的半導體疊層320”的寬度,舉例來說,剩餘的電極層370’的寬度大小只要能提供外接導線足夠的接合面積即可。 Next, part of the electrode layer 370, part of the semiconductor stack 320', part of the ohmic contact layer 330, part of the metal layer 332, and part of the base layer 340a of the precursor structure 40 are removed to expose the sacrificial layer 350. 10A to 11B are schematic cross-sectional views of an embodiment of the present invention for implementing this step. In this step, two removal processes are included. As shown in FIG. 10A, in one embodiment, the first removal process may utilize a lithography etching process to remove part of the electrode layer 370 and part of the semiconductor stack 320', and expose the ohmic contact layer 330. In this embodiment, the remaining semiconductor stack 320" has substantially the same width as the remaining electrode layer 370'. As shown in FIG. 10B, in another embodiment, the first removal process may utilize micro Shadow etching process to remove part of the electrode layer 370, part of the semiconductor stack 320' and part of the ohmic contact layer 330, and expose the metal layer 332. In this embodiment, the remaining semiconductor stack 320", the remaining The electrode layer 370' and the remaining ohmic contact layer 330' have substantially the same width. It should be noted that in the embodiment where the electrode layer 370 includes a light-transmitting conductive material, the width of the semiconductor stack 320" remaining after etching is substantially equal to the width of the remaining electrode layer 370'. The electrode layer 370 includes an opaque In the embodiment of the metal material, in order not to affect the light emitting efficiency of the light emitting diode, the width of the remaining electrode layer 370' after etching is generally smaller than the width of the remaining semiconductor stack 320". For example, the remaining electrode layer 370 The width of the'as long as it can provide enough bonding area for external wires.

如第11A圖所示,在一實施方式中,第二次移 除製程可利用微影蝕刻製程來移除部分的歐姆接觸層330、部分的金屬層332和部分的基底層340a,並暴露出犧牲層350。在這個實施方式中,剩餘的歐姆接觸層330’、剩餘的金屬層332’和剩餘的基底層340a’具有實質上相同的寬度,且剩餘的歐姆接觸層330’的寬度大於剩餘的半導體疊層320”的寬度。如第11B圖所示,在另一實施方式中,第二次移除製程可利用微影蝕刻製程來移除部分的金屬層332和部分的基底層340a,並暴露出犧牲層350。在這個實施方式中,剩餘的金屬層332’和剩餘的基底層340b’實質上具有相同的寬度,且剩餘的金屬層332’的寬度大於剩餘的半導體疊層320”的寬度。 As shown in FIG. 11A, in one embodiment, the second shift The removal process may utilize a lithography etching process to remove part of the ohmic contact layer 330, part of the metal layer 332, and part of the base layer 340a, and expose the sacrificial layer 350. In this embodiment, the remaining ohmic contact layer 330', the remaining metal layer 332', and the remaining base layer 340a' have substantially the same width, and the width of the remaining ohmic contact layer 330' is greater than the remaining semiconductor stack 320” width. As shown in FIG. 11B, in another embodiment, the second removal process may use a lithography etching process to remove part of the metal layer 332 and part of the base layer 340a, and expose the sacrifice Layer 350. In this embodiment, the remaining metal layer 332' and the remaining base layer 340b' have substantially the same width, and the width of the remaining metal layer 332' is greater than the width of the remaining semiconductor stack 320".

第12圖繪示發光二極體結構於其中一製造階段的上視圖。第13圖至第15圖繪示發光二極體結構於多個製造階段中根據第12圖線段A-A’的剖面示意圖。第16A圖至第16B圖繪示發光二極體結構於其中一製造階段中根據第12圖線段B-B’的剖面示意圖。須說明的是,由於剖面視角關係,所以在第13圖至第15圖中,剩餘的基底層340a’、剩餘的金屬層332’、剩餘的歐姆接觸層330’、剩餘的半導體疊層320”和剩餘的電極層370’都具有相同寬度。 FIG. 12 shows a top view of the light emitting diode structure at one of the manufacturing stages. 13 to 15 are schematic cross-sectional views of the light-emitting diode structure according to the line segment A-A' of FIG. 12 in multiple manufacturing stages. 16A to 16B are schematic cross-sectional views of the light-emitting diode structure according to the line segment B-B' of FIG. 12 in one of the manufacturing stages. It should be noted that, due to the cross-sectional viewing angle relationship, in FIGS. 13 to 15, the remaining base layer 340a′, the remaining metal layer 332′, the remaining ohmic contact layer 330′, and the remaining semiconductor stack 320” It has the same width as the remaining electrode layer 370'.

請同時參閱第13圖及第14圖,形成開口352於犧牲層350中,以暴露出承載基板360的一部分。具體而言,開口352鄰近於上述蝕刻後之剩餘的多層結構(包含340a’、332’、330’、320”和370’)。須注意的是,開口352並不屬於發光二極體結構中的一部分。 Please refer to FIG. 13 and FIG. 14 at the same time. An opening 352 is formed in the sacrificial layer 350 to expose a part of the carrier substrate 360. Specifically, the opening 352 is adjacent to the remaining multilayer structure (including 340a', 332', 330', 320", and 370') after the above etching. It should be noted that the opening 352 is not in the light-emitting diode structure a part of.

接著,請參閱第14圖,形成絕緣層380連續地覆蓋剩餘的基底層340a’、剩餘的金屬層332’、剩餘的歐姆接觸層330’、剩餘的半導體疊層320”、剩餘的電極層370’、犧牲層350之一頂表面的一部分350a、開口352以及承載基板360暴露的所述部分。具體的說,絕緣層380具有第一部分380a覆蓋犧牲層350頂表面的所述部分350a,且絕緣層380具有第二部分380b與其第一部分380a耦接並覆蓋剩餘多層結構(包含340a’、332’、330’、320”和370’)的側壁。絕緣層380的第一部分380a和第二部分380b構成如「L」型。而未被絕緣層380覆蓋之部分的犧牲層350(即暴露的部分350P)與被絕緣層380的第一部分380a覆蓋的犧牲層350頂表面的所述部分350a分別位於剩餘多層結構(包含340a’、332’、330’、320”和370’)的相對兩側。在本發明之某些實施方式中,絕緣層380的材料如前文絕緣層140所述,在此不再贅述。在本發明之某些實施方式中,可以使用化學氣相沉積法、印刷、塗佈或其他合適的方法來形成絕緣層380。具體的說,絕緣層380具有一厚度為500Å至20000Å。根據多個實施例,當絕緣層380的厚度大於某一數值,例如20000Å,會導致製造成本增加。反之,當絕緣層380的厚度小於某一數值,例如500Å,則會造成在製程中所提供的支撐力不足。因此,絕緣層380的厚度可例如為600Å、700Å、800Å、900Å、1000Å、2000Å、3000Å、4000Å、5000Å、6000Å、7000Å、8000Å、9000Å、10000Å或15000Å。 Next, referring to FIG. 14, an insulating layer 380 is formed to continuously cover the remaining base layer 340 a ′, the remaining metal layer 332 ′, the remaining ohmic contact layer 330 ′, the remaining semiconductor stack 320 ″, and the remaining electrode layer 370 ', a portion 350a of the top surface of one of the sacrificial layers 350, the opening 352, and the exposed portion of the carrier substrate 360. Specifically, the insulating layer 380 has a first portion 380a covering the portion 350a of the top surface of the sacrificial layer 350 and is insulated Layer 380 has a second portion 380b coupled to its first portion 380a and covers the sidewalls of the remaining multilayer structure (including 340a', 332', 330', 320", and 370'). The first portion 380a and the second portion 380b of the insulating layer 380 are formed like an "L" shape. The portion of the sacrificial layer 350 that is not covered by the insulating layer 380 (ie, the exposed portion 350P) and the portion 350a of the top surface of the sacrificial layer 350 that is covered by the first portion 380a of the insulating layer 380 are respectively located in the remaining multilayer structure (including 340a' , 332', 330', 320" and 370') on opposite sides. In some embodiments of the present invention, the material of the insulating layer 380 is as described above for the insulating layer 140, which is not repeated here. In the present invention In some embodiments, the insulating layer 380 may be formed by chemical vapor deposition, printing, coating, or other suitable methods. Specifically, the insulating layer 380 has a thickness of 500 Å to 20,000 Å. According to various embodiments When the thickness of the insulating layer 380 is greater than a certain value, such as 20,000 Å, it will cause an increase in manufacturing costs. Conversely, when the thickness of the insulating layer 380 is less than a certain value, such as 500 Å, it will cause insufficient support provided in the manufacturing process. Therefore, the thickness of the insulating layer 380 may be, for example, 600Å, 700Å, 800Å, 900Å, 1000Å, 2000Å, 3000Å, 4000Å, 5000Å, 6000Å, 7000Å, 8000Å, 9000Å, 10000Å, or 15000Å.

請同時參閱第15圖、第16A圖和第16B圖,移除犧牲層350。詳細的說,可以使用蝕刻溶液從犧牲層暴露的部分350P將犧牲層350移除。如第15圖所示,當犧牲層350被蝕刻後,絕緣層380的一部分會形成一支撐架382,且支撐架382可將剩餘的電極層370’、剩餘的半導體疊層320”、剩餘的歐姆接觸層330’、剩餘的金屬層332’和剩餘的基底層340a’懸空地支撐於承載基板360的上方。由於在移除犧牲層350後,僅有支撐架382支撐上方結構,因此可以容易地使支撐架382斷開。此外,在某些實施例中,僅移除部分的犧牲層350。舉例來說,自犧牲層350的上表面移除部分的犧牲層350,使得剩餘的電極層370’、剩餘的半導體疊層320”、剩餘的歐姆接觸層330’、剩餘的金屬層332’和剩餘的基底層340a’懸空於承載基板360之上。也就是說,可以無需完全移除犠牲層350,只要讓支撐架382可以折斷即可。在第16A圖和第16B圖中,絕緣層380至少連續地覆蓋剩餘基底層340a’之一側壁、剩餘金屬層332’之一側壁、剩餘歐姆接觸層330’之一側壁、剩餘半導體疊層320”之一側壁以及剩餘電極層370’之一側壁,並暴露出剩餘歐姆接觸層330’頂表面的一部分330’a或剩餘金屬層332’頂表面的一部分332’a。在某些實施方式中,絕緣層380亦可覆蓋剩餘電極層370’頂表面的一部分。 Please refer to FIG. 15, FIG. 16A and FIG. 16B at the same time to remove the sacrificial layer 350. In detail, the sacrificial layer 350 may be removed from the exposed portion 350P of the sacrificial layer using an etching solution. As shown in FIG. 15, after the sacrificial layer 350 is etched, a portion of the insulating layer 380 will form a support frame 382, and the support frame 382 may be used to replace the remaining electrode layer 370', the remaining semiconductor stack 320", and the remaining The ohmic contact layer 330', the remaining metal layer 332', and the remaining base layer 340a' are suspended above the carrier substrate 360. After the sacrificial layer 350 is removed, only the support frame 382 supports the upper structure, so it can be easily Ground to break the support frame 382. In addition, in some embodiments, only a portion of the sacrificial layer 350 is removed. For example, a portion of the sacrificial layer 350 is removed from the upper surface of the sacrificial layer 350 so that the remaining electrode layer 370', the remaining semiconductor stack 320", the remaining ohmic contact layer 330', the remaining metal layer 332', and the remaining base layer 340a' are suspended above the carrier substrate 360. In other words, it is not necessary to completely remove the animal layer 350, as long as the support frame 382 can be broken. In FIGS. 16A and 16B, the insulating layer 380 continuously covers at least one side wall of the remaining base layer 340a′, one side wall of the remaining metal layer 332′, one side wall of the remaining ohmic contact layer 330′, and the remaining semiconductor stack 320 One of the sidewalls and one of the sidewalls of the remaining electrode layer 370', and exposes a portion 330'a of the top surface of the remaining ohmic contact layer 330' or a portion 332'a of the top surface of the remaining metal layer 332'. In some embodiments The insulating layer 380 may also cover a part of the top surface of the remaining electrode layer 370'.

請回到第15圖,使絕緣層380的支撐架382斷裂,而形成單獨的一發光二極體結構。應注意,在使支撐架382斷裂的步驟之後,將會在單獨的發光二極體結構上形 成一支撐區域SP。更詳細的說,此支撐區域SP可包含支撐架382斷裂在第一部分380a和第二部分380b的轉折位置處382P,或者支撐架382斷裂在第一部分380a的任一處,又或者部分的第二部分380b脫離剩餘多層結構(340a’、332’、330’、320”或370’)的側壁。在一些實施方式中,可以將此單獨的發光二極體結構設置於固晶基板170上以形成如第1A和1B圖所示之發光二極體結構10。此外,可以進一步在固晶基板170上先形成黏著層160後,再將此單獨的發光二極體設置於黏著層160上,以增加兩者之間的附著力。有關第1A和1B圖所繪示之發光二極體結構10的各種特徵已記載於上文中,在此不在贅述。值得注意的是,上述製程操作僅為例示性的示出,各操作可以依照需求任意的調換順序。在某些實施例中,在上述製程之前、期間或之後可以執行額外的操作。 Returning to FIG. 15, the support frame 382 of the insulating layer 380 is broken to form a single light-emitting diode structure. It should be noted that after the step of breaking the support frame 382, it will be formed on a separate light emitting diode structure Into a support area SP. In more detail, the support area SP may include the support frame 382 breaking at the turning position 382P of the first part 380a and the second part 380b, or the support frame 382 breaking at any place of the first part 380a, or the second part The portion 380b is detached from the sidewall of the remaining multilayer structure (340a', 332', 330', 320", or 370'). In some embodiments, this separate light emitting diode structure may be disposed on the solid crystal substrate 170 to form As shown in FIGS. 1A and 1B, the light emitting diode structure 10. In addition, an adhesive layer 160 may be further formed on the solid crystal substrate 170, and then the separate light emitting diode may be disposed on the adhesive layer 160 to Increase the adhesion between the two. The various features of the light-emitting diode structure 10 shown in Figures 1A and 1B have been described above and are not repeated here. It is worth noting that the above process operations are only examples It is shown that each operation can be arbitrarily exchanged in accordance with requirements. In some embodiments, additional operations can be performed before, during, or after the above process.

本發明之另一實施方式是提供一種發光二極體結構10的製造方法。第17圖至第25圖繪示根據本發明一實施方式之製造發光二極體結構10於各階段的剖面示意圖。如第17圖所示,首先,提供一前驅結構50。此前驅結構50由上至下依序包含電極層370、半導體疊層320'、歐姆接觸層330、基底層340a、犧牲層350、支撐層410以及承載基板360。在一實施例中,此前驅結構50可以更包含一金屬層332夾置於歐姆接觸層330與基底層340a之間。在另一實施例中,此前驅結構50可以更包含一黏著層420位於支撐層410與承載基板360之間。以下皆以前驅結構50包含金屬層 332和黏著層420的實施方式說明。 Another embodiment of the present invention is to provide a method for manufacturing the light emitting diode structure 10. 17 to 25 are schematic cross-sectional views at various stages of manufacturing the light-emitting diode structure 10 according to an embodiment of the present invention. As shown in FIG. 17, first, a precursor structure 50 is provided. The precursor structure 50 includes an electrode layer 370, a semiconductor stack 320', an ohmic contact layer 330, a base layer 340a, a sacrificial layer 350, a support layer 410, and a carrier substrate 360 in order from top to bottom. In one embodiment, the precursor structure 50 may further include a metal layer 332 sandwiched between the ohmic contact layer 330 and the base layer 340a. In another embodiment, the precursor structure 50 may further include an adhesive layer 420 between the support layer 410 and the carrier substrate 360. The following are all precursor structures 50 including a metal layer The embodiment of 332 and the adhesive layer 420 are described.

第18至第22圖為本發明一實施例用以完成上述前驅結構的各製造階段的剖面示意圖。請先參照第18圖,在生長基板310上由下而上依序形成磊晶疊層320、歐姆接觸層330、金屬層332、基底層340a以及犧牲層350。更具體的說,磊晶疊層320包含未摻雜半導體層328、第二型半導體層326、發光層324和第一型半導體層322依序堆疊於生長基板310上。應注意,犧牲層350具有一開口350R暴露出基底層340a的一部分。 18 to 22 are schematic cross-sectional views of an embodiment of the present invention used to complete the aforementioned precursor structures at various manufacturing stages. Referring to FIG. 18 first, an epitaxial stack 320, an ohmic contact layer 330, a metal layer 332, a base layer 340a, and a sacrificial layer 350 are sequentially formed on the growth substrate 310 from bottom to top. More specifically, the epitaxial stack 320 includes an undoped semiconductor layer 328, a second-type semiconductor layer 326, a light-emitting layer 324, and a first-type semiconductor layer 322 sequentially stacked on the growth substrate 310. It should be noted that the sacrificial layer 350 has an opening 350R exposing a portion of the base layer 340a.

接著,如第19圖所示,形成支撐層410覆蓋犧牲層350並填滿開口350R。在一些實施例中,支撐層410可包含絕緣材料、金屬材料或其他具有支撐效果的材料。舉例來說,絕緣材料包含氧化矽、氮化矽、氮氧化矽、環氧樹脂;而金屬材料包含鋁、鈦金、鉑或鎳等,但不以此為限。 Next, as shown in FIG. 19, a support layer 410 is formed to cover the sacrificial layer 350 and fill the opening 350R. In some embodiments, the supporting layer 410 may include an insulating material, a metal material, or other materials having a supporting effect. For example, the insulating material includes silicon oxide, silicon nitride, silicon oxynitride, and epoxy resin; and the metal material includes aluminum, titanium, platinum, or nickel, but not limited thereto.

請參閱第20圖,繼續形成承載基板360於支撐層410上。在一些實施例中,可以藉由黏著層420將承載基板360黏附至支撐層410上,以提高承載基板360與支撐層410之間的結合力。在一實施例中,黏著層420的材料可包含絕緣膠、導電膠和/或金屬。舉例來說,黏著層420的材料可為絕緣膠,例如環氧樹脂或矽膠;黏著層420的材料可為導電膠,例如混合銀粉之環氧樹脂;黏著層420的材料可為金屬,例如銅、鋁、錫、金、銦和/或銀,但不以此為限。在此須說明的是,在形成承載基板360之後,將如第20圖所 繪示之結構翻轉使生長基板310位於頂部且承載基板360位於底部。 Please refer to FIG. 20 to continue forming the carrier substrate 360 on the support layer 410. In some embodiments, the carrier substrate 360 can be adhered to the support layer 410 through the adhesive layer 420 to improve the bonding force between the carrier substrate 360 and the support layer 410. In an embodiment, the material of the adhesive layer 420 may include insulating glue, conductive glue, and/or metal. For example, the material of the adhesive layer 420 may be an insulating adhesive, such as epoxy resin or silicone; the material of the adhesive layer 420 may be a conductive adhesive, such as an epoxy resin mixed with silver powder; and the material of the adhesive layer 420 may be a metal, such as copper , Aluminum, tin, gold, indium and/or silver, but not limited to this. It should be noted here that after the carrier substrate 360 is formed, it will be as shown in FIG. 20 The illustrated structure is turned so that the growth substrate 310 is at the top and the carrier substrate 360 is at the bottom.

然後,請參閱第21圖,移除生長基板310。在一些實施方式中,可利用雷射剝離(laser lift-off,LLO)、研磨或蝕刻等方式將生長基板310移除。具體的說,將生長基板310移除以暴露出磊晶疊層320的未摻雜半導體層328。 Then, referring to FIG. 21, the growth substrate 310 is removed. In some embodiments, the growth substrate 310 may be removed by laser lift-off (LLO), grinding, or etching. Specifically, the growth substrate 310 is removed to expose the undoped semiconductor layer 328 of the epitaxial stack 320.

請參閱第22圖,隨後,移除磊晶疊層320的一部分,以形成半導體疊層320’。更詳細的說,由於磊晶疊層320中的未摻雜半導體層328是不具有導電功能,因此,在此步驟中係完全移除磊晶疊層320中的未摻雜半導體層328,並暴露出第二型半導體層326。於此步驟後,半導體疊層320’(亦即剩餘的磊晶疊層)由上而下包含第二型半導體層326、發光層324和第一型半導體層322依序堆疊於歐姆接觸層330上。然後,形成電極層370於半導體疊層320’上,以完成如第17圖所示之前驅結構50。 Please refer to FIG. 22, and then, a part of the epitaxial stack 320 is removed to form a semiconductor stack 320'. In more detail, since the undoped semiconductor layer 328 in the epitaxial stack 320 does not have a conductive function, in this step, the undoped semiconductor layer 328 in the epitaxial stack 320 is completely removed, and The second type semiconductor layer 326 is exposed. After this step, the semiconductor stack 320' (that is, the remaining epitaxial stack) includes the second type semiconductor layer 326, the light emitting layer 324, and the first type semiconductor layer 322 sequentially stacked on the ohmic contact layer 330 from top to bottom on. Then, an electrode layer 370 is formed on the semiconductor stack 320' to complete the precursor structure 50 as shown in FIG.

接著,移除如第17圖所示前驅結構50之部分的電極層370、部分的半導體疊層320’、部分的歐姆接觸層330、部分的金屬層332和部分的基底層340a以暴露出犧牲層350。第23圖至第24圖為本發明一實施方式用以實現此步驟的剖面示意圖。在這個步驟中,包含了兩次的移除製程。如第23圖所示,在一實施方式中,第一次移除製程可利用微影蝕刻製程來移除部分的電極層370以及部分的半導體疊層320’,並暴露出歐姆接觸層330。在這個實施方式 中,剩餘的半導體疊層320”與剩餘的電極層370’實質上具有相同的寬度。 Next, part of the electrode layer 370, part of the semiconductor stack 320', part of the ohmic contact layer 330, part of the metal layer 332, and part of the base layer 340a of the precursor structure 50 as shown in FIG. 17 are removed to expose the sacrifice Floor 350. 23 to 24 are schematic cross-sectional views of an embodiment of the present invention for achieving this step. In this step, two removal processes are included. As shown in FIG. 23, in one embodiment, the first removal process may use a lithography etching process to remove part of the electrode layer 370 and part of the semiconductor stack 320', and expose the ohmic contact layer 330. In this embodiment In this case, the remaining semiconductor stack 320" has substantially the same width as the remaining electrode layer 370'.

如第24圖所示,在一實施方式中,第二次移除製程可利用微影蝕刻製程來移除部分的歐姆接觸層330、部分的金屬層332和部分的基底層340a,並暴露出犧牲層350。在這個實施方式中,剩餘的歐姆接觸層330’、剩餘的金屬層332’和剩餘的基底層340a’實質上具有相同的寬度,且剩餘的歐姆接觸層330’的寬度大於剩餘的半導體疊層320”的寬度。在實際的操作中,在第二次移除製程的過程中因製程上的公差使得剩餘的歐姆接觸層330’的某一側壁不完全與對應剩餘半導體疊層320”的同側側壁齊平。 As shown in FIG. 24, in one embodiment, the second removal process may use a lithography etching process to remove part of the ohmic contact layer 330, part of the metal layer 332, and part of the base layer 340a, and expose The sacrifice layer 350. In this embodiment, the remaining ohmic contact layer 330', the remaining metal layer 332', and the remaining base layer 340a' have substantially the same width, and the width of the remaining ohmic contact layer 330' is greater than the remaining semiconductor stack 320” width. In actual operation, during the second removal process, due to process tolerances, one side wall of the remaining ohmic contact layer 330' is not completely the same as the corresponding remaining semiconductor stack 320" The side walls are flush.

請繼續參閱第24圖,形成絕緣層380連續地覆蓋剩餘的基底層340a’、剩餘的金屬層332’、剩餘的歐姆接觸層330’、剩餘的半導體疊層320”以及剩餘的電極層370’。應注意,絕緣層380並不會完全覆蓋犧牲層350,也就是說,有一部分的犧牲層350是暴露在外的。接著,在一實施例中,可以藉由微影蝕刻的方式在絕緣層380中形成第一開口380R1和第二開口380R2以分別暴露出剩餘電極層370’的一部分以及剩餘歐姆接觸層330’的一部分。 Please continue to refer to FIG. 24, forming an insulating layer 380 to continuously cover the remaining base layer 340a', the remaining metal layer 332', the remaining ohmic contact layer 330', the remaining semiconductor stack 320", and the remaining electrode layer 370' It should be noted that the insulating layer 380 does not completely cover the sacrificial layer 350, that is, a portion of the sacrificial layer 350 is exposed. Then, in one embodiment, the insulating layer can be etched by lithography The first opening 380R1 and the second opening 380R2 are formed in 380 to expose a part of the remaining electrode layer 370' and a part of the remaining ohmic contact layer 330', respectively.

請參閱第25圖,移除犧牲層350。詳細的說,可以使用蝕刻溶液從犧牲層350暴露的部分將犧牲層350移除。當犧牲層350被蝕刻後,支撐層410的一部分會形成一支撐架412,且支撐架412可將絕緣層380、剩餘的電極層370’、剩餘的半導體疊層320”、剩餘的歐姆接觸層330’、 剩餘的金屬層332’和剩餘的基底層340a’懸空地支撐於支撐層410的上方。由於在移除犧牲層350後,僅有支撐架412支撐上方結構,因此可以容易地使支撐架412斷開。此外,在某些實施例中,僅移除部分的犧牲層350。舉例來說,自犧牲層350的上表面移除部分的犧牲層350,使得絕緣層380、剩餘的電極層370’、剩餘的半導體疊層320”、剩餘的歐姆接觸層330’、剩餘的金屬層332’和剩餘的基底層340a’懸空於犧牲層350之上。也就是說,可以無需完全移除犠牲層350,只要能讓支撐架412可以折斷即可。在第25圖中,絕緣層380至少連續地覆蓋剩餘基底層340a’之一側壁、剩餘金屬層332’之一側壁、剩餘歐姆接觸層330’之一側壁、剩餘半導體疊層320”之一側壁以及剩餘電極層370’之一側壁,並暴露出剩餘電極層370’的一部分和剩餘歐姆接觸層330’的一部分。在某些實施方式中,絕緣層380亦可覆蓋剩餘電極層370’頂表面的另一部分。 Referring to FIG. 25, the sacrificial layer 350 is removed. In detail, the sacrificial layer 350 may be removed from the exposed portion of the sacrificial layer 350 using an etching solution. After the sacrificial layer 350 is etched, a part of the support layer 410 will form a support frame 412, and the support frame 412 may be the insulating layer 380, the remaining electrode layer 370', the remaining semiconductor stack 320", the remaining ohmic contact layer 330', The remaining metal layer 332' and the remaining base layer 340a' are suspended above the support layer 410. Since only the support frame 412 supports the upper structure after the sacrificial layer 350 is removed, the support frame 412 can be easily broken. Furthermore, in some embodiments, only a portion of the sacrificial layer 350 is removed. For example, part of the sacrificial layer 350 is removed from the upper surface of the sacrificial layer 350, so that the insulating layer 380, the remaining electrode layer 370', the remaining semiconductor stack 320", the remaining ohmic contact layer 330', the remaining metal The layer 332' and the remaining base layer 340a' are suspended above the sacrificial layer 350. That is, it is not necessary to completely remove the layer 350, as long as the support frame 412 can be broken. In FIG. 25, the insulating layer 380 continuously covers at least one sidewall of the remaining base layer 340a', one sidewall of the remaining metal layer 332', one sidewall of the remaining ohmic contact layer 330', one sidewall of the remaining semiconductor stack 320", and one of the remaining electrode layers 370' The side walls expose a portion of the remaining electrode layer 370' and a portion of the remaining ohmic contact layer 330'. In some embodiments, the insulating layer 380 may also cover another part of the top surface of the remaining electrode layer 370'.

請繼續參閱第25圖,使支撐層410的支撐架412斷裂,而形成單獨的一發光二極體結構。在一實施例中,當支撐架412斷裂後,此單獨的發光二極體結構上可能會殘留支撐架412的一部分,且此殘留支撐架412的一部分並不會再次地被清除乾淨。在另一實施例中,當支撐架412斷裂後,此單獨的發光二極體結構上可能完全不會殘留支撐架412的一部分。在一些實施方式中,可以將此單獨的發光二極體結構設置於固晶基板170上以形成如第1A圖所示之發光二極體結構10。此外,可以進一步在固晶基板170 與此單獨的發光二極體之間設置黏著層160,以增加兩者之間的附著力。更詳細的說,位在單獨的發光二極體結構上之支撐架412的殘留部分會被黏著層160覆蓋,因此,於外觀上仍會形成如第1A圖所示之發光二極體結構10。有關第1A圖所繪示之發光二極體結構10的各種特徵已記載於上文中,在此不在贅述。值得注意的是,上述製程操作僅為例示性的示出,各操作可以依照需求任意的調換順序。在某些實施例中,在上述製程之前、期間或之後可以執行額外的操作。 Please continue to refer to FIG. 25 to break the support frame 412 of the support layer 410 to form a single light-emitting diode structure. In an embodiment, after the support frame 412 breaks, a part of the support frame 412 may remain on the separate light-emitting diode structure, and a part of the remaining support frame 412 will not be cleaned again. In another embodiment, after the support frame 412 is broken, a part of the support frame 412 may not remain on the structure of the single light-emitting diode at all. In some embodiments, this separate light emitting diode structure may be disposed on the solid crystal substrate 170 to form the light emitting diode structure 10 shown in FIG. 1A. In addition, the solid crystal substrate 170 can be further An adhesive layer 160 is provided between the separate light-emitting diodes to increase the adhesion between the two. In more detail, the remaining portion of the support frame 412 on the separate light-emitting diode structure will be covered by the adhesive layer 160, therefore, the light-emitting diode structure 10 as shown in FIG. 1A will still be formed in appearance . Various features of the light-emitting diode structure 10 shown in FIG. 1A have been described above, and are not repeated here. It is worth noting that the above-mentioned process operations are only illustrative, and each operation can be arbitrarily exchanged in accordance with requirements. In some embodiments, additional operations may be performed before, during, or after the above process.

本發明的又一態樣是提供一種發光二極體結構20的製造方法。第26圖至第38B圖繪示根據本發明另一實施方式之製造發光二極體結構20於各階段的剖面示意圖。 Another aspect of the present invention is to provide a method for manufacturing the light emitting diode structure 20. 26 to 38B are schematic cross-sectional views at various stages of manufacturing the light-emitting diode structure 20 according to another embodiment of the present invention.

如第26圖所示,首先,提供一前驅結構60。此前驅結構60由上至下依序包含電極層370、半導體疊層320'、歐姆接觸層330、基底層340b、犧牲層350以及承載基板360。第27圖至第30圖為本發明一實施方式用以完成上述前驅結構的各製造階段的剖面示意圖。為了便於比較與上述各實施方式之相異處並簡化說明,在下文之各實施例中使用相同的符號標注相同的元件,且主要針對各實施方式之相異處進行說明,而不再對重覆部分進行贅述。請參閱第27圖,在生長基板310上依序向上堆疊形成磊晶疊層320和歐姆接觸層330。 As shown in FIG. 26, first, a precursor structure 60 is provided. The precursor structure 60 includes an electrode layer 370, a semiconductor stack 320', an ohmic contact layer 330, a base layer 340b, a sacrificial layer 350, and a carrier substrate 360 in order from top to bottom. FIG. 27 to FIG. 30 are schematic cross-sectional views of an embodiment of the present invention used to complete each stage of the aforementioned precursor structure. In order to facilitate the comparison with the differences between the above embodiments and simplify the description, the same symbols are used in the following examples to mark the same elements, and the differences between the embodiments are mainly described, and no emphasis will be given. Repeat the details. Referring to FIG. 27, an epitaxial stack 320 and an ohmic contact layer 330 are sequentially stacked up on the growth substrate 310.

接著,請參閱第28圖,形成基底層340b於歐姆接觸層330上。在本實施方式中,基底層340b包含分散式 布拉格反射鏡(Distributed Bragg Reflector,DBR)。有關分散式布拉格反射鏡的技術內容已於前文詳述,在此不再贅述。應注意,於本實施例中,當基底層340b包含分散式布拉格反射鏡時,歐姆接觸層330必須只能包含透光導電材料,例如氧化銦錫(Indium tin oxide,ITO)、氧化銦鋅(IZO)、氧化鋁鋅(AZO)或具有透光導電效果的材料。 Next, referring to FIG. 28, a base layer 340b is formed on the ohmic contact layer 330. In this embodiment, the base layer 340b includes a decentralized Distributed Bragg Reflector (DBR). The technical content of the decentralized Bragg reflector has been detailed above, and will not be repeated here. It should be noted that, in this embodiment, when the base layer 340b includes a distributed Bragg reflector, the ohmic contact layer 330 must only contain a light-transmitting conductive material, such as indium tin oxide (ITO), indium zinc oxide ( IZO), Alumina Zinc (AZO) or materials with light-transmitting and conductive effect.

請參閱第29圖,形成犧牲層350於基底層340b上。在多個實施例中,犧牲層350包含苯并環丁烯(Benzocyclobutene,BCB)或聚醯亞胺(polyimide,PI)。 Referring to FIG. 29, a sacrificial layer 350 is formed on the base layer 340b. In various embodiments, the sacrificial layer 350 includes Benzocyclobutene (BCB) or polyimide (PI).

然後,請參閱第30圖,形成承載基板360於犧牲層350上。在多個實施例中,承載基板360可為矽基板或其他合適的基板。須說明的是,在犧牲層350上形成承載基板360之後,將如第30圖所繪示之結構翻轉使生長基板310位於頂部且承載基板360位於底部。 Then, referring to FIG. 30, a carrier substrate 360 is formed on the sacrificial layer 350. In various embodiments, the carrier substrate 360 may be a silicon substrate or other suitable substrates. It should be noted that after the carrier substrate 360 is formed on the sacrificial layer 350, the structure as shown in FIG. 30 is turned so that the growth substrate 310 is at the top and the carrier substrate 360 is at the bottom.

請參閱第31圖,移除生長基板310。在一些實施方式中,可利用雷射剝離(laser lift-off,LLO)、研磨或蝕刻等方式將生長基板310移除。具體的說,將生長基板310移除以暴露出磊晶疊層320的未摻雜半導體層328。 Referring to FIG. 31, the growth substrate 310 is removed. In some embodiments, the growth substrate 310 may be removed by laser lift-off (LLO), grinding, or etching. Specifically, the growth substrate 310 is removed to expose the undoped semiconductor layer 328 of the epitaxial stack 320.

請參閱第32圖,隨後,移除磊晶疊層320的一部分,以形成半導體疊層320’。更詳細的說,由於磊晶疊層320中的未摻雜半導體層328是不具有導電功能,因此,在此步驟中係完全移除磊晶疊層320中的未摻雜半導體層328,並暴露出第二型半導體層326。於此步驟後,半導體疊層320’(亦即剩餘的磊晶疊層)由上而下包含第二型半導 體層326、發光層324和第一型半導體層322依序堆疊於歐姆接觸層330上。 Please refer to FIG. 32, and then, a part of the epitaxial stack 320 is removed to form a semiconductor stack 320'. In more detail, since the undoped semiconductor layer 328 in the epitaxial stack 320 does not have a conductive function, in this step, the undoped semiconductor layer 328 in the epitaxial stack 320 is completely removed, and The second type semiconductor layer 326 is exposed. After this step, the semiconductor stack 320' (i.e., the remaining epitaxial stack) includes the second type semiconductor from top to bottom The bulk layer 326, the light emitting layer 324, and the first type semiconductor layer 322 are sequentially stacked on the ohmic contact layer 330.

然後,形成電極層370於半導體疊層320’上,以完成如第26圖所示之前驅結構60。在一實施方式中,電極層370包含透光導電材料,舉例來說,透光導電材料包含氧化銦錫(Indium tin oxide,ITO)、氧化銦鋅(IZO)、氧化鋁鋅(AZO)或具有透光導電效果的材料。此外,由於上述透光導電材料具有良好的導電性,故可減少與第二型半導體層326的表面電阻,進而降低發光二極體之驅動電壓,並可降低電極層370在製程上之困難度。在另一實施方式中,電極層370還可以包含不透光的金屬材料,舉例來說,不透光的金屬材料包含鉻(Cr)、鍺金(GeAu)、金(Au)、鈦(Ti)、鋁(Al)或與其類似之不透光的金屬材料。 Then, an electrode layer 370 is formed on the semiconductor stack 320' to complete the precursor structure 60 as shown in FIG. In one embodiment, the electrode layer 370 includes a light-transmitting conductive material. For example, the light-transmitting conductive material includes indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), or Light-transmitting conductive material. In addition, since the light-transmitting conductive material has good conductivity, it can reduce the surface resistance of the second type semiconductor layer 326, thereby reducing the driving voltage of the light emitting diode, and can reduce the difficulty of the electrode layer 370 in the manufacturing process . In another embodiment, the electrode layer 370 may further include an opaque metal material. For example, the opaque metal material includes chromium (Cr), germanium gold (GeAu), gold (Au), and titanium (Ti ), aluminum (Al) or similar opaque metal materials.

接著,移除前驅結構40之部分的電極層370、部分的半導體疊層320’、部分的歐姆接觸層330和部分的基底層340b以暴露出犧牲層350。第33圖至第34圖為本發明一實施方式用以實現此步驟的剖面示意圖。在這個步驟中,包含了兩次的移除製程。請參照第33圖,第一次移除製程可利用微影蝕刻製程來移除部分的電極層370以及部分的半導體疊層320’,並暴露出歐姆接觸層330。在電極層370包含透光導電材料的實施方式中,蝕刻後剩餘的半導體疊層320”的寬度實質上等於剩餘的電極層370’的寬度。在電極層370包含不透光的金屬材料的實施方式中,為了不影響發光二極體的出光效率,蝕刻後剩餘的電極層370’的 寬度通常小於剩餘的半導體疊層320”的寬度,舉例來說,剩餘的電極層370’的寬度大小只要能提供外接導線足夠的接合面積即可。 Next, part of the electrode layer 370, part of the semiconductor stack 320', part of the ohmic contact layer 330, and part of the base layer 340b of the precursor structure 40 are removed to expose the sacrificial layer 350. Figure 33 to Figure 34 are schematic cross-sectional views of an embodiment of the present invention for achieving this step. In this step, two removal processes are included. Referring to FIG. 33, the first removal process may use a lithography etching process to remove part of the electrode layer 370 and part of the semiconductor stack 320', and expose the ohmic contact layer 330. In the embodiment where the electrode layer 370 includes a light-transmitting conductive material, the width of the remaining semiconductor stack 320" after etching is substantially equal to the width of the remaining electrode layer 370'. In the implementation in which the electrode layer 370 includes an opaque metal material In the method, in order not to affect the light emitting efficiency of the light emitting diode, the remaining electrode layer 370' after etching The width is generally smaller than the width of the remaining semiconductor stack 320". For example, the width of the remaining electrode layer 370' is sufficient as long as it can provide a sufficient bonding area for the external wires.

請接著參閱第34圖,第二次移除製程可利用微影蝕刻製程來移除部分的歐姆接觸層330和部分的基底層340b,並暴露出犧牲層350。具體而言,剩餘的歐姆接觸層330’的寬度實質上等於剩餘的基底層340b’的寬度,且剩餘的歐姆接觸層330’的寬度大於剩餘的半導體疊層320”的寬度。 Please refer to FIG. 34. The second removal process may use a lithography etching process to remove part of the ohmic contact layer 330 and part of the base layer 340b, and expose the sacrificial layer 350. Specifically, the width of the remaining ohmic contact layer 330' is substantially equal to the width of the remaining base layer 340b', and the width of the remaining ohmic contact layer 330' is greater than the width of the remaining semiconductor stack 320".

第35圖繪示發光二極體結構20於其中一製造階段的上視圖。第36圖至第38A圖繪示發光二極體結構20於多個製造階段中根據第35圖線段A-A’的剖面示意圖。第38B圖繪示發光二極體結構20於其中一製造階段中根據第35圖線段B-B’的剖面示意圖。須說明的是,由於剖面視角關係,所以在第36圖至第38A圖中,剩餘的基底層340b’、剩餘的歐姆接觸層330’、剩餘的半導體疊層320”和剩餘的電極層370’都具有相同寬度。 FIG. 35 shows a top view of the light emitting diode structure 20 at one of the manufacturing stages. 36 to 38A are schematic cross-sectional views of the light-emitting diode structure 20 according to the line segment A-A' of FIG. 35 in multiple manufacturing stages. FIG. 38B is a schematic cross-sectional view of the light emitting diode structure 20 according to the line segment B-B' of FIG. 35 in one of the manufacturing stages. It should be noted that due to the cross-sectional viewing angle relationship, in FIGS. 36 to 38A, the remaining base layer 340b′, the remaining ohmic contact layer 330′, the remaining semiconductor stack 320″, and the remaining electrode layer 370′ Both have the same width.

請同時參閱第35圖及第36圖,形成開口352於犧牲層350中,以暴露出承載基板360的一部分。 Please refer to FIG. 35 and FIG. 36 at the same time. An opening 352 is formed in the sacrificial layer 350 to expose a part of the carrier substrate 360.

請參閱第37圖,接著形成絕緣層380連續地覆蓋剩餘的基底層340b’、剩餘的歐姆接觸層330’、剩餘的半導體疊層320”、剩餘的電極層370’、犧牲層350之一頂表面的一部分350a、開口352以及承載基板360暴露的所述部分。具體的說,絕緣層380具有第一部分380a覆蓋犧牲層 350頂表面的所述部分350a,且絕緣層380具有第二部分380b與其第一部分380a耦接並覆蓋剩餘多層結構(包含340b’、330’、320”和370’)的側壁。絕緣層380的第一部分380a和第二部分380b構成如「L」型。而未被絕緣層380覆蓋之部分的犧牲層350(即暴露的部分350P)與被絕緣層380的第一部分380a覆蓋的犧牲層350頂表面的所述部分350a分別位於剩餘多層結構(包含340b’、330’、320”和370’)的相對兩側。 Please refer to FIG. 37, then an insulating layer 380 is formed to continuously cover one of the remaining base layer 340b′, the remaining ohmic contact layer 330′, the remaining semiconductor stack 320″, the remaining electrode layer 370′, and the sacrificial layer 350 A portion 350a of the surface, the opening 352, and the exposed portion of the carrier substrate 360. Specifically, the insulating layer 380 has a first portion 380a covering the sacrificial layer The portion 350a of the top surface of 350, and the insulating layer 380 has a second portion 380b coupled to the first portion 380a and covers the sidewalls of the remaining multilayer structure (including 340b', 330', 320" and 370'). The first part 380a and the second part 380b are constructed like an "L" shape. The portion of the sacrificial layer 350 that is not covered by the insulating layer 380 (ie, the exposed portion 350P) and the portion 350a of the top surface of the sacrificial layer 350 that is covered by the first portion 380a of the insulating layer 380 are located in the remaining multilayer structure (including 340b' , 330', 320" and 370') on opposite sides.

請同時參閱第38A圖及第38B圖,移除犧牲層350。詳細的說,可以使用蝕刻溶液從犧牲層暴露的部分350P將犧牲層350移除。如第38A圖所示,當犧牲層350被蝕刻後,絕緣層380的一部分會形成一支撐架382,且支撐架382可將剩餘的電極層370’、剩餘的半導體疊層320”、剩餘的歐姆接觸層330’和剩餘的基底層340b’懸空地支撐於承載基板360的上方。由於在移除犧牲層350後,僅有支撐架382支撐上方結構,因此可以容易地使支撐架382斷開。此外,在某些實施例中,僅移除部分的犧牲層350。舉例來說,自犧牲層350的上表面移除部分的犧牲層350,使得剩餘的電極層370’、剩餘的半導體疊層320”、剩餘的歐姆接觸層330’和剩餘的基底層340b’懸空於承載基板360之上。也就是說,可以無需完全移除犠牲層350,只要讓支撐架382可以折斷即可。在第38B圖中,絕緣層380至少連續地覆蓋剩餘基底層340b’之一側壁、剩餘歐姆接觸層330’之一側壁、剩餘半導體疊層320”之一側壁以及剩餘電極層 370’之一側壁,並暴露出剩餘歐姆接觸層330’頂表面的一部分330’a。此剩餘歐姆接觸層330’頂表面暴露的部分330’a係作為電性接觸的載台。在某些實施方式中,絕緣層380亦可以覆蓋剩餘電極層370’頂表面的一部分。 Please refer to FIGS. 38A and 38B at the same time to remove the sacrificial layer 350. In detail, the sacrificial layer 350 may be removed from the exposed portion 350P of the sacrificial layer using an etching solution. As shown in FIG. 38A, after the sacrificial layer 350 is etched, a portion of the insulating layer 380 will form a support frame 382, and the support frame 382 may be used to replace the remaining electrode layer 370', the remaining semiconductor stack 320", and the remaining The ohmic contact layer 330' and the remaining base layer 340b' are suspended above the carrier substrate 360. Since only the support frame 382 supports the upper structure after the sacrificial layer 350 is removed, the support frame 382 can be easily broken In addition, in some embodiments, only part of the sacrificial layer 350 is removed. For example, part of the sacrificial layer 350 is removed from the upper surface of the sacrificial layer 350, so that the remaining electrode layer 370', the remaining semiconductor stack The layer 320 ″, the remaining ohmic contact layer 330 ′ and the remaining base layer 340 b ′ are suspended above the carrier substrate 360. In other words, it is not necessary to completely remove the animal layer 350, as long as the support frame 382 can be broken. In FIG. 38B, the insulating layer 380 at least continuously covers one side wall of the remaining base layer 340b', one side wall of the remaining ohmic contact layer 330', one side wall of the remaining semiconductor stack 320", and the remaining electrode layer One of the side walls of 370', and exposes a portion 330'a of the top surface of the remaining ohmic contact layer 330'. The exposed portion 330'a of the top surface of the remaining ohmic contact layer 330' serves as a stage for electrical contact. In some embodiments, the insulating layer 380 may also cover a portion of the top surface of the remaining electrode layer 370'.

請回到第38A圖,使絕緣層380的支撐架382斷裂,而形成單獨的發光二極體結構。應注意,在使支撐架382斷裂的步驟之後,將會在單獨的發光二極體結構上形成一支撐區域SP。更詳細的說,此支撐區域SP可包含支撐架382斷裂在第一部分380a和第二部分380b的轉折位置處382P,或者支撐架382斷裂在第一部分380a的任一處,又或者部分的第二部分380b脫離剩餘多層結構(340b’、330’、320”或370’)的側壁。在一些實施方式中,可以將此單獨的發光二極體結構設置於固晶基板170上以形成如第2圖所示之發光二極體結構20。此外,可以進一步在固晶基板170上先形成黏著層160後,再將此單獨的發光二極體設置於黏著層160上,以增加兩者之間的附著力。有關第2圖所繪示之發光二極體結構20的各種特徵已記載於上文中,在此不在贅述。值得注意的是,上述製程操作僅為例示性的示出,各操作可以依照需求任意的調換順序。在某些實施例中,在上述製程之前、期間或之後可以執行額外的操作。 Returning to FIG. 38A, the support frame 382 of the insulating layer 380 is broken to form a separate light-emitting diode structure. It should be noted that, after the step of breaking the support frame 382, a support area SP will be formed on the individual light emitting diode structure. In more detail, the support area SP may include the support frame 382 breaking at the turning position 382P of the first part 380a and the second part 380b, or the support frame 382 breaking at any place of the first part 380a, or the second part Part 380b is detached from the sidewall of the remaining multilayer structure (340b', 330', 320" or 370'). In some embodiments, this separate light emitting diode structure may be disposed on the solid crystal substrate 170 to form the second The light emitting diode structure 20 shown in the figure. In addition, an adhesive layer 160 may be further formed on the solid crystal substrate 170, and then the separate light emitting diode may be disposed on the adhesive layer 160 to increase the distance between the two. The adhesion of the light-emitting diode structure 20 shown in Figure 2 has been described above and will not be repeated here. It is worth noting that the above-mentioned process operations are only exemplary illustrations, each operation The order can be changed according to requirements. In some embodiments, additional operations can be performed before, during, or after the above process.

本發明之又一態樣是提供一種發光二極體結構30的製造方法。第39圖至第50圖繪示根據本發明一實施方式之製造發光二極體結構30於各階段的剖面示意圖。為了 便於比較與上述各實施方式之相異處並簡化說明,在下文之各實施例中使用相同的符號標注相同的元件,且主要針對各實施方式之相異處進行說明,而不再對重覆部分進行贅述。如第39圖所示,首先,提供一前驅結構70。此前驅結構70由上至下依序包含電極層370、磊晶疊層320以及生長基板310。具體的說,磊晶疊層320由上而下包含第一型半導體層322、發光層324、第二型半導體層326和未摻雜III-V族半導體層328位於生長基板310上,其中第二型半導體層326包含第一部分326a和第二部分326b,且第一部分326a位於第二部分326b上。 Another aspect of the present invention is to provide a method for manufacturing the light emitting diode structure 30. 39 to 50 are schematic cross-sectional views at various stages of manufacturing the light-emitting diode structure 30 according to an embodiment of the present invention. in order to It is convenient to compare the differences between the above embodiments and simplify the description. In the following examples, the same symbols are used to mark the same elements, and the differences between the embodiments are mainly described, and the description is not repeated. Repeat in part. As shown in FIG. 39, first, a precursor structure 70 is provided. The precursor structure 70 includes an electrode layer 370, an epitaxial stack 320, and a growth substrate 310 in order from top to bottom. Specifically, the epitaxial stack 320 includes a first-type semiconductor layer 322, a light-emitting layer 324, a second-type semiconductor layer 326, and an undoped III-V semiconductor layer 328 located on the growth substrate 310 from top to bottom. The type-two semiconductor layer 326 includes a first portion 326a and a second portion 326b, and the first portion 326a is located on the second portion 326b.

接著,請參閱第40圖,移除如第39圖所繪示前驅結構70之部分的電極層370和部分的磊晶疊層320,使得剩餘的第一部分326a’的寬度小於第二部分326b的寬度。更詳細的說,在移除部分的磊晶疊層320時,僅移除第二型半導體層326之第一部分326a的一部分,使得第二型半導體層326的第二部分326b暴露出來。因此,在完成此步驟之後,剩餘電極層370’的寬度實質上等於剩餘第一型半導體層322’的寬度,剩餘發光層324’的寬度實質上等於第一型半導體層322’的寬度,且第二型半導體層326之剩餘的第一部分326a’的寬度實質上等於第一型半導體層322’的寬度。在一實施例中,可以利用微影蝕刻製程並控制蝕刻製程的時間來完成此步驟。 Next, referring to FIG. 40, remove part of the electrode layer 370 and part of the epitaxial stack 320 of the precursor structure 70 as shown in FIG. 39, so that the width of the remaining first part 326a' is smaller than that of the second part 326b width. In more detail, when a part of the epitaxial stack 320 is removed, only a part of the first part 326a of the second type semiconductor layer 326 is removed, so that the second part 326b of the second type semiconductor layer 326 is exposed. Therefore, after completing this step, the width of the remaining electrode layer 370' is substantially equal to the width of the remaining first-type semiconductor layer 322', and the width of the remaining light-emitting layer 324' is substantially equal to the width of the first-type semiconductor layer 322', and The width of the remaining first portion 326a' of the second type semiconductor layer 326 is substantially equal to the width of the first type semiconductor layer 322'. In one embodiment, the lithography etching process and the time of the etching process can be controlled to complete this step.

請接著參閱第41圖,形成絕緣層380覆蓋在如第40圖所繪示之剩餘的前驅結構70’上。更具體的說,絕緣 層380是連續地覆蓋第二型半導體層326之第二部分326b暴露出來的表面、第二型半導體層326之剩餘的第一部分326a’的側壁、剩餘發光層324’的側壁、剩餘第一型半導體層322’的側壁以及剩餘電極層370’的側壁和表面。 Next, referring to FIG. 41, an insulating layer 380 is formed to cover the remaining precursor structure 70' as shown in FIG. 40. More specifically, insulation The layer 380 continuously covers the exposed surface of the second portion 326b of the second type semiconductor layer 326, the sidewall of the remaining first portion 326a' of the second type semiconductor layer 326, the sidewall of the remaining light emitting layer 324', and the remaining first type The sidewall of the semiconductor layer 322' and the sidewall and surface of the remaining electrode layer 370'.

如第42圖所示,然後移除部分的絕緣層380以及第二型半導體層326之第二部分326b的一部分,以暴露出未摻雜半導體層328。在一實施例中,可以利用微影蝕刻製程來完成此步驟。應注意,完成此步驟之後,剩餘的第二型半導體層326’之第二部分326b’的寬度必須大於第一部分326a’的寬度。這樣的設計,使得剩餘的第二型半導體層326’之第二部分326b’可以作為電性接觸的載台。 As shown in FIG. 42, a part of the insulating layer 380 and a part of the second part 326b of the second type semiconductor layer 326 are then removed to expose the undoped semiconductor layer 328. In one embodiment, a lithography etching process can be used to complete this step. It should be noted that after completing this step, the width of the second portion 326b' of the remaining second type semiconductor layer 326' must be greater than the width of the first portion 326a'. This design allows the second portion 326b' of the remaining second type semiconductor layer 326' to serve as a stage for electrical contact.

如第43圖所示,在某些實施方式中,可以在剩餘的第二型半導體層326’之第二部分326b’上形成一導電塊390。在一實施例中,形成導電塊390的方法例如包括下列步驟。首先,在預計形成導電塊390的絕緣層380上形成一圖案化罩幕(圖未示),而圖案化罩幕具有一開口(圖未示),以使剩餘第二型半導體層326’之第二部分326b’的一部分由開口380R2中暴露出來。之後,藉由濺鍍、蒸鍍、電鍍或化學鍍的方式在開口380R2中形成導電塊390。在一些實施例中,導電塊390包含鋁(aluminum)、銅(copper)、鎳(nickel)、金(gold)、鉑(platinum)、鈦(titanium)或其他合適的金屬材料。在一些實施例中,位於剩餘電極層370’上之絕緣層380的頂表面380t與導電塊390之頂表面390t實質上齊平。 As shown in FIG. 43, in some embodiments, a conductive block 390 may be formed on the second portion 326b' of the remaining second-type semiconductor layer 326'. In one embodiment, the method of forming the conductive block 390 includes the following steps, for example. First, a patterned mask (not shown) is formed on the insulating layer 380 where the conductive block 390 is expected to be formed, and the patterned mask has an opening (not shown) so that the remaining second type semiconductor layer 326' A part of the second part 326b' is exposed through the opening 380R2. Thereafter, a conductive block 390 is formed in the opening 380R2 by sputtering, evaporation, electroplating, or electroless plating. In some embodiments, the conductive block 390 includes aluminum, copper, nickel, gold, platinum, titanium, or other suitable metal materials. In some embodiments, the top surface 380t of the insulating layer 380 on the remaining electrode layer 370' is substantially flush with the top surface 390t of the conductive block 390.

如第44圖所示,在剩餘電極層370’上的絕緣層380中形成一開口380R1,以暴露出剩餘電極層370’的一部分。在一實施例中,形成開口380R1的方法例如可預計形成開口380R1的絕緣層380上形成一圖案化罩幕(圖未示),而圖案化罩幕具有一開口(圖未示),以使剩餘電極層370’的一部分由開口380R1中暴露出來。 As shown in FIG. 44, an opening 380R1 is formed in the insulating layer 380 on the remaining electrode layer 370' to expose a part of the remaining electrode layer 370'. In one embodiment, the method of forming the opening 380R1 can be expected to form a patterned mask (not shown) on the insulating layer 380 forming the opening 380R1, and the patterned mask has an opening (not shown), so that A part of the remaining electrode layer 370' is exposed through the opening 380R1.

接著,如第45圖所示,形成第一導電墊432於開口380R1中並形成第二導電墊434覆蓋導電塊390的頂表面390t及其側壁390s。在多個實施例中,第一導電墊432和第二導電墊434可以包含鋁(aluminum)、銅(copper)、鎳(nickel)、金(gold)、鉑(platinum)、鈦(titanium)或其他合適的導電材料。在某些實施例中,可以藉由濺鍍、蒸鍍、電鍍或化學鍍的方式來形成第一導電墊432和第二導電墊434。在一實施例中,第一導電墊432和第二導電墊434可以同時製作,或者可以分開製作。 Next, as shown in FIG. 45, a first conductive pad 432 is formed in the opening 380R1 and a second conductive pad 434 is formed to cover the top surface 390t of the conductive block 390 and its side wall 390s. In various embodiments, the first conductive pad 432 and the second conductive pad 434 may include aluminum, copper, nickel, gold, platinum, titanium, or titanium. Other suitable conductive materials. In some embodiments, the first conductive pad 432 and the second conductive pad 434 may be formed by sputtering, evaporation, electroplating, or electroless plating. In an embodiment, the first conductive pad 432 and the second conductive pad 434 can be fabricated at the same time, or can be fabricated separately.

請參閱第46圖,形成犧牲層350覆蓋如第45圖所繪示之結構。更詳細的說,犧牲層350覆蓋絕緣層380、第一導電墊432和第二導電墊434,且犧牲層350具有一開口350R暴露出絕緣層380。更詳細的說,開口350R位於第一導電墊432和第二導電墊434之間。 Referring to FIG. 46, a sacrificial layer 350 is formed to cover the structure shown in FIG. 45. In more detail, the sacrificial layer 350 covers the insulating layer 380, the first conductive pad 432 and the second conductive pad 434, and the sacrificial layer 350 has an opening 350R to expose the insulating layer 380. In more detail, the opening 350R is located between the first conductive pad 432 and the second conductive pad 434.

請參閱第47圖,接著,形成一支撐層410覆蓋犧牲層350上並填滿開口350R。在一些實施例中,支撐層410可包含絕緣材料、金屬材料或其他具有支撐效果的材料。舉例來說,絕緣材料包含氧化矽、氮化矽、氮氧化矽、 環氧樹脂;而金屬材料包含鋁、鈦、金、鉑或鎳等,但不以此為限。 Please refer to FIG. 47. Next, a support layer 410 is formed to cover the sacrificial layer 350 and fill the opening 350R. In some embodiments, the supporting layer 410 may include an insulating material, a metal material, or other materials having a supporting effect. For example, the insulating material includes silicon oxide, silicon nitride, silicon oxynitride, Epoxy resin; and metal materials include aluminum, titanium, gold, platinum or nickel, etc., but not limited to this.

如第48圖所示,然後形成承載基板360於支撐層410上。在多個實施例中,可以藉由一黏著層420將承載基板360黏附至支撐層410上,以提高承載基板360與支撐層410之間的結合力。應注意,在支撐層410上形成承載基板360之後,將如第48圖所繪示之結構翻轉使生長基板310位於頂部且承載基板360位於底部。接著,請參閱第49圖,移除生長基板310以及未摻雜半導體層328,並暴露出剩餘第二型半導體層326’之一表面326s。在一實施方式中,剩餘第二型半導體層326’所暴露出來的表面326s具有一粗糙紋理(圖未示)。在多個示例中,粗糙紋理可以包含規則圖案或不規則圖案。 As shown in FIG. 48, a carrier substrate 360 is then formed on the support layer 410. In various embodiments, an adhesive layer 420 may be used to adhere the carrier substrate 360 to the support layer 410 to improve the bonding force between the carrier substrate 360 and the support layer 410. It should be noted that after the carrier substrate 360 is formed on the support layer 410, the structure as shown in FIG. 48 is turned so that the growth substrate 310 is at the top and the carrier substrate 360 is at the bottom. Next, referring to FIG. 49, the growth substrate 310 and the undoped semiconductor layer 328 are removed, and a surface 326s of the remaining second type semiconductor layer 326' is exposed. In one embodiment, the exposed surface 326s of the remaining second type semiconductor layer 326' has a rough texture (not shown). In various examples, the rough texture may contain regular patterns or irregular patterns.

請參閱第50圖,移除犧牲層350。詳細的說,可以使用蝕刻溶液將犧牲層350移除。當犧牲層350被蝕刻後,支撐層410的一部分會形成一支撐架412,且支撐架412可將預計要形成的發光二極體結構懸空地支撐於支撐層410的上方。由於在移除犧牲層350後,僅有支撐架412支撐上方結構,因此可以容易地使支撐架412斷開。此外,在某些實施例中,僅移除部分的犧牲層350。也就是說,可以無需完全移除犠牲層350,只要能讓支撐架412可以折斷即可。然後,使支撐層410的支撐架412斷裂,而形成單獨的一發光二極體結構。在一實施例中,當支撐架412斷裂後,此單獨的發光二極體結構上可能會殘留支撐架412的一部 分,且此殘留的部分支撐架412並不會再次地被清除乾淨。在另一實施例中,當支撐架412斷裂後,此單獨的發光二極體結構上可能完全不會殘留支撐架412。在其他實施例中,為了要使支撐架412斷裂,可能會移除掉單獨的發光二極體結構上部分的絕緣層380。在一些實施方式中,可以將此單獨的發光二極體結構中的第一導電墊432和第二導電墊434分別藉由第一黏著層162和第二黏著層164電性對接至固晶基板170上以形成如第3圖所示之發光二極體結構30。有關第3圖所繪示之發光二極體結構30的各種特徵已記載於上文中,在此不在贅述。值得注意的是,上述製程操作僅為例示性的示出,各操作可以依照需求任意的調換順序。在某些實施例中,在上述製程之前、期間或之後可以執行額外的操作。 Referring to FIG. 50, the sacrificial layer 350 is removed. In detail, the sacrificial layer 350 can be removed using an etching solution. After the sacrificial layer 350 is etched, a part of the support layer 410 will form a support frame 412, and the support frame 412 may support the light emitting diode structure to be formed to be suspended above the support layer 410. Since only the support frame 412 supports the upper structure after the sacrificial layer 350 is removed, the support frame 412 can be easily broken. Furthermore, in some embodiments, only a portion of the sacrificial layer 350 is removed. In other words, it is not necessary to completely remove the animal layer 350, as long as the support frame 412 can be broken. Then, the support frame 412 of the support layer 410 is broken to form a single light-emitting diode structure. In an embodiment, after the support frame 412 breaks, a part of the support frame 412 may remain on the separate light-emitting diode structure The remaining partial support frame 412 will not be cleaned again. In another embodiment, after the support frame 412 is broken, the support frame 412 may not remain on the structure of the single light-emitting diode at all. In other embodiments, in order to break the support frame 412, the insulating layer 380 on the upper part of the separate light emitting diode structure may be removed. In some embodiments, the first conductive pad 432 and the second conductive pad 434 in the separate light-emitting diode structure can be electrically connected to the solid crystal substrate through the first adhesive layer 162 and the second adhesive layer 164, respectively 170 to form the light emitting diode structure 30 as shown in FIG. 3. Various features of the light emitting diode structure 30 shown in FIG. 3 have been described above, and are not repeated here. It is worth noting that the above-mentioned process operations are only illustrative, and each operation can be arbitrarily exchanged in accordance with requirements. In some embodiments, additional operations may be performed before, during, or after the above process.

本發明之發光二極體結構及其製造方法除了可以應用於傳統發光二極體和尺寸降至微米(μm)等級的微發光二極體之外,還可以廣泛地應用於顯示器及穿戴式裝置中。 The light-emitting diode structure and its manufacturing method of the present invention can be applied not only to traditional light-emitting diodes and micro-light-emitting diodes down to the micron (μm) level, but also to displays and wearable devices. in.

綜上所述,本發明所提供的發光二極體結構可包含分散式布拉格反射鏡或金屬層,以將發光二極體發出的光導引為向上發射的光線,進而增加出光效率。且由於本發明發光二極體結構中之電性接觸層的寬度大於半導體疊層的寬度,因此電性接觸層可以作為電性接觸的載台。再者,本發明發光二極體結構的電性接觸層還可以包含雙層導電層(例如,歐姆接觸層及金屬層)。導電層的設計可以確保發光二極體結構具有可以作為導電接觸的載台。此 外,本發明所提供的發光二極體結構還可以利用第二型半導體層的第二部分來代替電性接觸層作為電性接觸的載台,且第二型半導體層之第二部分所暴露出之具有粗糙紋理的表面可以提升出光效率。 In summary, the light-emitting diode structure provided by the present invention may include a distributed Bragg reflector or a metal layer to guide the light emitted by the light-emitting diode as upwardly emitted light, thereby increasing the light extraction efficiency. Moreover, since the width of the electrical contact layer in the light emitting diode structure of the present invention is greater than the width of the semiconductor stack, the electrical contact layer can be used as a stage for electrical contact. Furthermore, the electrical contact layer of the light emitting diode structure of the present invention may further include a double-layer conductive layer (for example, an ohmic contact layer and a metal layer). The design of the conductive layer can ensure that the light-emitting diode structure has a stage that can serve as a conductive contact. this In addition, the light-emitting diode structure provided by the present invention can also use the second part of the second type semiconductor layer to replace the electrical contact layer as a stage for electrical contact, and the second part of the second type semiconductor layer is exposed The surface with rough texture can improve the light extraction efficiency.

此外,相較於需經過兩次暫時基板的接合及兩次移除暫時基板製程的傳統製造方法,本發明所提供之發光二極體結構的製造方法僅需一次暫時基板的接合及一次移除暫時基板的製程。在製程良率、對位以及發光二極體間距的精準度上有大幅的改善。而且,在發光二極體結構轉移的過程中,利用支架的形成,可以減少發光二極體的轉移時間。 In addition, compared to the traditional manufacturing method that requires two temporary substrate bonding and two temporary substrate removal processes, the manufacturing method of the light emitting diode structure provided by the present invention only requires one temporary substrate bonding and one removal Temporary substrate manufacturing process. There is a significant improvement in process yield, alignment, and accuracy of LED spacing. Moreover, in the process of transferring the structure of the light emitting diode, the use of the formation of the bracket can reduce the transfer time of the light emitting diode.

雖然本發明已以實施方式揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed as above in an embodiment, it is not intended to limit the present invention. Anyone who is familiar with this art can make various modifications and retouching without departing from the spirit and scope of the present invention, so the protection of the present invention The scope shall be as defined in the appended patent application scope.

10‧‧‧發光二極體結構 10‧‧‧ LED structure

110‧‧‧基底層 110‧‧‧ Basement

120‧‧‧電性接觸層 120‧‧‧Electrical contact layer

122‧‧‧第一金屬層 122‧‧‧First metal layer

124‧‧‧歐姆接觸層 124‧‧‧ohm contact layer

130‧‧‧半導體疊層 130‧‧‧semiconductor stack

132‧‧‧第一型半導體層 132‧‧‧Type 1 semiconductor layer

134‧‧‧發光層 134‧‧‧luminous layer

136‧‧‧第二型半導體層 136‧‧‧Type 2 semiconductor layer

140‧‧‧絕緣層 140‧‧‧Insulation

150‧‧‧電極層 150‧‧‧electrode layer

160‧‧‧黏著層 160‧‧‧adhesive layer

170‧‧‧固晶基板 170‧‧‧Solid crystal substrate

W1、W2、W3、W4、W5‧‧‧最大寬度 W1, W2, W3, W4, W5 ‧‧‧ maximum width

Claims (19)

一種發光二極體結構,包含:一基底層,具有一最大第一寬度;一電性接觸層,具有一最大第二寬度並設置於該基底層上;一半導體疊層,具有一最大第三寬度並設置於該電性接觸層上,且該半導體疊層接觸該電性接觸層,該半導體疊層包括一第一型半導體層、一發光層及一第二型半導體層依序堆疊,其中該第一型半導體層、該發光層及該第二型半導體層的寬度實質上皆小於或等於該最大第三寬度;以及一絕緣層,至少覆蓋該基底層之一側壁、該電性接觸層之一側壁及該半導體疊層之一側壁,其中該最大第二寬度大於該最大第三寬度,且該最大第二寬度小於或等於該最大第一寬度。 A light emitting diode structure includes: a base layer having a maximum first width; an electrical contact layer having a maximum second width and disposed on the base layer; a semiconductor stack having a maximum third The width is set on the electrical contact layer, and the semiconductor stack contacts the electrical contact layer, the semiconductor stack includes a first type semiconductor layer, a light emitting layer and a second type semiconductor layer are sequentially stacked, wherein The widths of the first type semiconductor layer, the light emitting layer and the second type semiconductor layer are substantially less than or equal to the maximum third width; and an insulating layer covering at least one side wall of the base layer and the electrical contact layer A sidewall and a sidewall of the semiconductor stack, wherein the maximum second width is greater than the maximum third width, and the maximum second width is less than or equal to the maximum first width. 如申請專利範圍第1項的發光二極體結構,其中該電性接觸層為單層,且該最大第二寬度實質上等於該最大第一寬度。 As in the light-emitting diode structure of claim 1, the electrical contact layer is a single layer, and the maximum second width is substantially equal to the maximum first width. 如申請專利範圍第1項的發光二極體結構,該電性接觸層包括一歐姆接觸層及一第一金屬層,該歐姆接觸層具有一最大第四寬度並設置於該半導體疊層與該基底層之間,該第一金屬層具有一最大第五寬度並設置於 該歐姆接觸層與該基底層之間,該最大第四寬度小於或實質上等於該最大第一寬度,且該最大第五寬度實質上等於該最大第一寬度。 As in the light-emitting diode structure of claim 1, the electrical contact layer includes an ohmic contact layer and a first metal layer. The ohmic contact layer has a maximum fourth width and is disposed on the semiconductor stack and the Between the base layers, the first metal layer has a maximum fifth width and is disposed on Between the ohmic contact layer and the base layer, the maximum fourth width is less than or substantially equal to the maximum first width, and the maximum fifth width is substantially equal to the maximum first width. 如申請專利範圍第3項的發光二極體結構,其中該最大第四寬度實質上等於該最大第三寬度。 A light emitting diode structure as claimed in item 3 of the patent scope, wherein the maximum fourth width is substantially equal to the maximum third width. 如申請專利範圍第1項的發光二極體結構,更包含一電極層設置於該半導體疊層上。 For example, the light-emitting diode structure of the first item of the patent application scope further includes an electrode layer disposed on the semiconductor stack. 如申請專利範圍第5項的發光二極體結構,其中該電極層可被該發光層所發出的光穿透。 For example, in the light-emitting diode structure of claim 5, the electrode layer can be penetrated by the light emitted by the light-emitting layer. 如申請專利範圍第5項的發光二極體結構,其中該電極層為一第二金屬層。 For example, in the light-emitting diode structure of claim 5, the electrode layer is a second metal layer. 如申請專利範圍第1項的發光二極體結構,其中該基底層包含介電材料或金屬材料。 The light emitting diode structure as claimed in item 1 of the patent scope, wherein the base layer comprises a dielectric material or a metal material. 如申請專利範圍第1項的發光二極體結構,該基底層包含一分散式布拉格反射鏡(Distributed Bragg Reflector),且該絕緣層至少覆蓋該分散式布拉格反射鏡之一側壁。 As in the light-emitting diode structure of claim 1, the base layer includes a distributed Bragg reflector (Distributed Bragg Reflector), and the insulating layer covers at least one side wall of the distributed Bragg reflector. 如申請專利範圍第9項的發光二極體結構,當該基底層包含該分散式布拉格反射鏡時,該電性接觸層可被該發光層所發出的光穿透。 As in the light-emitting diode structure of the ninth patent application, when the base layer includes the dispersed Bragg reflector, the electrical contact layer can be penetrated by the light emitted by the light-emitting layer. 一種發光二極體結構,包含:一半導體疊層,由上而下依序包括一第一型半導體層、一發光層及一第二型半導體層,其中該第二型半導體層包含一第一部分和一第二部分,且該第一部分位於該第二部分上,該第二部分的最大寬度大於該第一部分的最大寬度;一絕緣層,覆蓋該半導體疊層之一側壁以及該第二部分之一上表面,且該絕緣層具有一第一開口以及一第二開口分別位於該第一型半導體層及該第二部分上;一第一導電墊,藉由該第一開口電性連接至該第一型半導體層;一第二導電墊,藉由該第二開口電性連接至該第二部分;以及一支撐區域,位於該絕緣層上方且位於該第一導電墊與該第二導電墊之間,該支撐區域與該第一導電墊和該第二導電墊之間分別間隔一距離。 A light emitting diode structure includes: a semiconductor stack including a first type semiconductor layer, a light emitting layer and a second type semiconductor layer in order from top to bottom, wherein the second type semiconductor layer includes a first portion And a second part, and the first part is located on the second part, the maximum width of the second part is greater than the maximum width of the first part; an insulating layer covering one side wall of the semiconductor stack and the second part An upper surface, and the insulating layer has a first opening and a second opening respectively located on the first type semiconductor layer and the second portion; a first conductive pad is electrically connected to the through the first opening A first-type semiconductor layer; a second conductive pad electrically connected to the second portion through the second opening; and a support area located above the insulating layer and located between the first conductive pad and the second conductive pad There is a distance between the supporting area and the first conductive pad and the second conductive pad respectively. 如申請專利範圍第11項的發光二極體結構,更包含一固晶基板電性對接該第一導電墊和該第二導電墊。 For example, the light-emitting diode structure according to item 11 of the patent application further includes a solid crystal substrate electrically connected to the first conductive pad and the second conductive pad. 如申請專利範圍第12項的發光二極體結構,更包含一第一黏著層以及一第二黏著層分別位於該第一導電墊與該固晶基板之間以及該第二導電墊與該固晶基板之間,其中該第一黏著層與該第二黏著層之間電性絕緣。 For example, the light-emitting diode structure according to item 12 of the patent application scope further includes a first adhesive layer and a second adhesive layer respectively located between the first conductive pad and the solid crystal substrate and the second conductive pad and the solid Between the crystal substrates, the first adhesive layer and the second adhesive layer are electrically insulated. 如申請專利範圍第11項的發光二極體結構,更包含一電極層設置於該第一型半導體層與該第一導電墊之間。 For example, the light-emitting diode structure of claim 11 of the patent application further includes an electrode layer disposed between the first type semiconductor layer and the first conductive pad. 如申請專利範圍第11項的發光二極體結構,更包含一導電塊設置於該第二開口中,且該第二導電墊覆蓋該導電塊之一頂表面及一側壁。 For example, the light-emitting diode structure of claim 11 further includes a conductive block disposed in the second opening, and the second conductive pad covers a top surface and a side wall of the conductive block. 如申請專利範圍第15項的發光二極體結構,其中位於該第一部分上之該絕緣層的一頂表面與該導電塊之該頂表面實質上齊平。 As in the light-emitting diode structure of claim 15, the top surface of the insulating layer on the first portion is substantially flush with the top surface of the conductive block. 如申請專利範圍第11項的發光二極體結構,其中該第一導電墊延伸覆蓋該絕緣層的一部分。 A light emitting diode structure as claimed in item 11 of the patent application, wherein the first conductive pad extends to cover a part of the insulating layer. 如申請專利範圍第11項的發光二極體結構,其中該第一導電墊之一頂表面與該第二導電墊之一頂 表面實質上齊平。 A light emitting diode structure as claimed in item 11 of the patent application, wherein a top surface of the first conductive pad and a top of the second conductive pad The surface is substantially flush. 如申請專利範圍第11項的發光二極體結構,其中該第二型半導體層具有暴露在外之一表面,且該表面具有一粗糙紋理。 A light emitting diode structure as claimed in item 11 of the patent application, wherein the second type semiconductor layer has a surface exposed to the outside, and the surface has a rough texture.
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