TW202327133A - Light-emitting element, light-emitting assembly and display device including the same and manufacturing method of display device - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 210
- 239000010410 layer Substances 0.000 claims description 214
- 239000000758 substrate Substances 0.000 claims description 77
- 239000000463 material Substances 0.000 claims description 35
- 239000011241 protective layer Substances 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 14
- 239000012790 adhesive layer Substances 0.000 claims description 12
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 5
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 4
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 3
- 239000011368 organic material Substances 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 238000007788 roughening Methods 0.000 claims description 2
- 239000013256 coordination polymer Substances 0.000 description 24
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 238000000605 extraction Methods 0.000 description 11
- 239000010936 titanium Substances 0.000 description 9
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 8
- 150000002739 metals Chemical class 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 238000012546 transfer Methods 0.000 description 5
- 229910005540 GaP Inorganic materials 0.000 description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229910002601 GaN Inorganic materials 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 3
- 239000011651 chromium Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 239000003292 glue Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- PFNQVRZLDWYSCW-UHFFFAOYSA-N (fluoren-9-ylideneamino) n-naphthalen-1-ylcarbamate Chemical compound C12=CC=CC=C2C2=CC=CC=C2C1=NOC(=O)NC1=CC=CC2=CC=CC=C12 PFNQVRZLDWYSCW-UHFFFAOYSA-N 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 238000000427 thin-film deposition Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920000307 polymer substrate Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- -1 region Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
- H01L33/54—Encapsulations having a particular shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Led Devices (AREA)
- Led Device Packages (AREA)
- Electroluminescent Light Sources (AREA)
- Illuminated Signs And Luminous Advertising (AREA)
Abstract
Description
本發明是有關於一種發光元件、包含其之發光組件及顯示裝置、以及顯示裝置之製造方法。The invention relates to a light-emitting element, a light-emitting component including the same, a display device, and a manufacturing method of the display device.
微型發光二極體(micro-LED)因其具低功耗、高亮度、高解析度及高色彩飽和度等特性,因而適用於構建微型發光二極體顯示裝置之畫素結構。由於微型發光二極體的尺寸極小,目前製作微型發光二極體顯示裝置的方法是採用巨量轉移(Mass Transfer)技術,亦即利用微機電陣列技術進行微型發光二極體晶粒取放,以將大量的微型發光二極體晶粒一次搬運到具有畫素電路的驅動背板上。Due to its low power consumption, high brightness, high resolution, and high color saturation, micro-LEDs are suitable for constructing pixel structures of micro-LED display devices. Due to the extremely small size of micro light emitting diodes, the current method of manufacturing micro light emitting diode display devices is to use mass transfer (Mass Transfer) technology, that is, to use micro electromechanical array technology to pick and place micro light emitting diode crystals. To transport a large number of miniature light-emitting diode crystals to the driver backplane with pixel circuits at one time.
為了能夠進行巨量轉移,必須使發光元件處於懸吊狀態。目前,用以懸吊發光元件的繫連件主要是使用氧化矽(SiOx),因其具有較低的斷裂強度(fracture strength)。然而,繫連件同時會形成於發光元件的表面,由於氧化矽的折射率相對於發光元件的半導體層較低,造成發光元件發出的光容易發生全反射,導致發光元件的光取出效率(light extraction efficiency,LEE)降低。In order to enable mass transfer, the light-emitting element must be in a suspended state. At present, silicon oxide (SiOx) is mainly used as a connecting member for suspending light-emitting devices because of its low fracture strength. However, the tie piece will be formed on the surface of the light-emitting element at the same time. Since the refractive index of silicon oxide is lower than that of the semiconductor layer of the light-emitting element, the light emitted by the light-emitting element is prone to total reflection, resulting in the light extraction efficiency of the light-emitting element (light extraction efficiency, LEE) decreased.
本發明提供一種發光元件,具有提高的光取出效率。The present invention provides a light emitting element having improved light extraction efficiency.
本發明提供一種發光組件,具有提高的光取出效率。The present invention provides a light emitting component with improved light extraction efficiency.
本發明提供一種顯示裝置,具有提高的光取出效率。The present invention provides a display device having improved light extraction efficiency.
本發明提供一種顯示裝置的製造方法,能夠提供具有提高的光取出效率的顯示裝置。The present invention provides a method for manufacturing a display device capable of providing a display device with improved light extraction efficiency.
本發明的一個實施例提出一種發光元件,包括:第一型半導體圖案;第二型半導體圖案,重疊於第一型半導體圖案,且位於第一型半導體圖案的第一側;發光圖案,位於第一型半導體圖案與第二型半導體圖案之間;第一電極,位於第一型半導體圖案的第二側,第二側與第一側相對,且第一電極連接第一型半導體圖案;第二電極,位於第二型半導體圖案上與第一型半導體圖案相同的一側,且連接第二型半導體圖案;以及保護層,位於第二型半導體圖案上與第一型半導體圖案相對的一側,且保護層與第二型半導體圖案的折射率差小於1.8。An embodiment of the present invention provides a light-emitting element, including: a first-type semiconductor pattern; a second-type semiconductor pattern overlapping the first-type semiconductor pattern and located on the first side of the first-type semiconductor pattern; a light-emitting pattern located on the second Between the first-type semiconductor pattern and the second-type semiconductor pattern; the first electrode is located on the second side of the first-type semiconductor pattern, the second side is opposite to the first side, and the first electrode is connected to the first-type semiconductor pattern; the second an electrode located on the second type semiconductor pattern on the same side as the first type semiconductor pattern and connected to the second type semiconductor pattern; and a protective layer located on the second type semiconductor pattern on the side opposite to the first type semiconductor pattern, And the refractive index difference between the protection layer and the second type semiconductor pattern is less than 1.8.
在本發明的一實施例中,上述的保護層的折射率大於1.46。In an embodiment of the present invention, the above protective layer has a refractive index greater than 1.46.
在本發明的一實施例中,上述的保護層包括氮化矽、氮氧化矽、氧化鋁、氧化鈦、二氧化鉿、二氧化鋯、類鑽碳或非晶碳。In an embodiment of the present invention, the protective layer includes silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, hafnium dioxide, zirconium dioxide, diamond-like carbon or amorphous carbon.
在本發明的一實施例中,上述的第二型半導體圖案包括P型半導體材料。In an embodiment of the present invention, the above-mentioned second-type semiconductor pattern includes a P-type semiconductor material.
在本發明的一實施例中,上述的第二型半導體圖案的厚度介於1 μm至3 μm之間。In an embodiment of the present invention, the above-mentioned second-type semiconductor pattern has a thickness between 1 μm and 3 μm.
在本發明的一實施例中,上述的第一型半導體圖案的厚度介於0.1 μm至1 μm之間。In an embodiment of the present invention, the above-mentioned first-type semiconductor pattern has a thickness between 0.1 μm and 1 μm.
本發明的一個實施例提出一種發光組件,包括:載板;多個支撐件,位於載板上;以及上述的發光元件,藉由繫連件懸吊於多個支撐件之間。An embodiment of the present invention provides a light-emitting component, including: a carrier board; a plurality of supports located on the carrier; and the above-mentioned light-emitting element suspended between the plurality of supports by means of a tie.
在本發明的一實施例中,上述的繫連件延伸於第二型半導體圖案、發光圖案以及第一型半導體圖案的側壁,且連接支撐件。In an embodiment of the present invention, the above-mentioned connecting member extends to the sidewalls of the second-type semiconductor pattern, the light-emitting pattern, and the first-type semiconductor pattern, and is connected to the supporting member.
在本發明的一實施例中,上述的繫連件還延伸於第一型半導體圖案及第二型半導體圖案上與保護層相對的一側,且第一電極及第二電極分別通過繫連件中的第一通孔連接第一型半導體圖案及第二型半導體圖案。In an embodiment of the present invention, the above-mentioned connecting member also extends on the side opposite to the protective layer on the first-type semiconductor pattern and the second-type semiconductor pattern, and the first electrode and the second electrode pass through the connecting member respectively. The first through hole in the connecting hole is connected with the first type semiconductor pattern and the second type semiconductor pattern.
在本發明的一實施例中,上述的繫連件的材料與保護層的材料不同。In an embodiment of the present invention, the material of the above-mentioned fastening element is different from that of the protective layer.
在本發明的一實施例中,上述的保護層的折射率大於繫連件的折射率。In an embodiment of the present invention, the refractive index of the protective layer is greater than the refractive index of the tie element.
在本發明的一實施例中,上述的繫連件包括氧化矽。In an embodiment of the present invention, the above-mentioned connecting element includes silicon oxide.
在本發明的一實施例中,上述的發光組件還包括支撐層,位於支撐件及發光元件與載板之間。In an embodiment of the present invention, the above-mentioned light-emitting component further includes a support layer located between the support member, the light-emitting element and the carrier.
本發明的一個實施例提出一種顯示裝置,包括:電路基板;以及上述的發光元件,位於電路基板上,且電性連接電路基板。An embodiment of the present invention provides a display device, including: a circuit substrate; and the above-mentioned light-emitting element located on the circuit substrate and electrically connected to the circuit substrate.
在本發明的一實施例中,上述的電路基板還包括第一接墊及第二接墊,且第一接墊電性連接第一電極,第二接墊電性連接第二電極。In an embodiment of the present invention, the above-mentioned circuit substrate further includes a first pad and a second pad, and the first pad is electrically connected to the first electrode, and the second pad is electrically connected to the second electrode.
在本發明的一實施例中,上述的電路基板還包括開關元件,且開關元件電性連接第一接墊或第二接墊。In an embodiment of the present invention, the above-mentioned circuit substrate further includes a switch element, and the switch element is electrically connected to the first pad or the second pad.
本發明的一個實施例提出一種顯示裝置的製造方法,包括:提供生長基板;形成多層半導體層於生長基板上;形成第一犧牲層於多層半導體層上;形成中介基板於第一犧牲層上;移除生長基板;圖案化多層半導體層,以形成半導體疊層;形成繫連件於半導體疊層及中介基板上,且繫連件具有露出半導體疊層的多個第一通孔;分別形成第一電極及第二電極於多個第一通孔中;形成多個支撐件於繫連件上,且支撐件不重疊半導體疊層;形成載板於多個支撐件及半導體疊層上;移除中介基板;移除部分的第一犧牲層,以露出半導體疊層;以及形成保護層於半導體疊層上。An embodiment of the present invention provides a method for manufacturing a display device, including: providing a growth substrate; forming a multi-layer semiconductor layer on the growth substrate; forming a first sacrificial layer on the multi-layer semiconductor layer; forming an intermediary substrate on the first sacrificial layer; removing the growth substrate; patterning multiple semiconductor layers to form a semiconductor stack; forming a tie on the semiconductor stack and the intermediary substrate, and the tie has a plurality of first through holes exposing the semiconductor stack; respectively forming a second An electrode and a second electrode are in a plurality of first through holes; forming a plurality of supports on the connecting member, and the supports do not overlap the semiconductor stack; forming a carrier plate on the plurality of supports and the semiconductor stack; moving removing the interposer substrate; removing part of the first sacrificial layer to expose the semiconductor stack; and forming a protection layer on the semiconductor stack.
在本發明的一實施例中,上述的形成多層半導體層於生長基板上包括:形成第一型半導體層於生長基板上;形成發光層於第一型半導體層上;以及形成第二型半導體層於發光層上。In an embodiment of the present invention, the above-mentioned formation of multiple semiconductor layers on the growth substrate includes: forming a first-type semiconductor layer on the growth substrate; forming a light-emitting layer on the first-type semiconductor layer; and forming a second-type semiconductor layer on the luminescent layer.
在本發明的一實施例中,上述的形成第一犧牲層於多層半導體層上包括:將多層半導體層的表面粗糙化;以及形成第一犧牲層於多層半導體層的粗糙化表面上。In an embodiment of the present invention, the above-mentioned forming the first sacrificial layer on the multi-layer semiconductor layer includes: roughening the surface of the multi-layer semiconductor layer; and forming the first sacrificial layer on the roughened surface of the multi-layer semiconductor layer.
在本發明的一實施例中,上述的形成中介基板於第一犧牲層上包括:形成黏合層於第一犧牲層上;以及形成中介基板於黏合層上。In an embodiment of the present invention, the formation of the intermediary substrate on the first sacrificial layer includes: forming an adhesive layer on the first sacrificial layer; and forming the intermediary substrate on the adhesive layer.
在本發明的一實施例中,上述的形成多個支撐件於繫連件上包括:形成第二犧牲層於半導體疊層及繫連件上,且第二犧牲層具有多個第二通孔,多個第二通孔不重疊半導體疊層且露出繫連件;以及形成支撐件於第二通孔中。In an embodiment of the present invention, the above-mentioned forming a plurality of support members on the tie member includes: forming a second sacrificial layer on the semiconductor stack and the tie member, and the second sacrificial layer has a plurality of second through holes , a plurality of second through holes do not overlap the semiconductor stack and expose the tie member; and forming a support member in the second through hole.
在本發明的一實施例中,上述的第二犧牲層包括有機材料。In an embodiment of the present invention, the above-mentioned second sacrificial layer includes organic materials.
在本發明的一實施例中,上述的顯示裝置的製造方法還包括在移除中介基板之後移除黏合層。In an embodiment of the present invention, the above-mentioned manufacturing method of the display device further includes removing the adhesive layer after removing the intermediary substrate.
在本發明的一實施例中,上述的顯示裝置的製造方法還包括在形成保護層之後移除第二犧牲層。In an embodiment of the present invention, the above-mentioned manufacturing method of the display device further includes removing the second sacrificial layer after forming the protection layer.
在本發明的一實施例中,上述的顯示裝置的製造方法還包括:提供電路基板,電路基板包括位於其表面上的第一接墊及第二接墊;將半導體疊層、第一電極、第二電極以及保護層轉置於電路基板上,使得第一電極位於半導體疊層與第一接墊之間,且第二電極位於半導體疊層與第二接墊之間;以及電性連接第一電極與第一接墊以及第二電極與第二接墊。In an embodiment of the present invention, the above-mentioned manufacturing method of the display device further includes: providing a circuit substrate, the circuit substrate includes a first pad and a second pad on the surface thereof; The second electrode and the protection layer are transposed on the circuit substrate, so that the first electrode is located between the semiconductor stack and the first pad, and the second electrode is located between the semiconductor stack and the second pad; and electrically connected to the first pad; An electrode and the first pad, and a second electrode and the second pad.
在本發明的一實施例中,上述的電路基板還包括開關元件,且開關元件電性連接第一接墊或第二接墊。In an embodiment of the present invention, the above-mentioned circuit substrate further includes a switch element, and the switch element is electrically connected to the first pad or the second pad.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.
在附圖中,為了清楚起見,放大了層、膜、面板、區域等的厚度。在整個說明書中,相同的附圖標記表示相同的元件。應當理解,當諸如層、膜、區域或基板的元件被稱為在另一元件「上」或「連接到」另一元件時,其可以直接在另一元件上或與另一元件連接,或者中間元件可以也存在。相反地,當元件被稱為「直接在另一元件上」或「直接連接到」另一元件時,不存在中間元件。如本文所使用的,「連接」可以指物理及/或電性連接。再者,「電性連接」或「耦接」可為二元件間存在其它元件。In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Throughout the specification, the same reference numerals denote the same elements. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that other elements exist between two elements.
應當理解,儘管術語「第一」、「第二」、「第三」等在本文中可以用於描述各種元件、部件、區域、層及/或部分,但是這些元件、部件、區域、層及/或部分不應受這些術語的限制。這些術語僅用於將一個元件、部件、區域、層或部分與另一個元件、部件、區域、層或部分區分開。因此,下面討論的第一「元件」、「部件」、「區域」、「層」或「部分」可以被稱為第二元件、部件、區域、層或部分而不脫離本文的教導。It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first "element," "component," "region," "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.
這裡使用的術語僅僅是為了描述特定實施例的目的,而不是限制性的。如本文所使用的,除非內容清楚地指示,否則單數形式「一」、「一個」和「該」旨在包括複數形式,包括「至少一個」或表示「及/或」。如本文所使用的,術語「及/或」包括一個或多個相關所列項目的任何和所有組合。還應當理解,當在本說明書中使用時,術語「包含」及/或「包括」指定所述特徵、區域、整體、步驟、操作、元件及/或部件的存在,但不排除一個或多個其它特徵、區域、整體、步驟、操作、元件、部件及/或其組合的存在或添加。The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include plural forms including "at least one" or meaning "and/or" unless the content clearly dictates otherwise. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the terms "comprising" and/or "comprising" designate the existence of said features, regions, integers, steps, operations, elements and/or components, but do not exclude one or more Existence or addition of other features, regions, integers, steps, operations, elements, parts and/or combinations thereof.
此外,諸如「下」或「底部」和「上」或「頂部」的相對術語可在本文中用於描述一個元件與另一元件的關係,如圖所示。應當理解,相對術語旨在包括除了圖中所示的方位之外的裝置的不同方位。例如,如果一個附圖中的裝置翻轉,則被描述為在其他元件的「下」側的元件將被定向在其他元件的「上」側。因此,示例性術語「下」可以包括「下」和「上」的取向,取決於附圖的特定取向。類似地,如果一個附圖中的裝置翻轉,則被描述為在其它元件「下」或「下方」的元件將被定向為在其它元件「上方」。因此,示例性術語「下」或「下方」可以包括上方和下方的取向。Additionally, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe one element's relationship to another element as shown in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "below" can encompass both an orientation of "below" and "upper," depending on the particular orientation of the drawing. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of above and below.
考慮到所討論的測量和與測量相關的誤差的特定數量(即,測量系統的限制),本文使用的「約」、「近似」、或「實質上」包括所述值和在本領域普通技術人員確定的特定值的可接受的偏差範圍內的平均值。例如,「約」可以表示在所述值的一個或多個標準偏差內,或±30%、±20%、±10%、±5%內。再者,本文使用的「約」、「近似」、或「實質上」可依光學性質、蝕刻性質或其它性質,來選擇較可接受的偏差範圍或標準偏差,而可不用一個標準偏差適用全部性質。The terms "about," "approximately," or "substantially" as used herein include stated values and those within ordinary skill in the art, taking into account the measurements in question and the specific amount of error associated with the measurements (i.e., limitations of the measurement system). The average value within an acceptable range of deviation from a specified value as determined by a human being. For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "about", "approximately", or "substantially" used herein may select a more acceptable range of deviation or standard deviation based on optical properties, etching properties or other properties, and may not use one standard deviation to apply to all nature.
本文參考作為理想化實施例的示意圖的截面圖來描述示例性實施例。因此,可以預期到作為例如製造技術及/或公差的結果的圖示的形狀變化。因此,本文所述的實施例不應被解釋為限於如本文所示的區域的特定形狀,而是包括例如由製造導致的形狀偏差。例如,示出或描述為平坦的區域通常可以具有粗糙及/或非線性特徵。此外,所示的銳角可以是圓的。因此,圖中所示的區域本質上是示意性的,並且它們的形狀不是旨在示出區域的精確形狀,並且不是旨在限制權利要求的範圍。Exemplary embodiments are described herein with reference to cross section illustrations that are schematic illustrations of idealized embodiments. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances are to be expected. Thus, embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region shown or described as flat, may, typically, have rough and/or non-linear features. Additionally, acute corners shown may be rounded. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.
圖1至圖11是依照本發明一實施例的顯示裝置10的製造方法的步驟流程的局部剖面示意圖。請參照圖1,在本實施例的顯示裝置10的製造方法的步驟流程中,首先,提供生長基板GS,生長基板GS可以是藍寶石(Sapphire)基板、砷化鎵(GaAs)基板、磷化鎵(GaP)基板、磷化銦(InP)基板、碳化矽(SiC)基板、氮化鎵(GaN)基板或其他適用於磊晶製程的基板,但不以此為限。FIG. 1 to FIG. 11 are partial cross-sectional schematic diagrams of the steps of the manufacturing method of the display device 10 according to an embodiment of the present invention. Please refer to FIG. 1 , in the steps of the manufacturing method of the display device 10 in this embodiment, firstly, a growth substrate GS is provided, and the growth substrate GS may be a sapphire (Sapphire) substrate, a gallium arsenide (GaAs) substrate, a gallium phosphide (GaP) substrate, indium phosphide (InP) substrate, silicon carbide (SiC) substrate, gallium nitride (GaN) substrate or other substrates suitable for epitaxial process, but not limited thereto.
接著,在一些實施例中,可以視需要形成離型層(圖未示)於生長基板GS的表面上,離型層可以有助於後續移除生長基板GS,同時還有助於後續進行磊晶製程。離型層的材質例如是氮化鋁(AlN)。Next, in some embodiments, a release layer (not shown) may be formed on the surface of the growth substrate GS as required. The release layer may facilitate the subsequent removal of the growth substrate GS and also facilitate subsequent epitaxy. crystal process. The material of the release layer is, for example, aluminum nitride (AlN).
接著,形成毯覆的多層半導體層於生長基板GS及離型層(若有的話)上。舉例而言,可以先形成第一型半導體層SL1於生長基板GS及離型層(若有的話)上;接著,形成發光層EL於第一型半導體層上SL1;接著,形成第二型半導體層SL2於發光層EL上。第一型半導體層SL1以及第二型半導體層SL2可以包括Ⅱ-Ⅵ族材料(例如:鋅化硒(ZnSe))或Ⅲ-Ⅴ族材料(例如:氮化鎵(GaN)、磷化鎵(GaP)、氮化鋁(AlN)、氮化銦(InN)、氮化銦鎵(InGaN)、磷化銦鎵(InGaP)、氮化鋁鎵(AlGaN)、氮化鋁銦鎵(AlInGaN)或磷化鋁銦鎵(AlInGaP))。舉例而言,在本實施例中,第一型半導體層SL1例如是N型摻雜半導體層,N型摻雜半導體層的材料例如是N型磷化鋁銦鎵(AlInGaP),第二型半導體層SL2例如包括P型摻雜半導體材料,P型摻雜半導體材料例如是P型磷化鎵(GaP),但不以此為限。在本實施例中,發光層EL的結構例如是多層量子井結構(Multiple Quantum Well,MQW),多重量子井結構包括交替堆疊的多層磷化銦鎵(InGaP)以及多層磷化鎵(GaP),藉由設計發光層EL中銦或鎵的比例,可調整發光層EL的發光波長範圍,但本發明不以此為限。Next, a blanket multi-layer semiconductor layer is formed on the growth substrate GS and the release layer (if any). For example, the first-type semiconductor layer SL1 can be formed first on the growth substrate GS and the release layer (if any); then, the light-emitting layer EL is formed on the first-type semiconductor layer SL1; then, the second-type semiconductor layer is formed. The semiconductor layer SL2 is on the light emitting layer EL. The first-type semiconductor layer SL1 and the second-type semiconductor layer SL2 may include II-VI group materials (for example: zinc selenide (ZnSe)) or III-V group materials (for example: gallium nitride (GaN), gallium phosphide ( GaP), Aluminum Nitride (AlN), Indium Nitride (InN), Indium Gallium Nitride (InGaN), Indium Gallium Phosphide (InGaP), Aluminum Gallium Nitride (AlGaN), Aluminum Indium Gallium Nitride (AlInGaN) or aluminum indium gallium phosphide (AlInGaP)). For example, in this embodiment, the first-type semiconductor layer SL1 is, for example, an N-type doped semiconductor layer, and the material of the N-type doped semiconductor layer is, for example, N-type aluminum indium gallium phosphide (AlInGaP), and the second-type semiconductor layer The layer SL2 includes, for example, a P-type doped semiconductor material, and the P-type doped semiconductor material is, for example, P-type gallium phosphide (GaP), but not limited thereto. In this embodiment, the structure of the light-emitting layer EL is, for example, a multiple quantum well structure (Multiple Quantum Well, MQW), and the multiple quantum well structure includes alternately stacked multi-layer indium gallium phosphide (InGaP) and multi-layer gallium phosphide (GaP), By designing the proportion of indium or gallium in the light emitting layer EL, the emission wavelength range of the light emitting layer EL can be adjusted, but the present invention is not limited thereto.
接著,在一些實施例中,可以視需要對第二型半導體層SL2的表面RS進行表面處理,例如,可以將第二型半導體層SL2的表面RS粗糙化,以利於後續膜層的附著。Next, in some embodiments, the surface RS of the second-type semiconductor layer SL2 may be subjected to surface treatment as required, for example, the surface RS of the second-type semiconductor layer SL2 may be roughened to facilitate the adhesion of subsequent film layers.
接著,請參照圖2,形成第一犧牲層SF1於第二型半導體層SL2的表面上,隨後可以視需要形成黏合層BL於第一犧牲層SF1上,再形成中介基板IS於黏合層BL及第一犧牲層SF1上。在本實施例中,可以藉由貼附的方式將中介基板IS設置於黏合層BL上,但不限於此。Next, referring to FIG. 2, a first sacrificial layer SF1 is formed on the surface of the second-type semiconductor layer SL2, and then an adhesive layer BL can be formed on the first sacrificial layer SF1 as required, and then an interposer IS is formed on the adhesive layer BL and on the first sacrificial layer SF1. In this embodiment, the interposer IS can be disposed on the adhesive layer BL by sticking, but it is not limited thereto.
第一犧牲層SF1的材質可以是相對於氧化矽(SiOx)具有蝕刻選擇性的材料。舉例而言,第一犧牲層SF1可以包含金屬、類鑽碳(Diamond-Like Carbon,DLC)或耐化學研磨材料,但不限於此。在一些實施例中,黏合層BL的材質可以是氧化矽(SiOx),但不限於此。The material of the first sacrificial layer SF1 may be a material having etching selectivity relative to silicon oxide (SiOx). For example, the first sacrificial layer SF1 may include metal, diamond-like carbon (Diamond-Like Carbon, DLC) or chemical grinding-resistant material, but not limited thereto. In some embodiments, the material of the adhesive layer BL may be silicon oxide (SiOx), but is not limited thereto.
接著,請參照圖3,移除生長基板GS,而露出第一型半導體層SL1。移除生長基板GS的方式可採用例如熱處理或雷射剝離(Laser Lift Off)製程,但不以此為限。Next, referring to FIG. 3 , the growth substrate GS is removed to expose the first-type semiconductor layer SL1 . The method of removing the growth substrate GS can be, for example, heat treatment or laser lift off (Laser Lift Off) process, but is not limited thereto.
接著,請參照圖4,將第一型半導體層SL1、發光層EL以及第二型半導體層SL2圖案化,以形成第一型半導體圖案SP1、發光圖案EP以及第二型半導體圖案SP2,其中,第一型半導體圖案SP1、發光圖案EP以及第二型半導體圖案SP2可以構成半導體疊層SS。在本實施例中,第一型半導體圖案SP1以及發光圖案EP可以局部重疊第二型半導體圖案SP2,且露出部分的第二型半導體圖案SP2。Next, referring to FIG. 4, the first-type semiconductor layer SL1, the light-emitting layer EL, and the second-type semiconductor layer SL2 are patterned to form the first-type semiconductor pattern SP1, the light-emitting pattern EP, and the second-type semiconductor pattern SP2, wherein, The first type semiconductor pattern SP1, the light emitting pattern EP, and the second type semiconductor pattern SP2 may constitute a semiconductor stack SS. In this embodiment, the first-type semiconductor pattern SP1 and the light-emitting pattern EP may partially overlap the second-type semiconductor pattern SP2 and expose part of the second-type semiconductor pattern SP2.
接著,形成繫連件TR於第一犧牲層SF1的表面Fs、第二型半導體圖案SP2的側壁W2、發光圖案EP的側壁We、第一型半導體圖案SP1的側壁W1以及第一型半導體圖案SP1的表面F1上,且繫連件TR具有分別露出第一型半導體圖案SP1及第二型半導體圖案SP2的第一通孔V11、V12。如此一來,繫連件TR與第二型半導體圖案SP2皆能夠貼合第一犧牲層SF1的表面Fs,使得繫連件TR與第二型半導體圖案SP2面對第一犧牲層SF1的表面能夠齊平。接著,分別形成第一電極E1及第二電極E2於第一通孔V11、V12中。Next, form the tie member TR on the surface Fs of the first sacrificial layer SF1, the sidewall W2 of the second-type semiconductor pattern SP2, the sidewall We of the light emitting pattern EP, the sidewall W1 of the first-type semiconductor pattern SP1, and the first-type semiconductor pattern SP1 On the surface F1 of , and the tie member TR has first through holes V11 and V12 exposing the first type semiconductor pattern SP1 and the second type semiconductor pattern SP2 respectively. In this way, both the tie piece TR and the second-type semiconductor pattern SP2 can adhere to the surface Fs of the first sacrificial layer SF1, so that the surface of the tie piece TR and the second-type semiconductor pattern SP2 facing the first sacrificial layer SF1 can be flush. Next, the first electrode E1 and the second electrode E2 are respectively formed in the first through holes V11 and V12.
在本實施例中,繫連件TR的材質例如氧化矽(SiOx),但不限於此。第一電極E1及第二電極E2的材質可以包括導電性良好的金屬,例如鋁(Al)、鈦(Ti)、金(Au)、鉑(Pt)、鎳(Ni)、鉻(Cr)等金屬、上述金屬之合金、或上述金屬及/或合金之組合或疊層。舉例而言,第一電極E1或第二電極E2可以包括Ti/Au、Ti/Al/Ti/Au或Cr/Al/Ti/Pt/Au等金屬疊層。In this embodiment, the material of the connecting member TR is, for example, silicon oxide (SiOx), but not limited thereto. The materials of the first electrode E1 and the second electrode E2 can include metals with good electrical conductivity, such as aluminum (Al), titanium (Ti), gold (Au), platinum (Pt), nickel (Ni), chromium (Cr), etc. Metals, alloys of the above metals, or combinations or stacks of the above metals and/or alloys. For example, the first electrode E1 or the second electrode E2 may include metal stacks such as Ti/Au, Ti/Al/Ti/Au or Cr/Al/Ti/Pt/Au.
接著,請參照圖5,在一些實施例中,還可以形成第二犧牲層SF2於半導體疊層SS、第一電極E1、第二電極E2以及繫連件TR上,且第二犧牲層SF2可以形成有多個第二通孔V2,各個第二通孔V2於中介基板IS的正投影不重疊半導體疊層SS於中介基板IS的正投影,且第二通孔V2可以露出繫連件TR的貼合第一犧牲層SF1的部分。第二犧牲層SF2可以包括有機材料,但不限於此。在一些實施例中,第二通孔V2可以具有上寬下窄的倒梯形,但不以此為限。Next, please refer to FIG. 5. In some embodiments, a second sacrificial layer SF2 may also be formed on the semiconductor stack SS, the first electrode E1, the second electrode E2, and the tie member TR, and the second sacrificial layer SF2 may be A plurality of second through holes V2 are formed, and the orthographic projection of each second through hole V2 on the intermediary substrate IS does not overlap the orthographic projection of the semiconductor stack SS on the intermediary substrate IS, and the second through holes V2 can expose the connecting member TR. The part where the first sacrificial layer SF1 is attached. The second sacrificial layer SF2 may include an organic material, but is not limited thereto. In some embodiments, the second through hole V2 may have an inverted trapezoid shape with a wide top and a narrow bottom, but not limited thereto.
接著,請參照圖6,可以形成支撐件PC於各第二通孔V2中。由於第二通孔V2可以露出繫連件TR,且第二通孔V2不重疊半導體疊層SS,因此,支撐件PC可以位於繫連件TR上且連接繫連件TR,且支撐件PC不重疊半導體疊層SS。在一些實施例中,還可以形成支撐層PL於支撐件PC以及第二犧牲層SF2上,且支撐層PL可以與支撐件PC屬於同一膜層,換言之,支撐層PL可與支撐件PC一體成形,但不限於此。如此一來,可以確保支撐件PC以及第二犧牲層SF2具有平坦的上表面。在一些實施例中,支撐件PC及/或支撐層PL可以包括具有一定剛性的材料,例如金屬。在某些實施例中,支撐件PC及/或支撐層PL還可以具有多層結構。Next, please refer to FIG. 6 , a supporting member PC may be formed in each of the second through holes V2 . Since the second through hole V2 can expose the tie piece TR, and the second through hole V2 does not overlap the semiconductor stack SS, the support PC can be located on the tie piece TR and connected to the tie piece TR, and the support piece PC does not overlap. Overlapping semiconductor stacks SS. In some embodiments, the support layer PL can also be formed on the support PC and the second sacrificial layer SF2, and the support layer PL can belong to the same film layer as the support PC, in other words, the support layer PL can be integrally formed with the support PC , but not limited to this. In this way, it can be ensured that the supporting member PC and the second sacrificial layer SF2 have flat upper surfaces. In some embodiments, the support PC and/or the support layer PL may include a material with certain rigidity, such as metal. In some embodiments, the support PC and/or the support layer PL may also have a multi-layer structure.
接著,可以形成載板CS於支撐層PL、支撐件PC、第二犧牲層SF2、第一電極E1、第二電極E2以及半導體疊層SS上。舉例而言,可以將載板CS貼合於支撐層PL的表面。接著,請參照圖7,在形成載板CS之後可以移除中介基板IS及黏合層BL,例如藉由雷射剝離、熱處理及/或蝕刻的方式移除中介基板IS及黏合層BL。Next, the carrier CS may be formed on the supporting layer PL, the supporting member PC, the second sacrificial layer SF2 , the first electrode E1 , the second electrode E2 and the semiconductor stack SS. For example, the carrier CS can be attached to the surface of the supporting layer PL. Next, please refer to FIG. 7 , after the carrier CS is formed, the interposer IS and the adhesive layer BL can be removed, for example, by laser lift-off, heat treatment and/or etching to remove the interposer IS and the adhesive layer BL.
接著,請參照圖8,移除部分的第一犧牲層SF1,以露出半導體疊層SS。舉例而言,在本實施例中,可以先藉由薄膜沉積製程及微影製程形成圖案化光阻層PR,再以蝕刻製程移除未被圖案化光阻層PR遮蔽的部分第一犧牲層SF1,從而露出半導體疊層SS的第二型半導體圖案SP2。Next, referring to FIG. 8 , a portion of the first sacrificial layer SF1 is removed to expose the semiconductor stack SS. For example, in this embodiment, the patterned photoresist layer PR can be formed by a thin film deposition process and a lithography process, and then the part of the first sacrificial layer that is not covered by the patterned photoresist layer PR can be removed by an etching process. SF1, thereby exposing the second-type semiconductor pattern SP2 of the semiconductor stack SS.
接著,請參照圖9,形成保護層CP於半導體疊層SS上。舉例而言,在本實施例中,可以再次利用圖案化光阻層PR作為遮罩來沉積保護層CP,使得保護層CP形成於半導體疊層SS的第二型半導體圖案SP2的表面上。在一些實施例中,保護層CP還可以延伸至繫連件TR的表面上。保護層CP的材質例如可以包括氮化矽(SiNx)、氮氧化矽(SiOxNy)、氧化鋁(Al 2O 3)、氧化鈦(TiOx)、二氧化鉿(HfO 2)、二氧化鋯(ZrO 2)、類鑽碳(DLC)或非晶碳(Amorphous Carbon),但不限於此。 Next, referring to FIG. 9 , a protection layer CP is formed on the semiconductor stack SS. For example, in this embodiment, the passivation layer CP can be deposited again using the patterned photoresist layer PR as a mask, so that the passivation layer CP is formed on the surface of the second-type semiconductor pattern SP2 of the semiconductor stack SS. In some embodiments, the protective layer CP may also extend onto the surface of the tether TR. The material of the protective layer CP can include, for example, silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al 2 O 3 ), titanium oxide (TiOx), hafnium dioxide (HfO 2 ), zirconium dioxide (ZrO 2 ), diamond-like carbon (DLC) or amorphous carbon (Amorphous Carbon), but not limited thereto.
至此,即於載板CS上形成了發光元件120,且發光元件120可以包括:第一型半導體圖案SP1;第二型半導體圖案SP2,重疊於第一型半導體圖案SP1,且位於第一型半導體圖案的第一側S1;發光圖案EP,位於第一型半導體圖案SP1與第二型半導體圖案SP2之間,其中,第一型半導體圖案SP1、第二型半導體圖案SP2以及發光圖案EP構成半導體疊層SS;第一電極E1,位於第一型半導體圖案SP1的第二側S2,第二側S2與第一側S1相對,且第一電極E1連接第一型半導體圖案SP1;第二電極E2,位於第二型半導體圖案SP2上與第一型半導體圖案SP1相同的一側,且連接第二型半導體圖案SP2;以及保護層CP,位於第二型半導體圖案SP2上與第一型半導體圖案SP1相對的一側,且保護層CP與第二型半導體圖案SP2的折射率差小於1.8。So far, the light-emitting element 120 is formed on the carrier CS, and the light-emitting element 120 may include: a first-type semiconductor pattern SP1; a second-type semiconductor pattern SP2, overlapping the first-type semiconductor pattern SP1, and located on the first-type semiconductor pattern SP1 The first side S1 of the pattern; the light-emitting pattern EP is located between the first-type semiconductor pattern SP1 and the second-type semiconductor pattern SP2, wherein the first-type semiconductor pattern SP1, the second-type semiconductor pattern SP2 and the light-emitting pattern EP form a semiconductor stack Layer SS; the first electrode E1 is located on the second side S2 of the first-type semiconductor pattern SP1, the second side S2 is opposite to the first side S1, and the first electrode E1 is connected to the first-type semiconductor pattern SP1; the second electrode E2, Located on the same side as the first-type semiconductor pattern SP1 on the second-type semiconductor pattern SP2, and connected to the second-type semiconductor pattern SP2; and a protective layer CP, located on the second-type semiconductor pattern SP2 opposite to the first-type semiconductor pattern SP1 One side, and the refractive index difference between the protection layer CP and the second-type semiconductor pattern SP2 is less than 1.8.
在一些實施例中,第一型半導體圖案SP1的厚度t1可以介於0.1 μm至1 μm之間,且第二型半導體圖案SP2的厚度t2可以介於1 μm至3 μm之間。藉由調整第一型半導體圖案SP1的厚度t1以及第二型半導體圖案SP2的厚度t2在上述範圍中,能夠使發光元件120射出的光波產生建設性干涉,從而提高發光元件120的光取出效率(LEE)。另外,藉由使保護層CP與第二型半導體圖案SP2的折射率差小於1.8,也能夠減少發光元件120射出的光線發生全反射的比例,進而提高發光元件120的光取出效率(LEE)。In some embodiments, the thickness t1 of the first-type semiconductor pattern SP1 may be between 0.1 μm and 1 μm, and the thickness t2 of the second-type semiconductor pattern SP2 may be between 1 μm and 3 μm. By adjusting the thickness t1 of the first-type semiconductor pattern SP1 and the thickness t2 of the second-type semiconductor pattern SP2 within the above-mentioned range, the light waves emitted by the light-emitting element 120 can be constructively interfered, thereby improving the light extraction efficiency of the light-emitting element 120 ( LEE). In addition, by making the refractive index difference between the protective layer CP and the second-type semiconductor pattern SP2 smaller than 1.8, the ratio of total reflection of light emitted from the light emitting element 120 can also be reduced, thereby improving the light extraction efficiency (LEE) of the light emitting element 120 .
在本實施例中,發光元件120的第一電極E1及第二電極E2位於半導體疊層SS的同一側,且發光元件120可以是覆晶式(Flip chip)發光二極體。在一些實施例中,發光元件120的半導體疊層SS的第二型半導體圖案SP2可以位於發光面,且第二型半導體圖案SP2可以包括P型半導體材料。在一些實施例中,發光元件120可以是發紅光且效率較高的發光二極體。In this embodiment, the first electrode E1 and the second electrode E2 of the light emitting element 120 are located on the same side of the semiconductor stack SS, and the light emitting element 120 may be a flip chip light emitting diode. In some embodiments, the second-type semiconductor pattern SP2 of the semiconductor stack SS of the light emitting element 120 may be located on the light-emitting surface, and the second-type semiconductor pattern SP2 may include a P-type semiconductor material. In some embodiments, the light emitting element 120 may be a light emitting diode that emits red light and has high efficiency.
接著,請參照圖10,在形成保護層CP之後還可以移除圖案化光阻層PR,以露出第一犧牲層SF1。接著,還可以移除第一犧牲層SF1,以露出繫連件TR。接著,在形成保護層CP以及移除圖案化光阻層PR及第一犧牲層SF1之後,還可以移除第二犧牲層SF2。舉例而言,可以藉由曝光及顯影的方式移除第二犧牲層SF2。至此,即完成依照本發明一實施例的發光組件10A,且發光組件10A可以包括:載板CS;多個支撐件PC,位於載板CS上;發光元件120,藉由繫連件TR懸吊於支撐件PC之間;以及支撐層PL,位於多個支撐件PC及發光元件120與載板CS之間。藉由使發光組件10A的發光元件120的保護層CP與第二型半導體圖案SP2的折射率差小於1.8,能夠降低發光元件120射出的光線發生全反射的比例,從而提高發光組件10A的光取出效率。Next, please refer to FIG. 10 , after the protective layer CP is formed, the patterned photoresist layer PR can be removed to expose the first sacrificial layer SF1 . Next, the first sacrificial layer SF1 may also be removed to expose the tie TR. Next, after forming the protective layer CP and removing the patterned photoresist layer PR and the first sacrificial layer SF1 , the second sacrificial layer SF2 may also be removed. For example, the second sacrificial layer SF2 can be removed through exposure and development. So far, the light-emitting assembly 10A according to an embodiment of the present invention is completed, and the light-emitting assembly 10A may include: a carrier board CS; a plurality of supports PC located on the carrier board CS; a light-emitting element 120 suspended by a tie member TR between the supports PC; and the support layer PL, located between the plurality of supports PC and the light emitting elements 120 and the carrier CS. By making the refractive index difference between the protective layer CP of the light-emitting element 120 of the light-emitting element 120 and the second-type semiconductor pattern SP2 less than 1.8, the ratio of total reflection of the light emitted by the light-emitting element 120 can be reduced, thereby improving the light extraction of the light-emitting element 10A. efficiency.
請同時參照圖4及圖10,在一些實施例中,繫連件TR延伸於第一型半導體圖案SP1的側壁W1、發光圖案EP的側壁We、第二型半導體圖案SP2的側壁W2以及支撐件PC上,且繫連件TR連接支撐件PC,使得發光元件120能夠懸吊於支撐件PC之間。另外,繫連件TR還可以延伸於第一型半導體圖案SP1及第二型半導體圖案SP2上與保護層CP相對的一側,且第一電極E1及第二電極E2分別通過繫連件TR中的第一通孔V11、V12連接第一型半導體圖案SP1及第二型半導體圖案SP2。Please refer to FIG. 4 and FIG. 10 at the same time. In some embodiments, the tether TR extends from the sidewall W1 of the first-type semiconductor pattern SP1, the sidewall We of the light-emitting pattern EP, the sidewall W2 of the second-type semiconductor pattern SP2, and the support member. PC, and the tether TR is connected to the support PC, so that the light emitting element 120 can be suspended between the support PC. In addition, the tie TR can also extend on the side opposite to the protective layer CP on the first-type semiconductor pattern SP1 and the second-type semiconductor pattern SP2, and the first electrode E1 and the second electrode E2 respectively pass through the tie TR. The first vias V11 and V12 are connected to the first-type semiconductor pattern SP1 and the second-type semiconductor pattern SP2.
在一些實施例中,繫連件TR的材料與保護層CP的材料可以不同,且保護層CP的折射率可以大於繫連件TR的折射率。在一些實施例中,繫連件TR可以包括氧化矽,以利於進行巨量轉移製程。在一些實施例中,保護層CP的折射率可以大於氧化矽的折射率,例如,保護層CP的折射率可以大於約1.46。在一些實施例中,保護層CP可以包括折射率約為1.6的氮氧化矽(SiON)。在一些實施例中,保護層CP可以包括折射率介於約1.85至2.1之間的HfO 2。在一些實施例中,保護層CP可以包括折射率介於約1.9至2.15之間的ZrO 2。在一些實施例中,保護層CP可以包括折射率約為2.4的類鑽碳。在一些實施例中,保護層CP可以包括折射率介於約1.5至3.1之間的非晶碳。 In some embodiments, the material of the tether TR and the material of the protective layer CP may be different, and the refractive index of the protective layer CP may be greater than that of the tether TR. In some embodiments, the tie member TR may include silicon oxide to facilitate mass transfer process. In some embodiments, the refractive index of the protective layer CP may be greater than that of silicon oxide, for example, the refractive index of the protective layer CP may be greater than about 1.46. In some embodiments, the protection layer CP may include silicon oxynitride (SiON) with a refractive index of about 1.6. In some embodiments, the protective layer CP may include HfO 2 with a refractive index between about 1.85 and 2.1. In some embodiments, the protective layer CP may include ZrO 2 with a refractive index between about 1.9 and 2.15. In some embodiments, the protective layer CP may include diamond-like carbon with a refractive index of about 2.4. In some embodiments, the protective layer CP may include amorphous carbon with a refractive index between about 1.5 and 3.1.
接著,請參照圖11,在移除第二犧牲層SF2之後還可以進一步提供電路基板110,其中,電路基板110可以包括位於其表面上的接墊PD1、PD2。之後,可以進行巨量轉移製程,也就是將圖10的發光組件10A中的發光元件120取出後轉置於電路基板110上,例如將發光元件120的第一電極E1置於接墊PD1上,且將發光元件120的第二電極E2置於接墊PD2上,使得第一電極E1位於半導體疊層SS與電路基板110的接墊PD1之間,且第二電極E2位於半導體疊層SS與電路基板110的接墊PD2之間。之後,還可以藉由例如熱處理而使發光元件120的第一電極E1及第二電極E2分別與接墊PD1、PD2電性連接。至此,即可完成依照本發明一實施例的顯示裝置10,且顯示裝置10可以包括:電路基板110;以及發光元件120,位於電路基板110上,且電性連接電路基板110。由於顯示裝置10的發光元件120的保護層CP與第二型半導體圖案SP2的折射率差小於1.8,發光元件120射出的光線較不易發生全反射,因此能夠提高顯示裝置10的光取出效率。Next, please refer to FIG. 11 , after removing the second sacrificial layer SF2 , a circuit substrate 110 may be further provided, wherein the circuit substrate 110 may include pads PD1 and PD2 on its surface. Afterwards, a mass transfer process can be performed, that is, the light-emitting element 120 in the light-emitting assembly 10A of FIG. And the second electrode E2 of the light emitting element 120 is placed on the pad PD2, so that the first electrode E1 is located between the semiconductor stack SS and the pad PD1 of the circuit substrate 110, and the second electrode E2 is located between the semiconductor stack SS and the circuit board. Between the pads PD2 of the substrate 110 . Afterwards, the first electrode E1 and the second electrode E2 of the light-emitting element 120 can be electrically connected to the pads PD1 and PD2 respectively by heat treatment, for example. So far, the display device 10 according to an embodiment of the present invention can be completed, and the display device 10 may include: a circuit substrate 110 ; and a light emitting element 120 located on the circuit substrate 110 and electrically connected to the circuit substrate 110 . Since the refractive index difference between the protection layer CP of the light-emitting element 120 and the second-type semiconductor pattern SP2 is less than 1.8, the light emitted from the light-emitting element 120 is less likely to be totally reflected, thereby improving the light extraction efficiency of the display device 10 .
舉例而言,電路基板110可以包括底板112以及驅動電路層114。電路基板110的底板112可以是透明基板、不透明基板、撓性基板或不可撓基板,其材質可以是石英基板、玻璃基板、高分子基板或其他適當材質。驅動電路層114可以包括顯示裝置10需要的元件或線路,例如驅動元件、開關元件、儲存電容、電源線、驅動訊號線、時序訊號線、電流補償線、檢測訊號線等等。可以利用薄膜沉積製程、微影製程以及蝕刻製程,在底板112上形成驅動電路層114。驅動電路層114可以包括至少一絕緣層及至少一導電層,且驅動電路層114可以視需要包括更多的絕緣層以及導電層。For example, the circuit substrate 110 may include a bottom plate 112 and a driving circuit layer 114 . The bottom plate 112 of the circuit substrate 110 can be a transparent substrate, an opaque substrate, a flexible substrate or an inflexible substrate, and its material can be a quartz substrate, a glass substrate, a polymer substrate or other suitable materials. The driving circuit layer 114 may include elements or circuits required by the display device 10 , such as driving elements, switching elements, storage capacitors, power lines, driving signal lines, timing signal lines, current compensation lines, detection signal lines, and so on. The driving circuit layer 114 can be formed on the base plate 112 by thin film deposition process, lithography process and etching process. The driving circuit layer 114 may include at least one insulating layer and at least one conductive layer, and the driving circuit layer 114 may include more insulating layers and conductive layers as required.
在一些實施例中,電路基板110的驅動電路層114還可以包括開關元件陣列,其中開關元件陣列包括排列成陣列的多個開關元件T,且開關元件T可以電性連接發光元件120。詳細而言,驅動電路層114例如可以包括開關元件T、電源線VL1、VL2、接墊PD1、PD2、緩衝層I1、閘極絕緣層I2、層間絕緣層I3以及絕緣層I4。開關元件T是由半導體層TC、閘極TG、源極TS以及汲極TD所構成。半導體層TC重疊閘極TG的區域可視為開關元件T的通道區。緩衝層I1位於底板112與半導體層TC之間,用於防止底板112中的雜質移入半導體層TC中,並增強半導體層TC與底板112之間的黏合性。閘極絕緣層I2位於閘極TG與半導體層TC之間。層間絕緣層I3設置在源極TS、汲極TD以及電源線VL1與閘極TG以及電源線VL2之間。絕緣層I4設置於源極TS、汲極TD以及電源線VL1與接墊PD1、PD2之間。接墊PD1、PD2可以分別通過絕緣層I4中的通孔VA1、VA2電性連接電源線VL1以及汲極TD,且源極TS可以通過絕緣層I3中的通孔VA3電性連接電源線VL2。當閘極TG接收來自例如驅動元件的訊號而開啟開關元件T時,源極TS接收自電源線VL2的訊號可被傳送至發光元件120的第二電極E2。在某些實施例中,接墊PD1可以電性連接開關元件T,且接墊PD2可以電性電源線VL1。In some embodiments, the driving circuit layer 114 of the circuit substrate 110 may further include a switch element array, wherein the switch element array includes a plurality of switch elements T arranged in an array, and the switch elements T may be electrically connected to the light emitting element 120 . In detail, the driving circuit layer 114 may include switching elements T, power lines VL1 , VL2 , pads PD1 , PD2 , buffer layer I1 , gate insulating layer I2 , interlayer insulating layer I3 and insulating layer I4 . The switching element T is composed of a semiconductor layer TC, a gate TG, a source TS and a drain TD. The region where the semiconductor layer TC overlaps the gate TG can be regarded as the channel region of the switching element T. The buffer layer I1 is located between the base plate 112 and the semiconductor layer TC for preventing impurities in the base plate 112 from moving into the semiconductor layer TC and enhancing the adhesion between the semiconductor layer TC and the base plate 112 . The gate insulating layer I2 is located between the gate TG and the semiconductor layer TC. The interlayer insulating layer I3 is disposed between the source TS, the drain TD and the power line VL1 , and the gate TG and the power line VL2 . The insulating layer I4 is disposed between the source TS, the drain TD, the power line VL1 and the pads PD1, PD2. The pads PD1 and PD2 can be electrically connected to the power line VL1 and the drain TD through the through holes VA1 and VA2 in the insulating layer I4 respectively, and the source TS can be electrically connected to the power line VL2 through the through hole VA3 in the insulating layer I3 . When the gate TG receives a signal from, for example, a driving element to turn on the switching element T, the source TS receives a signal from the power line VL2 to be transmitted to the second electrode E2 of the light emitting element 120 . In some embodiments, the pad PD1 can be electrically connected to the switch element T, and the pad PD2 can be electrically connected to the power line VL1.
半導體層TC的材質可以包括矽質半導體材料(例如多晶矽、非晶矽等)、氧化物半導體材料、有機半導體材料,但不限於此。閘極TG、源極TS、汲極TD、電源線VL1、VL2以及接墊PD1、PD2的材質可以包括導電性良好的金屬,例如鋁、鉬、鈦、銅等金屬、上述金屬之合金,或上述金屬及合金之疊層,但不限於此。舉例而言,接墊PD1可以包括依續堆疊的鈦層、鋁層以及鈦層或是依續堆疊的鉬層、鋁層以及鉬層,但不以此為限。The material of the semiconductor layer TC may include silicon semiconductor materials (such as polysilicon, amorphous silicon, etc.), oxide semiconductor materials, organic semiconductor materials, but not limited thereto. The material of the gate TG, the source TS, the drain TD, the power lines VL1, VL2 and the pads PD1, PD2 may include metals with good electrical conductivity, such as aluminum, molybdenum, titanium, copper and other metals, alloys of the above metals, or Lamination of the above metals and alloys, but not limited thereto. For example, the pad PD1 may include a sequentially stacked titanium layer, an aluminum layer, and a titanium layer or a sequentially stacked molybdenum layer, an aluminum layer, and a molybdenum layer, but not limited thereto.
緩衝層I1、閘極絕緣層I2、層間絕緣層I3以及絕緣層I4的材質可以包括透明的無機絕緣材料,例如氧化矽、氮化矽、氮氧化矽或上述材料的疊層,但不限於此。在一些實施例中,緩衝層I1、閘極絕緣層I2、層間絕緣層I3以及絕緣層I4也可以分別具有單層結構或多層結構,多層結構例如上述絕緣材料中任意兩層或更多層的疊層,可視需要進行組合與變化。The material of the buffer layer I1, the gate insulating layer I2, the interlayer insulating layer I3, and the insulating layer I4 may include transparent inorganic insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, or a stack of the above materials, but is not limited thereto. . In some embodiments, the buffer layer I1, the gate insulating layer I2, the interlayer insulating layer I3, and the insulating layer I4 can also have a single-layer structure or a multi-layer structure, such as any two or more layers of any of the above-mentioned insulating materials. Layers can be combined and changed as needed.
在一些實施例中,第一電極E1及第二電極E2還可以分別透過連接材電性連接至接墊PD1、PD2,連接材的材質例如為導電膠(例如銀膠)、焊料、金屬或其他材料。在一些實施例中,上述連接材與接墊PD1、PD2、第一電極E1或第二電極E2之間還可以包括其他導電材料或導電膠。In some embodiments, the first electrode E1 and the second electrode E2 can also be electrically connected to the pads PD1 and PD2 through connecting materials, such as conductive glue (such as silver glue), solder, metal or other materials. Material. In some embodiments, other conductive materials or conductive glue may be included between the above-mentioned connecting material and the pads PD1 , PD2 , the first electrode E1 or the second electrode E2 .
綜上所述,本發明的發光元件、發光組件以及顯示裝置藉由使保護層與第二型半導體圖案的折射率差小於約1.8,能夠降低發光元件射出的光線發生全反射的比例,從而提高發光元件、發光組件以及顯示裝置的光取出效率。In summary, the light-emitting element, light-emitting component, and display device of the present invention can reduce the ratio of total reflection of light emitted by the light-emitting element by making the refractive index difference between the protective layer and the second-type semiconductor pattern less than about 1.8, thereby improving Light extraction efficiency of light-emitting elements, light-emitting components and display devices.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.
10:顯示裝置 10A:發光組件 110:電路基板 112:底板 114:驅動電路層 120:發光元件 BL:黏合層 CP:保護層 CS:載板 E1:第一電極 E2:第二電極 EL:發光層 EP:發光圖案 F1、Fs:表面 GS:生長基板 I1:緩衝層 I2:閘極絕緣層 I3:層間絕緣層 I4:絕緣層 IS:中介基板 PC:支撐件 PD1、PD2:接墊 PL:支撐層 PR:圖案化光阻層 RS:表面 S1:第一側 S2:第二側 SF1:第一犧牲層 SF2:第二犧牲層 SL1:第一型半導體層 SL2:第二型半導體層 SP1:第一型半導體圖案 SP2:第二型半導體圖案 SS:半導體疊層 T:開關元件 TC:半導體層 TD:汲極 TG:閘極 TR:繫連件 TS:源極 t1、t2:厚度 V11、V12:第一通孔 V2:第二通孔 VA1、VA2、VA3:通孔 VL1、VL2:電源線 W1、W2、We:側壁 10: Display device 10A: Lighting components 110: circuit substrate 112: Bottom plate 114: Drive circuit layer 120: Light emitting element BL: Bonding layer CP: protective layer CS: carrier board E1: first electrode E2: second electrode EL: light emitting layer EP: Luminous pattern F1, Fs: surface GS: growth substrate I1: buffer layer I2: Gate insulating layer I3: interlayer insulating layer I4: insulating layer IS:Intermediate Substrate PC: support PD1, PD2: Pads PL: supporting layer PR: patterned photoresist layer RS: surface S1: first side S2: second side SF1: the first sacrificial layer SF2: the second sacrificial layer SL1: first type semiconductor layer SL2: Second type semiconductor layer SP1: Type 1 semiconductor pattern SP2: Second type semiconductor pattern SS: Semiconductor stack T: switching element TC: semiconductor layer TD: drain TG: gate TR: Ties TS: source t1, t2: Thickness V11, V12: the first through hole V2: the second through hole VA1, VA2, VA3: through holes VL1, VL2: power cord W1, W2, We: side wall
圖1至圖11是依照本發明一實施例的顯示裝置10的製造方法的步驟流程的局部剖面示意圖。FIG. 1 to FIG. 11 are partial cross-sectional schematic diagrams of the steps of the manufacturing method of the display device 10 according to an embodiment of the present invention.
10:顯示裝置 10: Display device
110:電路基板 110: circuit substrate
112:底板 112: Bottom plate
114:驅動電路層 114: Drive circuit layer
120:發光元件 120: Light emitting element
CP:保護層 CP: protective layer
E1:第一電極 E1: first electrode
E2:第二電極 E2: second electrode
EP:發光圖案 EP: Luminous pattern
I1:緩衝層 I1: buffer layer
I2:閘極絕緣層 I2: Gate insulating layer
I3:層間絕緣層 I3: interlayer insulating layer
I4:絕緣層 I4: insulating layer
PD1、PD2:接墊 PD1, PD2: Pads
SP1:第一型半導體圖案 SP1: Type 1 semiconductor pattern
SP2:第二型半導體圖案 SP2: Second type semiconductor pattern
SS:半導體疊層 SS: Semiconductor stack
T:開關元件 T: switching element
TC:半導體層 TC: semiconductor layer
TD:汲極 TD: drain
TG:閘極 TG: gate
TR:繫連件 TR: Ties
TS:源極 TS: source
VA1、VA2、VA3:通孔 VA1, VA2, VA3: through holes
VL1、VL2:電源線 VL1, VL2: power cord
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