CN114975722A

CN114975722A - Light emitting element, light emitting module including the same, display device including the same, and method of manufacturing the same

Info

Publication number: CN114975722A
Application number: CN202210518500.9A
Authority: CN
Inventors: 黄建富; 李锡烈
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2021-12-29
Filing date: 2022-05-12
Publication date: 2022-08-30
Also published as: TW202327071A; TWI802192B

Abstract

A light emitting element, a light emitting module including the same, a display device and a method of manufacturing the same, the light emitting element comprising: a semiconductor stack, a metal electrode, a transparent electrode, and a interconnect. The metal electrode is located on the semiconductor lamination. The transparent electrode is located on the side of the semiconductor stack opposite to the metal electrode. The tie extends at least from the side wall of the semiconductor lamination and the transparent electrode, and the surface of the tie away from the metal electrode is flush with the surface of the transparent electrode away from the metal electrode.

Description

Light emitting element, light emitting module including the same, display device including the same, and method of manufacturing the same

Technical Field

The present invention relates to a light-emitting element, a light-emitting module and a display device including the same, and a method for manufacturing the display device.

Background

micro-LEDs (micro-LEDs) are suitable for constructing pixel structures of micro-LED display devices due to their low power consumption, high brightness, high resolution, and high color saturation. Because of the extremely small size of the micro light emitting diode, the current method for manufacturing the micro light emitting diode display device adopts a Mass Transfer (Mass Transfer) technology, that is, a micro electro mechanical array technology is used for picking and placing the micro light emitting diode crystal grains, so that a large number of micro light emitting diode crystal grains are transported to the driving back plate with the pixel circuit at one time.

In addition, the micro led die can be classified into horizontal, vertical and flip-chip micro leds according to the packaging method. As the size of the micro led die is smaller, it is expected that the vertical micro led will provide a larger light emitting area. However, the top electrode of the vertical micro led employs a metal electrode, which causes current to be locally concentrated on the metal electrode, and the metal electrode also shields light to affect light extraction (light extraction).

Disclosure of Invention

The invention provides a light-emitting element having good light extraction efficiency.

The invention provides a light emitting module with good light extraction efficiency.

The invention provides a display device with good light extraction efficiency.

The invention provides a method for manufacturing a display device, which can provide a display device with good light extraction efficiency.

One embodiment of the present invention provides a light emitting element including: a semiconductor stack; a metal electrode on the semiconductor stack; a transparent electrode on a side of the semiconductor stack opposite the metal electrode; and the tie piece at least extends to the side wall of the semiconductor lamination and the transparent electrode, and the surface of the tie piece far away from the metal electrode is flush with the surface of the transparent electrode far away from the metal electrode.

In an embodiment of the invention, the interconnection includes a silicon oxide, a silicon nitride, or a bragg reflector.

In an embodiment of the invention, the bragg reflector layer includes a plurality of titanium oxide layers and a plurality of silicon oxide layers overlapped with each other.

In an embodiment of the invention, the semiconductor stack includes: a first type semiconductor pattern between the metal electrode and the transparent electrode; the second type semiconductor pattern is overlapped with the first type semiconductor pattern and is positioned between the first type semiconductor pattern and the transparent electrode; and a light emitting pattern between the first type semiconductor pattern and the second type semiconductor pattern.

In an embodiment of the invention, the second type semiconductor pattern includes a P-type semiconductor material.

In an embodiment of the invention, the light emitting device further includes a matching pattern between the semiconductor stack and the transparent electrode.

One embodiment of the present invention provides a light emitting assembly, including: a carrier plate; the support pieces are positioned on the carrier plate; and the light-emitting element is suspended between the supporting pieces through the connecting piece.

In an embodiment of the invention, an orthogonal projection of the connecting member on the carrier is outside an orthogonal projection of the metal electrode on the carrier.

In an embodiment of the invention, the connecting member further extends to a plurality of supporting members.

In an embodiment of the invention, the light emitting assembly further includes a supporting layer located between the plurality of supporting members and the carrier and between the light emitting elements and the carrier.

In an embodiment of the invention, the supporting layer and the supporting member are integrally formed.

One embodiment of the present invention provides a display device including: a circuit substrate; and the light-emitting element is positioned on the circuit substrate and is electrically connected with the circuit substrate.

In an embodiment of the invention, the metal electrode is located between the semiconductor stack and the circuit substrate.

In an embodiment of the invention, the circuit substrate further includes a switch element, and the switch element is electrically connected to the transparent electrode or the metal electrode.

One embodiment of the present invention provides a method of manufacturing a display device, including: providing a growth substrate; forming a plurality of semiconductor layers on a growth substrate; forming a transparent electrode layer on the multilayer semiconductor layer; forming an intermediate substrate on the transparent electrode layer; removing the growth substrate; patterning the plurality of semiconductor layers and the transparent electrode layer to form a semiconductor stack and a transparent electrode; forming a metal electrode on the semiconductor lamination; and forming a tie on the semiconductor stack and the sidewalls of the transparent electrode and the interposer, wherein a surface of the tie facing the interposer is flush with a surface of the transparent electrode facing the interposer.

In an embodiment of the invention, the forming the multi-layer semiconductor layer includes: forming a first type semiconductor layer on a growth substrate; forming a light emitting layer on the first type semiconductor layer; and forming a second type semiconductor layer on the light emitting layer.

In an embodiment of the invention, the forming the transparent electrode layer includes: forming a matching layer on the multi-layer semiconductor layer; and forming a transparent electrode layer on the matching layer.

In an embodiment of the invention, the method of manufacturing the display device further includes forming a plurality of supporting members on the connecting member, wherein the supporting members do not overlap the semiconductor stack.

In an embodiment of the invention, the forming the plurality of supporting members on the connecting member includes: forming a sacrificial layer on the metal electrode and the tie, wherein the sacrificial layer has a plurality of through holes which do not overlap the semiconductor stack and expose the tie; and forming a support member in each through hole.

In an embodiment of the invention, the sacrificial layer includes an organic material.

In an embodiment of the invention, the method of manufacturing the display device further includes forming a carrier on the plurality of supporting members and the metal electrodes.

In an embodiment of the invention, after the forming the carrier substrate, the removing the interposer substrate is further included.

In an embodiment of the invention, the removing the interposer substrate further includes removing the sacrificial layer.

In an embodiment of the invention, after removing the sacrificial layer, the method further includes: providing a circuit substrate, wherein the circuit substrate comprises a connecting pad on the surface of the circuit substrate; transposing the transparent electrode, the semiconductor stack, the metal electrode and the tie member onto a pad of the circuit substrate such that the metal electrode is located between the semiconductor stack and the pad; and electrically connecting the metal electrode and the pad.

In an embodiment of the invention, the method of manufacturing a display device further includes a switch element electrically connecting the transparent electrode and the circuit substrate.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1A to 1J are partial cross-sectional views illustrating a process flow of a method for manufacturing a display device 10 according to an embodiment of the invention.

Fig. 2 is a schematic cross-sectional view of a light emitting device 20A according to an embodiment of the invention.

Fig. 3 is a partial cross-sectional view of a display device 20 according to an embodiment of the invention.

Description of reference numerals:

10. 20: display device

10A, 20A: light emitting assembly

110: circuit board

112: base plate

114: drive circuit layer

120. 120A: light emitting element

CR1, CR2, CR 3: conductive structure

CS: support plate

EL: luminescent layer

EP: light-emitting pattern

Fi. Fr, Fra, Ft: surface of

GS: growth substrate

I1: buffer layer

I2: gate insulating layer

I3: interlayer insulating layer

I4, I5, I6: insulating layer

IS: interposer substrate

ME: metal electrode

ML: matching layer

MP: matching patterns

PC: support piece

PD: connecting pad

PL: supporting layer

SF: sacrificial layer

SL 1: first type semiconductor layer

SL 2: second type semiconductor layer

SP 1: first type semiconductor pattern

SP 2: second type semiconductor pattern

And SS: semiconductor stack

T: switching element

TC: semiconductor layer

TD: drain electrode

TE: transparent electrode

TG: grid electrode

TL: transparent electrode layer

TR, TRa: tie-connecting piece

TS: source electrode

V1, V2, V3, V4, VA: through hole

VL1, VL 2: power line

We, Wm, Ws, Wt: side wall

Detailed Description

In the drawings, the thickness of layers, films, panels, regions, etc. have been exaggerated for clarity. Like reference numerals refer to like elements throughout the specification. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connections. Further, "electrically connected" or "coupled" may mean that there are additional elements between the elements.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first "element," "component," "region," "layer" or "portion" discussed below could be termed a second element, component, region, layer or portion without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, including "at least one" or mean "and/or" unless the content clearly indicates otherwise. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another element, as illustrated. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" can include both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "under" or "beneath" can encompass both an orientation of above and below.

As used herein, "about", "approximately", or "substantially" includes mean values between the recited value and the specified value within an acceptable range of deviation as determined by one of ordinary skill in the art, taking into account the measurement in question and the particular amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "approximately" may mean within one or more standard deviations of the stated value, or within ± 30%, ± 20%, ± 10%, ± 5%. Further, as used herein, "about", "approximately", or "substantially" may be selected based on optical properties, etch properties, or other properties, with a more acceptable range of deviation or standard deviation, and not all properties may be applied with one standard deviation.

Exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region shown or described as flat may generally have rough and/or nonlinear features. Further, the acute angles shown may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

Fig. 1A to 1J are partial cross-sectional views illustrating a process flow of a method for manufacturing a display device 10 according to an embodiment of the invention. Referring to fig. 1A, in the step flow of the method for manufacturing the display device 10 of the present embodiment, first, a growth substrate GS is provided, and the growth substrate GS may be a Sapphire (Sapphire) substrate, a gallium arsenide (GaAs) substrate, a gallium phosphide (GaP) substrate, an indium phosphide (InP) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or other substrate suitable for an epitaxial process, but not limited thereto.

Next, in some embodiments, a release layer (not shown) may be formed on the surface of the growth substrate GS as required, and the release layer may facilitate the subsequent removal of the growth substrate GS and also facilitate the subsequent epitaxial process. The release layer is made of, for example, aluminum nitride (AlN) or gallium nitride (GaN).

Next, a blanket multi-layer semiconductor layer is formed on the growth substrate GS and the release layer (if any). For example, the first type semiconductor layer SL1 may be formed on the growth substrate GS and the release layer (if any); next, a light-emitting layer EL is formed over the first-type semiconductor layer SL 1; next, a second type semiconductor layer SL2 is formed on the light emitting layer EL. The first type semiconductor layer SL1 and the second type semiconductor layer SL2 may include ii-vi materials such as zinc selenide (ZnSe) or iii-v nitride materials such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), or aluminum indium gallium nitride (AlInGaN). For example, in the present embodiment, the first type semiconductor layer SL1 is, for example, an N-type doped semiconductor layer, the material of the N-type doped semiconductor layer is, for example, N-type gallium nitride (N-GaN), the second type semiconductor layer SL2 includes, for example, a P-type doped semiconductor material, the P-type doped semiconductor material is, for example, P-type gallium nitride (GaN), but not limited thereto. In the present embodiment, the structure of the light emitting layer EL is, for example, a multi-Quantum Well (MQW) structure, the multi-Quantum Well structure includes a plurality of layers of indium gallium nitride (InGaN) and a plurality of layers of gallium nitride (GaN) which are alternately stacked, and the light emitting wavelength range of the light emitting layer EL can be adjusted by designing the ratio of indium or gallium in the light emitting layer EL, but the invention is not limited thereto.

Next, referring to fig. 1B, a transparent electrode layer TL IS formed on the first-type semiconductor layer SL1, the light-emitting layer EL and the second-type semiconductor layer SL2, and then an intermediate substrate IS formed on the transparent electrode layer TL. In the present embodiment, the material of the transparent electrode layer TL may include Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Indium Gallium Zinc Oxide (IGZO), or other suitable conductive oxides, or a stack of any two or more layers of the above conductive oxides, but is not limited thereto. In the present embodiment, the intermediate substrate IS may be disposed on the transparent electrode layer TL by means of an adhesion method, but IS not limited thereto.

In some embodiments, before forming the transparent electrode layer TL, a transparent matching layer ML may be formed on the first-type semiconductor layer SL1, the light-emitting layer EL and the second-type semiconductor layer SL2, and then the transparent electrode layer TL is formed on the matching layer ML. The matching layer ML facilitates ohmic contact between the second type semiconductor layer SL2 and the transparent electrode layer TL, and the material of the matching layer ML is, for example, P-type gallium nitride (P-GaN), but is not limited thereto.

Next, referring to fig. 1C, the growth substrate GS is removed to expose the first type semiconductor layer SL 1. The growth substrate GS may be removed by, for example, a thermal treatment or a Laser Lift Off (Laser Lift Off) process, but not limited thereto.

Next, referring to fig. 1D, the first-type semiconductor layer SL1, the light emitting layer EL, the second-type semiconductor layer SL2, the matching layer ML and the transparent electrode layer TL are patterned to form a first-type semiconductor pattern SP1, a light emitting pattern EP, a second-type semiconductor pattern SP2, a matching pattern MP and a transparent electrode TE, wherein the first-type semiconductor pattern SP1, the light emitting pattern EP and the second-type semiconductor pattern SP2 may form a semiconductor stack SS.

Next, a metal electrode ME is formed on the semiconductor stack SS. In some embodiments, a metal electrode layer (not shown) may be formed on the first type semiconductor layer SL1, and then the metal electrode layer, the first type semiconductor layer SL1, the light emitting layer EL, the second type semiconductor layer SL2, the matching layer ML, and the transparent electrode layer TL are patterned to form a transparent electrode TE, a matching pattern MP, a semiconductor stack SS, and a metal electrode ME stacked on the intermediate substrate IS. The material of the metal electrode ME may include a metal having good conductivity, for example, a metal such as aluminum (Al), titanium (Ti), gold (Au), platinum (Pt), nickel (Ni), or chromium (Cr), an alloy of the above metals, or a combination or a laminate of the above metals and/or alloys. For example, the metal electrode ME may comprise a metal stack of Ti/Al/Ti/Au, Cr/Pt/Au or Cr/Al/Ti/Pt/Au.

Next, referring to fig. 1E, a tie TR IS formed on the sidewall Ws of the semiconductor stack SS, the sidewall Wm of the matching pattern MP, the sidewall Wt of the transparent electrode TE, and the surface Fi of the interposer IS. In this way, the tie TR and the transparent electrode TE can be attached to the surface Fi of the interposer IS, so that the surface Fr of the tie TR facing the interposer IS can be flush with the surface Ft of the transparent electrode TE facing the interposer IS. The term "flush" as used herein means "approximately flush". For example, in some embodiments, surface Fr and/or surface Ft may have surface undulations less than or equal to 3 μm due to process tolerances, and thus, certain regions of surface Fr and certain regions of surface Ft may have surface height differences of about 5 μm. In certain embodiments, certain regions of surface Fr may have a surface height difference of about 3 μm, 2 μm, or 1 μm from certain regions of surface Ft. In some embodiments, the tie TR may also be formed on the sidewall We of the metal electrode ME. The material of the tie TR is, for example, silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

To this end, the light emitting element 120 IS formed on the interposer IS, and the light emitting element 120 may include: a semiconductor stack SS; a metal electrode ME on the semiconductor stack SS; a transparent electrode TE on the side of the semiconductor stack SS opposite to the metal electrode ME; a matching pattern MP between the semiconductor stack SS and the transparent electrode TE; and a tie TR extending at least sidewalls of the semiconductor stack SS and the transparent electrode TE, and a surface Fr of the tie TR away from the metal electrode ME is flush with a surface Ft of the transparent electrode TE away from the metal electrode ME, wherein the semiconductor stack SS may include a first-type semiconductor pattern SP1, a second-type semiconductor pattern SP2, and a light emitting pattern EP, wherein the first-type semiconductor pattern SP1 may be between the metal electrode ME and the transparent electrode TE, the second-type semiconductor pattern SP2 may overlap the first-type semiconductor pattern SP1 and be between the first-type semiconductor pattern SP1 and the transparent electrode TE, and the light emitting pattern EP may be between the first-type semiconductor pattern SP1 and the second-type semiconductor pattern SP 2. The metal electrode ME and the transparent electrode TE of the light emitting device 120 are respectively located at two opposite sides of the light emitting pattern EP, that is, the light emitting device 120 is a vertical light emitting diode. In some embodiments, the light emitting element 120 may be a vertical light emitting diode emitting blue light or green light, but is not limited thereto.

Next, referring to fig. 1F, in some embodiments, a sacrificial layer SF may be further formed on the metal electrode ME and the tie TR, and the sacrificial layer SF may be formed with a plurality of vias VA, an orthographic projection of each via VA on the interposer IS does not overlap an orthographic projection of the semiconductor stack SS on the interposer IS, and the vias VA may expose a portion of the tie TR attached to the interposer IS. The sacrificial layer SF may include an organic material, but is not limited thereto. The through hole VA may have an inverted trapezoid shape with a wide top and a narrow bottom, but is not limited thereto.

Next, referring to fig. 1G, a support PC may be further formed in each through hole VA. Since the via VA may expose the tie TR and the via VA does not overlap the semiconductor stack SS, the support PC may connect the tie TR and the support PC does not overlap the semiconductor stack SS. In some embodiments, the support layer PL may be formed on the support PC and the sacrificial layer SF, and the support layer PL may belong to the same film layer as the support PC. Thus, the support member PC and the sacrificial layer SF can be ensured to have flat upper surfaces. The support member PC and/or the support layer PL may include a material having a certain rigidity, such as a metal, and the support member PC and/or the support layer PL may have a multi-layer structure.

Next, referring to fig. 1G, a carrier CS may be further formed on the support PC, the metal electrode ME and the support layer PL. For example, the carrier CS may be attached to the supporting layer PL. Next, referring to fig. 1H, after the carrier CS IS formed, the intermediate substrate IS may be removed, for example, by laser lift-off or thermal treatment. Next, referring to fig. 1I, the sacrificial layer SF may be removed after the intermediate substrate IS removed. For example, the sacrificial layer SF may be removed by exposure and development. To this end, the light emitting device 10A according to an embodiment of the present invention is completed, and the light emitting device 10A may include: a carrier plate CS; a plurality of supports PC located on the carrier plate CS; a light emitting element 120 suspended between the supports PC by a tie TR; and a support layer PL between the plurality of supports PC and the light emitting element 120 and the carrier substrate CS, wherein a surface Fr of the tie TR away from the metal electrode ME is flush with a surface Ft of the transparent electrode TE away from the metal electrode ME.

In some embodiments, the orthogonal projection of the tie TR on the carrier CS may be outside the orthogonal projection of the metal electrode ME on the carrier CS. In some embodiments, the tie TR also extends over the support PC, so that the tie TR can be connected to the support PC.

Next, referring to fig. 1J, after removing the sacrificial layer SF, a circuit substrate 110 may be further provided, wherein the circuit substrate 110 may include a pad PD on a surface thereof. Then, a bulk transfer process may be performed, that is, the light emitting device 120 in the light emitting assembly 10A is taken out and transferred onto the circuit substrate 110, for example, the metal electrode ME of the light emitting device 120 is placed on the pad PD, so that the metal electrode ME is located between the semiconductor stack SS and the pad PD of the circuit substrate 110, and then the metal electrode ME of the light emitting device 120 is electrically connected to the pad PD through, for example, a heat treatment. To this end, the display device 10 according to an embodiment of the invention is completed, and the display device 10 may include: a circuit substrate 110; and a light emitting element 120 disposed on the circuit substrate 110 and electrically connected to the circuit substrate 110. Since the upper electrode of the light emitting element 120 of the display device 10 is the transparent electrode TE, the current in the light emitting element 120 can be uniformly distributed to the transparent electrode TE, and the display device 10 can have good light extraction efficiency.

For example, the circuit substrate 110 may include a bottom plate 112 and a driving circuit layer 114. The bottom plate 112 of the circuit substrate 110 may be a transparent substrate, an opaque substrate, a flexible substrate or an inflexible substrate, and may be made of a quartz substrate, a glass substrate, a polymer substrate or other suitable materials. The driving circuit layer 114 may include elements or lines required for the display device 10, such as driving elements, switching elements, storage capacitors, power supply lines, driving signal lines, timing signal lines, current compensation lines, detection signal lines, and the like. The driving circuit layer 114 may be formed on the base plate 112 using a thin film deposition process, a photolithography process, and an etching process. The driving circuit layer 114 may include at least one insulating layer and at least one conductive layer, and the driving circuit layer 114 may include more insulating layers and conductive layers as required.

In some embodiments, the driving circuit layer 114 of the circuit substrate 110 may further include a switching element array, wherein the switching element array includes a plurality of switching elements T arranged in an array, and the switching elements T may be electrically connected to the light emitting elements 120. In detail, the driving circuit layer 114 may include, for example, a switching element T, power lines VL1, VL2, conductive structures CR1, CR2, a pad PD, a buffer layer I1, a gate insulating layer I2, an interlayer insulating layer I3, and insulating layers I4 and I5. The switching element T is composed of a semiconductor layer TC, a gate electrode TG, a source electrode TS, and a drain electrode TD. A region where the semiconductor layer TC overlaps the gate electrode TG may be regarded as a channel region of the switching element T. The buffer layer I1 is located between the base plate 112 and the semiconductor layer TC to prevent impurities in the base plate 112 from moving into the semiconductor layer TC and to enhance adhesion between the semiconductor layer TC and the base plate 112. The gate insulating layer I2 is located between the gate electrode TG and the semiconductor layer TC. The interlayer insulating layer I3 is disposed between the source and drain electrodes TS and TD and the gate electrode TG and the power supply line VL 2. The gate TG and the source TS may respectively receive signals from, for example, driving elements. The insulating layer I4 is disposed between the source TS, the drain TD, the power line VL1, the conductive structures CR1 and CR2, the insulating layer I5 is disposed between the conductive structures CR1 and CR2 and the pad PD, and the pad PD may be disposed on the insulating layer I5. The conductive structure CR1 can be electrically connected to the power line VL1 through a via V1 in the insulating layer I4, the conductive structure CR2 can be electrically connected to the drain TD through a via V2 in the insulating layer I4, and the pad PD can be electrically connected to the conductive structure CR1 through a via V3 in the insulating layer I5. In some embodiments, the pad PD may not be electrically connected to the conductive structure CR1, and the pad PD may be electrically connected to the conductive structure CR2 through another through hole in the insulating layer I5, so that the switching element T may be electrically connected to the metal electrode ME of the light emitting element 120.

The material of the semiconductor layer TC may include a silicon semiconductor material (e.g., polysilicon, amorphous silicon, etc.), an oxide semiconductor material, and an organic semiconductor material, but is not limited thereto. The gate TG, the source TS, the drain TD, the power lines VL1, VL2, the conductive structures CR1, CR2 and the pad PD may be made of a metal with good conductivity, such as aluminum, molybdenum, titanium, copper, but not limited thereto. In some embodiments, the conductive structures CR1, CR2 and the pad PD may have a single-layer structure or a multi-layer structure, such as a stack of two or more layers of any of the above conductive metals or conductive oxides, which may be combined or changed as needed. For example, the conductive structure CR1 may include, but is not limited to, a titanium layer, an aluminum layer, and a titanium layer stacked in sequence or a molybdenum layer, an aluminum layer, and a molybdenum layer stacked in sequence.

The buffer layer I1, the gate insulating layer I2, the interlayer insulating layer I3, and the insulating layers I4 and I5 may be made of transparent inorganic insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but not limited thereto. In some embodiments, the buffer layer I1, the gate insulating layer I2, the interlayer insulating layer I3, and the insulating layers I4 and I5 may also have a single-layer structure or a multi-layer structure, such as a stack of two or more layers of any of the above insulating materials, which may be combined or changed as needed.

In some embodiments, after electrically connecting the metal electrode ME and the pad PD, the transparent electrode TE may be electrically connected to the switching element T of the circuit substrate 110. For example, the insulating layer I6 may be formed on the insulating layer I5, and at least the transparent electrode TE of the light emitting device 120 is exposed. Next, a via hole V4 penetrating through the insulating layers I5, I6 and exposing the conductive structure CR2 is formed. Then, a conductive structure CR3 is formed on the transparent electrode TE and in the via hole V4, so that the transparent electrode TE can be electrically connected to the drain TD of the switching element T through the conductive structure CR3 and the conductive structure CR 2. The conductive structure CR3 may be made of Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Indium Gallium Zinc Oxide (IGZO) or other suitable conductive oxides, and the insulating layer I6 may be made of a transparent inorganic insulating material, such as silicon oxide, silicon nitride, silicon oxynitride or a stack thereof, but is not limited thereto.

In some embodiments, when the pad PD is electrically connected to the conductive structure CR2, a via penetrating through the insulating layers I5 and I6 and exposing the conductive structure CR1 may be formed, and then another conductive structure is formed on the transparent electrode TE and in the via exposing the conductive structure CR1 to electrically connect the transparent electrode TE and the power line VL 1.

Hereinafter, other embodiments of the present invention will be described with reference to fig. 2 to 3, and the reference numerals and related contents of the elements of the embodiment of fig. 1A to 1J are used, wherein the same reference numerals are used to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted portions, reference may be made to the embodiments of fig. 1A to 1J, which will not be repeated in the following description.

Fig. 2 is a schematic cross-sectional view of a light emitting device 20A according to an embodiment of the invention. The light emitting assembly 20A may include: a carrier plate CS; a plurality of supports PC located on the carrier plate CS; a light emitting element 120A suspended between the supports PC by a tether TRa; and a support layer PL between the plurality of support members PC and the light emitting element 120A and the carrier plate CS, wherein a surface Fra of the tie member TRa away from the metal electrode ME is flush with a surface Ft of the transparent electrode TE away from the metal electrode ME.

Compared with the light emitting assembly 10A shown in fig. 1I, the light emitting assembly 20A shown in fig. 2 is different in that: the series TRa of the light emitting elements 120A of the light emitting assembly 20A may include a Distributed Bragg Reflector (DBR), wherein the DBR of the series TRa may include, for example, a plurality of titanium oxide (TiO) layers that overlap ₂ ) Layer and plurality of silicon oxide (SiO) ₂ ) And (3) a layer. By providing the connection member TRa including the bragg reflector to control the total transmittance or total reflectance of the specific wavelength band for filtering, it is ensured that the light emitted by the light emitting element 120A provided by the light emitting component 20A can be converted into light with complete color conversion, and the total reflectance wavelength band can be converted into light with additional color conversion to increase the light intensity. In addition, since the upper electrode of the light emitting device 120A is the transparent electrode TE, when the light emitting device 120A is enabled, the light emitting device 120A can have good light extraction efficiency, and the current can be uniformly distributed in the transparent electrode TE.

Fig. 3 is a partial cross-sectional view of a display device 20 according to an embodiment of the invention. The display device 20 may include: a circuit substrate 110; and a light emitting element 120A disposed on the circuit substrate 110 and electrically connected to the circuit substrate 110.

The display device 20 shown in fig. 3 differs from the display device 10 shown in fig. 1J in that: the series TRa of the light emitting elements 120A of the display device 20 may include a Distributed Bragg Reflector (DBR), wherein the DBR of the series TRa may include, for example, a plurality of titanium oxide (TiO) that are overlapped ₂ ) Layer and plurality of silicon oxide (SiO) ₂ ) A layer. By providing the connection TRa including the Bragg reflection layer to control the total penetration or total reflection of the specific wavelength band for filtering, the color light conversion of the display device 20 can be ensured to be complete, and the total reflected wave can be ensuredThe segments may be color converted again to increase the light intensity, thereby improving the full color display effect of the display device 20. In addition, since the upper electrode of the light emitting element 120A in the display device 20 is the transparent electrode TE, the current in the light emitting element 120A can be uniformly distributed to the transparent electrode TE, and the display device 20 can provide good light extraction efficiency.

In summary, the light emitting device, the light emitting assembly and the display apparatus of the present invention can make the current in the light emitting device uniformly distributed on the transparent upper electrode by making the upper electrode of the vertical light emitting device be the transparent electrode, and the light emitting device, the light emitting assembly and the display apparatus can have good light extraction efficiency.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A light emitting element comprising:

a semiconductor stack;

a metal electrode on the semiconductor stack;

a transparent electrode on a side of the semiconductor stack opposite the metal electrode; and

and the series piece at least extends to the side walls of the semiconductor lamination layer and the transparent electrode, and the surface of the series piece far away from the metal electrode is flush with the surface of the transparent electrode far away from the metal electrode.

2. The light-emitting element according to claim 1, wherein the tie comprises silicon oxide, silicon nitride, or a bragg reflective layer.

3. The light emitting device according to claim 2, wherein the bragg reflector comprises a plurality of titanium oxide layers and a plurality of silicon oxide layers overlapping each other.

4. The light-emitting element according to claim 1, wherein the stacked semiconductor layers comprise:

a first type semiconductor pattern between the metal electrode and the transparent electrode;

the second type semiconductor pattern is overlapped with the first type semiconductor pattern and is positioned between the first type semiconductor pattern and the transparent electrode; and

and the light-emitting pattern is positioned between the first type semiconductor pattern and the second type semiconductor pattern.

5. The light emitting device of claim 4, wherein the second type semiconductor pattern comprises a P type semiconductor material.

6. The light-emitting element according to claim 1, further comprising a matching pattern between the semiconductor laminated layer and the transparent electrode.

7. A light emitting assembly comprising:

a carrier plate;

a plurality of supporting members positioned on the carrier plate; and

the light-emitting element according to any one of claims 1 to 6, suspended between the supporting members by the tether.

8. The light-emitting device according to claim 7, wherein an orthogonal projection of the contact on the carrier is outside an orthogonal projection of the metal electrode on the carrier.

9. The light emitting assembly of claim 7, wherein the tie further extends onto the plurality of supports.

10. The light emitting assembly of claim 7, further comprising a support layer between the plurality of support members and the light emitting elements and the carrier plate.

11. The light emitting assembly of claim 10, wherein the support layer is integrally formed with the support member.

12. A display device, comprising:

a circuit substrate; and

the light-emitting device according to any one of claims 1 to 6, located on the circuit substrate and electrically connected to the circuit substrate.

13. The display device according to claim 12, wherein the metal electrode is located between the semiconductor stack and the circuit substrate.

14. The display device according to claim 12, wherein the circuit substrate further comprises a switching element, and the switching element is electrically connected to the transparent electrode or the metal electrode.

15. A method of manufacturing a display device, comprising:

providing a growth substrate;

forming a plurality of semiconductor layers on the growth substrate;

forming a transparent electrode layer on the multilayer semiconductor layer;

forming an intermediate substrate on the transparent electrode layer;

removing the growth substrate;

patterning the multilayer semiconductor layer and the transparent electrode layer to form a semiconductor stack and a transparent electrode;

forming a metal electrode on the semiconductor lamination; and

forming a tie on the semiconductor stack and the sidewalls of the transparent electrode and the interposer, wherein a surface of the tie facing the interposer is flush with a surface of the transparent electrode facing the interposer.

16. The method for manufacturing a display device according to claim 15, wherein the forming of the multilayer semiconductor layer comprises:

forming a first type semiconductor layer on the growth substrate;

forming a light emitting layer on the first type semiconductor layer; and

and forming a second type semiconductor layer on the light emitting layer.

17. The method of manufacturing a display device according to claim 15, wherein the forming of the transparent electrode layer comprises:

forming a matching layer on the multilayer semiconductor layer; and

and forming a transparent electrode layer on the matching layer.

18. The method of claim 15, further comprising forming a plurality of supports on the tie, wherein the supports do not overlap the stack of semiconductor layers.

19. The method of claim 18, wherein the forming a plurality of supports on the interconnects comprises:

forming a sacrificial layer on the metal electrode and the tie, the sacrificial layer having a plurality of vias that do not overlap the semiconductor stack and expose the tie; and

forming the supporting member in each through hole.

20. The method for manufacturing a display device according to claim 19, wherein the sacrificial layer comprises an organic material.

21. The method of claim 18, further comprising forming a carrier plate on the plurality of supports and the metal electrode.

22. The method according to claim 21, wherein the forming of the carrier further comprises removing the interposer substrate.

23. The method of claim 22, wherein the removing the interposer further comprises removing the sacrificial layer.

24. The method for manufacturing a display device according to claim 23, wherein the removing the sacrifice layer further comprises:

providing a circuit substrate comprising a pad on a surface thereof;

transposing the transparent electrode, the semiconductor laminate layer, the metal electrode, and the interconnection on the bonding pad of the circuit substrate such that the metal electrode is located between the semiconductor laminate layer and the bonding pad; and

and electrically connecting the metal electrode and the pad.

25. The method for manufacturing a display device according to claim 24, further comprising a switching element electrically connecting the transparent electrode and the circuit substrate.