TWI673888B - Manufacturing method of a light-emitting element - Google Patents

Abstract

A method for manufacturing a light emitting element includes the following steps. On the growth substrate A first semiconductor layer, a light emitting layer, and a second semiconductor layer are sequentially formed. A sacrificial layer is formed on the second semiconductor layer. An opening is formed in the sacrificial layer to expose a portion of the second semiconductor layer, wherein the sidewall of the opening and the second semiconductor layer form an inclination angle, and the angle of the inclination angle ranges from 45 ° to 90 °. A first bonding layer is formed and its convex portions are overlapped and opened. A carrier substrate is provided. Forming a second bonding layer and bonding the second bonding layer and the first bonding layer. A first patterned semiconductor layer and a second patterned semiconductor layer are formed. The sacrificial layer is removed to expose the protruding portion and the bonding portion formed by the portion of the first insulating layer that contacts the protruding portion. The bonding portion contacts the second patterned semiconductor layer.

Description

Manufacturing method of light emitting element

The present invention relates to a method for manufacturing a light-emitting element, and in particular, to a method for manufacturing a light-emitting element vertically stacked on a joint portion.

Light emitting diodes (LEDs) have advantages such as long life, small size, high shock resistance, low heat generation, and low power consumption, so they have been widely used as indicators or light sources in homes and various devices. In recent years, light-emitting diodes have developed toward multi-color and high brightness, so their application fields have expanded to large outdoor signages, traffic lights, and related fields. In the future, light emitting diodes may even become the main lighting source with both power saving and environmental protection functions.

Generally speaking, the light-emitting diode is first fabricated on a wafer, and then the light-emitting diode is transferred to the display panel by mass transfer technology. Therefore, how to provide more number of transmissive light-emitting diodes on the same wafer, in order to reduce the production cost and save the production time, is a problem to be solved at present.

The manufacturing method of the light emitting element of the present invention includes the following steps. First, a first semiconductor layer, a light emitting layer, and a second semiconductor layer are sequentially formed on a growth substrate. A sacrificial layer is formed on the second semiconductor layer. An opening is formed in the sacrificial layer to expose a portion of the second semiconductor layer, wherein the sidewall of the opening and the second semiconductor layer form an inclination angle, and the angle of the inclination angle ranges from 45 ° to 90 °. A first insulating layer is formed on the sacrificial layer and contacts the second semiconductor layer through the opening. A first bonding layer is formed on the first insulating layer. The first bonding layer has a flat portion and a convex portion and covers the first insulating layer. A carrier substrate is provided. A second bonding layer is formed on the carrier substrate. Bond the second bonding layer and the first bonding layer. The growth substrate is removed by laser peeling. A portion of the first semiconductor layer and a portion of the second semiconductor layer are removed to form a first patterned semiconductor layer and a second patterned semiconductor layer, respectively. A second insulating layer is formed and covers the first and second semiconductor layers. The second insulating layer has a first contact hole and a second contact hole. Forming a first electrode and electrically connecting the first patterned semiconductor layer through the first contact hole. Forming a second electrode and electrically connecting the second patterned semiconductor layer through the second contact hole. And, the sacrificial layer is removed so that the convex portion and a portion of the first insulating layer contacting the convex portion form a joint portion, and the joint portion contacts the second patterned semiconductor layer.

The manufacturing method of the light emitting element of the present invention includes the following steps. First, a first semiconductor layer, a light emitting layer, and a second semiconductor layer are sequentially formed on a growth substrate. A portion of the first semiconductor layer and a portion of the second semiconductor layer are removed to form a first patterned semiconductor layer and a second patterned semiconductor layer, respectively. A second insulating layer is formed and covers the first and second semiconductor layers. The second insulating layer has a first contact hole and a second contact hole. Forming a first electrode and electrically connecting the first patterned semiconductor layer through the first contact hole. form The second electrode is electrically connected to the second patterned semiconductor layer through the second contact hole. A sacrificial layer is formed on the growth substrate to cover the second patterned semiconductor layer. An opening is formed in the sacrificial layer to expose a portion of the second patterned semiconductor layer, wherein the sidewall of the opening and the second patterned semiconductor layer form an inclination angle, and the angle of the inclination angle ranges from 45 ° to 90 °. A first insulating layer is formed on the sacrificial layer and contacts the second patterned semiconductor layer through the opening. A first bonding layer is formed on the first insulating layer. The first bonding layer has a flat portion and a convex portion and covers the first insulating layer. A carrier substrate is provided. A second bonding layer is formed on the carrier substrate. Bond the second and first bonding layers. Remove the growth substrate. And, the sacrificial layer is removed so that the convex portion and a portion of the first insulating layer contacting the convex portion form a joint portion, and the joint portion contacts the second patterned semiconductor layer.

Based on the above, in the method for manufacturing a light-emitting element according to an embodiment of the present invention, since the light-emitting elements can be vertically stacked on the joint portion, the joint portion does not occupy the surface of the carrier substrate, so as to increase the number of light-emitting elements on the carrier substrate and density. When the number of light-emitting elements that can be fixed on the same carrier substrate is increased, in addition to reducing the manufacturing cost, it can also reduce the time for changing wafers during the transposition process and the number of alignments required to reduce the alignment correction. The error. Overall, you can reduce production costs and achieve time savings. In addition, the bonding portion is directly fabricated on the second patterned semiconductor layer. Therefore, when transferring the material forming the light-emitting element onto the carrier substrate, it is not necessary to align with the anchor point on the carrier substrate. Therefore, the present invention can reduce the number of times of alignment correction, and reduce errors generated by the alignment correction. In addition, since the opening can define the size at which the bonding portion contacts the light emitting element, the connection reliability of the light emitting element and the bonding portion can be improved.

One of the objectives of the present invention is to increase the number of light emitting elements on a carrier substrate.

One of the objectives of the present invention is to increase the density of light emitting elements on a carrier substrate.

One of the objects of the present invention is to reduce the errors caused by the alignment correction.

One of the objects of the present invention is to improve the reliability of the connection between the light emitting element and the joint portion.

One of the objects of the present invention is to reduce the manufacturing cost.

One of the objects of the present invention is to save production time.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

10, 10 ’, 10A, 10A’‧‧‧ light-emitting element

100‧‧‧ Growth substrate

110, 110A‧‧‧First patterned semiconductor layer

110 ’, 110A’‧‧‧first semiconductor layer

120, 120A‧‧‧ luminescent pattern layer

120 ’, 120A’‧‧‧ luminescent layer

130, 130A‧‧‧Second patterned semiconductor layer

130 ’, 130A’‧‧‧Second semiconductor layer

140, 140A‧‧‧ sacrificial layer

141, 141A‧‧‧ sidewall

142, 142A‧‧‧ opening

150‧‧‧first insulating layer

152‧‧‧Second insulation layer

154‧‧‧ part of the first insulating layer contacting the convex portion

160‧‧‧First Bonding Layer

162‧‧‧ flat

164‧‧‧ convex

170, 170A‧‧‧First electrode

172, 172A, 182, 182A‧‧‧ metal pads

180, 180A‧‧‧Second electrode

190‧‧‧Joint

200‧‧‧ carrier substrate

220‧‧‧Second Bonding Layer

240‧‧‧ Bonding Structure

A1‧‧‧first area

A2‧‧‧Second Area

O1‧‧‧First contact hole

O2‧‧‧Second contact hole

θ‧‧‧ tilt angle

1A to 1K are schematic cross-sectional views illustrating a manufacturing process of a light emitting device according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a light-emitting element according to another embodiment of the present invention.

3A to 3K are schematic cross-sectional views illustrating a manufacturing process of a light emitting device according to still another embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view of a light emitting device according to another embodiment of the present invention.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of each element and the like is exaggerated for clarity. Throughout the description, the same reference numerals denote the same elements. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on another element" or "connected to another element" or "overlapping on another element", it may be directly on the other element It may be connected to another element, or an intermediate element may be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and / or electrical connection.

It should be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, and / or sections, and / Or in part should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer," or "portion" discussed below may be termed a second element, component, region, layer, or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms including "at least one" unless the content clearly indicates otherwise. "Or" means "and / or". As used herein, the term "and / or" includes Include any and all combinations of one or more of the related listed items. It should also be understood that when used in this specification, the terms "including" and / or "including" specify the stated features, regions, wholes, steps, operations, presence of elements and / or components, but do not exclude one or more The presence or addition of other features, whole regions, steps, operations, elements, components, and / or combinations thereof.

In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element, as shown. It should be understood that relative terms are intended to include different orientations of the device in addition to the orientation shown in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "down" may include orientations of "down" and "up", depending on the particular orientation of the drawings. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "below" may include orientations above and below.

As used herein, "about", "substantially", "substantially", or "approximately" includes the stated value and the average value within an acceptable deviation range of a particular value determined by one of ordinary skill in the art, taking The measurement in question and the specific number of measurement-related errors (ie, limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the stated value, or within ± 30%, ± 20%, ± 10%, ± 5%.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Righteousness. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the related art and the present invention, and will not be interpreted as idealized or excessive Formal meaning unless explicitly defined as such in this article.

Exemplary embodiments are described herein with reference to cross-sectional views that are schematic views of idealized embodiments. Accordingly, variations in the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Therefore, the embodiments described herein should not be construed as limited to the particular shape of the area as shown herein, but include shape deviations caused by, for example, manufacturing. For example, a region shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, the acute angles shown may be round. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

1A to 1K are schematic cross-sectional views illustrating a manufacturing process of a light emitting device according to an embodiment of the present invention. The method for manufacturing the light-emitting element 10 (shown in FIG. 1K) will be described below with an embodiment. Referring to FIG. 1A, first, a growth substrate 100 is provided. In this embodiment, the growth substrate 100 is, for example, a sapphire substrate, but the invention is not limited thereto.

Next, a first semiconductor layer 110 ', a light emitting layer 120', and a second semiconductor layer 130 'are sequentially formed on the growth substrate 100. For example, in this embodiment, the first semiconductor layer 110 'includes an N-type semiconductor layer, the second semiconductor layer 130' includes a P-type semiconductor layer, and the light-emitting layer 120 'includes a multiple quantum well structure (multiple quantum well, MQW). ), But the invention is not limited to this. N-type semiconductor layer The material is, for example, N-type gallium nitride (n-GaN) doped with a Group IVA element (such as silicon), and the material of the P-type semiconductor layer is, for example, P-type nitride doped with a Group IIA element (such as Mg). Gallium (p-GaN). The multiple quantum well structure includes a plurality of quantum well layers (Well) and a plurality of quantum barrier layers (Barrier) alternately arranged in a repeating manner. Further, the material of the light-emitting layer 120 'includes, for example, multiple layers of indium gallium nitride and multilayer gallium nitride (InGaN / GaN) that are alternately stacked. By designing the ratio of indium or gallium in the light-emitting layer 120', the light-emitting layer 120 'emits different emission wavelength ranges. The first semiconductor layer 110 ', the light emitting layer 120', and the second semiconductor layer 130 'can be formed by, for example, a metal-organic chemical vapor deposition (MOCVD) method. It should be noted that the materials or formation methods of the first semiconductor layer 110 ', the light emitting layer 120', and the second semiconductor layer 130 'described above are merely examples, and the present invention is not limited thereto.

Referring to FIG. 1B, a sacrificial layer 140 is formed on the second semiconductor layer 130 '. In this embodiment, a material of the sacrificial layer 140 includes a photoresist material or an organic glue material. The organic rubber material includes epoxy resin, polyurethane or acrylic resin, but the invention is not limited thereto. In this embodiment, the thickness of the sacrificial layer 140 is, for example, 1 micrometer to 3 micrometers, but the present invention is not limited thereto.

Referring to FIG. 1C, an opening 142 is formed in the sacrificial layer 140 to expose a portion of the second semiconductor layer 130 '. The method for forming the opening 142 includes removing a part of the sacrificial layer 140 to form the opening 142 through a yellow light lithography etching method, a laser removal method, or a cutter cutting method, but the invention is not limited thereto. In this embodiment, the opening 142 is defined as a space that penetrates the sacrificial layer 140 and has an interface between the sacrificial layer 140 and the second semiconductor layer 130 '. In addition, the diameter of the opening 142 is the same as that of the second semiconductor layer 130 '. A portion exposed on the interface of the sacrificial layer 140 has the same diameter. The diameter of the opening 142 is 2 micrometers to 4 micrometers, but is not limited thereto. In this embodiment, the cross-sectional shape of the opening 142 is, for example, a taper, but is not limited thereto. The sidewall 141 of the opening 142 and the second semiconductor layer 130 'form an inclination angle θ. The angle range of the inclination angle θ is 45 ° to 90 °, but is not limited thereto. Under the above-mentioned setting, the joint portion 190 (shown in FIG. 1K) defined by the subsequent through-opening 142 may have a proper size to firmly join the light-emitting element 10 without affecting other elements on the light-emitting element 10. .

Referring to FIG. 1D, a first insulating layer 150 is formed on the sacrificial layer 140. In this embodiment, the first insulating layer 150 contacts the second semiconductor layer 130 'through the opening 142. In other words, in the direction of the vertical growth substrate 100, the opening 142 may define an orthographic projection area where the first insulating layer 150 contacts the second semiconductor layer 130 '. For example, the diameter of the opening 142 is 4 micrometers for description. The area where the first insulating layer 150 contacts the second semiconductor layer 130 'is 16 square micrometers, but the invention is not limited thereto. In this embodiment, the material of the first insulating layer 150 is, for example, an inorganic material, including silicon oxide or silicon nitride or a combination thereof, but the invention is not limited thereto. The method for forming the first insulating layer 150 includes a chemical vapor deposition (CVD) method, but is not limited thereto.

Referring to FIG. 1E, a first bonding layer 160 is formed on the first insulating layer 150. The first bonding layer 160 covers the first insulating layer 150 and the opening 142. Specifically, the first bonding layer 160 includes a flat portion 162 and a convex portion 164. The convex portion 164 is defined as a portion where the first bonding layer 160 overlaps the opening 142. The flat portion 162 is defined as a convex portion The first bonding layer 160 other than 164. From another perspective, the flat portion 162 covers a portion where the first insulating layer 150 does not overlap the opening 142, and the convex portion 164 covers a portion where the first insulating layer 150 overlaps the opening 142. In this embodiment, since the opening 142 may be tapered, the convex portion 164 filled in the opening 142 may have a tapered shape corresponding to the opening 142, but the present invention is not limited thereto. The thickness of the flat portion 162 of the first bonding layer 160 is, for example, 1 micrometer, but the invention is not limited thereto. In this embodiment, a material of the first bonding layer 160 is, for example, an organic material. The organic material includes Benzocyclobutene (BCB), but is not limited thereto. In some embodiments, the material of the first bonding layer 160 may also be a non-insulating material, such as a metal or a metal alloy.

Please refer to FIG. 1F. Next, a carrier substrate 200 is provided. The material of the carrier substrate 200 may include glass, quartz, plastic, opaque / reflective materials (such as conductive materials, metals, wafers, ceramics, or other applicable materials) or other applicable materials. Since the light emitting element 10 is, for example, a light emitting diode as an example, a wafer can be used as the carrier substrate 200, but the present invention is not limited thereto.

Then, a second bonding layer 220 is formed on the carrier substrate 200. The thickness of the second bonding layer 220 is, for example, 1 micrometer, but the invention is not limited thereto. The material of the second bonding layer 220 may be similar to the material of the first bonding layer 160, such as an organic material. The organic material includes Benzocyclobutene (BCB), but is not limited thereto. In some embodiments, the material of the second bonding layer 220 may also include a metal or a metal alloy.

Referring to FIG. 1G, the second bonding layer 220 and the first bonding layer are bonded together. 160. Before performing the above-mentioned bonding step, the growth substrate 100 is first inverted so that the first bonding layer 160 faces the second bonding layer 220 on the carrier substrate 200. Next, the first bonding layer 160 is pressed onto the second bonding layer 220. The bonding method includes, but is not limited to, a pressure method, a heating method, or a pressure heating method. In this embodiment, after being pressed and heated, the first bonding layer 160 and the second bonding layer 220 may be pressed into an integrated bonding structure 240. In other words, before bonding, the first bonding layer 160 and the second bonding layer 220 are two separate film layers. After bonding, the first bonding layer 160 and the second bonding layer 220 can be fused into a film-shaped bonding structure 240.

Please refer to FIG. 1G and FIG. 1H. Then, before performing the step of removing a portion of the first semiconductor layer 110 'and the second semiconductor layer 130', the growth substrate 100 is removed. The above method for removing the growth substrate 100 includes separating the growth substrate 100 from the first semiconductor layer 110 'by laser lift off, but the present invention is not limited thereto.

Referring to FIG. 1H and FIG. 1I, an etching process (etching process) is performed on the first semiconductor layer 110 'and the second semiconductor layer 130' to remove part of the first semiconductor layer 110 'and part of the second semiconductor layer 130'. . For example, part of the first semiconductor layer 110 ′, part of the second semiconductor layer 130 ′, and part of the light emitting layer 120 ′ may be removed by plasma etching. In some embodiments, boron trichloride (BCl ₃ ) and / or chlorine (Cl ₂ ) can be used as the etching reaction gas, and the first method is performed by reactive ion etching (Reactive-Ion Etching, RIE). The semiconductor layer 110 ', the second semiconductor layer 130', and the light emitting layer 120 'are etched, but the present invention is not limited thereto.

In this embodiment, part of the first semiconductor layer 110 'and part of the first semiconductor layer 110' are removed. After the two semiconductor layers 130 ', a first patterned semiconductor layer 110 and a second patterned semiconductor layer 130 may be formed respectively. In other words, the first semiconductor layer 110 'forms a first patterned semiconductor layer 110 after etching. The second semiconductor layer 130 'forms a second patterned semiconductor layer 130 after etching. In addition, the light emitting layer 120 'forms a light emitting pattern layer 120 after being etched, and is located between the first patterned semiconductor layer 110 and the second patterned semiconductor layer 130. In this embodiment, the orthographic projection of the first patterned semiconductor layer 110 is smaller than the orthographic projection of the second patterned semiconductor layer 130 in the direction perpendicular to the substrate 200. For example, the cross sections of the first patterned semiconductor layer 110 and the second patterned semiconductor layer 130 may be stepped, but the invention is not limited thereto. In this embodiment, the first patterned semiconductor layer 110 is an N-type semiconductor layer, and the second patterned semiconductor layer 130 is a P-type semiconductor layer, but it is not limited thereto.

As shown in FIG. 1I, a second insulating layer 152 is formed on the first patterned semiconductor layer 110 and the second patterned semiconductor layer 130. The second insulating layer 152 covers the first patterned semiconductor layer 110 and the second patterned semiconductor layer 130. In this embodiment, the material of the second insulating layer 152 may include silicon oxide, silicon nitride, or other suitable materials.

Next, a yellow light lithography method is used to pattern and develop the second insulating layer 152. A plurality of Via holes are formed in the second insulating layer 152 by etching. The contact holes serve as windows for the patterned semiconductor layers 110 and 130 to be electrically connected to the electrodes. The above-mentioned etching method may be dry etching or wet etching, but the invention is not limited thereto. In this embodiment, the plurality of contact holes include a first contact hole O1 and a second contact hole O2. First contact hole O1 On the first patterned semiconductor layer 110. The second contact hole O2 is located on the second patterned semiconductor layer 130.

Please refer to FIG. 1J. Then, a first electrode 170 is formed on the second insulating layer 152. The first electrode 170 is electrically connected to the first patterned semiconductor layer 110 through the first contact hole O1. Next, a second electrode 180 is formed on the second insulating layer 152. The second electrode 180 is electrically connected to the second patterned semiconductor layer 130 through the second contact hole O2. In this embodiment, the first electrode 170 and the second electrode 180 are formed by, for example, a physical vapor deposition (PVD) method, and then formed by photolithography and etching processes. But not limited to this. The first electrode 170 may be a transparent electrode, a reflective electrode, or a combination thereof. For example, the material of the transparent electrode may be a metal oxide, such as: indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, or other suitable oxides, or It is a stacked layer of at least two of the above; the material of the reflective electrode may be metal or other suitable materials, but the invention is not limited thereto. The material of the second electrode 180 is metal, but the present invention is not limited thereto. In other embodiments, the second electrode 180 may also use other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, and metals. Nitrogen oxides of materials, thin graphite, stacked layers of metallic materials, or stacked layers of other conductive materials.

In this embodiment, the light emitting element 10 includes a first electrode 170, a first patterned semiconductor layer 110, a light emitting pattern layer 120, a second patterned semiconductor layer 130, a second electrode 180, and a second insulating layer 152. The second patterned semiconductor layer 130 is located between the first electrode 170 and the second electrode 180 and the carrier substrate 200. For example In other words, each of the first electrode 170 and the second electrode 180 faces a side far from the carrier substrate 200. Under the above arrangement, the light-emitting element 10 may be referred to as a light-emitting diode (LED). For example, the light-emitting element 10 is a lateral LED chip.

In this embodiment, the carrier substrate 200 is, for example, a wafer, and is configured to carry a plurality of light emitting elements 10. For clarity of illustration and convenience of description, the present invention only illustrates one light-emitting element 10 on the carrier substrate 200. Those of ordinary skill in the art should be able to know that thousands of light emitting elements 10 can be carried on the carrier substrate 200 to be applied to the conventional mass transfer technology.

Please refer to FIG. 1J and FIG. 1K. Then, the sacrificial layer 140 is removed. The foregoing method for removing the sacrificial layer 140 includes an etching method, but is not limited thereto. In this embodiment, after the sacrificial layer 140 is removed, the convex portion 164 and the portion 154 of the first insulating layer 150 contacting the convex portion 164 may form a joint portion 190. In detail, after the sacrificial layer 140 is removed, the convex portion 164 overlapping the opening 142 and the first insulating layer 150 in the opening 142 contacting the second patterned semiconductor layer 130 and the convex portion 164 may be defined as the joint portion 190. From another perspective, the joint portion 190 includes a convex portion 164 and a portion 154 of the first insulating layer 150 that contacts the convex portion 164. Wherein, the portion 154 of the first insulating layer 150 that contacts the convex portion 164 may abut and contact the second patterned semiconductor layer 130. That is, the bonding portion 190 contacts the second patterned semiconductor layer 130. In this embodiment, the joint portion 190 may be applied as an anchor to fix the light emitting element 10 on the carrier substrate 200. Wherein, the first insulating layer 150 and / or a portion 154 of the first insulating layer 150 can be used as a separation layer to reduce the light emitting element 10 in the subsequent process of massive transposition. The chance of causing damage.

It is worth noting that, in this embodiment, since the bonding portion 190 serving as an anchor point can overlap the second patterned semiconductor layer 130 in the direction of the vertical bearing substrate 200. In other words, the second patterned semiconductor layer 130 is vertically stacked on the bonding portion 190. Under the above-mentioned setting, compared with the conventional tether, the anchor point is set on the side of the light-emitting element to be fixed to the surface of the wafer. The joint portion 190 of this embodiment is fixed to the light-emitting The bottom of the element 10 overlaps the second patterned semiconductor layer 130. As such, the bonding portion 190 does not occupy an additional surface of the carrier substrate 200. Therefore, the omitted extra surface can be used to carry more light emitting elements 10. Accordingly, the present invention can increase the number of light-emitting elements 10 and increase the density of the light-emitting elements 10 on the carrier substrate 200.

In addition, the portion 154 of the first insulating layer 150 and the convex portion 164 of the first bonding layer 160 are directly formed on the second semiconductor layer 130 'as shown in FIG. 1E. Therefore, when the second semiconductor layer 130 ′, the light emitting layer 120 ′, and the first semiconductor layer 110 ′ are transferred onto the carrier substrate 200 (as shown in FIG. 1G), the anchor points on the carrier substrate 200 need not be aligned. . In addition, it is not necessary to perform alignment correction after the above-mentioned transposition procedure to form anchor points on the sides of the light emitting element 10. Therefore, the present invention can reduce the number of times of alignment correction, and reduce errors generated by the alignment correction.

In addition, please refer to FIG. 1J and FIG. 1K. Since the diameter of the opening 142 in this embodiment is defined as a portion of the surface of the second patterned semiconductor layer 130 (the second semiconductor layer 130 'after etching) exposed by the opening 142 The diameter is the same. In addition, the joint portion 190 may be defined by the opening 142. Therefore, the bonding portion 190 contacts the second patterned semiconductor The diameter of the portion of the interface of the bulk layer 130 is the same as the diameter of the opening 142. In other words, in the direction of the vertical carrying substrate 200, the orthographic projection area of the interface of the bonding portion 190 contacting the second patterned semiconductor layer 130 is the same as the orthographic projection area of the opening 142. Next, the ratio of the orthographic projection area (for example, the first area A1) of the opening 142 to the carrier substrate 200 to the orthographic projection area (for example, the second area A2) of the second patterned semiconductor layer 130 on the carrier substrate 200 is in the range of 1: Between 2 and 1: 625. That is, the orthographic projection area of the bonding portion 190 contacting the light emitting element 10 is smaller than the orthographic projection area of the light emitting element 10. For example, the first area A1 is smaller than the second area A2. Under the above-mentioned setting, the joint portion 190 can be fixed to the light emitting element 10 without affecting the arrangement of the electrodes 170, 180 or other elements on the light emitting element 10. In addition, within the above-mentioned ratio range, the bonding portion 190 can achieve a pulling force of less than 1 kilogram-force (kgw) with the light-emitting element 10. In this way, in addition to improving the reliability of the connection between the light-emitting element 10 and the joint portion 190, it will not affect the subsequent mass transfer process.

In addition, in some embodiments, the plurality of light-emitting elements 10 described above can then be applied to the manufacture of a display panel (not shown). For example, the plurality of light-emitting elements 10 described above can be fixed on the carrier substrate 200 through the plurality of bonding portions 190. Next, through a mass transfer process, a plurality of light emitting elements 10 are transferred onto an array substrate (not shown) to produce a light emitting diode display panel (LED display panel). The above-mentioned mass transfer process may include a pick and place technique to extract the light emitting element 10 through a joint, and then place the light emitting element 10 on the array substrate after alignment.

It is worth noting that, since the light-emitting element 10 of the present invention can be vertically stacked on the bonding portion 190, a single carrier substrate 200 (eg, a wafer) can be lifted. Above, the number and density of the light emitting elements 10 can be set. When the number of the light-emitting elements 10 that can be fixed on the same carrier substrate 200 is increased, in addition to reducing the manufacturing cost, the time for changing wafers during the transposition process and the number of alignments required are reduced to reduce the alignment correction. The resulting error. Overall, you can reduce production costs and achieve time savings. In addition, since the light emitting elements 10 are vertically stacked on the joint portion 190, the space saved on the carrier substrate 200 can allow more margin for the arrangement of the light emitting elements 10. For example, the arrangement pattern of the light emitting elements 10 can be designed according to the pixel requirements of the display panel. Thereby, the manufacturing time of the display panel using the light-emitting element 10 is further saved, and the display quality is further improved.

In short, since the light-emitting elements 10 can be vertically stacked on the bonding portion 190, the bonding portion 190 does not occupy the surface of the carrier substrate 200 to increase the number and density of the light-emitting elements 10 on the carrier substrate 200. When the number of the light-emitting elements 10 that can be fixed on the same carrier substrate 200 is increased, in addition to reducing the manufacturing cost, the time for changing wafers during the transposition process and the number of alignments required are reduced to reduce the alignment correction. The resulting error. Overall, you can reduce production costs and achieve time savings. In addition, the bonding portion 190 is directly formed on the second patterned semiconductor layer 130. Therefore, when transferring the material forming the light-emitting element 10 onto the carrier substrate 200, the anchor points on the carrier substrate 200 need not be aligned. In addition, it is not necessary to perform alignment correction after the above-mentioned transposition procedure to form anchor points on the sides of the light emitting element 10. Therefore, the present invention can reduce the number of times of alignment correction, and reduce errors generated by the alignment correction. In addition, the reliability of the connection between the bonding portion 190 and the light emitting element 10 can be improved without affecting the subsequent mass transfer process.

In the following embodiments, the component numbers and parts of the previous embodiments are used, and the same reference numerals are used to indicate the same or similar components. For the description of parts that omit the same technical content, refer to the foregoing embodiments, and the following embodiments are no longer Repeat.

FIG. 2 is a schematic cross-sectional view of a light-emitting element according to another embodiment of the present invention. 1K and FIG. 2, the light-emitting element 10 ′ of this embodiment is similar to the light-emitting element 10 of FIG. 1K. The main difference is that the method of manufacturing the light-emitting element 10 ′ further includes, before the step of removing the sacrificial layer 140 A plurality of metal pads 172 and 182 are formed to electrically connect the first electrode 170 and the second electrode 180, respectively. In this embodiment, the metal pad 172 is disposed on the first patterned semiconductor layer 110 and covers the first electrode 170. The metal pad 182 is disposed on the second patterned semiconductor layer 130 and covers the second electrode 180. The top surface of the metal pad 172 is aligned with the top surface of the metal pad 182, but it is not limited thereto. The material of the metal pads 172 and 182 is metal, but the present invention is not limited thereto. In other embodiments, the metal pads 172 and 182 may also use other conductive materials, such as alloys, nitrides of metal materials, Oxide, oxynitride of metallic materials, graphite dilute, stacked layers of metallic materials, or stacked layers of other conductive materials. In this way, the light-emitting element 10 'can further improve the electrical quality. In addition, the light emitting element 10 'can also obtain technical effects similar to those of the above embodiment.

3A to 3K are schematic cross-sectional views illustrating a manufacturing process of a light emitting device according to still another embodiment of the present invention. The light-emitting element 10A illustrated in FIGS. 3A to 3K is similar to the light-emitting element 10 illustrated in FIGS. 1A to 1K, and the materials and forming methods of the same or similar film layers may be similar, and will not be described again. In the following embodiments, the light emitting element 10A is a flip-chip LED chip with a flip-chip structure, which will be briefly described.

Please refer to FIG. 3A first, and provide a growth substrate 100 first. Next, a first semiconductor 110A ', a light emitting layer 120A', and a second semiconductor layer 130A 'are sequentially formed on the growth substrate 100. In this embodiment, the first semiconductor layer 110A ′ includes an N-type semiconductor layer, the second semiconductor layer 130A ′ includes a P-type semiconductor layer, and the light-emitting layer 120A ′ includes a multiple quantum well structure (MQW). The invention is not limited to this.

Referring to FIG. 3B, an etching process (etching process) is performed on the first semiconductor layer 110A 'and the second semiconductor layer 130A' to remove part of the first semiconductor layer 110A 'and part of the second semiconductor layer 130A'. In addition, the light emitting layer 120A 'is also etched, but the present invention is not limited thereto.

In this embodiment, after removing a portion of the first semiconductor layer 110A 'and a portion of the second semiconductor layer 130A', a first patterned semiconductor layer 110A and a second patterned semiconductor layer 130A may be formed respectively. In other words, the first semiconductor layer 110A 'forms a first patterned semiconductor layer 110A after etching. After the second semiconductor layer 130A 'is etched, a second patterned semiconductor layer 130A is formed. In addition, the light emitting layer 120A 'forms a light emitting pattern layer 120A after being etched, and is located between the first patterned semiconductor layer 110A and the second patterned semiconductor layer 130A. In this embodiment, in a direction perpendicular to the growth substrate 100, the orthographic projection of the second patterned semiconductor layer 130A is smaller than the orthographic projection of the first patterned semiconductor layer 110A. For example, the cross sections of the first patterned semiconductor layer 110A and the second patterned semiconductor layer 130A may be stepped, but the present invention Not limited to this. In this embodiment, the first patterned semiconductor layer 110A is an N-type semiconductor layer, and the second patterned semiconductor layer 130A is a P-type semiconductor layer, but it is not limited thereto.

As shown in FIG. 3B, a second insulating layer 152 is formed on the first patterned semiconductor layer 110A and the second patterned semiconductor layer 130A. The second insulating layer 152 covers the first patterned semiconductor layer 110A and the second patterned semiconductor layer 130A. In this embodiment, the material of the second insulating layer 152 may include silicon oxide, silicon nitride, or other suitable materials.

Next, a yellow light lithography method is used to pattern and develop the second insulating layer 152. A plurality of contact holes are formed in the second insulating layer 152 by etching. In this embodiment, the plurality of contact holes include a first contact hole O1 and a second contact hole O2. The first contact hole O1 is located on the second patterned semiconductor layer 130A. The second contact hole O2 is located on the first patterned semiconductor layer 110A.

Referring to FIG. 3C, a first electrode 170A is formed on the second insulating layer 152. The first electrode 170A is electrically connected to the first patterned semiconductor layer 110A through the second contact hole O2. Next, a second electrode 180A is formed on the second insulating layer 152. The second electrode 180 is electrically connected to the second patterned semiconductor layer 130A through the first contact hole O1. In this embodiment, the second electrode 180A may be a transparent electrode, a reflective electrode, or a combination thereof. The material of the first electrode 170A is metal, but the present invention is not limited thereto. The top surface of the first electrode 170A is aligned with the top surface of the second electrode 180A, but the invention is not limited thereto.

In this embodiment, the light-emitting element 10A includes a first electrode 170A, The patterned semiconductor layer 110A, the light emitting pattern layer 120A, the second patterned semiconductor layer 130A, the second electrode 180A, and the second insulating layer 152. Each of the first electrode 170A and the second electrode 180A faces a side remote from the growth substrate 100. Under the above arrangement, the light-emitting element 10A is a light-emitting diode wafer having a flip-chip structure.

Referring to FIG. 1D, a sacrificial layer 140A is formed on the growth substrate 100, and the sacrificial layer 140A covers the second patterned semiconductor 130A and the first patterned semiconductor 110A. In this embodiment, the thickness of the sacrificial layer 140A is, for example, 1 micrometer to 3 micrometers, but the invention is not limited thereto.

Referring to FIG. 1E, an opening 142A is formed in the sacrificial layer 140A to expose a portion of the second patterned semiconductor layer 130A '. In this embodiment, the opening 142A is defined as a space penetrating the sacrificial layer 140A and having an interface between the sacrificial layer 140A and the second patterned semiconductor layer 130A '. In addition, the diameter of the opening 142A is the same as the diameter of a portion of the second patterned semiconductor layer 130A 'exposed on the interface of the sacrificial layer 140A. The diameter of the opening 142A is 2 micrometers to 4 micrometers, but is not limited thereto. In this embodiment, the cross-sectional shape of the opening 142A is, for example, a taper, but is not limited thereto. The sidewall 141A of the opening 142A and the second patterned semiconductor layer 130A 'constitute an inclination angle θ. The angle range of the inclination angle θ is 45 ° to 90 °, but is not limited thereto. Under the above settings, the joint portion 190 (shown in FIG. 3K) defined by the subsequent through-opening 142A may have an appropriate size to be firmly joined to the light emitting element 10A without affecting other elements on the light emitting element 10A .

Please refer to FIG. 3F. Then, a first insulating layer 150 is formed on the sacrificial layer 140A. In this embodiment, the first insulating layer 150 contacts the second pattern through the opening 142A. 130A '. In other words, in the direction of the vertical growth substrate 100, the opening 142A may define an orthographic projection area where the first insulating layer 150 contacts the second patterned semiconductor layer 130A '. On the other hand, the front projection area of the first insulating layer 150 in contact with the second patterned semiconductor layer 130A 'is the same as the front projection area of the opening 142A.

Referring to FIG. 3G, a first bonding layer 160 is formed on the first insulating layer 150. The first bonding layer 160 covers the first insulating layer 150 and the opening 142A. Specifically, the first bonding layer 160 includes a flat portion 162 and a convex portion 164. The convex portion 164 is defined as a portion where the first bonding layer 160 overlaps the opening 142A. The flat portion 162 is defined as the first bonding layer 160 other than the convex portion 164. From another perspective, the flat portion 162 covers a portion where the first insulating layer 150 does not overlap the opening 142A, and the convex portion 164 covers a portion where the first insulating layer 150 overlaps the opening 142A. In this embodiment, since the opening 142A may be tapered, the convex portion 164 filled in the opening 142A may have a tapered shape corresponding to the opening 142A, but the present invention is not limited thereto. The thickness of the flat portion 162 of the first bonding layer 160 is, for example, 1 micrometer, but the invention is not limited thereto.

Please refer to FIG. 3H. Then, a carrier substrate 200 is provided. Next, a second bonding layer 220 is formed on the carrier substrate 200. The thickness of the second bonding layer 220 is, for example, 1 micrometer, but the invention is not limited thereto.

Please refer to FIG. 3I. Next, the second bonding layer 220 and the first bonding layer 160 are bonded. Before performing the above-mentioned bonding step, the growth substrate 100 is first inverted so that the first bonding layer 160 faces the second bonding layer 220 on the carrier substrate 200. Next, the first bonding layer 160 is pressed onto the second bonding layer 220. In this embodiment, before the bonding, the first bonding layer 160 and the second bonding layer 220 are two separate film layers. After joining, The first bonding layer 160 and the second bonding layer 220 may be fused into a film layer bonding structure 240, but not limited thereto.

Please refer to FIGS. 3I and 3J. Then, the growth substrate 100 is removed. The method for removing the growth substrate 100 includes separating the growth substrate 100 from the first patterned semiconductor layer 110A by laser lift off, but the present invention is not limited thereto.

Please refer to FIG. 3J and FIG. 3K. Next, the sacrificial layer 140A is removed. In this embodiment, after the sacrificial layer 140A is removed, the convex portion 164 and the portion 154 of the first insulating layer 150 contacting the convex portion 164 may form a joint portion 190. In detail, after the sacrificial layer 140A is removed, the convex portion 164 overlapping the opening 142A and the first insulating layer 150 in the opening 142A that contacts the second patterned semiconductor layer 130A and the convex portion 164 may be defined as the joint portion 190. From another perspective, the joint portion 190 includes a convex portion 164 and a portion 154 of the first insulating layer 150 that contacts the convex portion 164. Among them, the portion 154 of the first insulating layer 150 that contacts the convex portion 164 may abut and contact the second patterned semiconductor layer 130A. That is, the bonding portion 190 contacts the second patterned semiconductor layer 130A. In this embodiment, the joint portion 190 may be applied as an anchor that fixes the light emitting element 10A on the carrier substrate 200. The first insulating layer 150 and / or a portion 154 of the first insulating layer 150 can be used as a separation layer to reduce the probability of causing damage to the light-emitting element 10A in a subsequent large-scale transposition process. In this embodiment, the light emitting element 10A may be vertically stacked on the joint portion 190. Therefore, the light-emitting element 10A can obtain technical effects similar to those of the above embodiment.

In this embodiment, the orthographic projection area of the opening 142A on the carrier substrate 200 The ratio (for example, the first area A1) to the orthographic projection area (for example, the second area A2) of the second patterned semiconductor layer 130A on the carrier substrate 200 ranges from 1: 2 to 1: 625. That is, the orthographic projection area of the bonding portion 190 contacting the light emitting element 10A is smaller than the orthographic projection area of the light emitting element 10A. For example, the first area A1 is smaller than the second area A2. Under the above-mentioned setting, the bonding portion 190 can be fixed to the light emitting element 10A without affecting the configuration of the electrodes 170A, 180A or other elements on the light emitting element 10A. In addition, within the above-mentioned ratio range, the bonding portion 190 can further achieve a pulling force of less than 1 kilogram-force (kgw) with the light-emitting element 10A. Thereby, the connection reliability of the light emitting element 10A and the joint portion 190 can be improved.

In addition, in this embodiment, the first electrode 170A and the second electrode 180A are located between the first patterned semiconductor layer 110A and the carrier substrate 200. In other words, the light emitting element 10A is fixed to the joint portion 190 in a flip-chip structure. In this way, in the subsequent mass transfer process, it can be directly placed on the array substrate (not shown) through the pick-and-place technology, so as to be applied to the manufacture of the display panel. In this way, there is no need to use an additional wire connection process to further reduce production costs and save production time.

FIG. 4 is a schematic cross-sectional view of a light emitting device according to another embodiment of the present invention. Please refer to FIG. 3K and FIG. 4. The light-emitting element 10A ′ in this embodiment is similar to the light-emitting element 10A in FIG. 3K. The main difference is that the method of manufacturing the light-emitting element 10A ′ further includes: The plurality of metal pads 172A and 182A are electrically connected to the first electrode 170A and the second electrode 180A, respectively. In this embodiment, the metal pad 172A is disposed on the first patterned semiconductor layer 110A and covers the first electrode 170A. The metal pad 182A is disposed on the second patterned semiconductor layer 130A. And cover the second electrode 180A. The top surface of the metal pad 172A is aligned with the top surface of the metal pad 182A, but it is not limited thereto. The material of the metal pads 172A and 182A is metal, but the present invention is not limited thereto. In other embodiments, the metal pads 172A and 182A may also use other conductive materials, such as alloys, nitrides of metal materials, and metal materials. Oxide, oxynitride of metallic materials, graphite dilute, stacked layers of metallic materials, or stacked layers of other conductive materials. In this way, the light-emitting element 10A 'can further improve the electrical quality. In addition, the light-emitting element 10A 'can also obtain technical effects similar to those of the above embodiments.

In summary, in the method for manufacturing a light-emitting element according to an embodiment of the present invention, since the light-emitting element can be vertically stacked on the joint portion, the joint portion does not occupy the surface of the carrier substrate, so as to increase the number of light-emitting elements on the carrier substrate and density. When the number of light-emitting elements that can be fixed on the same carrier substrate is increased, in addition to reducing the manufacturing cost, it can also reduce the time for changing wafers during the transposition process and the number of alignments required to reduce the alignment correction. The error. Overall, you can reduce production costs and achieve time savings. In addition, the bonding portion is directly fabricated on the second patterned semiconductor layer. Therefore, when transferring the material forming the light-emitting element onto the carrier substrate, it is not necessary to align with the anchor point on the carrier substrate. Therefore, the present invention can reduce the number of times of alignment correction, and reduce errors generated by the alignment correction. In addition, since the opening can define the area where the bonding portion contacts the light emitting element, and the ratio of the orthographic projection area of the opening to the orthographic area of the light emitting element can make the bonding portion and the light emitting element have a pulling force of less than 1 kilogram force (kgw). Therefore, the reliability of the connection between the light-emitting element and the joint can be improved without affecting the subsequent mass transfer process. In addition, the carrier base The space saved on the board can make the arrangement of the light-emitting elements more marginal, so as to further save the production time of the display panel to which the light-emitting elements are applied, and further improve the display quality.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims (10)

A method for manufacturing a light-emitting device includes: sequentially forming a first semiconductor layer, a light-emitting layer, and a second semiconductor layer on a growth substrate; forming a sacrificial layer on the second semiconductor layer; and forming on the sacrificial layer An opening to expose a part of the second semiconductor layer, wherein the side wall of the opening and the second semiconductor layer form an inclined angle, and the angle range of the inclined angle is between 45° and 90°; a first insulating layer is formed On the sacrificial layer and contacting the second semiconductor layer through the opening; forming a first bonding layer on the first insulating layer, the first bonding layer has a flat portion and a convex portion, wherein the flat Covering the first insulating layer, and the convex portion overlapping the opening; providing a carrier substrate; forming a second bonding layer on the carrier substrate; joining the second bonding layer and the first bonding layer; removing Part of the first semiconductor layer and part of the second semiconductor layer to form a first patterned semiconductor layer and a second patterned semiconductor layer respectively; forming a second insulating layer to cover the first patterned semiconductor layer and the first Two patterned semiconductor layers, the second insulating layer has a first contact hole and a second contact hole; forming a first electrode and electrically connecting the first patterned semiconductor layer through the first contact hole; forming a first The two electrodes are electrically connected to the second patterned semiconductor layer through the second contact hole; and the sacrificial layer is removed so that the convex portion and the portion of the first insulating layer contacting the convex portion form a bonding portion, The bonding portion contacts the second patterned semiconductor layer. The method for manufacturing a light-emitting element as described in item 1 of the patent application range, wherein the growth substrate is removed before the step of removing part of the first semiconductor layer and part of the second semiconductor layer. The method for manufacturing a light-emitting element as described in item 1 of the patent application range, wherein the second patterned semiconductor layer is located between the first electrode and the second electrode and the carrier substrate. The method for manufacturing a light-emitting element as described in item 1 of the patent application range, wherein the first patterned semiconductor layer is an N-type semiconductor layer, and the second patterned semiconductor layer is a P-type semiconductor layer. The method for manufacturing a light-emitting device as described in item 1 of the patent application range, wherein in the direction perpendicular to the carrier substrate, the orthographic projection area of the opening on the carrier substrate and the second patterned semiconductor layer on the front of the carrier substrate The ratio of the projected area ranges from 1:2 to 1:625. The method for manufacturing a light-emitting element as described in item 1 of the patent application scope further includes, before the step of removing the sacrificial layer, forming a plurality of metal pads to electrically connect the first electrode and the second electrode, respectively. A manufacturing method of a light-emitting device, comprising: sequentially forming a first semiconductor layer, a light-emitting layer and a second semiconductor layer on a growth substrate; removing part of the first semiconductor layer and part of the second semiconductor layer to respectively Forming a first patterned semiconductor layer and a second patterned semiconductor layer; forming a second insulating layer covering the first patterned semiconductor layer and the second patterned semiconductor layer, the second insulating layer having a first contact A hole and a second contact hole; forming a first electrode and electrically connecting the first patterned semiconductor layer through the first contact hole; forming a second electrode and electrically connecting the second pattern through the second contact hole Forming a sacrificial layer on the growth substrate to cover the second patterned semiconductor layer; forming an opening in the sacrificial layer to expose a portion of the second patterned semiconductor layer, wherein the side wall of the opening and The second patterned semiconductor layer forms an inclination angle, and the angle range of the inclination angle is between 45° and 90°; forming a first insulating layer on the sacrificial layer and contacting the second patterning through the opening A semiconductor layer; forming a first bonding layer on the first insulating layer, the first bonding layer has a flat portion and a convex portion, wherein the flat portion covers the first insulating layer, and the convex portion overlaps the Opening; providing a carrier substrate; forming a second bonding layer on the carrier substrate; joining the second bonding layer and the first bonding layer; removing the growth substrate; and removing the sacrificial layer, so that The convex portion and a portion of the first insulating layer contacting the convex portion form a bonding portion, and the bonding portion contacts the second patterned semiconductor layer. The method for manufacturing a light-emitting element as described in item 7 of the patent application range, wherein the first electrode and the second electrode are located between the first patterned semiconductor layer and the carrier substrate. The method for manufacturing a light-emitting element as described in item 7 of the patent application range, wherein the first patterned semiconductor layer is an N-type semiconductor layer, and the second patterned semiconductor layer is a P-type semiconductor layer. The method for manufacturing a light-emitting element as described in item 7 of the patent application scope further includes, before the step of forming the sacrificial layer, forming a plurality of metal pads to electrically connect the first electrode and the second electrode, respectively.