CN113725333A - Red light-emitting diode chip and preparation method thereof - Google Patents

Red light-emitting diode chip and preparation method thereof Download PDF

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Publication number
CN113725333A
CN113725333A CN202110820728.9A CN202110820728A CN113725333A CN 113725333 A CN113725333 A CN 113725333A CN 202110820728 A CN202110820728 A CN 202110820728A CN 113725333 A CN113725333 A CN 113725333A
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layer
type
groove
substrate
type electrode
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CN113725333B (en
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兰叶
王江波
吴志浩
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HC Semitek Zhejiang Co Ltd
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HC Semitek Zhejiang Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating

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Abstract

The disclosure provides a red light emitting diode chip and a preparation method thereof. The red light emitting diode chip includes: the device comprises a substrate, a p-type layer, a multi-quantum well layer, an n-type layer, a passivation layer, an n-type electrode and a p-type electrode; the p-type layer, the multi-quantum well layer and the n-type layer are sequentially laminated on the substrate, the n-type electrode is positioned on the surface of the n-type layer, the middle part of the n-type layer is provided with a first groove exposing the p-type layer, and the p-type electrode is positioned on the surface of the p-type layer and positioned on the bottom surface of the first groove; the passivation layer at least covers the surfaces of the n-type layer, the first groove and the p-type layer; the surface of the passivation layer, which is far away from the substrate, is provided with a second groove, and the orthographic projection of the bottom surface of the second groove on the substrate is not overlapped with the orthographic projection of the multiple quantum well layer on the substrate. The embodiment of the disclosure can effectively avoid the problem that the epitaxial structure is damaged by the impact of the thimble when the red light emitting diodes are sorted, thereby improving the yield and reducing the cost.

Description

Red light-emitting diode chip and preparation method thereof
Technical Field
The disclosure relates to the technical field of photoelectron manufacturing, in particular to a red light emitting diode chip and a preparation method thereof.
Background
The Light Emitting Diode (LED) is a new product with great influence in the photoelectronic industry, has the characteristics of small volume, long service life, rich and colorful colors, low energy consumption and the like, and is widely applied to the fields of illumination, display screens, signal lamps, backlight sources, toys and the like. The core structure of the LED is a light emitting diode chip, and the manufacturing of the light emitting diode chip has great influence on the photoelectric characteristics of the LED.
The light emitting diode chip generally includes a substrate, a p-type layer, a multiple quantum well layer, an n-type layer, and a p-type electrode and an n-type electrode connected to the p-type layer and the n-type layer, respectively, which are sequentially stacked. In the related art, before the LEDs are mounted on application products, sorting devices are required to be used to sort the LEDs into corresponding package structures, and the ejector pins of the sorting devices are directly inserted into the front surfaces of the LEDs during sorting, so that the ejector pins have a large impact force.
Particularly, in the red light emitting diode, because the epitaxial material of the red light emitting diode is AlGaInP, which has relatively high brittleness and low hardness, the epitaxial structure is easily cracked by the thimble after being impacted by the thimble, and if the multiple quantum well layer in the epitaxial structure is damaged, the current leakage problem is generated, which affects the use of the light emitting diode chip.
Disclosure of Invention
The embodiment of the disclosure provides a red light emitting diode chip and a preparation method thereof, which can effectively avoid the problem that an epitaxial structure is damaged by being impacted by a thimble when red light emitting diodes are sorted, improve the yield of the red light emitting diode chip and reduce the cost. The technical scheme is as follows:
in one aspect, an embodiment of the present disclosure provides a red light emitting diode chip, where the red light emitting diode chip includes: the device comprises a substrate, a p-type layer, a multi-quantum well layer, an n-type layer, a passivation layer, an n-type electrode and a p-type electrode; the p-type layer, the multi-quantum well layer and the n-type layer are sequentially laminated on the substrate, the n-type electrode is positioned on the surface of the n-type layer, a first groove exposing the p-type layer is formed in the middle of the n-type layer, and the p-type electrode is positioned on the surface of the p-type layer and positioned on the bottom surface of the first groove; the passivation layer at least covers the surfaces of the n-type layer, the first groove and the p-type layer; the surface, far away from the substrate, of the passivation layer is provided with a second groove, and the orthographic projection of the bottom surface of the second groove on the substrate is not overlapped with the orthographic projection of the multiple quantum well layer on the substrate.
Optionally, the side wall of the second groove is an inclined surface, and an included angle between the side wall of the second groove and the bottom surface of the second groove is an obtuse angle.
Optionally, the bottom surface of the second groove is circular, and the side wall of the second groove is a conical surface.
Optionally, the groove depth of the second groove is 6000 angstroms to 10000 angstroms.
Optionally, an included angle between the side wall of the second groove and the bottom surface of the second groove is 130 ° to 140 °.
Optionally, the p-type electrode includes an electrode portion and a connection portion connected to each other, an orthogonal projection of the electrode portion on the substrate is located within an orthogonal projection of the second groove on the substrate, and an orthogonal projection of the connection portion on the substrate is located outside the orthogonal projection of the second groove on the substrate.
Optionally, the passivation layer includes a silicon oxide layer, a DBR layer, and a silicon nitride layer stacked in sequence, the silicon oxide layer is connected to the n-type layer, the n-type electrode, the first groove, the p-type layer, and the p-type electrode, and the second groove is located in the silicon nitride layer.
Optionally, the silicon oxide layer has a thickness of 4000 to 6000 angstroms, the silicon nitride layer has a thickness of 0.5 to 2 μm, and the DBR layer includes a plurality of TiO layers alternately stacked periodically2Layer and SiO2And (3) a layer.
Optionally, the light emitting diode chip further includes a first pad block and a second pad block, and the first pad block and the second pad block are both located on the surface of the passivation layer away from the substrate; the passivation layer is provided with a first through hole exposing the n-type electrode and a second through hole exposing the p-type electrode, the first welding spot block covers the first through hole and is connected with the n-type electrode, and the second welding spot block covers the second through hole and is connected with the p-type electrode.
On the other hand, the embodiment of the present disclosure further provides a method for manufacturing a red light emitting diode chip, where the method includes:
providing a substrate;
sequentially growing an n-type layer, a multi-quantum well layer and a p-type layer on the substrate;
bonding a substrate on the p-type layer, and removing the substrate;
etching the middle part of the n-type layer to expose a first groove of the p-type layer;
forming an n-type electrode on the surface of the n-type layer, and forming a p-type electrode on the bottom surface of the first groove;
manufacturing passivation layers on the surfaces of the n-type layer, the n-type electrode, the first groove, the p-type layer and the p-type electrode;
and forming a second groove on the surface of the passivation layer far away from the substrate, wherein the orthographic projection of the bottom surface of the second groove on the substrate is not overlapped with the orthographic projection of the multiple quantum well layer on the substrate.
The beneficial effects brought by the technical scheme provided by the embodiment of the disclosure at least comprise:
in the red light emitting diode provided by the embodiment of the disclosure, a p-type layer, a multiple quantum well layer and an n-type layer are sequentially laminated on a substrate, wherein the middle part of the n-type layer is provided with a first groove exposing the p-type layer, that is, the n-type layer and the multiple quantum well layer in the middle region of the n-type layer are removed through the first groove; meanwhile, an n-type electrode is arranged on the surface of the n-type layer, a p-type electrode is arranged in the first groove, and the p-type electrode is arranged in the first groove, so that the overall thickness of the epitaxial structure is thinned, and the impact resistance of the epitaxy is improved after thinning; and the passivation layer covers the surfaces of the n-type layer, the n-type electrode, the first groove, the p-type layer and the p-type electrode, the surface of the passivation layer is provided with a second groove which does not penetrate through the passivation layer, the orthographic projection of the bottom surface of the second groove on the substrate is not overlapped with the orthographic projection of the multiple quantum well layer on the substrate, and the second groove is opposite to the first groove. When the sorting device sorts the red light emitting diodes, the second groove is used as an ejector pin impact area of the sorting device, the second groove and the first groove are oppositely arranged, and the position of the first groove is free of the multi-quantum well layer, so that the applied impact force of the ejector pin can be effectively guided to the non-quantum well area in the epitaxial structure, the situation that the ejector pin is mistakenly jacked to the multi-quantum well layer is avoided, the problem that the epitaxial structure is damaged due to the impact of the ejector pin when the red light emitting diodes are sorted is effectively avoided, the yield of the red light emitting diode chips is improved, and the cost is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a red light emitting diode chip provided in an embodiment of the present disclosure;
fig. 2 is a top view of a red light emitting diode chip provided in an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a p-type electrode provided in an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a passivation layer provided in an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of an epitaxial structure of a red light emitting diode provided in an embodiment of the present disclosure;
fig. 6 is a flowchart of a method for manufacturing a red light emitting diode chip according to an embodiment of the present disclosure;
fig. 7 is a schematic view illustrating a manufacturing process of a red light emitting diode chip according to an embodiment of the present disclosure;
fig. 8 is a schematic view illustrating a manufacturing process of a red light emitting diode chip according to an embodiment of the present disclosure;
fig. 9 is a schematic view illustrating a manufacturing process of a red light emitting diode chip according to an embodiment of the present disclosure;
fig. 10 is a schematic view illustrating a manufacturing process of a red light emitting diode chip according to an embodiment of the present disclosure;
fig. 11 is a schematic view of a manufacturing process of a red light emitting diode chip according to an embodiment of the present disclosure.
The various symbols in the figure are illustrated as follows:
101-substrate, 102-GaAs substrate;
a 20-p type layer, a 201-p type AlInP limiting layer, a 202-p type GaP window layer;
30-MQW layer;
a 40-n type layer, a 401-n type AlGaInP extension layer, and a 402-n type AlInP limiting layer;
50-passivation layer, 501-silicon oxide layer, 502-DBR layer, 503-silicon nitride layer;
61-p-type electrode, 611-electrode section, 612-connection section, 62-n-type electrode;
71-first solder bump, 72-second solder bump;
81-GaInP cut-off layer, 82-transparent bonding layer;
a-a first groove, B-a second groove, C-a first via hole, D-a second via hole and E-a protective layer.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," "third," and similar terms in the description and claims of the present disclosure are not intended to indicate any order, quantity, or importance, but rather are used to distinguish one element from another. Also, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprise" or "comprises", and the like, means that the element or item listed before "comprises" or "comprising" covers the element or item listed after "comprising" or "comprises" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", "top", "bottom", and the like are used merely to indicate relative positional relationships, which may also change accordingly when the absolute position of the object being described changes.
Fig. 1 is a schematic structural diagram of a red light emitting diode chip according to an embodiment of the present disclosure. As shown in fig. 1, the red light emitting diode chip includes: a substrate 101, a p-type layer 20, a multiple quantum well layer 30, an n-type layer 40, a passivation layer 50, an n-type electrode 62, and a p-type electrode 61.
As shown in fig. 1, a p-type layer 20, a multiple quantum well layer 30, and an n-type layer 40 are sequentially stacked on a substrate 101, an n-type electrode 62 is located on the surface of the n-type layer 40, a first groove a exposing the p-type layer 20 is formed in the middle of the n-type layer 40, and a p-type electrode 61 is located on the surface of the p-type layer 20 and on the bottom surface of the first groove a.
As shown in fig. 1, the passivation layer 50 covers at least the n-type layer 40, the surface of the first recess A, p type layer 20.
As shown in fig. 1, the surface of the passivation layer 50 away from the substrate 101 has a second groove B, and the bottom surface of the second groove B does not overlap with the orthographic projection of the multiple quantum well layer 30 on the substrate 101 in the orthographic projection of the substrate 101.
In the red light emitting diode provided by the embodiment of the present disclosure, a p-type layer 20, a multiple quantum well layer 30, and an n-type layer 40 are sequentially stacked on a substrate 101, wherein a first groove a exposing the p-type layer 20 is formed in the middle of the n-type layer 40, that is, the n-type layer 40 and the multiple quantum well layer 30 in the middle region of the n-type layer 40 are removed through the first groove a; meanwhile, the n-type electrode 62 is arranged on the surface of the n-type layer, the p-type electrode 61 is arranged in the first groove A, and the p-type electrode 61 is arranged in the first groove A, so that the overall thickness of the epitaxial structure is reduced, and the impact resistance of the epitaxy is improved after the thickness is reduced; the passivation layer 50 covers the surfaces of the n-type layer 40, the n-type electrode 62, the first groove A, p, the type layer 20, and the p-type electrode 61, the surface of the passivation layer 50 has a second groove B that does not penetrate through the passivation layer 50, the orthographic projection of the bottom surface of the second groove B on the substrate 101 does not overlap with the orthographic projection of the multiple quantum well layer 30 on the substrate 101, and the second groove B is opposite to the first groove a. When the sorting device sorts the red light emitting diodes, the second groove B is used as an ejector pin impact area of the sorting device, the second groove B and the first groove A are oppositely arranged, and the position of the first groove A is not provided with the multi-quantum well layer 30, so that the impact force applied by the ejector pin can be effectively guided to the non-quantum well area in the epitaxial structure, the situation that the ejector pin is mistakenly ejected to the multi-quantum well layer 30 is avoided, the problem that the epitaxial structure is damaged due to the impact of the ejector pin when the red light emitting diodes are sorted is effectively avoided, the yield of the red light emitting diode chips is improved, and the cost is reduced.
Optionally, the substrate 101 is a sapphire substrate. The sapphire substrate has a relatively high transmittance, i.e., the substrate 101 is a transparent substrate. And the sapphire material is hard, the chemical property is stable, and the red light-emitting diode has good light-emitting effect and stability.
Optionally, as shown in fig. 1, the side wall of the second groove B is an inclined surface, and an included angle between the side wall of the second groove B and the bottom surface of the second groove B is an obtuse angle.
Thus, even if the thimble is pushed against the side wall of the second groove B, the thimble can slide to the bottom surface of the second groove B under the guidance of the side wall of the second groove B. Therefore, the impact force applied by the ejector pin is guided to the non-quantum well region in the epitaxial structure, the phenomenon that the ejector pin is mistakenly ejected to the multi-quantum well layer 30 is avoided, the problem that the epitaxial structure is damaged due to impact of the ejector pin when the red light emitting diodes are sorted is effectively avoided, the yield of red light emitting diode chips is improved, and the cost is reduced.
Fig. 2 is a top view of a red light emitting diode chip according to an embodiment of the present disclosure. As shown in fig. 1 and 2, the bottom surface of the second groove B is circular, and the side wall of the second groove B is a conical surface. The second groove B is set to be a conical groove, so that when the thimble strikes the conical groove, the thimble can abut against the side wall of the second groove B from any direction and slide to the bottom surface of the second groove B along the side wall.
Alternatively, as shown in fig. 1, the groove depth H of the second groove B is 6000 to 10000 angstroms. Setting the groove depth H to be within this depth range facilitates the confinement of the thimble within the second groove B to prevent the thimble from slipping out of the second groove B.
By way of example, in embodiments of the present disclosure, the trench depth H is 7000 angstroms.
Alternatively, as shown in fig. 1, the side wall of the second groove B may form an angle α of 130 ° to 140 ° with the bottom surface of the second groove B. The included angle alpha is set within the angle range, so that the ejector pin can conveniently slide to the bottom surface of the second groove B along the side wall of the second groove B.
By way of example, in the disclosed embodiment, the included angle α is 135 °.
As shown in fig. 1 and 2, the led chip further includes a first pad block 71 and a second pad block 72, where the first pad block 71 and the second pad block 72 are both located on a surface of the passivation layer 50 away from the substrate 101; the passivation layer 50 is provided with a first via hole C exposing the n-type electrode 62 and a second via hole D exposing the p-type electrode 61, the first pad block 71 is covered on the first via hole C and connected with the n-type electrode 62, and the second pad block 72 is covered on the second via hole D and connected with the p-type electrode 61.
The electrical connection of the n-type electrode 62 is facilitated by providing a first pad block 71 on the surface of the passivation layer 50, which is connected to the n-type electrode 62; a second pad 72 connected to the p-type electrode 61 is provided on the surface of the passivation layer 50 to facilitate electrical connection of the p-type electrode 61.
As shown in fig. 2, the first pad block 71 and the second pad block 72 are rectangular blocks, which increase the area and facilitate electrical conduction. And on the surface of the passivation layer 50, the second groove B is located between the first pad block 71 and the second pad block 72, and both the first pad block 71 and the second pad block 72 are spaced apart from the second groove B.
Fig. 3 is a schematic structural diagram of a p-type electrode provided in an embodiment of the present disclosure. As shown in fig. 3, the p-type electrode 61 includes an electrode portion 611 and a connection portion 612 connected.
As shown in fig. 1, the orthographic projection of the electrode portion 611 on the substrate 101 is located inside the orthographic projection of the second groove B on the substrate 101, and the orthographic projection of the connecting portion 612 on the substrate 101 is located outside the orthographic projection of the second groove B on the substrate 101.
Since the p-type electrode 61 is made of a metal material and can bear a large impact force by disposing the p-type electrode 61 in the first groove a and facing the p-type electrode 61 to the second groove B, the electrode portion 611 of the p-type electrode 61 is disposed below the second groove B, and the impact resistance of the red light emitting diode chip can be effectively improved.
Meanwhile, the connecting portion 612 connected to the electrode portion 611 in the n-type electrode 62 extends the n-type electrode 62 to the position of the second via D, so that the n-type electrode 62 can extend to the surface of the passivation layer 50 away from the substrate 101 through the second via D, and the n-type electrode 62 is electrically connected.
Illustratively, as shown in fig. 3, the area of the connection portion 612 is smaller than that of the electrode portion 611, and since the connection portion 612 is used for conducting electricity, the size of the connection portion 612 is designed to be smaller, which facilitates reducing the manufacturing cost of the n-type electrode 62.
As an example, the connection portion 612 may have a bar shape, one end of the connection portion 612 is connected to the electrode portion 611, and the other end of the connection portion 612 extends to below the second via hole D.
Fig. 4 is a schematic structural diagram of a passivation layer provided in an embodiment of the present disclosure. As shown in fig. 4, the passivation layer 50 includes a silicon oxide layer 501, a DBR layer 502, and a silicon nitride layer 503, which are sequentially stacked, the silicon oxide layer 501 is connected to the n-type layer 40, the n-type electrode 62, the first groove A, p, the type layer 20, and the p-type electrode 61, and the second groove B is located in the silicon nitride layer 503.
In the embodiment of the present disclosure, the second groove B is located in the silicon nitride layer 503, and since the toughness of the silicon nitride is higher, the impact of the thimble can be borne, so as to prevent the passivation layer 50 from being easily damaged, thereby improving the yield of the led chips during the sorting process.
Alternatively, the silicon nitride layer 503 has a thickness of 0.5 μm to 2 μm. The thickness of the silicon nitride layer 503 is set within the range, so that the requirement of the opening size of the second groove B can be met, and the problem that the preparation cost is increased due to the fact that the thickness of the silicon nitride layer 503 is too large is also avoided.
As an example, in the embodiments of the present disclosure, the thickness of the silicon nitride layer 503 is 1 μm.
Optionally, the silicon oxide layer 501 has a thickness of 4000 to 6000 angstroms.
As an example, in the disclosed embodiment, the thickness of the silicon oxide layer 501 is 5000 angstroms.
Optionally, the DBR layer 502 includes a plurality of periodically alternately stacked TiO' s2Layer and SiO2And (3) a layer. And the number of periods of the DBR layer 502 may be between 20 and 50. For example, the number of periods of the DBR layer 502 is 32.
Wherein, TiO in the DBR layer 5022The thickness of the layer may be 500 to 900 angstroms, SiO2The thickness of the layer may be 800 angstroms to 1200 angstroms.
As an example, in the embodiments of the present disclosure, TiO2The thickness of the layer may be 700 angstroms, SiO2The thickness of the layer may be 1050 angstroms.
Optionally, the led chip further includes a transparent adhesive layer 82, the transparent adhesive layer 82 is located between the substrate 101 and the p-type layer 20, and the transparent adhesive layer 82 is made of a material including: SiO 22、ZnO、SiN、ITO、In2O3、SnO2、TiO2、ZrO2And a polyimide.
The substrate 101 and the p-type layer 20 are connected together in a bonding manner, and since the light-emitting surface of the red light emitting diode chip in the embodiment of the present disclosure is the surface where the substrate 101 is located, a transparent bonding layer made of a material with relatively high light transmittance is provided between the substrate 101 and the p-type layer 20, so that the red light emitting diode chip has a good light-emitting effect.
Illustratively, in the disclosed embodiment, the transparent bonding layer 82 may be SiO2And (5) film layer.
Fig. 5 is a schematic structural diagram of an epitaxial structure of a red light emitting diode according to an embodiment of the present disclosure. As shown in fig. 5, the n-type layer 40 includes an n-type AlGaInP extension layer 401 and an n-type AlInP confinement layer 402 stacked in this order on a substrate.
The n-type AlGaInP extension layer 401 has a high conductivity, and allows current to be spread as uniformly as possible throughout the n-type layer 40, thereby allowing each region of the multiple quantum well to emit light.
As an example, in the embodiment of the present disclosure, the thickness of the n-type AlGaInP extension layer 401 is 1 μm to 3 μm; the thickness of the n-type AlInP confinement layer 402 is 0.2 μm to 0.5 μm.
Alternatively, the multiple quantum well layer 30 includes 3 to 8 AlxGa1-xInP quantum well layer and AlyGa1-yAnd the InP quantum barrier layer, wherein x is more than 0 and less than y is less than 1. That is, the multiple quantum well layer 30 includes Al of 3 to 8 periods alternately stackedxGa1-xInP quantum well layer and AlyGa1-yAnd an InP quantum barrier layer.
As an example, in the embodiment of the present disclosure, the multiple quantum well layer 30 includes 5 periods of Al alternately stackedxGa1-xInP quantum well layer and AlyGa1-yAnd an InP quantum barrier layer.
Alternatively, the thickness of the multiple quantum well layer 30 may be 150nm to 200 nm.
In the embodiment of the present disclosure, as shown in fig. 4, the p-type layer 20 includes a p-type AlInP confinement layer 201 and a p-type GaP window layer 202 sequentially stacked on the multiple quantum well layer 30.
Illustratively, the thickness of the p-type AlInP confinement layer 201 may be 200nm to 300 nm; the thickness of the p-type GaP window layer 202 may be 0.2 μm to 0.5 μm.
Fig. 6 is a flowchart of a method for manufacturing a red light emitting diode chip according to an embodiment of the present disclosure. The method is used for preparing the red light-emitting diode chip shown in figure 1. As shown in fig. 6, the preparation method includes:
s11: a substrate is provided.
S12: an n-type layer 40, a multiple quantum well layer 30, and a p-type layer 20 are sequentially grown on the substrate.
S13: a base plate 101 is bonded on the p-type layer 20, and the substrate is removed.
S14: a first recess a is etched in the middle of the n-type layer 40 exposing the p-type layer 20.
S15: an n-type electrode 62 is formed on the surface of the n-type layer 40, and a p-type electrode 61 is formed on the bottom surface of the first groove a.
S16: and a passivation layer 50 is manufactured on the surfaces of the n-type layer 40, the n-type electrode 62, the first groove A, p, the type layer 20 and the p-type electrode 61.
The passivation layer 50 is provided with a first via hole C and a second via hole D at a position thereon, the first via hole C and the second via hole D are distributed at intervals, the n-type electrode 62 extends to the surface of the passivation layer 50 away from the substrate 101 through the first via hole C, and the p-type electrode 61 extends to the surface of the passivation layer 50 away from the substrate 101 through the second via hole D.
S17: the surface of the passivation layer 50 remote from the substrate 101 forms a second groove B.
The orthographic projection of the bottom surface of the second groove B on the substrate 101 does not overlap the orthographic projection of the multiple quantum well layer 30 on the substrate 101.
In the red light emitting diode provided by the embodiment of the present disclosure, a p-type layer 20, a multiple quantum well layer 30, and an n-type layer 40 are sequentially stacked on a substrate 101, wherein a first groove a exposing the p-type layer 20 is formed in the middle of the n-type layer 40, that is, the n-type layer 40 and the multiple quantum well layer 30 in the middle region of the n-type layer 40 are removed through the first groove a; meanwhile, the n-type electrode 62 is arranged on the surface of the n-type layer, the p-type electrode 61 is arranged in the first groove A, and the p-type electrode 61 is arranged in the first groove A, so that the overall thickness of the epitaxial structure is reduced, and the impact resistance of the epitaxy is improved after the thickness is reduced; the passivation layer 50 covers the surfaces of the n-type layer 40, the n-type electrode 62, the first groove A, p, the type layer 20, and the p-type electrode 61, the surface of the passivation layer 50 has a second groove B that does not penetrate through the passivation layer 50, the orthographic projection of the bottom surface of the second groove B on the substrate 101 does not overlap with the orthographic projection of the multiple quantum well layer 30 on the substrate 101, and the second groove B is opposite to the first groove a. When the sorting device sorts the red light emitting diodes, the second groove B is used as an ejector pin impact area of the sorting device, the second groove B and the first groove A are oppositely arranged, and the position of the first groove A is not provided with the multi-quantum well layer 30, so that the impact force applied by the ejector pin can be effectively guided to the non-quantum well area in the epitaxial structure, the situation that the ejector pin is mistakenly ejected to the multi-quantum well layer 30 is avoided, the problem that the epitaxial structure is damaged due to the impact of the ejector pin when the red light emitting diodes are sorted is effectively avoided, the yield of the red light emitting diode chips is improved, and the cost is reduced.
Alternatively, the substrate may be a GaAs substrate 102, which may be a flat substrate or a patterned substrate.
In step S11, the GaAs substrate 102 may be pretreated, the GaAs substrate 102 is placed in an MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber, and the GaAs substrate 102 is baked for 12 minutes to 18 minutes. As an example, in the embodiment of the present disclosure, the GaAs substrate 102 is subjected to the baking process for 15 minutes.
Specifically, the baking temperature can be 1000 ℃ to 1200 ℃, and the pressure in the MOCVD reaction chamber during baking can be 100mbar to 200 mbar.
Step S12 may be preceded by: a GaInP stop layer 81 is epitaxially grown on the substrate.
Fig. 7 is a schematic view of a manufacturing process of a red light emitting diode chip according to an embodiment of the present disclosure. As shown in fig. 7, a GaInP cutoff layer 81 is formed on a GaAs substrate 102 by the MOCVD technique.
Alternatively, the thickness of the GaInP cutoff layer 81 may be 1000A to 4000A. The thickness of the GaAs substrate 102 is 350 μm.
In step S12, as shown in fig. 7, the n-type layer 40 grown on the GaInP stop layer 81 includes an n-type AlGaInP extension layer 401 and an n-type AlInP confinement layer 402.
Illustratively, the structure of the n-type AlGaInP extension layer 401 is n-type AlyGaInP, wherein, 0.5<y<0.7. The thickness of the n-type AlGaInP extension layer 401 is 1 μm to 3 μm.
As shown in fig. 7, a multiple quantum well layer 30 is grown on the n-type AlInP confinement layer 402.
In practice, the MQW layer 30 may include a plurality of layers of Al alternately stackedxGa1-xInP quantum well layer and multilayer AlyGa1-yAnd the InP quantum barrier layer, wherein x is more than 0 and less than y is less than 1.
Alternatively, AlxGa1-xInP quantum well layer and AlyGa1-yThe number of periods in which the InP quantum barrier layers are alternately stacked may be 3 to 8. Exemplarily, in the embodiments of the present disclosure, AlxGa1-xInP quantum well layer and AlyGa1-yThe number of cycles of alternately stacking the InP quantum barrier layers is 5.
Alternatively, AlxGa1-xThe thickness of the InP quantum well layer may be 2nm to 4 nm. Al (Al)yGa1-yThe thickness of the InP quantum barrier layer may be 9 to 14 nm.
Exemplarily, in the embodiments of the present disclosure, AlxGa1-xThe thickness of the InP quantum well layer is 3 nm. Al (Al)yGa1-yThe thickness of the InP quantum barrier layer is 11 nm.
As shown in fig. 7, a p-type layer 20 is grown on the multiple quantum well layer 30.
As shown in fig. 7, the p-type layer 20 includes a p-type AlInP confinement layer 201 and a p-type GaP window layer 202 sequentially grown on the multiple quantum well layer 30.
Illustratively, the p-type AlInP confinement layers 201 are each 200nm to 300nm thick.
Illustratively, a p-type GaP window layer 202. The thickness of the p-type GaP window layer 202 is 2 μm to 10 μm. For example, the thickness of the p-type GaP window layer 202 is 6 μm.
When the p-type GaP window layer 202 is formed, the p-type GaP window layer 202 needs to be roughened, and the roughening method uses a temperature adjusting mode in the epitaxial growth process, so that the obtained roughening size is small, and the roughening density is high.
In step S13, as shown in FIG. 8, silicon oxide was deposited on the surface of the p-type GaP window layer 202 to a thickness of 3 μm, the ratio of laughing gas and ammonia gas was 20:1, and the deposition temperature was selected to be 200 degrees to prepare the transparent adhesive layer 82.
Then, a substrate 101, for example, a sapphire substrate is selected, and the substrate 101 is bonded on the transparent adhesive layer 82, and at the same time, the GaAs substrate 102 and the GaInP cutoff layer 81 are removed by a wet process.
As shown in fig. 7, a substrate 101 is attached to p-type layer 20. I.e. the base plate 101 and the GaAs substrate 102 are located on opposite surfaces of the epitaxial structure.
In the above implementation, the GaAs substrate 102 and the GaInP cutoff layer 81 are removed by a wet process by providing the base plate 101 on a surface opposite to the GaAs substrate 102 in the epitaxial structure so as to have the base plate 101 as a base plate.
In step S14, a first groove a exposing the p-type layer 20 is etched in the middle of the n-type layer 40.
As shown in fig. 9, the method may specifically include: and etching the middle area of the n-type layer 40 by adopting a dry etching mode, wherein the etching area is positioned at the center of the red light-emitting diode chip and is etched until the p-type layer 20 is exposed.
In step S15, as shown in fig. 9, forming the n-type electrode 62 and the p-type electrode 61 may include: the p-type electrode 61 and the n-type electrode 62 are respectively processed by negative photoresist stripping.
As shown in fig. 10, the n-type electrode 62 is located on the surface of the n-type layer 40, and the p-type electrode 61 is located on the bottom surface of the first groove a.
The p-type electrode 61 is evaporated by using gold beryllium as a base material, the evaporation power needs to be ensured when the gold beryllium alloy is evaporated, and the evaporation time is prevented from exceeding 5 seconds so as to prevent the deviation of alloy components. The n-type electrode 62 adopts evaporation plating using gold germanium as a base material, and the evaporation power needs to be ensured when the gold germanium alloy is evaporated, so that the evaporation time is prevented from exceeding 5 seconds, and the deviation of alloy components is prevented.
Alternatively, the preparation of the p-type electrode 61 and the n-type electrode 62 may further include: and manufacturing a protective structure of the multi-quantum well layer 30, namely manufacturing a protective negative photoresist photoetching pattern and obtaining etching of a vertical surface, then forming etching of an inclined surface by using positive photoresist, and finally obtaining adhesion of an aluminum layer by using an inclined wafer placed on the vertical surface, wherein the depth of the protective structure of the multi-quantum well layer 30 is correspondingly adjusted according to the final thinning thickness, and the adjustment aims at blocking laser photons to the maximum extent.
In step S16, as shown in fig. 11, the passivation layer 50 includes a silicon oxide layer, a DBR layer, and a silicon nitride layer stacked in this order, the silicon oxide layer being connected to the n-type layer 40, the n-type electrode 62, the first groove A, p-type layer 20, and the p-type electrode 61, and the second groove B being located in the silicon nitride layer 503.
In the embodiment of the present disclosure, the second groove B is located in the silicon nitride layer 503, and since the toughness of the silicon nitride is higher, the impact of the thimble can be borne, so as to prevent the passivation layer 50 from being easily damaged, thereby improving the yield of the led chips during the sorting process.
Alternatively, the silicon nitride layer 503 has a thickness of 0.5 μm to 2 μm. The thickness of the silicon nitride layer 503 is set within the range, so that the requirement of the opening size of the second groove B can be met, and the problem that the preparation cost is increased due to the fact that the thickness of the silicon nitride layer 503 is too large is also avoided.
As an example, in the embodiments of the present disclosure, the thickness of the silicon nitride layer 503 is 1 μm.
Optionally, the silicon oxide layer 501 has a thickness of 4000 to 6000 angstroms.
As an example, in the disclosed embodiment, the thickness of the silicon oxide layer 501 is 5000 angstroms.
Optionally, the DBR layer 502 includes a plurality of periodically alternately stacked TiO' s2Layer and SiO2And (3) a layer. And the number of periods of the DBR layer 502 may be between 20 and 50. For example, the number of periods of the DBR layer 502 is 32.
Wherein, TiO in the DBR layer 5022The thickness of the layer may be 500 to 900 angstroms, SiO2The thickness of the layer may be 800 angstroms to 1200 angstroms.
As an example, in the embodiments of the present disclosure, TiO2The thickness of the layer may be 700 angstroms, SiO2The thickness of the layer may be 1050 angstroms.
In step S17, as shown in fig. 1, forming the second groove B may include: forming a photoresist opening with the diameter of about 50 microns in the central area of the red light-emitting diode chip, baking the photoresist at 150 degrees to form a slope with a step of about 45 degrees, and etching to the etching depth of about 7000 angstroms to obtain a second groove B with an inclined side wall.
In the embodiment of the present disclosure, after forming the second groove B, the method may further include: forming a first via hole C and a second via hole D on the passivation layer 50, and forming a first solder bump 71 on the surface of the passivation layer 50 by photolithography, so that the first solder bump 71 is connected to the n-type layer 40 through the first via hole C; then, a second pad block 72 is formed on the surface of the passivation layer 50 by photolithography such that the second pad block 72 is connected to the p-type layer 20 through the second via hole D.
As shown in fig. 1, after forming the first pad blocks 71 and the second pad blocks 72, a protective layer E may be formed on the surface of the passivation layer 50, and the protective layer E extends from the surface of the passivation layer 50 to the substrate 101.
Illustratively, in the embodiment of the present disclosure, the protective layer E may be a silicon oxide film layer.
It should be noted that after the passivation layer 50 is grown on the surface of the passivation layer, a through hole exposing the pad may be etched on the surface of the passivation layer E by using a photolithography technique, so as to facilitate electrical connection.
Finally, the substrate 101 is thinned to a final thickness of 80 μm of the thinned substrate 101. Then, stealth dicing and scribing can be carried out on the sapphire, and the loss of brightness can be well reduced through stealth dicing and scribing. Then, testing to obtain the red light LED chip.
The above description is intended to be exemplary only and not to limit the present disclosure, and any modification, equivalent replacement, or improvement made without departing from the spirit and scope of the present disclosure is to be considered as the same as the present disclosure.

Claims (10)

1. A red light-emitting diode chip, comprising: a substrate (101), a p-type layer (20), a multi-quantum well layer (30), an n-type layer (40), a passivation layer (50), an n-type electrode (62), and a p-type electrode (61);
the p-type layer (20), the multiple quantum well layer (30) and the n-type layer (40) are sequentially laminated on the substrate (101), the n-type electrode (62) is located on the surface of the n-type layer (40), a first groove (A) exposing the p-type layer (20) is formed in the middle of the n-type layer (40), and the p-type electrode (61) is located on the surface of the p-type layer (20) and located on the bottom surface of the first groove (A);
the passivation layer (50) covers at least the n-type layer (40), the first groove (A), the surface of the p-type layer (20);
the surface of the passivation layer (50) far away from the substrate (101) is provided with a second groove (B), and the orthographic projection of the bottom surface of the second groove (B) on the substrate (101) is not overlapped with the orthographic projection of the multi-quantum well layer (30) on the substrate (101).
2. The red led chip of claim 1, wherein the side wall of the second groove (B) is a slope, and an included angle between the side wall of the second groove (B) and the bottom surface of the second groove (B) is an obtuse angle.
3. The red led chip of claim 1, wherein the bottom surface of the second recess (B) is circular, and the sidewall of the second recess (B) is conical.
4. The red led chip of claim 3, wherein the second recess (B) has a trench depth of 6000 to 10000 a.
5. The red led chip of claim 3, wherein an angle between a sidewall of the second groove (B) and a bottom surface of the second groove (B) is 130 ° to 140 °.
6. The red led chip of claim 1, wherein the p-type electrode (61) comprises an electrode portion (611) and a connecting portion (612) connected, an orthogonal projection of the electrode portion (611) on the substrate (101) is located within an orthogonal projection of the second recess (B) on the substrate (101), and an orthogonal projection of the connecting portion (612) on the substrate (101) is located outside an orthogonal projection of the second recess (B) on the substrate (101).
7. The red light-emitting diode chip according to any one of claims 1 to 6, wherein the passivation layer (50) comprises a silicon oxide layer (501), a DBR layer (502) and a silicon nitride layer (503) which are sequentially stacked, the silicon oxide layer (501) is connected with the n-type layer (40), the n-type electrode (62), the first groove (A), the p-type layer (20) and the p-type electrode (61), and the second groove (B) is located in the silicon nitride layer (503).
8. The red led chip of claim 7, wherein the silicon oxide layer (501) has a thickness of 4000 to 6000 angstroms and the silicon nitride layer (503) has a thickness of 0.5 to 2 μmμ m, the DBR layer (502) including a plurality of TiO layers alternately stacked periodically2Layer and SiO2And (3) a layer.
9. The red light emitting diode chip according to any of claims 1 to 6, wherein the light emitting diode chip further comprises a first solder bump (71) and a second solder bump (72), the first solder bump (71) and the second solder bump (72) each being located on a surface of the passivation layer (50) remote from the substrate (101);
the passivation layer (50) is provided with a first through hole (C) exposing the n-type electrode (62) and a second through hole (D) exposing the p-type electrode (61), the first welding point block (71) covers the first through hole (C) and is connected with the n-type electrode (62), and the second welding point block (72) covers the second through hole (D) and is connected with the p-type electrode (61).
10. A preparation method of a red light LED chip is characterized by comprising the following steps:
providing a substrate;
sequentially growing an n-type layer, a multi-quantum well layer and a p-type layer on the substrate;
bonding a substrate on the p-type layer, and removing the substrate;
etching the middle part of the n-type layer to expose a first groove of the p-type layer;
forming an n-type electrode on the surface of the n-type layer, and forming a p-type electrode on the bottom surface of the first groove;
manufacturing passivation layers on the surfaces of the n-type layer, the n-type electrode, the first groove, the p-type layer and the p-type electrode;
and forming a second groove on the surface of the passivation layer far away from the substrate, wherein the orthographic projection of the bottom surface of the second groove on the substrate is not overlapped with the orthographic projection of the multiple quantum well layer on the substrate.
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