TW202327071A - Light-emitting element, light-emitting assembly and display device including the same and manufacturing method of display device - Google Patents

Abstract

A light-emitting element includes a semiconductor stack, a metal electrode, a transparent electrode and a tether piece. The metal electrode is disposed on the semiconductor stack. The transparent electrode is disposed on the semiconductor stack opposite to the metal electrode. The tether piece extends at least on sidewalls of the semiconductor stack and the transparent electrode, and a surface of the tether piece far away from the metal electrode is aligned with a surface of the transparent electrode far away from the metal electrode. A light-emitting assembly including the light-emitting element, a display device including the light-emitting element and a manufacturing method of the display device are also provided.

Description

Light-emitting element, light-emitting component including same, display device, and manufacturing method of display device

The invention relates to a light-emitting element, a light-emitting component including the same, a display device, and a manufacturing method of the display device.

Due to its low power consumption, high brightness, high resolution, and high color saturation, micro-LEDs are suitable for constructing pixel structures of micro-LED display devices. Due to the extremely small size of micro light emitting diodes, the current method of manufacturing micro light emitting diode display devices is to use mass transfer (Mass Transfer) technology, that is, to use micro electromechanical array technology to pick and place micro light emitting diode crystals. To transport a large number of miniature light-emitting diode crystals to the driver backplane with pixel circuits at one time.

In addition, according to the packaging method, micro-LEDs can be classified into horizontal, vertical and flip-chip micro-LEDs. As the grain size of micro-LEDs becomes smaller, it is expected that vertical micro-LEDs will be able to provide a larger light-emitting area. However, at present, the upper electrode of the vertical miniature light-emitting diode adopts a metal electrode, which causes the current to be locally concentrated on the metal electrode, and the metal electrode also blocks light to affect light extraction.

The present invention provides a light emitting element with good light extraction efficiency.

The invention provides a light-emitting component with good light extraction efficiency.

The invention provides a display device with good light extraction efficiency.

The present invention provides a method for manufacturing a display device, which can provide a display device with good light extraction efficiency.

One embodiment of the present invention proposes a light-emitting element, comprising: a semiconductor stack; a metal electrode positioned on the semiconductor stack; a transparent electrode positioned on the side of the semiconductor stack opposite to the metal electrode; and a tie extending at least over The side walls of the semiconductor laminate and the transparent electrode, and the surface of the connecting member away from the metal electrode is flush with the surface of the transparent electrode away from the metal electrode.

In an embodiment of the present invention, the above-mentioned connecting member includes silicon oxide, silicon nitride or a Bragg reflective layer.

In an embodiment of the present invention, the above-mentioned Bragg reflection layer includes a plurality of overlapping titanium oxide layers and a plurality of silicon oxide layers.

In an embodiment of the present invention, the above-mentioned semiconductor stack includes: a first-type semiconductor pattern located between the metal electrode and a transparent electrode; a second-type semiconductor pattern overlapping the first-type semiconductor pattern and located between the first-type semiconductor pattern Between the semiconductor pattern and the transparent electrode; and the light emitting pattern, located between the first type semiconductor pattern and the second type semiconductor pattern.

In an embodiment of the present invention, the above-mentioned second-type semiconductor pattern includes a P-type semiconductor material.

In an embodiment of the present invention, the above-mentioned light-emitting element further includes a matching pattern located between the semiconductor stack and the transparent electrode.

An embodiment of the present invention provides a light-emitting component, including: a carrier board; a plurality of support members located on the carrier board; and the above-mentioned light-emitting element suspended between the support members by a tie member.

In an embodiment of the present invention, the above-mentioned orthographic projection of the connecting member on the carrier is outside the orthographic projection of the metal electrode on the carrier.

In an embodiment of the present invention, the above-mentioned tie element further extends to a plurality of supporting elements.

In an embodiment of the present invention, the above-mentioned light-emitting component further includes a support layer located between the plurality of supports, the light-emitting element and the carrier.

In an embodiment of the present invention, the above-mentioned supporting layer and the supporting member are integrally formed.

An embodiment of the present invention provides a display device, including: a circuit substrate; and the above-mentioned light-emitting element located on the circuit substrate and electrically connected to the circuit substrate.

In an embodiment of the present invention, the above-mentioned metal electrodes are located between the semiconductor stack and the circuit substrate.

In an embodiment of the present invention, the above-mentioned circuit substrate further includes a switch element, and the switch element is electrically connected to the transparent electrode or the metal electrode.

An embodiment of the present invention provides a method for manufacturing a display device, including: providing a growth substrate; forming a multi-layer semiconductor layer on the growth substrate; forming a transparent electrode layer on the multi-layer semiconductor layer; forming an intermediary substrate on the transparent electrode layer; Growth substrate; patterning multiple layers of semiconductor layers and transparent electrode layers to form semiconductor stacks and transparent electrodes; forming metal electrodes on semiconductor stacks; , and the surface of the connecting member facing the intermediary substrate is flush with the surface of the transparent electrode facing the intermediary substrate.

In an embodiment of the present invention, the above-mentioned forming a multi-layer semiconductor layer includes: forming a first-type semiconductor layer on the growth substrate; forming a light-emitting layer on the first-type semiconductor layer; and forming a second-type semiconductor layer on the light-emitting layer .

In an embodiment of the present invention, the formation of the transparent electrode layer includes: forming a matching layer on the multi-layer semiconductor layer; and forming the transparent electrode layer on the matching layer.

In an embodiment of the present invention, the above-mentioned manufacturing method of the display device further includes forming a plurality of support members on the tie member, and the support members do not overlap the semiconductor stack.

In an embodiment of the present invention, the above-mentioned forming a plurality of support members on the tie member includes: forming a sacrificial layer on the metal electrode and the tie member, and the sacrificial layer has a plurality of through holes, and the plurality of through holes do not overlap semiconductor stacking and exposing the connecting piece; and forming a supporting piece in each through hole.

In an embodiment of the present invention, the aforementioned sacrificial layer includes organic materials.

In an embodiment of the present invention, the above-mentioned manufacturing method of the display device further includes forming a carrier plate on the plurality of supports and the metal electrodes.

In an embodiment of the present invention, after the formation of the above-mentioned carrier, it further includes removing the intermediary substrate.

In an embodiment of the present invention, removing the sacrificial layer is further included after removing the interposer substrate.

In an embodiment of the present invention, after removing the sacrificial layer, it further includes: providing a circuit substrate, the circuit substrate including pads on its surface; On the pad of the circuit substrate, the metal electrode is located between the semiconductor laminate and the pad; and the metal electrode is electrically connected to the pad.

In an embodiment of the present invention, the above-mentioned manufacturing method of the display device further includes electrically connecting the transparent electrode and the switching element of the circuit substrate.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Throughout the specification, the same reference numerals denote the same elements. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that other elements exist between two elements.

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first "element," "component," "region," "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include plural forms including "at least one" or meaning "and/or" unless the content clearly dictates otherwise. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the terms "comprising" and/or "comprising" designate the existence of said features, regions, integers, steps, operations, elements and/or components, but do not exclude one or more Existence or addition of other features, regions, integers, steps, operations, elements, parts and/or combinations thereof.

Additionally, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe one element's relationship to another element as shown in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "below" can encompass both an orientation of "below" and "upper," depending on the particular orientation of the drawing. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of above and below.

The terms "about," "approximately," or "substantially" as used herein include stated values and those within ordinary skill in the art, taking into account the measurements in question and the specific amount of error associated with the measurements (i.e., limitations of the measurement system). The average value within an acceptable range of deviation from a specified value as determined by a human being. For example, "approximately" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "about", "approximately", or "substantially" used herein may select a more acceptable range of deviation or standard deviation based on optical properties, etching properties or other properties, and may not use one standard deviation to apply to all nature.

Exemplary embodiments are described herein with reference to cross section illustrations that are schematic illustrations of idealized embodiments. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances are to be expected. Thus, embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region shown or described as flat, may, typically, have rough and/or non-linear features. Additionally, acute corners shown may be rounded. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

FIG. 1A to FIG. 1J are partial cross-sectional schematic diagrams of the steps of the manufacturing method of the display device 10 according to an embodiment of the present invention. Please refer to FIG. 1A , in the steps of the manufacturing method of the display device 10 of this embodiment, firstly, a growth substrate GS is provided, and the growth substrate GS can be a sapphire (Sapphire) substrate, a gallium arsenide (GaAs) substrate, a gallium phosphide (GaP) substrate, indium phosphide (InP) substrate, silicon carbide (SiC) substrate, gallium nitride (GaN) substrate or other substrates suitable for epitaxial process, but not limited thereto.

Next, in some embodiments, a release layer (not shown) may be formed on the surface of the growth substrate GS as required. The release layer may facilitate the subsequent removal of the growth substrate GS and also facilitate subsequent epitaxy. crystal process. The material of the release layer is, for example, aluminum nitride (AlN) or gallium nitride (GaN).

Next, a blanket multi-layer semiconductor layer is formed on the growth substrate GS and the release layer (if any). For example, the first-type semiconductor layer SL1 can be formed first on the growth substrate GS and the release layer (if any); then, the light-emitting layer EL is formed on the first-type semiconductor layer SL1; then, the second-type semiconductor layer is formed. The semiconductor layer SL2 is on the light emitting layer EL. The first-type semiconductor layer SL1 and the second-type semiconductor layer SL2 may include II-VI materials (for example: zinc selenide (ZnSe)) or III-V nitride materials (for example: gallium nitride (GaN), nitride Aluminum (AlN), Indium Nitride (InN), Indium Gallium Nitride (InGaN), Aluminum Gallium Nitride (AlGaN), or Aluminum Indium Gallium Nitride (AlInGaN)). For example, in this embodiment, the first-type semiconductor layer SL1 is, for example, an N-type doped semiconductor layer, the material of the N-type doped semiconductor layer is, for example, N-type gallium nitride (n-GaN), and the second-type semiconductor layer The layer SL2 includes, for example, a P-type doped semiconductor material, and the P-type doped semiconductor material is, for example, P-type gallium nitride (GaN), but not limited thereto. In this embodiment, the structure of the light-emitting layer EL is, for example, a multiple quantum well structure (Multiple Quantum Well, MQW). The multiple quantum well structure includes alternately stacked multiple layers of indium gallium nitride (InGaN) and multiple layers of gallium nitride (GaN), By designing the proportion of indium or gallium in the light emitting layer EL, the emission wavelength range of the light emitting layer EL can be adjusted, but the present invention is not limited thereto.

Next, referring to FIG. 1B , a transparent electrode layer TL is formed on the first-type semiconductor layer SL1 , the light-emitting layer EL and the second-type semiconductor layer SL2 , and then an interposer substrate IS is formed on the transparent electrode layer TL. In this embodiment, the material of the transparent electrode layer TL may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO) or other suitable conductive oxides, or the above conductive oxides Any stack of two or more layers in an object, but not limited to. In this embodiment, the interposer substrate IS may be disposed on the transparent electrode layer TL by sticking, but it is not limited thereto.

In some embodiments, before forming the transparent electrode layer TL, a transparent matching layer ML may be formed on the first-type semiconductor layer SL1, the light-emitting layer EL, and the second-type semiconductor layer SL2, and then the transparent electrode layer TL is formed on the on the matching layer ML. The matching layer ML facilitates the ohmic contact between the second-type semiconductor layer SL2 and the transparent electrode layer TL, and the material of the matching layer ML is, for example, p-type gallium nitride (p-GaN), but not limited thereto.

Next, referring to FIG. 1C , the growth substrate GS is removed to expose the first-type semiconductor layer SL1 . The method of removing the growth substrate GS can be, for example, heat treatment or laser lift off (Laser Lift Off) process, but is not limited thereto.

Next, referring to FIG. 1D, the first-type semiconductor layer SL1, the light-emitting layer EL, the second-type semiconductor layer SL2, the matching layer ML, and the transparent electrode layer TL are patterned to form the first-type semiconductor pattern SP1, the light-emitting pattern EP, The second-type semiconductor pattern SP2, the matching pattern MP and the transparent electrode TE, wherein the first-type semiconductor pattern SP1, the light emitting pattern EP and the second-type semiconductor pattern SP2 may constitute a semiconductor stack SS.

Next, a metal electrode ME is formed on the semiconductor stack SS. In some embodiments, a blanket metal electrode layer (not shown) can also be formed on the first-type semiconductor layer SL1 first, and then the metal electrode layer, the first-type semiconductor layer SL1, the light-emitting layer EL, the second The semiconductor layer SL2, the matching layer ML, and the transparent electrode layer TL are patterned to form the transparent electrode TE, the matching pattern MP, the semiconductor stack SS, and the metal electrode ME stacked on the intermediary substrate IS. The material of the metal electrode ME can include metals with good conductivity, such as aluminum (Al), titanium (Ti), gold (Au), platinum (Pt), nickel (Ni), chromium (Cr) and other metals, and alloys of the above metals , or a combination or laminate of the above metals and/or alloys. For example, the metal electrode ME may include metal stacks such as Ti/Al/Ti/Au, Cr/Pt/Au or Cr/Al/Ti/Pt/Au.

Next, please refer to FIG. 1E , forming a tie member TR on the sidewall Ws of the semiconductor stack SS, the sidewall Wm of the matching pattern MP, the sidewall Wt of the transparent electrode TE, and the surface Fi of the interposer substrate IS. In this way, both the connecting piece TR and the transparent electrode TE can be attached to the surface Fi of the intermediary substrate IS, so that the surface Fr of the connecting piece TR facing the intermediary substrate IS can be aligned with the surface Ft of the transparent electrode TE facing the intermediary substrate IS flat. The term "flush" as used herein means "approximately flush". For example, in some embodiments, due to the tolerable error of the manufacturing process, there may be surface relief less than or equal to 3 μm on the surface Fr and/or the surface Ft. Therefore, some regions of the surface Fr and some regions of the surface Ft A surface height difference of about 5 μm is possible. In certain embodiments, certain regions of surface Fr may have a surface height difference of about 3 μm, 2 μm, or 1 μm from certain regions of surface Ft. In some embodiments, the tether TR may also be formed on the sidewall We of the metal electrode ME. The material of the connecting piece TR is, for example, silicon oxide (SiOx) or silicon nitride (SiNx), but not limited thereto.

So far, the light-emitting element 120 is formed on the intermediary substrate IS, and the light-emitting element 120 may include: a semiconductor stack SS; a metal electrode ME located on the semiconductor stack SS; a transparent electrode TE located on the semiconductor stack SS and the metal electrode The opposite side of ME; the matching pattern MP is located between the semiconductor stack SS and the transparent electrode TE; and the tie TR extends at least on the sidewall of the semiconductor stack SS and the transparent electrode TE, and the tie TR is away from the metal electrode The surface Fr of the ME is flush with the surface Ft of the transparent electrode TE away from the metal electrode ME, wherein the semiconductor stack SS may include a first-type semiconductor pattern SP1, a second-type semiconductor pattern SP2, and an emission pattern EP, wherein the first-type semiconductor The pattern SP1 may be located between the metal electrode ME and the transparent electrode TE, the second-type semiconductor pattern SP2 may overlap the first-type semiconductor pattern SP1 and be located between the first-type semiconductor pattern SP1 and the transparent electrode TE, and the light emitting pattern EP may be located between the first-type semiconductor pattern SP1 and the transparent electrode TE. Between the first type semiconductor pattern SP1 and the second type semiconductor pattern SP2. The metal electrode ME and the transparent electrode TE of the light emitting element 120 are respectively located on opposite sides of the light emitting pattern EP, that is to say, the light emitting element 120 is a vertical light emitting diode. In some embodiments, the light emitting element 120 may be a vertical light emitting diode emitting blue light or green light, but is not limited thereto.

Next, please refer to FIG. 1F. In some embodiments, a sacrificial layer SF can also be formed on the metal electrode ME and the tie member TR, and the sacrificial layer SF can be formed with a plurality of via holes VA, and each via hole VA is formed on the intermediary substrate. The orthographic projection of the IS does not overlap the orthographic projection of the semiconductor stack SS on the interposer IS, and the through hole VA can expose the portion of the tie member TR attached to the interposer IS. The sacrificial layer SF may include an organic material, but is not limited thereto. The through hole VA may have an inverted trapezoidal shape with a wide top and a narrow bottom, but not limited thereto.

Next, please refer to FIG. 1G , a support PC may also be formed in each through hole VA. Since the via VA can expose the tie piece TR and the via hole VA does not overlap the semiconductor stack SS, the support PC can connect the tie piece TR and the support PC does not overlap the semiconductor stack SS. In some embodiments, the support layer PL can also be formed on the support PC and the sacrificial layer SF, and the support layer PL can belong to the same film layer as the support PC, in other words, the support layer PL can be integrally formed with the support PC, but Not limited to this. In this way, it can be ensured that the supporting member PC and the sacrificial layer SF have flat upper surfaces. The support PC and/or the support layer PL may include a material with certain rigidity, such as metal, and the support PC and/or the support layer PL may also have a multi-layer structure.

Next, please refer to FIG. 1G , the carrier CS may also be formed on the support PC, the metal electrodes ME and the support layer PL. For example, the carrier CS can be pasted on the supporting layer PL. Next, please refer to FIG. 1H , after the carrier CS is formed, the interposer IS can be removed, for example, by laser lift-off or heat treatment. Next, please refer to FIG. 1I , after removing the interposer IS, the sacrificial layer SF may also be removed. For example, the sacrificial layer SF can be removed by exposing and developing. So far, the light-emitting assembly 10A according to an embodiment of the present invention is completed, and the light-emitting assembly 10A may include: a carrier board CS; a plurality of supports PC located on the carrier board CS; a light-emitting element 120 suspended by a tie member TR Between the supports PC; and the support layer PL, located between the plurality of supports PC and the light-emitting element 120 and the carrier CS, wherein the connecting member TR is away from the surface Fr of the metal electrode ME and the transparent electrode TE is away from the metal electrode ME The surface Ft is flush.

In some embodiments, the orthographic projection of the tether TR on the carrier CS may be outside the orthographic projection of the metal electrode ME on the carrier CS. In some embodiments, the tether TR also extends on the support PC so that the tether TR can be connected to the support PC.

Next, please refer to FIG. 1J , after removing the sacrificial layer SF, a circuit substrate 110 may be further provided, wherein the circuit substrate 110 may include pads PD on its surface. Afterwards, a mass transfer process can be performed, that is, the light-emitting element 120 in the light-emitting assembly 10A is taken out and then transferred to the circuit substrate 110, for example, the metal electrode ME of the light-emitting element 120 is placed on the pad PD, so that the metal electrode ME It is located between the semiconductor stack SS and the pad PD of the circuit substrate 110 , and then the metal electrode ME of the light emitting element 120 is electrically connected to the pad PD through heat treatment, for example. So far, the display device 10 according to an embodiment of the present invention can be completed, and the display device 10 may include: a circuit substrate 110 ; and a light emitting element 120 located on the circuit substrate 110 and electrically connected to the circuit substrate 110 . Since the upper electrode of the light emitting element 120 of the display device 10 is the transparent electrode TE, the current in the light emitting element 120 can be evenly distributed on the transparent electrode TE, and the display device 10 can have good light extraction efficiency.

For example, the circuit substrate 110 may include a bottom plate 112 and a driving circuit layer 114 . The bottom plate 112 of the circuit substrate 110 can be a transparent substrate, an opaque substrate, a flexible substrate or an inflexible substrate, and its material can be a quartz substrate, a glass substrate, a polymer substrate or other suitable materials. The driving circuit layer 114 may include elements or circuits required by the display device 10 , such as driving elements, switching elements, storage capacitors, power lines, driving signal lines, timing signal lines, current compensation lines, detection signal lines, and so on. The driving circuit layer 114 can be formed on the base plate 112 by thin film deposition process, lithography process and etching process. The driving circuit layer 114 may include at least one insulating layer and at least one conductive layer, and the driving circuit layer 114 may include more insulating layers and conductive layers as required.

In some embodiments, the driving circuit layer 114 of the circuit substrate 110 may further include a switch element array, wherein the switch element array includes a plurality of switch elements T arranged in an array, and the switch elements T may be electrically connected to the light emitting element 120 . In detail, the driving circuit layer 114 may include, for example, switching elements T, power lines VL1, VL2, conductive structures CR1, CR2, pads PD, buffer layer I1, gate insulating layer I2, interlayer insulating layer I3 and insulating layer I4, I5. The switching element T is composed of a semiconductor layer TC, a gate TG, a source TS and a drain TD. The region where the semiconductor layer TC overlaps the gate TG can be regarded as the channel region of the switching element T. The buffer layer I1 is located between the base plate 112 and the semiconductor layer TC for preventing impurities in the base plate 112 from moving into the semiconductor layer TC and enhancing the adhesion between the semiconductor layer TC and the base plate 112 . The gate insulating layer I2 is located between the gate TG and the semiconductor layer TC. The interlayer insulating layer I3 is disposed between the source TS, the drain TD, the gate TG, and the power line VL2. The gate TG and the source TS can respectively receive signals from, for example, driving elements. The insulating layer I4 is disposed between the source TS, the drain TD, the power line VL1 and the conductive structures CR1, CR2, and the insulating layer I5 is disposed between the conductive structures CR1, CR2 and the pad PD, and the pad PD can be disposed on the insulating on layer I5. The conductive structure CR1 can be electrically connected to the power line VL1 through the through hole V1 in the insulating layer I4, the conductive structure CR2 can be electrically connected to the drain electrode TD through the through hole V2 in the insulating layer I4, and the pad PD can pass through the insulating layer I5. The via hole V3 is electrically connected to the conductive structure CR1. In some embodiments, the pad PD may not be electrically connected to the conductive structure CR1, and the pad PD may be electrically connected to the conductive structure CR2 through other via holes in the insulating layer I5, so that the switching element T may be electrically connected to the light emitting element. 120 metal electrodes ME.

The material of the semiconductor layer TC may include silicon semiconductor materials (such as polysilicon, amorphous silicon, etc.), oxide semiconductor materials, organic semiconductor materials, but not limited thereto. The material of the gate TG, the source TS, the drain TD, the power lines VL1, VL2, the conductive structures CR1, CR2 and the pad PD may include metals with good conductivity, such as aluminum, molybdenum, titanium, copper and other metals, but not limited to this. In some embodiments, the conductive structures CR1, CR2, and the pads PD can also have a single-layer structure or a multi-layer structure, such as a stack of any two or more layers of the above-mentioned conductive metal or conductive oxide. Combine and change. For example, the conductive structure CR1 may include a sequentially stacked titanium layer, an aluminum layer, and a titanium layer or a sequentially stacked molybdenum layer, an aluminum layer, and a molybdenum layer, but not limited thereto.

The material of the buffer layer I1, the gate insulating layer I2, the interlayer insulating layer I3 and the insulating layers I4, I5 may include transparent inorganic insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride or a stack of the above materials, but not limited to this. In some embodiments, the buffer layer I1, the gate insulating layer I2, the interlayer insulating layer I3, and the insulating layers I4 and I5 can also have a single-layer structure or a multi-layer structure, such as any two or more layers of the above-mentioned insulating materials. Layer stacking can be combined and changed as required.

In some embodiments, after the metal electrode ME and the pad PD are electrically connected, the transparent electrode TE may also be electrically connected to the switch element T of the circuit substrate 110 . For example, the insulating layer I6 can be formed on the insulating layer I5 and at least expose the transparent electrode TE of the light emitting element 120 . Next, a via hole V4 penetrating through the insulating layers I5 and I6 and exposing the conductive structure CR2 is formed. Afterwards, a conductive structure CR3 is formed on the transparent electrode TE and in the via hole V4 , so that the transparent electrode TE can be electrically connected to the drain TD of the switch element T through the conductive structure CR3 and the conductive structure CR2 . The material of the conductive structure CR3 may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO) or other suitable conductive oxides, and the material of the insulating layer I6 may include transparent inorganic insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride or a stack of the above materials, but not limited thereto.

In some embodiments, when the pad PD is electrically connected to the conductive structure CR2, a via hole penetrating through the insulating layers I5, I6 and exposing the conductive structure CR1 can be formed, and then on the transparent electrode TE and a via hole exposing the conductive structure CR1 can be formed. Another conductive structure is formed in the hole to electrically connect the transparent electrode TE and the power line VL1.

In the following, other embodiments of the present invention are continued to be described using FIGS. 2 to 3 , and the element numbers and related contents of the embodiment in FIGS. 1A to 1J are used, wherein the same numbers are used to represent the same or similar elements, and Descriptions of the same technical contents are omitted. For the description of the omitted parts, reference may be made to the embodiment shown in FIG. 1A to FIG. 1J , which will not be repeated in the following description.

FIG. 2 is a schematic cross-sectional view of a light emitting component 20A according to an embodiment of the present invention. The light-emitting assembly 20A may include: a carrier board CS; a plurality of supports PC located on the carrier board CS; a light-emitting element 120A suspended between the supports PC by a tie member TRa; and a supporting layer PL located on a plurality of supports. Between the component PC and the light emitting element 120A and the carrier CS, wherein the surface Fra of the tethering component TRa far away from the metal electrode ME is flush with the surface Ft of the transparent electrode TE far away from the metal electrode ME.

Compared with the light emitting assembly 10A shown in FIG. 1I , the light emitting assembly 20A shown in FIG. 2 is different in that: the tether TRa of the light emitting element 120A of the light emitting assembly 20A may include a Bragg reflector (Distributed Bragg Reflector, DBR ), wherein, for example, the Bragg reflection layer of the tie TRa may include multiple overlapping titanium oxide (TiO ₂ ) layers and multiple silicon oxide (SiO ₂ ) layers. By setting the connecting piece TRa including the Bragg reflective layer to control the total penetration or total reflection of a specific wavelength band for light filtering, it can be ensured that the light emitted by the light emitting element 120A provided by the light emitting component 20A can be completely converted into color and light, and fully reflective. The bands can again be light-color converted to increase light intensity. In addition, since the upper electrode of the light emitting element 120A is the transparent electrode TE, when the light emitting element 120A is enabled, the light emitting element 120A can have good light extraction efficiency, and the current can be uniformly distributed on the transparent electrode TE.

FIG. 3 is a schematic partial cross-sectional view of a display device 20 according to an embodiment of the invention. The display device 20 may include: a circuit substrate 110 ; and a light emitting element 120A located on the circuit substrate 110 and electrically connected to the circuit substrate 110 .

Compared with the display device 10 shown in FIG. 1J , the display device 20 shown in FIG. 3 is different in that: the tether TRa of the light emitting element 120A of the display device 20 may include a Bragg reflector (Distributed Bragg Reflector, DBR ), wherein, for example, the Bragg reflection layer of the tie TRa may include multiple overlapping titanium oxide (TiO ₂ ) layers and multiple silicon oxide (SiO ₂ ) layers. By setting the connecting piece TRa including the Bragg reflection layer to control the total penetration or total reflection of a specific wavelength band for light filtering, it can ensure that the color and light conversion of the display device 20 is complete, and the total reflection wavelength band can be converted again to increase the light color. light intensity, thereby improving the full-color display effect of the display device 20 . In addition, since the upper electrode of the light emitting element 120A in the display device 20 is the transparent electrode TE, the current in the light emitting element 120A can be evenly distributed on the transparent electrode TE, and the display device 20 can provide good light extraction efficiency.

In summary, the light-emitting element, light-emitting component and display device of the present invention can make the current in the light-emitting element evenly distributed on the transparent upper electrode by making the upper electrode of the vertical light-emitting element a transparent electrode, and make the light-emitting element, light-emitting The module and the display device can have good light extraction efficiency.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

10, 20: display device 10A, 20A: light-emitting components 110: circuit substrate 112: Bottom plate 114: Drive circuit layer 120, 120A: light emitting element CR1, CR2, CR3: conductive structure CS: carrier board EL: light emitting layer EP: Luminous pattern Fi, Fr, Fra, Ft: surface GS: growth substrate I1: buffer layer I2: Gate insulating layer I3: interlayer insulating layer I4, I5, I6: insulating layer IS:Intermediate Substrate ME: metal electrode ML: Matching Layer MP: matching pattern PC: support PD: Pad PL: supporting layer SF: sacrificial layer SL1: first type semiconductor layer SL2: Second type semiconductor layer SP1: Type 1 semiconductor pattern SP2: Second type semiconductor pattern SS: Semiconductor stack T: switching element TC: semiconductor layer TD: drain TE: transparent electrode TG: Gate TL: transparent electrode layer TR, TRa: Ties TS: source V1, V2, V3, V4, VA: through hole VL1, VL2: power cord We, Wm, Ws, Wt: side wall

FIG. 1A to FIG. 1J are partial cross-sectional schematic diagrams of the steps of the manufacturing method of the display device 10 according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of a light emitting component 20A according to an embodiment of the present invention. FIG. 3 is a schematic partial cross-sectional view of a display device 20 according to an embodiment of the invention.

10: Display device

110: circuit substrate

112: Bottom plate

114: Drive circuit layer

120: Light emitting element

CR1, CR2, CR3: conductive structure

EP: Luminous pattern

I1: buffer layer

I2: Gate insulating layer

I3: interlayer insulating layer

I4, I5, I6: insulating layer

ME: metal electrode

MP: matching pattern

PD: Pad

SP1: Type 1 semiconductor pattern

SP2: Second type semiconductor pattern

SS: Semiconductor stack

T: switching element

TC: semiconductor layer

TD: drain

TE: transparent electrode

TG: Gate

TR: Ties

TS: source

V1, V2, V3, V4: through holes

VL1, VL2: power cord

Claims (25)

A light emitting element, comprising: semiconductor stack; a metal electrode on the semiconductor stack; a transparent electrode located on the side of the semiconductor stack opposite to the metal electrode; and The tie member at least extends over the semiconductor stack and the sidewall of the transparent electrode, and the surface of the tie member away from the metal electrode is flush with the surface of the transparent electrode away from the metal electrode. The light-emitting device as claimed in claim 1, wherein the connecting member comprises silicon oxide, silicon nitride or a Bragg reflective layer. The light-emitting device as claimed in claim 2, wherein the Bragg reflective layer comprises a plurality of overlapping titanium oxide layers and a plurality of silicon oxide layers. The light-emitting element according to claim 1, wherein the semiconductor stack comprises: a first-type semiconductor pattern located between the metal electrode and the transparent electrode; a second type semiconductor pattern overlapping the first type semiconductor pattern and located between the first type semiconductor pattern and the transparent electrode; and The light emitting pattern is located between the first type semiconductor pattern and the second type semiconductor pattern. The light-emitting element as claimed in claim 4, wherein the second-type semiconductor pattern comprises a P-type semiconductor material. The light emitting element according to claim 1, further comprising a matching pattern located between the semiconductor laminate and the transparent electrode. A lighting assembly, comprising: carrier board; a plurality of supports on the carrier; and The light-emitting element according to any one of claims 1 to 6, suspended between the support members by the tie member. The light-emitting component as claimed in claim 7, wherein the orthographic projection of the connecting member on the carrier is outside the orthographic projection of the metal electrode on the carrier. The lighting assembly as claimed in claim 7, wherein the tie member further extends to the plurality of support members. The light-emitting component according to claim 7, further comprising a support layer located between the plurality of supports, the light-emitting element and the carrier. The light-emitting component as claimed in claim 10, wherein the support layer is integrally formed with the support member. A display device comprising: circuit substrates; and The light-emitting element according to any one of claims 1 to 6, located on the circuit substrate and electrically connected to the circuit substrate. The display device according to claim 12, wherein the metal electrode is located between the semiconductor laminate and the circuit substrate. The display device according to claim 12, wherein the circuit substrate further includes a switching element, and the switching element is electrically connected to the transparent electrode or the metal electrode. A method of manufacturing a display device, comprising: Provide a growth substrate; forming multiple semiconductor layers on the growth substrate; forming a transparent electrode layer on the multi-layer semiconductor layer; forming an intermediary substrate on the transparent electrode layer; removing the growth substrate; patterning the multiple semiconductor layers and the transparent electrode layer to form a semiconductor stack and a transparent electrode; forming metal electrodes on the semiconductor stack; and At least a tie is formed on the sidewall of the semiconductor stack and the transparent electrode and the intermediary substrate, and the surface of the tie facing the intermediary substrate and the transparent electrode face the intermediary substrate surface flush. The method for manufacturing a display device according to claim 15, wherein said forming multiple semiconductor layers comprises: forming a first-type semiconductor layer on the growth substrate; forming a light emitting layer on the first type semiconductor layer; and A second type semiconductor layer is formed on the light emitting layer. The method for manufacturing a display device according to claim 15, wherein said forming a transparent electrode layer comprises: forming a matching layer on the multi-layer semiconductor layer; and A transparent electrode layer is formed on the matching layer. The method for manufacturing a display device as claimed in claim 15 further includes forming a plurality of support members on the tie member, and the support members do not overlap the semiconductor stack. The manufacturing method of a display device according to claim 18, wherein the forming a plurality of support members on the tie member includes: forming a sacrificial layer on the metal electrode and the tie member, and the sacrificial layer has a plurality of through holes, the plurality of through holes do not overlap the semiconductor stack and expose the tie member; and The supporting member is formed in each of the through holes. The method of manufacturing a display device as claimed in claim 19, wherein the sacrificial layer includes an organic material. The method of manufacturing a display device according to claim 18, further comprising forming a carrier on the plurality of supports and the metal electrodes. The method for manufacturing a display device according to claim 21, further comprising removing the intermediary substrate after forming the carrier. The method for manufacturing a display device according to claim 22, wherein after removing the intermediary substrate, further includes removing the sacrificial layer. The method for manufacturing a display device according to claim 23, wherein after removing the sacrificial layer, it further includes: providing a circuit substrate comprising pads on a surface thereof; Transposing the transparent electrode, the semiconductor stack, the metal electrode and the connecting piece on the pad of the circuit substrate, so that the metal electrode is located between the semiconductor stack and the pad. between the pads; and Electrically connecting the metal electrode and the pad. The method of manufacturing a display device according to claim 24, further comprising a switch element electrically connecting the transparent electrode and the circuit substrate.

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