TWI750838B - Display panel and method for manufacturing the same - Google Patents

Abstract

A display panel includes a first substrate, a driving circuit layer, a first display element stack layer, a first insulating layer and a connecting electrode. The driving circuit layer is disposed on the first substrate and includes a first pad and a second pad separate from the first pad. The first display element stack layer is disposed on the driving circuit layer and electrically connected to the first pad. The first display element stack layer includes a first semiconductor pattern, a second semiconductor pattern and a first light emitting pattern. The second semiconductor pattern is disposed between the first semiconductor pattern and the driving circuit layer. The first light emitting pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The first insulating layer at least contacts a side wall of the first display element stack layer and the second pad, and has a first via and a second via exposing the first display element stack layer and the second pad respectively. The connecting electrode is disposed on the first insulating layer, and contacts the first display element stack layer and the second pad through the first via and the second via respectively. A method for manufacturing the display panel is also provided.

Description

Display panel and manufacturing method thereof

The present invention relates to a display panel and a manufacturing method thereof, and more particularly, to a miniature light emitting diode display panel and a manufacturing method thereof.

Because of its low power consumption, high brightness, high resolution and high color saturation, micro-LEDs are suitable for building the pixel structure of micro-LED display panels. Due to the extremely small size of the micro-LEDs, the current method of manufacturing the micro-LED display panel is to use the Mass Transfer technology, that is, to use the micro-electromechanical array technology to pick and place the micro-LED grains. In order to transport a large number of micro light-emitting diode chips to the driving backplane with pixel circuit at one time.

However, the mass transfer technology not only uses expensive equipment, but also has a yield problem of bonding the micro light-emitting diodes to the pixel circuits. In addition, limited by the minimum size of die pick and place, it is difficult to increase the pixel density.

The present invention provides a display panel with improved pixel density and production yield.

The present invention provides a method of manufacturing a display panel, which has improved production yield and does not require the use of mass transfer technology.

An embodiment of the present invention provides a display panel, including: a first substrate; a driving circuit layer disposed on the first substrate and including a first pad and a second pad spaced apart from each other; a first display element stack , disposed on the driving circuit layer and electrically connected to the first pad, wherein the first display element stack comprises: a first semiconductor pattern; a second semiconductor pattern, disposed between the first semiconductor pattern and the driving circuit layer; and The first light-emitting pattern is arranged between the first semiconductor pattern and the second semiconductor pattern; the first insulating layer is at least in contact with the sidewall of the first display element stack and the second pad, and has a layer that exposes the first display element stack a first through hole and a second through hole with the second pad; and a connecting electrode, which is arranged on the first insulating layer, wherein the connecting electrode contacts the first display element stack and the first display element stack in the first through hole and the second through hole respectively. Second pad.

In an embodiment of the present invention, the above-mentioned first pad and second pad include a stacked first conductive layer and a second conductive layer.

In an embodiment of the present invention, the materials of the first conductive layer and the second conductive layer are different.

In an embodiment of the present invention, the above-mentioned display panel further includes a second insulating layer, the second insulating layer is disposed between the first conductive layer and the second conductive layer, the second insulating layer has third through holes, the second insulating layer The conductive layer is connected to the first conductive layer through the third through hole.

In an embodiment of the present invention, the above-mentioned display panel further includes a bonding metal pattern, and the bonding metal pattern is disposed between the driving circuit layer and the first display element stack.

In an embodiment of the present invention, the above-mentioned material for bonding the metal pattern includes indium, copper or tin.

In an embodiment of the present invention, the above-mentioned second semiconductor pattern is bonded to the bonding metal pattern.

In an embodiment of the present invention, the above-mentioned first display element stack further includes: a matching pattern disposed on the first semiconductor pattern, and the first semiconductor pattern is located between the matching pattern and the first light-emitting pattern.

In an embodiment of the present invention, the above-mentioned first display element stack further includes: a reflective pattern disposed between the bonding metal pattern and the second semiconductor pattern.

In an embodiment of the present invention, the material of the above-mentioned reflection pattern includes silver.

In an embodiment of the present invention, the above-mentioned display panel further includes a second display element stack, and the driving circuit layer further includes a third pad and a fourth pad, wherein the second display element stack includes: a first The electrode is arranged on the driving circuit layer and is electrically connected to the third pad; the third semiconductor pattern is arranged on the first electrode and is electrically connected to the first electrode; the second light-emitting pattern is arranged on the third semiconductor pattern one side, and the third semiconductor pattern is located between the second light emitting pattern and the first electrode; the fourth semiconductor pattern is disposed on one side of the second light emitting pattern, and the second light emitting pattern is located between the third semiconductor pattern and the fourth semiconductor pattern and a second electrode disposed on one side of the fourth semiconductor pattern and electrically connected to the fourth pad; wherein the first electrode and the second electrode are located on the same side of the fourth semiconductor pattern.

Another embodiment of the present invention provides a method for manufacturing a display panel, including: providing a driving array substrate, wherein the driving array substrate includes: a first substrate; and a driving circuit layer disposed on the first substrate and including spaced apart a first pad and a second pad; an epitaxial substrate is provided, wherein the epitaxial substrate includes: a second substrate; and an epitaxial stack is disposed on the second substrate, wherein the epitaxial stack comprises sequentially stacked on the second The first semiconductor layer, the first light-emitting layer and the second semiconductor layer on the substrate; the epitaxial stack is attached to the driving array substrate and the second substrate is removed; the epitaxial stack is patterned on the driving array substrate and exposed extracting a second pad, wherein a part of the epitaxial stack remains on the first pad to form a first display element stack, and another part of the epitaxial stack is removed to expose the second pad; in depositing a first insulating layer on the second pad and the first display element stack, wherein the first insulating layer has a first through hole and a second through hole exposing the first display element stack and the second pad; and on A connection electrode is formed on the first insulating layer, and the connection electrode contacts the first display element stack and the second pad respectively in the first through hole and the second through hole.

In an embodiment of the present invention, the above-mentioned epitaxial stack is attached to the driving array substrate through a bonding metal layer, so that the bonding metal layer is located between the driving circuit layer and the epitaxial stack.

In an embodiment of the present invention, after the above-mentioned patterned epitaxial stack, the bonding metal layer is exposed, and the manufacturing method of the display panel further includes: providing oxygen to oxidize the bonding metal layer to form a metal oxide layer; and using The acid solution etches the metal oxide layer to expose the second pad. In an embodiment of the present invention, the above-mentioned acid solution includes hydrochloric acid.

In an embodiment of the present invention, the above-mentioned second pad includes a stacked first conductive layer and a second conductive layer, and the manufacturing method of the display panel further includes: forming a second insulating layer, and the second insulating layer is disposed on the first conductive layer. between a conductive layer and the second conductive layer; and a third through hole is formed in the second insulating layer, so that the second conductive layer is connected to the first conductive layer through the third through hole, and the second conductive layer is in the patterned epitaxial layer. After the stack is exposed, the first conductive layer is still covered by the second insulating layer after the patterned epitaxial stack.

In an embodiment of the present invention, the above-mentioned epitaxial stack further includes a reflective layer, and after the epitaxial stack is attached to the driving array substrate, the reflective layer is located between the driving array substrate and the second semiconductor layer.

In an embodiment of the present invention, the above-mentioned method for patterning an epitaxial stack includes: using an acid solution to pattern a reflective layer. In an embodiment of the present invention, the above-mentioned acid solution includes phosphoric acid, nitric acid or acetic acid.

In an embodiment of the present invention, the above-mentioned method for removing the second substrate includes laser lift-off.

The display panel of the present invention utilizes the lithography etching process to form the display element stack, which can reduce the size of the display element stack and improve the pixel density and the resolution of the display panel. In addition, the way of attaching the epitaxial stack to the driving array substrate is very simple, which can improve the production yield. In addition, there is no need to use mass transfer technology, which can save the cost of expensive mass transfer equipment.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

FIG. 1A is a schematic top view of a display panel 10 according to an embodiment of the present invention. FIG. 1B is an enlarged schematic view of the sub-pixels PXs of the display panel 10 of FIG. 1A . Fig. 1C is a schematic cross-sectional view taken along line A-A' of Fig. 1B. In order to simplify the expression of the drawings, FIG. 1A schematically illustrates the first substrate 110 , the driving circuit layer 120 and the first display element stack 130 , and other components are omitted. 1B schematically illustrates the driving element DC, the driving circuit layer 120 , the first display element stack 130 , the connecting electrode 150 , the first pad P1 , the second pad P2 , the first via V1 and the second via V2 relative position. Hereinafter, please refer to FIGS. 1A to 1C at the same time for a clear understanding of the overall structure of the display panel 10 .

Referring to FIGS. 1A to 1C , the display panel 10 includes a first substrate 110 , a driving circuit layer 120 , a first display element stack 130 , a first insulating layer 140 and a connection electrode 150 . The driving circuit layer 120 is disposed on the first substrate 110 and includes a first pad P1 and a second pad P2 spaced apart from each other. The first display element stack 130 is disposed on the driving circuit layer 120 and is electrically connected to the first pad P1. The first insulating layer 140 at least contacts the sidewall S1 of the first display element stack 130 and the second pad P2, and has a first through hole V1 and a second through hole V1 exposing the first display element stack 130 and the second pad P2 Via V2. The connection electrode 150 is disposed on the first insulating layer 140, and the connection electrode 150 contacts the first display element stack 130 and the second pad P2 through the first through hole V1 and the second through hole V2, respectively.

In the display panel 10 according to an embodiment of the present invention, the first display element stack 130 has a light emitting diode structure, and is formed by patterning the semiconductor epitaxial stack on the driving circuit layer 120 through a lithography etching process . The bonding method between the semiconductor epitaxial stack and the driving circuit layer 120 is simple, so not only can the bonding yield be improved, but also the high cost of mass transfer equipment can be saved. In addition, the size of the first display element stack 130 can be further reduced as required, so that the pixel density and the resolution of the display panel can be improved.

Specifically, the display panel 10 includes a plurality of sub-pixels PXs, and the plurality of sub-pixels PXs are arranged in an array. Each sub-pixel PXs is mainly composed of a first display element stack 130 having a light emitting diode structure. In some embodiments, the plurality of sub-pixels PXs may all be blue light-emitting diodes, and the display panel 10 may further include a color conversion layer CT disposed on the plurality of sub-pixels PXs, wherein the color conversion layer CT may include fluorescent Light powder or wavelength conversion material with similar properties, so that the blue light emitted by the blue light-emitting diode can now be converted into light of different colors to achieve a full-color display effect. In other embodiments, the plurality of sub-pixels PXs may be a plurality of red light-emitting diodes, a plurality of green light-emitting diodes, and a plurality of blue light-emitting diodes, so as to achieve a full-color display effect. When the emission colors of the sub-pixels PXs themselves are different, the color conversion layer CT in FIG. 1C can be selectively omitted or retained in the display panel 10 . In other embodiments, the plurality of sub-pixels PXs may all be white light emitting diodes, and the color conversion layer CT may be a color filter layer to achieve a full-color display effect.

In this embodiment, the display panel 10 may further include a driving element DC, and the driving element DC may be electrically connected to the sub-pixels PXs to transmit signals to the first display element stack 130 . For example, the first display element stack 130 is electrically connected to the first pad P1 and the second pad P2, and the driving element DC can be electrically connected to the first pad P1 and the second pad P2, respectively. In some embodiments, the first pads P1 in the plurality of sub-pixels PXs are separated from each other, and independently receive signals provided by the driving element DC. In some embodiments, the second pads P2 in the plurality of sub-pixels PXs may be electrically connected to each other and/or the second pads P2 may be applied with the same common voltage during operation. In some embodiments, the driving element DC may be a wafer bonded to the first substrate 110 or a circuit element (including active elements, passive elements, or a combination thereof) formed directly in the driving circuit layer 120 .

Hereinafter, with reference to FIG. 1A to FIG. 1C , the implementation of each sub-pixel of the display panel 10 will continue to be described, but the present invention is not limited thereto.

Referring to FIGS. 1A to 1C , each sub-pixel PXs of the display panel 10 includes, for example, a first substrate 110 , a driving circuit layer 120 , a first display element stack 130 , a first insulating layer 140 , connection electrodes 150 and bonding metal patterns 160. The driving circuit layer 120 is disposed on the first substrate 110 and has a first pad P1 and a second pad P2. The first display element stack 130 has, for example, a general structure of a light emitting diode. One end of the first display element stack 130 is bonded to the first pad P1 on the driving circuit layer 120 through the bonding metal pattern 160 , and the other end is electrically connected to the second pad P2 on the driving circuit layer 120 through the connecting electrode 150 . The first insulating layer 140 is disposed between the first display element stack 130 and the connection electrode 150 , and the first insulating layer 140 is at least disposed between the sidewall S1 of the first display element stack 130 and the connection electrode 150 to avoid An unwanted electrical connection relationship is created between the connection electrode 150 and the first display element stack 130 .

The first substrate 110 may be a transparent substrate or a non-transparent substrate, and the material thereof may be a quartz substrate, a glass substrate, a polymer substrate or other suitable materials, but the invention is not limited thereto. A driving circuit layer 120 may be disposed on the first substrate 110 . The driving circuit layer 120 includes components or circuits required by the display panel 10 , such as driving components, switching components, storage capacitors, power lines, driving signal lines, timing signal lines, and current compensation lines. , test signal lines, etc.

In this embodiment, the driving circuit layer 120 includes a buffer layer 121, an active element 122, a gate insulating layer 123, an interlayer insulating layer 124, a flat layer 125, a second insulating layer 126, a first conductive layer 127, and a third insulating layer 128 and the second conductive layer 129. In other embodiments, the driving circuit layer 120 may include more insulating layers and conductive layers as required. The active element 122 is composed of a semiconductor layer 122C, a gate electrode 122G, a source electrode 122S and a drain electrode 122D. The region where the semiconductor layer 122C overlaps the gate electrode 122G can be regarded as a channel region of the active device 122 . The gate insulating layer 123 is located between the gate electrode 122G and the semiconductor layer 122C, and the interlayer insulating layer 124 is provided between the source electrode 122S and the gate electrode 122G and between the drain electrode 122D and the gate electrode 122G. The gate electrode 122G can be electrically connected to the driving element DC through a scan line (not shown in the figure), and the source electrode 122S can be electrically connected to the driving element DC through a data line (not shown in the figure).

The material of the semiconductor layer 122C may include silicon semiconductor materials (eg, polysilicon, amorphous silicon, etc.), oxide semiconductor materials, and organic semiconductor materials. The materials of the gate electrode 122G, the source electrode 122S and the drain electrode 122D may include metals with good conductivity, such as metals such as aluminum, molybdenum, titanium, and copper, but the invention is not limited thereto. In addition, although the active element 122 in this embodiment is a top-gate TFT, in other embodiments, the active element 122 can also be a bottom-gate TFT, a double-gate TFT or Other types of thin film transistors.

The first conductive layer 127 includes a first conductive pattern 127a and a second conductive pattern 127b, and the second conductive layer 129 includes a third conductive pattern 129a and a fourth conductive pattern 129b. In this embodiment, the first pad P1 includes a stacked first conductive pattern 127a and a third conductive pattern 129a, and the third insulating layer 128 is disposed between the first conductive pattern 127a and the third conductive pattern 129a. The second pad P2 includes the stacked second conductive pattern 127b and the fourth conductive pattern 129b, and the third insulating layer 128 is disposed between the second conductive pattern 127b and the fourth conductive pattern 129b. The third insulating layer 128 has a third via V3 and a fourth via V4, the third conductive pattern 129a is connected to the first conductive pattern 127a through the third via V3, and the fourth conductive pattern 129b is connected to the second conductive pattern 129b via the fourth via V4 Conductive pattern 127b. In this embodiment, the first pads P1 and the second pads P2 are double-layered structures, but the invention is not limited thereto. In some embodiments, the first pad P1 or the second pad P2 may be a single-layer structure or a structure in which three or more conductive layers are stacked.

The material of the second conductive layer 129 can be different from that of the first conductive layer 127 , so that the second conductive layer 129 can serve as an etching protection layer for the first conductive layer 127 during the etching process. For example, the material of the first conductive layer 127 may include metals with good electrical conductivity, such as aluminum, molybdenum, titanium, copper and other metals, and the material of the second conductive layer 129 may include indium tin oxide (ITO), indium zinc oxide oxide (IZO), indium gallium zinc oxide (IGZO) or other suitable conductive oxide. In some embodiments, the first conductive layer 127 and the second conductive layer 129 may also have a single-layer structure or a multi-layer structure, respectively. Combinations and changes can be made as needed. For example, the first conductive layer 127 may include a sequentially stacked titanium layer, an aluminum layer, and a titanium layer, or a sequentially stacked molybdenum layer, an aluminum layer, and a molybdenum layer, but the invention is not limited thereto.

The buffer layer 121 , the gate insulating layer 123 , the interlayer insulating layer 124 , the second insulating layer 126 and the third insulating layer 128 may be made of transparent insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, or the above materials. laminated, but the present invention is not limited to this. The material of the flat layer 125 may include transparent insulating materials, such as organic materials, acrylic materials, siloxane materials, polyimide materials, epoxy materials, etc. However, the present invention is not limited to this. The buffer layer 121 , the gate insulating layer 123 , the interlayer insulating layer 124 , the flat layer 125 , the second insulating layer 126 and the third insulating layer 128 may also have a single-layer structure or a multi-layer structure, respectively, such as any two of the above-mentioned insulating materials. Layers or stacks of layers, combined and varied as desired.

The first display element stack 130 includes: a first semiconductor pattern 131 , a second semiconductor pattern 132 and a first light emitting pattern 133 . The second semiconductor pattern 132 is disposed between the first semiconductor pattern 131 and the driving circuit layer 120 . The first light emitting pattern 133 is disposed between the first semiconductor pattern 131 and the second semiconductor pattern 132 . The first semiconductor patterns 131 and the second semiconductor patterns 132 of the first display element stack 130 may include II-VI group materials (eg, zinc selenide (ZnSe)) or III-V nitride materials (eg, gallium nitride) (GaN), Aluminum Nitride (AlN), Indium Nitride (InN), Indium Gallium Nitride (InGaN), Aluminum Indium Gallium Nitride (AlGaN) or Aluminum Indium Gallium Nitride (AlInGaN)). For example, in this embodiment, the first semiconductor pattern 131 is, for example, an N-type doped semiconductor layer, and the material of the N-type doped semiconductor layer is, for example, N-type gallium nitride (n-GaN), and the second semiconductor pattern 132 For example, it is a P-type doped semiconductor layer, and the material of the P-type doped semiconductor layer is, for example, p-type gallium nitride (p-GaN), but the invention is not limited to this. In addition, the structure of the first light emitting pattern 133 is, for example, a multi-layer quantum well structure (MQW). The multi-quantum well structure includes alternately stacked multi-layer indium gallium nitride (InGaN) and multi-layer gallium nitride (GaN). By designing the ratio of indium or gallium in the first light-emitting pattern 133, the light-emitting wavelength range of the first light-emitting pattern 133 can be adjusted, but the invention is not limited thereto.

The first display element stack 130 may further include other layers that can adjust the light-emitting characteristics of the elements, such as epitaxial buffer patterns 134 and matching patterns 135 . In this embodiment, the matching pattern 135 is disposed between the epitaxial buffer pattern 134 and the first semiconductor pattern 131 , and the first semiconductor pattern 131 is disposed between the matching pattern 135 and the first light emitting pattern 133 . The epitaxial buffer pattern 134 and the matching pattern 135 can be used to adjust material properties of the first semiconductor pattern 131 , such as lattice constant, carrier transmission efficiency, and the like. The epitaxial buffer pattern 134 may have an opening OP to expose the matching pattern 135, and the connection electrode 150 may contact the matching pattern 135 in the opening OP. The setting position and recessed depth of the opening OP can be adjusted according to actual needs, and the present invention is not limited thereto. In other embodiments, the epitaxial buffer pattern 134 may be omitted, or the epitaxial buffer pattern 134 and the matching pattern 135 may be omitted simultaneously. In addition, both the epitaxial buffer pattern 134 and the matching pattern 135 may be made of a semiconductor material, such as gallium nitride, so there may not be a clear boundary between the first semiconductor pattern 131 , the epitaxial buffer pattern 134 and the matching pattern 135 .

The bonding metal pattern 160 is disposed between the driving circuit layer 120 and the first display element stack 130 . In some embodiments, the bonding metal pattern 160 may be disposed on the surface of the driving circuit layer 120 , such as the first pad P1 , the second pad P2 and the third insulating layer 128 , and the second semiconductor pattern 132 is bonded to the bonding on the metal pattern 160 . Alternatively, in other embodiments, a part of the bonding metal pattern 160 may be disposed on the surface of the driving circuit layer 120 , and the other part may be disposed on the second semiconductor pattern 132 of the first display element stack 130 . The material of the bonding metal pattern 160 includes indium, copper or tin, but the present invention is not limited thereto. In addition, the first display element stack 130 may further include reflective patterns 136 to increase the reflection of light. The reflection pattern 136 may be disposed between the bonding metal pattern 160 and the second semiconductor pattern 132, but the invention is not limited thereto. The material of the reflection pattern 136 may include a material with high reflectivity, such as silver or chrome.

In this embodiment, the first insulating layer 140 extends from the driving circuit layer 120 to the first display element stack 130 , and the first insulating layer 140 contacts the second pad P2 , the sidewall S1 of the first display element stack 130 and the The top surface of the matching pattern 135 . Specifically, the first via V1 of the first insulating layer 140 overlaps with the opening OP of the epitaxial buffer pattern 134 , and thus, the first via V1 may expose the matching pattern 135 . Meanwhile, the second through holes V2 of the first insulating layer 140 may expose the second pads P2. In this way, the connection electrode 150 can contact the matching pattern 135 of the first display element stack 130 through the first through hole V1 and the opening OP, and can contact the second pad P2 through the second through hole V2.

In the display panel 10 of this embodiment, the second semiconductor pattern 132 can be electrically coupled to the first pad P1 through the bonding metal pattern 160 , and the first semiconductor pattern 131 can be electrically coupled to the second pad through the connecting electrode 150 P2, since the bonding metal pattern 160 is a large-area coupling between the second semiconductor pattern 132 and the first pad P1, and the connecting electrode 150 is fabricated through deposition and patterning processes, the first display element stack 130 and the first The bonding of the pads P1 and the second pads P2 does not require precise alignment, and the bonding yield is high. In addition, the size of the first display element stack 130 can be adjusted through a lithography etching process, so that the display panel 10 can have improved pixel density and resolution.

2A to 2F are schematic cross-sectional views illustrating the steps of a manufacturing method of the display panel 10 according to an embodiment of the present invention. In the following embodiments of FIGS. 2A to 2F , embodiments of the manufacturing method of the display panel 10 are described, and the component numbers and related contents of the embodiments of FIGS. 1A to 1C are used, wherein the same numbers are used to indicate The same or similar elements, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the embodiments of FIGS. 1A to 1C , which will not be repeated in the following description.

First, referring to FIG. 2A , a driving array substrate 100 is provided, wherein the driving array substrate 100 includes a first substrate 110 and a driving circuit layer 120 . The driving circuit layer 120 is disposed on the first substrate 110 and includes a first pad P1 and a second pad P2 spaced apart from each other. In one embodiment, a buffer layer 121 , a semiconductor layer 122C, a gate insulating layer 123 , a gate 122G, an interlayer insulating layer 124 , a source electrode 122S, a drain electrode 122D, and a planarization layer may be sequentially formed on the first substrate 110 125 , the second insulating layer 126 and the first conductive layer 127 , wherein the semiconductor layer 122C, the gate electrode 122G, the source electrode 122S and the drain electrode 122D constitute the active element 122 .

After that, the first conductive layer 127 is patterned to form a first conductive pattern 127a and a second conductive pattern 127b. Next, a third insulating layer 128 is formed on the first conductive pattern 127a, the second conductive pattern 127b and the second insulating layer 126, and a third via V3 exposing the first conductive pattern 127a is formed in the third insulating layer 128 and the fourth via V4 exposing the second conductive pattern 127b.

After that, a second conductive layer 129 is formed on the third insulating layer 128, and then the second conductive layer 129 is patterned to form a third conductive pattern 129a and a fourth conductive pattern 129b, so that the third conductive pattern 129a passes through the third through holes V3 is connected to the first conductive pattern 127a, and the fourth conductive pattern 129b is connected to the second conductive pattern 127b through the fourth via V4. Therefore, in this embodiment, the first pad P1 includes the stacked first conductive pattern 127a and the third conductive pattern 129a, and the second pad P2 includes the stacked second conductive pattern 127b and the fourth conductive pattern 129b.

A bonding metal layer 161 may also be provided on the driving array substrate 100 . For example, the bonding metal layer 161 may be formed on the first pad P1 , the second pad P2 and the third insulating layer 128 . The bonding metal layer 161 may be a metal layer formed by physical vapor deposition (PVD). The material of the bonding metal layer 161 may include indium, copper or tin, but the invention is not limited thereto.

Next, referring to FIG. 2B , an epitaxial substrate 200 is provided. The epitaxial substrate 200 includes a second substrate 210 and an epitaxial stack 220 . . The second substrate 210 may be a growth substrate for growing epitaxial materials, such as a sapphire (Sapphire) substrate. In this embodiment, the epitaxial stack 220 includes an epitaxial buffer layer 224 , a matching layer 225 , a first semiconductor layer 221 , a first light emitting layer 223 , a second semiconductor layer 222 and Reflective layer 226 . In some embodiments, the epitaxial buffer layer 224 , the matching layer 225 , the first semiconductor layer 221 , the first light emitting layer 223 and the second semiconductor layer 222 are grown on the second substrate 210 by epitaxial growth. Materials include gallium nitride, but can contain different doping. However, the main materials of these epitaxial layers are not limited thereto. The reflective layer 226 is formed on the second semiconductor layer 222 by deposition, for example, and its material may include a material with high reflectivity, such as silver or chromium. In other embodiments, the reflective layer 226 may be a non-Lager reflective layer instead of being limited to a metal reflective layer. A bonding metal layer 262 may also be disposed on the epitaxial substrate 200 , and the formation method and material of the bonding metal layer 262 may be similar to the bonding metal layer 161 , but the invention is not limited thereto.

Next, referring to FIG. 2C , the driving array substrate 100 is roughly aligned with the epitaxial substrate 200 , and the epitaxial stack 220 is attached to the driving array substrate 100 , and then the second substrate 210 is removed. In this embodiment, the epitaxial stack 220 can be attached to the bonding metal layer 161 of the driving array substrate 100 through the bonding metal layer 262, so that the reflective layer 226 is located between the driving array substrate 100 and the second semiconductor layer 222, And the bonding metal layers 161 and 262 are located between the driving circuit layer 120 and the epitaxial stack 220 . After the bonding metal layer 161 and the bonding metal layer 262 are in contact with each other, a eutectic process may be performed to attach the epitaxial stack 220 to the driving array substrate 100 . For example, the eutectic process may include laser melting of the bonding metal layers 161 and 262 , so that the bonding metal layer 161 and the bonding metal layer 262 are combined into the bonding metal layer 260 . In some embodiments, the second substrate 210 may be removed by laser lift-off.

Next, referring to FIG. 2D , the epitaxial stack 220 and the bonding metal layer 260 are patterned on the driving array substrate 100 , and the second pad P2 is exposed, wherein part of the epitaxial stack 220 remains on the first pad On P1, the first display element stack 130 is formed, and another part of the epitaxial stack 220 is removed to expose the second pad P2. In one embodiment, the patterning of the epitaxial stack 220 and the bonding metal layer 260 may utilize an etching process, and the epitaxial buffer layer 224 , the matching layer 225 , and the first semiconductor are sequentially patterned using the etchant required for each layer. layer 221, the first light-emitting layer 223, the second semiconductor layer 222, the reflective layer 226, and the bonding metal layer 260 to form the epitaxial buffer pattern 134, the matching pattern 135, the first semiconductor pattern 131, the first light-emitting pattern 133, the first Two semiconductor patterns 132 , reflective patterns 136 and bonding metal patterns 160 , wherein the epitaxial buffer pattern 134 , the matching pattern 135 , the first semiconductor pattern 131 , the first light-emitting pattern 133 , the second semiconductor pattern 132 and the reflective pattern 136 constitute the first display Element stack 130 . In some embodiments, the epitaxial buffer layer 224 may be further patterned to form an opening OP on the top surface of the first display element stack 130 , so that the opening OP may expose the matching pattern 135 , but not limited thereto.

In some embodiments, the material of the reflective layer 226 is metal, such as silver, and the step of patterning the reflective layer 226 may use an acid solution such as phosphoric acid, nitric acid, or acetic acid, but not limited thereto. In some embodiments, the material of the bonding metal layer 260 includes indium. After the reflective layer 226 is patterned, oxygen may be supplied to oxidize the exposed bonding metal layer 260 to form a metal oxide layer; then, for example, hydrochloric acid may be used. acid solution to etch the metal oxide layer until the second pad P2 is exposed. In this embodiment, the first pads P1 and the second pads P2 are each made of conductive patterns of various materials. For example, the first conductive pattern 127a of the first pad P1 and the second conductive pattern 127b of the second pad P2 can be made of metal materials, while the third conductive pattern 129a and the second pad of the first pad P1 The fourth conductive pattern 129b of P2 may be made of a non-metallic conductive material. In this way, the bonding metal layer 260 directly contacts the third conductive pattern 129a, the fourth conductive pattern 129b and the third insulating layer 128 of the non-metallic conductive material, but does not contact the first conductive pattern 127a and the second conductive pattern of the metal material 127b. During the patterning process of the bonding metal layer 260, the fourth conductive pattern 129b and the third insulating layer 128 of the non-metallic conductive material can serve as a protective layer for the second conductive pattern 127b, so as to prevent the second conductive pattern 127b made of the metal material from being subjected to the oxidation step or etchant damage. Therefore, although the second pads P2 are exposed in the process of patterning the bonding metal layer 260 , they can maintain ideal electrical conductivity, which helps to improve the fabrication yield.

Next, referring to FIG. 2E, a first insulating layer 140 is deposited on the third insulating layer 128, the second pads P2 and the first display element stack 130, wherein the first insulating layer 140 contacts the second pads P2, the first The sidewall S1 of the display element stack 130 , the top surface of the epitaxial buffer pattern 134 , and the matching pattern 135 are displayed. Next, the first insulating layer 140 is patterned by an etching process to form a first via V1 and a second via V2, wherein the orthographic projection of the first via V1 on the first substrate 110 can overlap the epitaxial buffer pattern 134 The orthographic projection of the opening OP on the first substrate 110 , and the orthographic projection of the second through hole V2 on the first substrate 110 may overlap the orthographic projection of the second pad P2 on the first substrate 110 . In this way, the first through hole V1 and the opening OP can expose the matching pattern 135 of the first display element stack 130, and the second through hole V2 can expose the four conductive patterns 129b of the second pad P2.

Next, referring to FIG. 2F , a conductive layer is deposited on the first insulating layer 140 and patterned to form the connection electrode 150 . The connection electrode 150 can contact the matching pattern 135 of the first display element stack 130 through the first through hole V1 and the opening OP, and can contact the four conductive patterns 129b of the second pad P2 through the second through hole V2. The material of the connection electrode 150 may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO) or other suitable conductive oxides, but the invention is not limited thereto.

Based on the above, in the manufacturing method of the display panel 10 of this embodiment, the epitaxial stack 220 can be attached to the driving array substrate 100 by connecting the driving array substrate 100 and the epitaxial substrate 200 . The bonding yield between the 220 and the driving circuit layer 120 is high. In addition, the first display element stack 130 is formed by patterning after the epitaxial stack 220 is bonded to the driving circuit layer 120. Therefore, the arrangement position, size and spacing of the first display element stack 130 are mainly determined by lithography The etching process accuracy is determined. Compared with the process precision of mass transfer, the process precision of lithography etching is obviously higher. Therefore, the size and spacing of the first display element stack 130 can be reduced, thereby improving the pixel density and resolution of the display panel 10 . In addition, high cost of mass transfer equipment can be saved because mass transfer technology is not required.

FIG. 3 is a schematic cross-sectional view of a display panel 30 according to an embodiment of the present invention. In the embodiment of FIG. 3 , the implementation of the display panel 30 is described, and the element numbers and related contents of the embodiment of FIG. 1C are used, wherein the same numbers are used to represent the same or similar elements, and the same technology is omitted. Description of the content. For the description of the omitted part, reference may be made to the embodiment of FIG. 1C , which will not be repeated in the following description.

3 , the display panel 30 includes a first substrate 110 , a driving circuit layer 320 , a first display element stack 130 , a first insulating layer 140 , a connection electrode 150 , a bonding metal pattern 160 and a second display element stack 330 . In this embodiment, for the materials, detailed structures and formation methods of the first substrate 110 , the first display element stack 130 , the first insulating layer 140 , the connecting electrodes 150 and the bonding metal patterns 160 , please refer to the above description, and will not be repeated here. Repeat.

The driving circuit layer 320 may include a plurality of conductive layers and a plurality of insulating layers for forming the active element 122 , the first pads P1 , the second pads P2 , the third pads P3 and the fourth pads P4 . For example, the first pad P1 includes a stacked first conductive pattern 127 a and a third conductive pattern 129 a , and the third conductive pattern 129 a is connected to the first conductive pattern 127 a through a third via V3 in the third insulating layer 128 . The second pad P2 includes a stacked second conductive pattern 127 b and a fourth conductive pattern 129 b , and the fourth conductive pattern 129 b is connected to the second conductive pattern 127 b through a fourth via V4 in the third insulating layer 128 . The third pad P3 and the fourth pad P4 may have structures similar to the first pad P1 and the second pad P2, for example, the third pad P3 may include the stacked fifth conductive pattern 127c and the seventh conductive pattern 129c, And the seventh conductive pattern 129c is connected to the fifth conductive pattern 127c through the fifth through hole V5 in the third insulating layer 128; the fourth pad P4 may include the stacked sixth conductive pattern 127d and the eighth conductive pattern 129d, and the eighth The conductive patterns 129d are connected to the sixth conductive patterns 127d through the sixth through holes V6 in the third insulating layer 128, but the present invention is not limited thereto.

The first display element stack 130 may have a general structure of a light emitting diode. One end of the first display element stack 130 can be bonded to the first pad P1 through the bonding metal pattern 160 . The first insulating layer 140 is disposed between the sidewall S1 of the first display element stack 130 and the connection electrode 150 to avoid unnecessary electrical connection between the connection electrode 150 and the first display element stack 130 . One end of the connection electrode 150 contacts the first display element stack 130 through the first through hole V1 in the first insulating layer 140 and the opening OP of the first display element stack 130 , and the other end of the connection electrode 150 passes through the first insulating layer 140 The second through hole V2 in the device contacts the second pad P2 so that the other end of the first display element stack 130 can be electrically connected to the second pad P2 through the connecting electrode 150 .

For example, after the second display element stack 330 is formed on the substrate 301 , it is directly electrically connected to the third pad P3 and the fourth pad P4 of the driving circuit layer 320 through the first connecting material 362 and the second connecting material 364 . . In some embodiments, the second display element stack 330 is formed on the growth substrate and singulated, and then transposed to the substrate 301, and then electrically connected through the first connecting material 362 and the second connecting material 364, respectively. It is electrically connected to the third pad P3 and the fourth pad P4 of the driving circuit layer 320 . The first connecting material 362 and the second connecting material 364 are, for example, solder, conductive glue or other materials.

In some embodiments, the second display element stack 330 includes an epitaxial buffer pattern 334 , a matching pattern 335 , a fourth semiconductor pattern 331 , a second light emitting pattern 333 , a third semiconductor pattern 332 and Reflection pattern 336 . In addition, the second display element stack 330 further includes a first electrode 352 and a second electrode 354. The first electrode 352 and the second electrode 354 are electrically connected to the third connection through the first connecting material 362 and the second connecting material 364, respectively. The pad P3 and the fourth pad P4 are disposed on the driving circuit layer 320 . In this embodiment, the first electrode 352 and the second electrode 354 are disposed on the same side of the fourth semiconductor pattern 331 , therefore, the second display element stack 330 is a horizontal micro light-emitting diode, and the first electrode 352 is a The anode, the second electrode 354 is the cathode, but the invention is not limited to this.

In this embodiment, the first electrode 352 is electrically coupled to the third pad P3 to the third semiconductor pattern 332 , and the first electrode 352 of each second display element stack 330 is electrically connected to a third pad respectively. Pad P3. In this embodiment, the second electrodes 354 are electrically coupled to the fourth pads P4 to the fourth semiconductor patterns 331 , and the second electrodes 354 of the plurality of second display element stacks 330 are electrically connected to a fourth pad P4. In other embodiments, the first electrode 352 is electrically coupled to the fourth pad P4 to the third semiconductor pattern 332 , and the second electrode 354 is electrically coupled to the third pad P3 to the fourth semiconductor pattern 331 . In this embodiment, the materials of the first electrode 352 and the second electrode 354 may include alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or other suitable materials, or metal materials and other materials. Stacked layers of conductive material or other low-resistance material.

For example, in some embodiments, when one of the first display element stacks 130 in the display panel 10 shown in FIG. 1A to FIG. 1C is damaged, a laser can be used first on a surface perpendicular to the first substrate 110 . The outer edge of the damaged first display element stack 130 is cut in the direction, and then the damaged first display element stack 130 is removed, leaving the third pad P3 and the fourth pad P4, and then the second display The first electrode 352 and the second electrode 354 of the device stack 330 are connected to the third pad P3 and the fourth pad P4 by the first connecting material 362 and the second connecting material 364 respectively, and the repair can be completed, and the display is obtained. panel 30. However, the second display element stack 330 is not limited to be bonded to the third pad P3 and the fourth pad P4 for repair.

In conclusion, in the display panel and the display panel manufacturing method of the present invention, the attachment method of the epitaxial stack and the driving array substrate is very simple, and the production yield can be improved; the lithography etching process is used to form the display element Lamination can reduce the size and spacing of the display element stack to improve the pixel density and the resolution of the display panel; and does not need to use mass transfer technology, which can save the cost of expensive mass transfer equipment.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

10, 30: Display panel 100: Drive array substrate 110: The first substrate 120: Driver circuit layer 121: Buffer layer 122: Active Components 122C: Semiconductor layer 122D: Drain 122G: Gate 122S: source 123: gate insulating layer 124: interlayer insulating layer 125: flat layer 126: Second insulating layer 127: first conductive layer 127a: first conductive pattern 127b: second conductive pattern 127c: Fifth conductive pattern 127d: sixth conductive pattern 128: The third insulating layer 129: second conductive layer 129a: the third conductive pattern 129b: fourth conductive pattern 129c: seventh conductive pattern 129d: Eighth conductive pattern 130: first display element stack 131: first semiconductor pattern 132: Second semiconductor pattern 133: The first light-emitting pattern 134: Epitaxial buffer pattern 135: Match Pattern 136: Reflection Pattern 140: first insulating layer 150: Connect electrodes 160: Join Metal Pattern 161, 260, 262: bonding metal layers 200: Epitaxial substrate 210: Second substrate 220: Epitaxy stack 221: first semiconductor layer 222: the second semiconductor layer 223: the first light-emitting layer 224: epitaxial buffer layer 225: Matching Layer 226: Reflective layer 301: Substrate 320: Driving circuit layer 330: Second display element stack 331: Fourth semiconductor pattern 332: Third semiconductor pattern 333: Second light-emitting pattern 334: epitaxial buffer layer 335: Match Pattern 336: Reflection Pattern 352: First Electrode 354: Second Electrode 362: The first connecting material 364: Second connecting material A-A': line CT: color conversion layer DC: drive element OP: opening P1: first pad P2: Second pad P3: The third pad P4: Fourth pad PXs: Subpixels S1: Sidewall V1: first through hole V2: second via V3: third via V4: Fourth through hole V5: Fifth through hole V6: sixth through hole

FIG. 1A is a schematic top view of a display panel according to an embodiment of the present invention. FIG. 1B is an enlarged schematic view of sub-pixels PXs of the display panel of FIG. 1A . Fig. 1C is a schematic cross-sectional view taken along line A-A' of Fig. 1B. 2A to 2F are schematic cross-sectional views illustrating the steps of a manufacturing method of a display panel according to an embodiment of the present invention. 3 is a schematic cross-sectional view of a display panel according to an embodiment of the present invention.

10: Display panel

110: The first substrate

120: Driver circuit layer

121: Buffer layer

122: Active Components

122C: Semiconductor layer

122D: Drain

122G: Gate

122S: source

123: gate insulating layer

124: interlayer insulating layer

125: flat layer

126: Second insulating layer

127: first conductive layer

127a: first conductive pattern

127b: second conductive pattern

128: The third insulating layer

129: second conductive layer

129a: the third conductive pattern

129b: fourth conductive pattern

130: first display element stack

131: first semiconductor pattern

132: Second semiconductor pattern

133: The first light-emitting pattern

134: Epitaxial buffer pattern

135: Match Pattern

136: Reflection Pattern

140: first insulating layer

150: Connect electrodes

160: Join Metal Pattern

CT: color conversion layer

OP: opening

P1: first pad

P2: Second pad

S1: Sidewall

V1: first through hole

V2: second via

V3: third via

V4: Fourth through hole

Claims (20)

A display panel, comprising: a first substrate; a driving circuit layer disposed on the first substrate and including first pads and second pads spaced apart from each other; a first display element stack, disposed on the first substrate The driving circuit layer and the first pad are electrically connected to the first pad, wherein the first display element stack includes: a first semiconductor pattern; a second semiconductor pattern, disposed on the first semiconductor between the pattern and the driving circuit layer; and a first light-emitting pattern, disposed between the first semiconductor pattern and the second semiconductor pattern; a first insulating layer, at least in contact with the first display element stack sidewalls and the second pads, and have first through holes and second through holes exposing the first display element stack and the second pads; and a connection electrode, disposed on the first insulation layer, wherein the connection electrode contacts the first display element stack and the second pad in the first through hole and the second through hole, respectively, wherein the first pad is in the The orthographic projection of the first substrate overlaps the orthographic projection of the second semiconductor pattern on the first substrate. The display panel of claim 1, wherein the first pad and the second pad comprise a stacked first conductive layer and a second conductive layer. The display panel according to claim 2, wherein the materials of the first conductive layer and the second conductive layer are different. The display panel according to claim 2, further comprising a second insulating layer disposed between the first conductive layer and the second conductive layer, the second insulating layer having third through holes, and the second insulating layer The two conductive layers are connected to the first conductive layer through the third through hole. The display panel of claim 1, further comprising a bonding metal pattern disposed between the driving circuit layer and the first display element stack. The display panel of claim 5, wherein the material of the bonding metal pattern comprises indium, copper or tin. The display panel of claim 5, wherein the second semiconductor pattern is bonded to the bonding metal pattern. The display panel of claim 5, wherein the first display element stack further comprises: a matching pattern disposed on the first semiconductor pattern, and the first semiconductor pattern is located between the matching pattern and the between the first light-emitting patterns. The display panel of claim 5, wherein the first display element stack further comprises: a reflective pattern disposed between the bonding metal pattern and the second semiconductor pattern. The display panel of claim 9, wherein the material of the reflective pattern comprises silver. The display panel according to claim 1, further comprising a second display element stack, and the driving circuit layer further comprising a third pad and a fourth pad, wherein the second display element stack comprises: a first an electrode disposed on the driving circuit layer and electrically connected to the third pad; a third semiconductor pattern disposed on the first electrode and electrically connected to the first electrode; a second light emitting pattern , which is arranged on one side of the third semiconductor pattern, and the third semiconductor pattern is located between the second light-emitting pattern and the first electrode; the fourth semiconductor pattern is arranged on the side of the second light-emitting pattern. one side, and the second light-emitting pattern is located between the third semiconductor pattern and the fourth semiconductor pattern; and a second electrode is disposed on one side of the fourth semiconductor pattern and is electrically connected to the a fourth pad; wherein the first electrode and the second electrode are located on the same side of the fourth semiconductor pattern. A manufacturing method of a display panel, comprising: providing a driving array substrate, wherein the driving array substrate comprises: a first substrate; and a driving circuit layer disposed on the first substrate and including first pads spaced apart from each other and a second pad; providing an epitaxial substrate, wherein the epitaxial substrate includes: a second substrate; and an epitaxial stack disposed on the second substrate, wherein the epitaxial stack includes a first semiconductor layer, a first light-emitting layer and a second layer sequentially stacked on the second substrate semiconductor layer; attaching the epitaxial stack on the driving array substrate and removing the second substrate; patterning the epitaxial stack on the driving array substrate and exposing the second substrate pads, wherein part of the epitaxial stack remains on the first pad to form a first display element stack, and another part of the epitaxial stack is removed to expose the first two pads; depositing a first insulating layer on the second pad and the first display element stack, wherein the first insulating layer has exposed the first display element stack and the second a first through hole and a second through hole of the pad; and a connection electrode is formed on the first insulating layer, and the connection electrode contacts the first through hole and the second through hole respectively The display element stack and the second pad. The method for manufacturing a display panel according to claim 12, wherein the epitaxial stack is attached to the driving array substrate through a bonding metal layer, so that the bonding metal layer is located between the driving circuit layer and the driving circuit layer. between epitaxial layers. The method for manufacturing a display panel according to claim 13, wherein after patterning the epitaxial stack, the bonding metal layer is exposed, and the method for manufacturing the display panel further comprises: Oxygen gas is provided to oxidize the bonding metal layer to form a metal oxide layer; and an acid solution is used to etch the metal oxide layer to expose the second pad. The method for manufacturing a display panel according to claim 14, wherein the acid solution includes hydrochloric acid. The method for manufacturing a display panel according to claim 13, wherein the second pad comprises a stacked first conductive layer and a second conductive layer, and the method for manufacturing the display panel further comprises: forming a second insulating layer, The second insulating layer is disposed between the first conductive layer and the second conductive layer; and a third through hole is formed in the second insulating layer, so that the second conductive layer passes through the first conductive layer. Three vias are connected to the first conductive layer, the second conductive layer is exposed after patterning the epitaxial stack, and the first conductive layer is still exposed after patterning the epitaxial stack The second insulating layer covers. The method for manufacturing a display panel according to claim 12, wherein the epitaxial stack further comprises a reflective layer, and after the epitaxial stack is attached to the driving array substrate, the reflective layer is located on the between the driving array substrate and the second semiconductor layer. The method for manufacturing a display panel according to claim 17, wherein the method for patterning the epitaxial stack comprises: patterning the reflective layer using an acid solution. The method for manufacturing a display panel according to claim 18, wherein the acid solution includes phosphoric acid, nitric acid or acetic acid. The method for manufacturing a display panel according to claim 12, wherein the method for removing the second substrate includes laser lift-off.

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