CN220796782U - Micro LED display chip - Google Patents

Abstract

The utility model discloses a Micro LED display chip. The display chip comprises a first chip and a second chip, wherein an N electrode of the first chip is connected with a P electrode of the second chip to form a series structure. The chip comprises a metal electrode, a passivation layer, an N-type gallium nitride layer, a multiple quantum well, a P-type gallium nitride layer, a transparent conductive layer and an oxide supporting layer from top to bottom in sequence. According to the utility model, two Micro LED chips form a serial structure, so that the Micro LED chips can bear higher working voltage. The oxide supporting layer is used for supporting the two Micro LED chips, so that the two chips can be prevented from being broken, and the subsequent bonding with the driving substrate is facilitated.

Description

Micro LED display chip

Technical Field

The utility model relates to the technical field of semiconductors, in particular to a Micro LED display chip.

Background

As a next-generation display, the Micro LED display has the advantages of low power consumption, quick response, high luminous efficiency and the like, and has larger advantages in the aspects of brightness, resolution, contrast ratio, energy consumption, service life, response speed, thermal stability and the like compared with the traditional LCD and OLED. In addition, micro-LEDs can be widely used in the fields of high performance display devices, AR, VR, smart phones/watches, high-end televisions, vehicle-mounted/on-board displays, flexible displays, and transparent displays.

In the prior art, in a manufacturing method (CN 114400276 a) of a high-voltage LED chip, a sapphire substrate PSS has an upper layer and a lower layer, the upper layer is silicon oxide SiO2, and the lower layer is sapphire Al2O3. Before patterning the sapphire Al2O3, depositing a layer of silicon oxide SiO2 on the sapphire Al2O3, then manufacturing a sapphire substrate PSS by dry etching, using the substrate to operate the high-voltage LED chip, etching the bridge isolation groove by inductively coupled plasma ICP, and then etching the sapphire substrate PSS to remove the silicon oxide SiO2 above the sapphire Al2O3.

In the prior art, a Micro-LED chip structure and a preparation method thereof (CN 116632034A) belong to the technical field of LED semiconductors. The Micro-LED chip structure comprises a plurality of Micro-LED chips distributed in an array, and is characterized by comprising a substrate, a Micro-LED main body and an active addressing driving circuit, wherein the Micro-LED main body comprises a Si doped n-type GaN layer, a multiple quantum well layer and a Mg doped p-type GaN layer which are sequentially deposited on the substrate from bottom to top; the Micro-LED main body is of a step structure with a step surface, and the step surface is the upper surface of the Si-doped n-type GaN layer; the Micro-LED main body further comprises a first metal layer which is separated by a first insulating layer and is respectively connected with the Si-doped n-type GaN layer and the Mg-doped p-type GaN layer; the active addressing driving circuit comprises a first transistor, a second transistor and a capacitor which are all arranged on the substrate, and the Micro-LED main body, the first transistor and the second transistor are sequentially distributed on the substrate; the pixel circuit of the Micro-LED main body is controlled to be turned on or off through the first transistor, the second transistor is communicated with a power supply and provides stable current for the Micro-LED main body in a specific pulse time period, and the capacitor for storing signals provides stable current for the Micro-LED main body after the pulse is ended, so that active addressing drives the Micro-LED main body.

In the prior art, a Micro-LED chip with full color display column and a manufacturing method thereof (CN 116564947A) are provided, wherein the chip sequentially comprises a red light chip layer, a filter layer, a green light chip layer, a sapphire substrate and a blue light chip layer from bottom to top; the red light chip layer, the green light chip layer and the blue light chip layer are longitudinally stacked and assembled from bottom to top. According to the utility model, three epitaxial structures of red light, green light and blue light are longitudinally stacked and assembled, the filter layer is arranged between the red light epitaxial layer and the green light epitaxial layer, the filter layer can reflect blue light and green light, and red light can be transmitted, so that the three epitaxial structures can independently emit light, and a longitudinally arranged full-color display Micro-LED is formed.

In the prior art, a Micro LED chip and a preparation method thereof (CN 116544263A). The method comprises the following steps: providing a substrate, growing a gallium nitride layer on the substrate, and etching the gallium nitride layer to periodically prepare a plurality of LED arrays; providing a filling layer, wherein the filling layer is flush with the surface of the LED array; providing a driving chip, and bonding the filling layer with the driving chip; removing the substrate and the redundant gallium nitride layer to form a wafer structure comprising a driving chip and an LED array; forming a light guiding layer on the wafer structure; a plurality of reflecting portions are etched on the light guiding layer to integrate the display positions of the LED array. Through the steps, the utility model etches the light guide layer to form the plurality of reflecting parts, and the light emitting direction of the LED arrays is changed through the reflecting action of the reflecting parts, so that the aim that the display positions of different LED arrays on the whole chip can be arranged according to the pixel arrangement requirement is fulfilled.

In the prior art, a Micro-LED chip and a manufacturing method thereof (CN 116137306A) comprise a P electrode, an N electrode, a passivation layer, a first semiconductor layer, a light-emitting layer, a second semiconductor layer and a GaAs substrate; the P electrode is on the first semiconductor layer and passes through the passivation layer; the first semiconductor layer consists of a GaP window layer and a P-AlGaInP limiting layer; the second semiconductor layer consists of an N-AlGaInP limiting layer, a GaAs contact layer, an N-AlGaInP current spreading layer and a GaAs sacrificial layer; the N electrode is arranged on the GaAs contact layer and penetrates through the passivation layer; after the GaAs sacrificial layer is removed, the second semiconductor layer and the GaAs substrate are in a hollowed-out state, and after the epitaxial layer is separated from the GaAs substrate, the epitaxial layer is connected with the GaAs substrate through a passivation layer at one side close to the P electrode; the passivation layer covers the surfaces of the chips except the P electrode and the N electrode, covers the side wall of the chip close to one side of the P electrode and is connected with the GaAs substrate, the side wall close to one side of the N electrode is exposed, and the passivation layer only covers the GaAs contact layer; the passivation layer is composed of polyimide.

Micro LED chips are difficult to operate at high voltages due to size and pitch limitations compared to large-sized LED chips. In addition, the Micro-LED chip and the driving substrate are electrically and physically connected through a flip-chip bonding process. In the conventional flip chip bonding technology, the substrate needs to be removed, so that the Micro LED cannot etch the isolation groove structure.

Disclosure of Invention

The present utility model aims to solve at least one of the technical problems existing in the prior art. Therefore, the utility model provides a Micro LED display chip.

The utility model provides a Micro LED chip serial structure which can bear higher working voltage.

The utility model provides a Micro LED display chip, which comprises a first chip and a second chip;

the first chip and the second chip comprise a transparent conductive layer, a P-type gallium nitride layer, a multiple quantum well and an N-type gallium nitride layer which are stacked from bottom to top; the first chip and the second chip are both positioned on the oxide supporting layer;

in the first chip and the second chip, N electrodes are deposited on the N-type gallium nitride layer, and P electrodes are deposited on the transparent conductive layer; passivation layers are deposited on the first chip and the second chip except for the positions where the N electrode and the P electrode are deposited;

the N electrode of the first chip is connected with the P electrode of the second chip.

Further, the oxide support layer includes a first oxide support layer and a second oxide support layer.

Further, the first oxide support layer is silicon dioxide.

Further, the second oxide support layer is silicon dioxide.

Further, the first oxide support layer and the second oxide support layer are used as support structures of the first chip and the second chip. The second oxide support layer is located on the first oxide support layer.

Further, the passivation layer is silicon dioxide.

The substrate used in the preparation of the first chip and the second chip is a sapphire substrate.

Further, the substrate comprises a first substrate and a second substrate; sequentially growing a gallium nitride layer and the first oxide support layer on the first substrate; and an N-type gallium nitride layer, a multiple quantum well, a P-type gallium nitride layer, a transparent conducting layer and a second oxide supporting layer are sequentially grown on the second substrate.

Further, the bonding of the first substrate and the second substrate is a silicon dioxide activated bonding.

Further, the Micro LED display chip can be manufactured by the following method, and specifically comprises the following steps:

s1, providing a first substrate, and sequentially growing a gallium nitride layer and a first oxide supporting layer on the first substrate;

s2, providing a second substrate, and sequentially growing an N-type gallium nitride layer, a multiple quantum well, a P-type gallium nitride layer, a transparent conductive layer and a second oxide supporting layer on the second substrate;

s3, bonding the first substrate and the second substrate through a first oxide supporting layer and a second oxide supporting layer;

s4, stripping the bonded second substrate to expose the N-type gallium nitride layer;

s5, etching the N-type gallium nitride layer to the transparent conductive layer, wherein the transparent conductive layer is partially etched to form a mesa structure, and the mesa structure comprises the transparent conductive layer, the P-type gallium nitride layer, the multiple quantum wells and the N-type gallium nitride layer which are stacked from bottom to top; deep trench etching the N-type gallium nitride layer to the second oxide supporting layer to form a first chip and a second chip;

s6, depositing passivation layers on the first chip and the second chip, and etching the passivation layers to open positions of N electrodes and P electrodes of the first chip and the second chip;

s7, depositing N electrodes and P electrodes of the first chip and the second chip at the opening of the passivation layer, wherein the N electrodes of the first chip are connected with the P electrodes of the second chip;

s8, stripping the first substrate to form a Micro LED display chip with a series structure, and taking the first oxide supporting layer and the second oxide supporting layer as supporting structures of the first chip and the second chip.

Further, the gallium nitride layer grown on the first substrate is an undoped gallium nitride thin layer.

Further, the first substrate and the second substrate are sapphire substrates.

Further, the bonding of the first substrate and the second substrate is a silicon dioxide activated bonding.

Further, the peeling of the second substrate and the peeling of the first substrate are laser peeling.

Further, the gallium nitride layer is decomposed in the process of peeling the first substrate; the first oxide supporting layer and the second oxide supporting layer are used as supporting structures of the first chip and the second chip.

Compared with the prior art, the utility model has the advantages that:

according to the utility model, two Micro LED chips are connected to form a serial structure, so that the Micro LED chip can bear higher working voltage. In order to facilitate subsequent bonding with the drive substrate, an oxide support layer is provided that enables etching of the isolation trench structure. The supporting layer structure effectively avoids the breakage of the two Micro LED chips in the bonding process, and improves the stability.

Drawings

Fig. 1 is a schematic diagram of a Micro LED chip according to an embodiment of the present utility model.

Fig. 2 is an epitaxial structure diagram of the LED chip in step S1 according to the embodiment of the present utility model;

fig. 3 is a schematic structural diagram of the LED chip in step S2 according to the embodiment of the present utility model;

fig. 4 is a schematic diagram of a bonding structure of an LED chip in step S3 according to an embodiment of the present utility model;

fig. 5 is a schematic structural diagram of the LED chip in step S4 according to the embodiment of the present utility model;

FIG. 6 is a schematic diagram of a mesa structure of an LED chip in step S5 according to an embodiment of the present utility model

Fig. 7 is a schematic structural diagram of the LED chip in step S6 according to the embodiment of the present utility model;

fig. 8 is a schematic structural diagram of the LED chip in step S7 according to the embodiment of the present utility model;

fig. 9 is a schematic three-dimensional structure diagram of the Micro LED chip in step S8 according to the embodiment of the present utility model.

Detailed Description

The utility model mainly realizes that two Micro LED chips are connected to form a serial structure through structure optimization, so that the Micro LED chip can bear higher working voltage, and the structure can be manufactured through the embodiment.

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the application, its application, or uses. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

In the description of the present utility model, it should be understood that references to orientation descriptions, such as directions of up, down, left, right, etc., are based on the orientation or positional relationship shown in the drawings, are merely for convenience of describing the present utility model, and do not indicate or imply that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present utility model.

It should be understood that, although the terms first, second, etc. may be used in one or more embodiments of the present specification to describe various information, these information should not be limited to these terms, these terms should be used merely to distinguish one from another and should not be used in order or sequence of features described in one or more embodiments of the present specification. Furthermore, the terms "comprises," "comprising," and "includes" are intended to cover a non-exclusive scope, e.g., a process, method, system, article, or apparatus that comprises a list of steps or modules is not necessarily limited to the details of those steps or modules, but may include inherent elements not expressly listed for such steps or modules.

Examples:

a Micro LED display chip, as shown in figure 1, comprises a first chip and a second chip;

the first chip and the second chip each include a transparent conductive layer 401, a P-type gallium nitride layer 203, a multiple quantum well 301, and an N-type gallium nitride layer 202 stacked from bottom to top; the first chip and the second chip are both positioned on the oxide supporting layer;

in the first chip and the second chip, N electrodes are deposited on the N-type gallium nitride layer 202, and P electrodes are deposited on the transparent conductive layer 401; passivation layers 503 are deposited on the first chip and the second chip except for the positions where the N electrode and the P electrode are deposited;

the N electrode of the first chip is connected with the P electrode of the second chip.

The method for preparing the Micro LED display chip comprises the following steps:

s1, as shown in fig. 2, providing a first substrate 101, and sequentially growing a gallium nitride layer 201 and a first oxide support layer 501 on the first substrate 101, as shown in fig. 3;

s2, providing a second substrate 102, and sequentially growing an N-type gallium nitride layer 202, a multi-quantum well 301, a P-type gallium nitride layer 203, a transparent conductive layer 401 and a second oxide supporting layer 502 on the second substrate 102, as shown in FIG. 3;

s3, bonding the first substrate 101 and the second substrate 102 through a first oxide support layer 501 and a second oxide support layer 502, as shown in fig. 4;

s4, stripping the bonded second substrate 102 to expose the N-type gallium nitride layer 202, as shown in FIG. 5;

s5, etching the N-type gallium nitride layer 202 to the transparent conductive layer 401, wherein the transparent conductive layer 401 is partially etched to form a mesa structure, and the mesa structure comprises the transparent conductive layer 401, the P-type gallium nitride layer 203, the multiple quantum well 301 and the N-type gallium nitride layer 202 which are stacked from bottom to top; deep trench etching the N-type gallium nitride layer 202 to the second oxide support layer 502 to form a first chip and a second chip, as shown in fig. 6;

in one embodiment, the etching is a dry etching.

S6, depositing a passivation layer 503 on the first chip and the second chip, and etching the passivation layer 503 to open positions of N electrodes and P electrodes of the first chip and the second chip, as shown in FIG. 7;

s7, depositing N electrodes and P electrodes of the first chip and the second chip at the opening of the passivation layer, wherein the N electrodes of the first chip are connected with the P electrodes of the second chip to realize electrical connection, as shown in FIG. 8;

s8, peeling the first substrate 101 to form a Micro LED display chip with a series structure, wherein a first oxide supporting layer 501 and a second oxide supporting layer 502 are used as supporting structures of the first chip and the second chip, as shown in FIG. 9.

In one embodiment, the gallium nitride layer 201 grown on the first substrate 101 is an undoped gallium nitride thin layer having a thickness of 10nm.

In one embodiment, the first oxide support layer 501 is silicon dioxide.

In one embodiment, the second oxide support layer 502 is silicon dioxide.

In one embodiment, the first substrate 101 and the second substrate 102 are sapphire substrates.

In one embodiment, the bonding of the first substrate 101 and the second substrate 102 is a silicon dioxide activated bonding.

In one embodiment, the peeling of the second substrate 102 and the peeling of the first substrate 101 is laser peeling.

In one embodiment, the gallium nitride layer 201 is decomposed during the peeling of the first substrate 101; the first oxide support layer 501 and the second oxide support layer 502 are used as support structures for the first chip and the second chip.

In one embodiment, the passivation layer 503 is silicon dioxide.

The embodiments of the present utility model have been described in detail with reference to the accompanying drawings, but the present utility model is not limited to the above embodiments, and various changes can be made within the knowledge of one of ordinary skill in the art without departing from the spirit of the present utility model. Furthermore, embodiments of the utility model and features of the embodiments may be combined with each other without conflict.

Claims (10)

1. The Micro LED display chip is characterized by comprising a first chip and a second chip;

the first chip and the second chip comprise a transparent conductive layer (401), a P-type gallium nitride layer (203), a multiple quantum well (301) and an N-type gallium nitride layer (202) which are stacked from bottom to top; the first chip and the second chip are both positioned on the oxide supporting layer;

in the first chip and the second chip, N electrodes are deposited on the N-type gallium nitride layer (202), and P electrodes are deposited on the transparent conductive layer (401); passivation layers (503) are deposited on the first chip and the second chip except for the positions where the N electrode and the P electrode are deposited;

the N electrode of the first chip is connected with the P electrode of the second chip.

2. The Micro LED display chip of claim 1, wherein the oxide support layer comprises a first oxide support layer (501) and a second oxide support layer (502).

3. A Micro LED display chip according to claim 2, characterized in that the first oxide support layer (501) is silicon dioxide.

4. The Micro LED display chip of claim 2, wherein the second oxide support layer (502) is silicon dioxide.

5. A Micro LED display chip according to claim 2, characterized in that the first oxide support layer (501) and the second oxide support layer (502) are used as support structures for the first chip and the second chip.

6. The Micro LED display chip of claim 5, wherein the second oxide support layer (502) is located on the first oxide support layer (501).

7. A Micro LED display chip according to claim 1, characterized in that the passivation layer (503) is silicon dioxide.

8. The Micro LED display chip of claim 2, wherein the substrate used in the preparation of the first chip and the second chip is a sapphire substrate.

9. The Micro LED display chip of claim 8, wherein said substrate comprises a first substrate (101) and a second substrate (102); sequentially growing a gallium nitride layer and the first oxide support layer (501) on the first substrate; and an N-type gallium nitride layer (202), a multiple quantum well (301), a P-type gallium nitride layer (203), a transparent conductive layer (401) and a second oxide supporting layer (502) are sequentially grown on the second substrate (102).

10. The Micro LED display chip of claim 9, wherein the bonding of the first substrate and the second substrate is silica activated bonding.