JP2016167512A - Semiconductor light emitting element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light emitting element which can improve breakdown voltage.SOLUTION: A semiconductor light emitting element 110 includes a substrate 70, first through third semiconductor layers 10, 20, 30, a first conductive layer 51 and an insulation layer 81. The substrate 70 is conductive. The first semiconductor layer 10 includes a first conductivity type region. The second semiconductor layer 20 is provided between the first semiconductor layer 10 and the substrate 70 and has a second conductivity type. The third semiconductor layer 30 is provided between the first semiconductor layer 10 and the second semiconductor layer 20. The first conductive layer 51 is provided between the second semiconductor layer 20 and the substrate 70 and electrically connected with the second semiconductor layer 20. The insulation layer 81 is provided between the substrate 70 and the first conductive layer 51; and electrically insulates the first conductive layer 51 and the substrate 70; and electrically insulates the first semiconductor layer 10 and the substrate 70.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a semiconductor light emitting device.

  In semiconductor light emitting devices such as light emitting diodes (LEDs), there is a demand for an improvement in dielectric strength.

Japanese Patent No. 4998773

  Embodiments of the present invention provide a semiconductor light emitting device capable of improving the withstand voltage.

  According to the embodiment of the present invention, the semiconductor light emitting device includes a base, first to third semiconductor layers, a first conductive layer, and an insulating layer. The substrate is conductive. The first semiconductor layer includes a region of a first conductivity type. The second semiconductor layer is provided between the first semiconductor layer and the base and has a second conductivity type. The third semiconductor layer is provided between the first semiconductor layer and the second semiconductor layer. The first conductive layer is provided between the second semiconductor layer and the base body and is electrically connected to the second semiconductor layer. The insulating layer is provided between the base and the first conductive layer, electrically insulates the first conductive layer and the base, and electrically insulates the first semiconductor layer and the base. To do.

FIG. 1A and FIG. 1B are schematic views illustrating the semiconductor light emitting element according to the first embodiment. 1 is a schematic cross-sectional view illustrating a part of a semiconductor light emitting element according to a first embodiment. FIG. 3A to FIG. 3F are schematic cross-sectional views in order of the processes, illustrating the method for manufacturing the semiconductor light emitting element according to the first embodiment. 1 is a schematic cross-sectional view illustrating a light emitting device using a semiconductor light emitting element according to a first embodiment. FIG. 5A and FIG. 5B are schematic views illustrating another semiconductor light emitting element according to the first embodiment. FIG. 6 is a schematic cross-sectional view illustrating a semiconductor light emitting element according to a second embodiment. FIG. 6 is a schematic cross-sectional view illustrating a semiconductor light emitting element according to a third embodiment. FIG. 8A and FIG. 8B are schematic views illustrating the method for manufacturing the semiconductor light emitting element according to the third embodiment. FIG. 9A to FIG. 9F are schematic cross-sectional views illustrating other semiconductor light emitting elements according to the third embodiment. FIG. 6 is a schematic cross-sectional view illustrating another semiconductor light emitting element according to the third embodiment. 1 is a schematic cross-sectional view illustrating a part of a semiconductor light emitting element according to an embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(First embodiment)
FIG. 1A and FIG. 1B are schematic views illustrating the semiconductor light emitting element according to the first embodiment.
FIG. 1B is a plan view seen from the direction of the arrow AA shown in FIG. FIG. 1A is a cross-sectional view taken along line A1-A2 of FIG. In FIG. 1B, a state in which some elements are seen through is indicated by a broken line.

  As shown in FIGS. 1A and 1B, the semiconductor light emitting device 110 according to this embodiment includes a base body 70, a first semiconductor layer 10, a second semiconductor layer 20, and a third semiconductor layer 30. And a first conductive layer 51 and an insulating layer 81.

  The base 70 is conductive. As the base body 70, for example, a semiconductor substrate such as Si is used. A substrate containing metal may be used as the base 70.

The first semiconductor layer 10 includes a first conductivity type region.
The second semiconductor layer 20 is provided between the first semiconductor layer 10 and the base body 70. The second semiconductor layer 20 is of the second conductivity type.

  For example, the first conductivity type is n-type and the second conductivity type is p-type. The first conductivity type may be p-type and the second conductivity type may be n-type. In the following example, the first conductivity type is n-type, and the second conductivity type is p-type.

  The third semiconductor layer 30 is provided between the first semiconductor layer 10 and the second semiconductor layer 20. The third semiconductor layer 30 is an active layer. The third semiconductor layer 30 is, for example, a light emitting unit. An example of the third semiconductor layer 30 will be described later.

  A direction from the second semiconductor layer 20 toward the first semiconductor layer 10 is taken as a Z-axis direction. The Z-axis direction is a direction in which the second semiconductor layer 20 and the first semiconductor layer 10 are stacked. One direction perpendicular to the Z-axis direction is taken as an X-axis direction. A direction perpendicular to the Z-axis direction and the X-axis direction is taken as a Y-axis direction.

  A direction from the base body 70 toward the second semiconductor layer 20 is defined as a first direction D1. The first direction D1 is along the Z-axis direction. The first direction D1 is substantially parallel to the Z-axis direction.

  The first semiconductor layer 10, the second semiconductor layer 20, and the third semiconductor layer 30 include, for example, a nitride semiconductor.

  The first semiconductor layer 10, the second semiconductor layer 20, and the third semiconductor layer 30 are included in the stacked body 15. The stacked body 15 extends along the XY plane.

  The first conductive layer 51 is provided between the second semiconductor layer 20 and the base body 70. The first conductive layer 51 is electrically connected to the second semiconductor layer 20.

  In the present specification, the electrically connected state includes a state in which the first conductor and the second conductor are in direct contact. Further, in the electrically connected state, the third conductor is inserted between the first conductor and the second conductor, and a current flows between the first conductor and the second conductor via the third conductor. Includes state.

  The first conductive layer 51 is light reflective. At least a part of the first conductive layer 51 is in ohmic contact with the second semiconductor layer 20.

  The insulating layer 81 is provided between the base body 70 and the first conductive layer 51. The insulating layer 81 electrically insulates the first conductive layer 51 and the base body 70. The insulating layer 81 electrically insulates the first semiconductor layer 10 and the base body 70.

  In this example, the semiconductor light emitting device 110 is provided with a first pad 45 and a second pad 55.

  The first semiconductor layer 10 is disposed between the first pad 45 and the third semiconductor layer 30. The first pad 45 is electrically connected to the first semiconductor layer 10. When the first semiconductor layer 10 is an n-type semiconductor, the first pad 45 is an n-side pad.

  As shown in FIG. 1B, in this example, a linear electrode 46 is provided. The electrode 46 is connected to the first pad 45. The first semiconductor layer 10 is disposed between the electrode 46 and the third semiconductor layer 30. The electrode 46 has, for example, a function of spreading current.

  For example, a part of the first conductive layer 51 (first conductive portion 51 a) is disposed between the second semiconductor layer 20 and the base body 70. Another part (second conductive portion 51 b) of the first conductive layer 51 is disposed between the second pad 55 and the base body 70. The second pad 55 is electrically connected to another part (second conductive portion 51 b) of the first conductive layer 51.

  In this example, the first conductive layer 51 has a laminated film configuration. That is, the first conductive layer 51 includes a first metal region 51p and a second metal region 51q. The first metal region 51p is provided between a part 51qa of the second metal region 51q and the second semiconductor layer 20. The part of the first conductive layer (first conductive part 51a) includes the first metal region 51p and the part 51qa of the second metal region 51q. On the other hand, the other part (second conductive part 51b) of the first conductive layer 51 includes another part 51qb of the second metal region 51q.

  The first metal region 51 p of the first conductive layer 51 is in ohmic contact with the second semiconductor layer 20. The second metal region 51q in the first conductive layer 51 covers, for example, the first metal region 51p and protects the first metal region 51p. The second metal region 51q has a function of spreading the current. A second pad 55 is provided on the other part 51qb of the second metal region 51q.

  At least a part of the second pad 55 overlaps at least a part of the stacked body 15 in a direction (for example, the second direction D2) intersecting the first direction D1 (for example, the Z-axis direction). For example, at least part of the second pad 55 overlaps with at least part of the second semiconductor layer 20 in the second direction. At least a part of the second pad 55 may overlap with at least a part of the third semiconductor layer 30 in the second direction. At least a part of the second pad 55 may overlap with at least a part of the first semiconductor layer 10 in the second direction D2.

  In this example, the semiconductor light emitting device 110 is further provided with a metal layer 73 and a metal film 71.

  The metal layer 73 is provided between the base body 70 and the insulating layer 81. For example, the metal layer 73 bonds the stacked body 15, the first conductive layer 51, and the base body 70. The metal layer 73 is, for example, a bonding layer.

  The base body 70 is provided between the metal film 71 and the metal layer 73 (that is, between the metal film 71 and the first conductive layer 51). As will be described later, the metal film 71 is used, for example, as a mounting portion when the semiconductor light emitting element 110 is mounted.

  Thus, in the semiconductor light emitting device 110, the base body 70 is provided on the metal film 71. A metal layer 73 is provided on the substrate 70. A second metal region 51q is provided on part of the metal layer 73. The first metal region 51p, the second semiconductor layer 20, the third semiconductor layer 30, the first semiconductor layer 10, and the first pad 45 are provided in this order on the part 51qa of the second metal region 51q. . A second pad 55 is provided on the other part 51qb of the second metal region 51q.

  A voltage is applied between the first pad 45 and the second pad 55. Current is supplied from these pads, and light is emitted from the stacked body 15 (specifically, the third semiconductor layer 30).

  The semiconductor light emitting device 110 is an LED. The light (emitted light) emitted from the third semiconductor layer 30 is reflected by the first conductive layer 51 and emitted to the outside of the semiconductor light emitting device 110. The surface of the first semiconductor layer 10 becomes a light emitting surface.

  For example, the semiconductor light emitting device 110 is a thin film type LED. As will be described later, in the semiconductor light emitting device 110, after the crystal of the stacked body 15 is grown on the growth substrate, the stacked body 15 is bonded to the base body 70. Then, the growth substrate is removed. The growth substrate is thick and the growth substrate has a large heat capacity. In the semiconductor light emitting device 110, since the growth substrate is removed, the heat capacity of the semiconductor light emitting device 110 can be reduced and the heat dissipation can be improved.

  In the semiconductor light emitting device 110, the conductive substrate 70 is insulated from the n-side conductor (the first pad 45 and the first semiconductor layer 10). The conductive substrate 70 is insulated from the p-side conductor (second pad 55, first conductive layer 51, and second semiconductor layer 20).

  For this reason, for example, even when a high voltage (voltage due to static electricity or the like) is applied to the base body 70, the high voltage can be prevented from flowing into the n-side conductor or the p-side conductor. It can be suppressed that the crystal of the laminated body 15 is damaged by such a high voltage. In the semiconductor light emitting device 110, the withstand voltage can be improved.

  For example, when the semiconductor light emitting device 110 is used, the lower surface of the base body 70 (in this example, the metal film 71) is disposed so as to face the mounting substrate. Since the base body 70 is insulated from the n-side conductor and the p-side conductor, it is possible to suppress a short circuit between the conductor and the mounting substrate via the base body 70 in use. According to the embodiment, the withstand voltage during use can be improved.

  For example, as a thin film type LED, there is a first reference example in which an n-type semiconductor layer is electrically connected to a base. As a thin film type LED, there is a second reference example in which a p-type semiconductor layer is electrically connected to a base. In these reference examples, a high voltage tends to flow through the n-side conductor or the p-side conductor, and the insulation resistance may be low.

  As a third reference example, there is a face-up type LED. In this reference example, an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer are sequentially formed on a sapphire growth substrate, and a part of the light-emitting layer and the p-type semiconductor layer is removed. An n-side pad is provided on a part of the n-type semiconductor layer, and a p-side pad is provided on the p-type semiconductor layer. In this reference example, the reflective conductive layer is not provided under the n-type semiconductor layer, and the emitted light passes through the growth substrate and is emitted to the outside from the side surface of the growth substrate. For this reason, the light utilization efficiency is low unless special measures are taken on the package side where the LED is mounted. The heat generated in the semiconductor layer is conducted to the outside through the growth substrate having low thermal conductivity. For this reason, heat dissipation is low and efficiency is inadequate.

  On the other hand, in the semiconductor light emitting device 110 according to the embodiment, since the growth substrate is removed, light does not enter the substrate, and light loss can be suppressed. Since substantially all of the emitted light is emitted from the surface of the first semiconductor layer 10, the loss of light is reduced by forming a structure on the surface of the first semiconductor layer 10 that increases the light extraction efficiency. Can do. Since the light emission region is substantially limited to the surface of the first semiconductor layer 10, the emitted light can be easily controlled.

  In the embodiment, a conductive substrate 70 is used. The conductive substrate 70 has a high thermal conductivity. The heat generated in the laminated body 15 can be efficiently transferred to the mounting substrate or the like through the base body 70, and high heat dissipation is obtained. At this time, since the conductive base 70 is insulated from the n-side and p-side conductors, a high withstand voltage is obtained.

  In this example, unevenness 10 dp is provided on the light emitting surface of the first semiconductor layer 10. That is, the first semiconductor layer 10 has a first surface 10a and a second surface 10b. The first surface 10 a is a surface on the third semiconductor layer 30 side. The first surface 10 a faces the third semiconductor layer 30. The second surface 10b is a surface opposite to the first surface 10a. The second surface 10b is a light exit surface.

  The height (depth) of the unevenness 10 dp is, for example, not less than 0.5 times and not more than 30 times the peak wavelength. The height (depth) of the unevenness 10 dp is, for example, not less than 0.2 micrometers (μm) and not more than 2 μm. By providing the unevenness 10 dp, light can be efficiently extracted from the stacked body 15. The width of the convex portion of the unevenness 10 dp in the direction perpendicular to the first direction D1 (for example, the second direction D2) is, for example, not less than 0.5 times and not more than 30 times the peak wavelength. The intensity of light emitted from the third semiconductor layer 30 substantially reaches a peak (maximum) at the peak wavelength.

  In the semiconductor light emitting device 110, since the growth substrate is removed, the distance between the upper surface of the first semiconductor layer 10 (light emitting surface, that is, the second surface 10b) and the first conductive layer 51 is short.

  For example, the distance t15 between the first conductive layer 51 and the second surface 10b of the first semiconductor layer 10 is not less than 1.5 μm and not more than 30 μm. With the configuration in which the growth substrate is removed, the distance t15 can be shortened in this way.

  For example, the distance t15 is the shortest distance between the first conductive layer 51 and the second surface 10b. When the unevenness 10 dp is provided, the distance t15 corresponds to the distance between the bottom of the unevenness 10 dp and the first conductive layer 51. In this example, the distance t15 corresponds to the distance (shortest distance) between the first pad 45 and the first conductive layer 51.

  In the semiconductor light emitting device 110, an insulating film 87 is further provided. The insulating film 87 is provided on the side surface of the stacked body 15. The insulating film 87 covers the side surface of the stacked body 15. The side surface of the stacked body 15 is a surface that intersects the XY plane. The insulating film 87 can suppress the current flowing through the side surface of the stacked body 15 and can improve the withstand voltage. And high reliability is obtained. The insulating film 87 includes, for example, silicon oxide. The insulating film 87 is formed by plasma CDV (Chemical Vapor Deposition), for example.

  The first metal region 51p of the first conductive layer 51 includes, for example, at least one of silver and rhodium. The first metal region 51p may include a silver alloy. A silver layer, a rhodium layer, or a silver alloy layer is used as the first metal region 51p. Thereby, a high light reflectance is obtained. A low contact resistance is obtained between the first metal region 51p and the second semiconductor layer 20. The first metal region 51p may include aluminum.

  The second metal region 51q is, for example, reflective. Second metal region 51q contains at least one of silver and aluminum.

  The insulating layer 81 includes, for example, an oxide including at least one selected from the group consisting of silicon, aluminum, zirconium, hafnium, and titanium. The insulating layer 81 may include, for example, a nitride including at least one selected from the above group. The insulating layer 81 may include oxynitride including at least one selected from the above group. The insulating layer 81 includes, for example, at least one of silicon oxide and silicon nitride. When silicon oxide is used for the insulating layer 81, light absorption is small. And high reliability is obtained. When silicon nitride is used as the insulating layer 81, high thermal conductivity is obtained. And a low thermal resistance is obtained.

  When the insulating layer 81 includes silicon oxide, the thickness of the insulating layer 81 is 0.1 μm or more and 3 μm or less. When the thickness of the silicon oxide layer exceeds 3 μm, the heat dissipation becomes worse. When the insulating layer 81 includes silicon nitride, the thickness of the insulating layer 81 is 0.1 μm or more and 20 μm or less. When the thickness of the silicon oxide layer exceeds 20 μm, the heat dissipation becomes worse.

  The first pad 45 includes, for example, an Al film, a Ni film, and an Au film. A Ni film is provided between the Au film and the first semiconductor layer 10. An Al film is provided between the Ni film and the first semiconductor layer 10.

  The metal film 71 includes, for example, at least one of Ni and Ti. The metal film 71 includes, for example, a Ni film 71a and a Ti film 71b. The Ti film 71 b is provided between the Ni film 71 a and the base body 70.

FIG. 2 is a schematic cross-sectional view illustrating a part of the semiconductor light emitting element according to the first embodiment. FIG. 2 illustrates the laminate 15.
As shown in FIG. 2, the third semiconductor layer 30 includes a plurality of barrier layers 31 and a well layer 32 provided between the plurality of barrier layers 31. For example, the plurality of barrier layers 31 and the plurality of well layers 32 are alternately arranged along the Z-axis direction.

The well layer 32 includes, for example, Al _x1 Ga _1-x1-x2 In _x2 N (0 ≦ x1 ≦ 1, 0 ≦ x2 ≦ 1, x1 + x2 ≦ 1). The barrier layer 31 includes Al _y1 Ga _1-y1-y2 In _y2 N (0 ≦ y1 ≦ 1, 0 ≦ y2 ≦ 1, y1 + y2 ≦ 1). The band gap energy in the barrier layer 31 is larger than the band gap energy in the well layer 32.

  For example, the third semiconductor layer 30 has a single quantum well (SQW) configuration. At this time, the third semiconductor layer 30 includes two barrier layers 31 and a well layer 32 provided between the barrier layers 31.

  For example, the third semiconductor layer 30 may have a multiple quantum well (MQW) configuration. At this time, the third semiconductor layer 30 includes three or more barrier layers 31 and a well layer 32 provided between the barrier layers 31.

  The peak wavelength of light (emitted light) emitted from the third semiconductor layer 30 is, for example, 210 nanometers (nm) or more and 780 nm or less. In the embodiment, the peak wavelength is arbitrary.

In this example, the first semiconductor layer 10 includes a first conductivity type region 11 (for example, an n-type semiconductor layer) and a low impurity concentration region 12. A region 11 of the first conductivity type is provided between the third semiconductor layer 30 and the low impurity concentration region 12. The impurity concentration in the low impurity concentration region 12 is lower than the impurity concentration in the first conductivity type region 11. The impurity concentration in the low impurity concentration region 12 is, for example, 1 × 10 ¹⁷ cm ⁻³ or less.

  For the first conductivity type region 11 of the first semiconductor layer 10, for example, a GaN layer containing an n-type impurity is used. As the n-type impurity, at least one of Si, O, Ge, Te, and Sn is used. The region 11 of the first conductivity type includes, for example, an n-side contact layer.

  For the low impurity concentration region 12, for example, a non-doped GaN layer is used. The low impurity concentration region 12 may include a nitride semiconductor (AlGaN or AlN) containing Al. These GaN layer, AlGaN layer, or AlN layer may include, for example, a buffer layer used for crystal growth of the semiconductor layer.

  For example, a GaN layer containing p-type impurities is used for the second semiconductor layer 20. As the p-type impurity, at least one of Mg, Zn, and C is used. The second semiconductor layer 20 includes, for example, a p-side contact layer.

The thickness of the region 11 of the first conductivity type is, for example, not less than 100 nm and not more than 10000 nm. The thickness of the low impurity concentration region 12 is, for example, not less than 1 nm and not more than 10,000 nm.
The thickness of the first semiconductor layer 10 is, for example, not less than 100 nm and not more than 20000 nm.
The thickness of the second semiconductor layer 20 is, for example, not less than 10 nm and not more than 5000 nm.
The thickness of the third semiconductor layer 30 is, for example, not less than 0.3 nm and not more than 1000 nm.
The thickness of the barrier layer 31 is, for example, not less than 0.1 nm and not more than 500 nm.
The thickness of the well layer 32 is, for example, not less than 0.1 nm and not more than 100 nm.

Hereinafter, an example of a method for manufacturing the semiconductor light emitting device 110 will be described.
FIG. 3A to FIG. 3F are schematic cross-sectional views in order of the processes, illustrating the method for manufacturing the semiconductor light emitting element according to the first embodiment.

  As shown in FIG. 3A, a low impurity concentration film 12f is formed on a substrate 18 (growth substrate). The low impurity concentration film 12f includes, for example, a buffer film (for example, a laminated film of a nitride semiconductor film containing Al). The low impurity concentration film 12f may further include a non-doped nitride semiconductor film (such as a non-doped GaN layer). A first semiconductor film 11f is formed on the low impurity concentration film 12f. The first semiconductor film 11 f becomes at least a part of the first semiconductor layer 10. At least a part of the low impurity concentration film 12 f may be at least a part of the first semiconductor layer 10. An active film 30f to be the third semiconductor layer 30 is formed on the first semiconductor film 11f. A second semiconductor film 20f to be the second semiconductor layer 20 is formed on the active film 30f. Thereby, the laminated film 15f is obtained.

  In the formation of these films, epitaxial crystal growth is performed. For example, Metal-Organic Chemical Vapor Deposition (MOCVD) method, Metal-Organic Vapor Phase Epitaxy (MOVPE) method, Molecular Beam Epitaxy (MBE) method, and A halide vapor phase epitaxy (HVPE) method or the like is used.

For the substrate 18, for example, any one of Si, SiO ₂ , AlO ₂ , quartz, sapphire, GaN, SiC, and GaAs is used. The substrate 18 may be a combination of them. The plane orientation of the substrate 18 is arbitrary.

  As shown in FIG. 3B, a first metal region 51p having a predetermined shape is formed on the second semiconductor film 20f. The first metal region 51p is, for example, a silver film. The thickness of this silver film is, for example, about 200 nm (for example, 150 nm or more and 250 nm or less). After the formation of the silver film, for example, heat treatment (sinter treatment) is performed in an atmosphere containing oxygen. The ratio of oxygen in the atmosphere is, for example, 0.1% or more and 100% or less. The ratio of the inert gas (for example, nitrogen) in the atmosphere containing oxygen is 0% or more and 99.9% or less. The temperature of the heat treatment is, for example, about 400 ° C. (eg, 350 ° C. or higher and 450 ° C. or lower).

  A second metal region 51q is formed on the first metal region 51p (silver film) and on the second semiconductor layer 20. For example, a metal laminated film is formed as the second metal region 51q. The metal laminated film is, for example, Ti / Pt / Au / Ti. The metal laminated film has a thickness of 1 μm, for example.

  An insulating layer 81 is formed thereon. Further, a metal film 73 a that becomes a part of the metal layer 73 is formed. Thereby, the structure 15fs is formed.

  For example, as the metal film 73a, a first Pt film, a first Ti film, a second Pt film, a second Ti film, and a first AuSn film are formed in this order. These films are formed by sputtering, for example. A second Ti film is provided between the first AuSn film and the first conductive layer 51. A second Pt film is provided between the second Ti film and the first conductive layer 51. A first Ti film is provided between the second Pt film and the first conductive layer 51. A first Pt film is provided between the first Ti film and the first conductive layer 51. The thickness of the metal film 73a is, for example, about 2 μm (for example, 1.5 μm or more and 2.5 μm or less).

  As shown in FIG. 3C, a counter substrate 75 is prepared. The counter substrate 75 includes a base body 70 and a metal film 73 b provided on the upper surface of the base body 70. The metal film 73b includes a third Ti film, a third Pt film, a fourth Ti film, and a second AuSn film. A fourth Ti film is provided between the second AuSn film and the substrate 70. A third Pt film is provided between the fourth Ti film and the base body 70. A third Ti film is provided between the third Pt film and the base body 70. The thickness of the metal film 73b is, for example, about 2 μm (for example, 1.5 μm or more and 2.5 μm or less). The thickness of the substrate 70 is, for example, about 700 μm (for example, 500 μm or more and 1000 μm or less).

  The structure body 15fs and the counter substrate 75 are disposed in contact with the metal film 73b and the metal film 73a. By heating in this state, the metal film 73b and the metal film 73a are melted and bonded. The heating temperature is, for example, 220 ° C. or more and 300 ° C. or less (for example, about 280 ° C.). The heating time is, for example, 3 minutes to 10 minutes (for example, about 5 minutes).

  As shown in FIG. 3D, the substrate 18 is removed. For example, when the substrate 18 is a silicon substrate, grinding and dry etching (for example, RIE: Reactive Ion Etching) are used for the removal. For example, when the substrate 18 is a sapphire substrate, LLO (Laser Lift Off) or the like is used for removal. In this example, at least a part of the low impurity concentration film 12f remains. The surface of the low impurity concentration film 12f is exposed. In the embodiment, the low impurity concentration film 12f may be removed. In this case, the surface of the first semiconductor film 11f is exposed.

  As shown in FIG. 3E, unevenness 10dp is formed on the surface of the low impurity concentration film 12f or the surface of the first semiconductor film 11f. For example, the unevenness 10 dp is formed by wet treatment using an acid.

  A part of the laminated film 15f is removed. For example, RIE or wet etching is used for the removal. A laminated body 15 is obtained from the laminated film 15f. That is, the first semiconductor layer 10, the second semiconductor layer 20, and the third semiconductor layer 30 are formed. The second conductive portion 51b (corresponding to a part of the second metal region 51q) of the first conductive layer 51 is exposed.

  Thereafter, an insulating film 87 (for example, a silicon oxide film) is formed by, for example, CVD (Chemical Vapor Deposition). The thickness of the silicon oxide film is, for example, about 100 nm (for example, not less than 50 nm and not more than 200 nm).

  As shown in FIG. 3F, a part of the silicon oxide film is removed, and a first pad 45 and a second pad 55 are formed in a region exposed by the removal. For example, the first pad 45 is formed on the first semiconductor layer 10. A second pad 55 is formed on the second conductive portion 51 b of the first conductive layer 51.

  Further, a metal film 71 is formed on the lower surface (back surface) of the base body 70. The metal film 71 includes, for example, a Ni film and a Ti film. A Ti film is provided between the Ni film and the substrate 70. The metal film 71 may be provided on the counter substrate 75 in the state shown in FIG.

The wafer is divided into predetermined shapes. Thereby, the semiconductor light emitting device 110 is obtained.
In the above manufacturing process, the processing order may be changed within a technically possible range. An annealing treatment may be performed as appropriate.

  For example, a plurality of semiconductor light emitting elements can be obtained by forming a laminated body to be a plurality of semiconductor light emitting elements on one wafer and dividing it. The passivation (insulating film 87) on the divided dicing street may be removed. Thereby, the crack of a passivation can be suppressed and a yield improves.

  If necessary, a process of reducing the thickness of the base body 70 (for example, a silicon substrate) may be performed. For example, the thickness of the base body 70 is set to, for example, about 150 μm (for example, 100 μm or more and 200 μm or less) by a process such as grinding. The heat capacity can be further reduced.

FIG. 4 is a schematic cross-sectional view illustrating a light emitting device using the semiconductor light emitting element according to the first embodiment.
As shown in FIG. 4, the light emitting device 220 according to the embodiment includes a first semiconductor light emitting element 110, a second semiconductor light emitting element 110 </ b> A, and a mounting substrate 160. The second semiconductor light emitting element 110 </ b> A has a configuration similar to that of the first semiconductor light emitting element 110.

  That is, the second semiconductor light emitting element 110A includes a conductive base 70A, a fourth semiconductor layer 10A including a first conductivity type region, and a second semiconductor layer 10A provided between the fourth semiconductor layer 10A and the base 70A. It includes a fifth semiconductor layer 20A of conductive type, a sixth semiconductor layer 30A provided between the fourth semiconductor layer 10A and the fifth semiconductor layer 20A, a conductive layer 51A, and an insulating layer 81A. The conductive layer 51A is provided between the fifth semiconductor layer 20A and the base body 70A, and is electrically connected to the fifth semiconductor layer 20A. The fourth semiconductor layer 10A, the fifth semiconductor layer 20A, and the sixth semiconductor layer 30A are included in the stacked body 15A. The insulating layer 81A is provided between the base body 70A and the conductive layer 51A. The insulating layer 81A electrically insulates the conductive layer 51A and the base body 70A, and electrically insulates the fourth semiconductor layer 10A and the base body 70A.

  The second semiconductor light emitting device 110A includes a third pad 45A, a fourth pad 55A, a metal layer 73A, and a metal film 71A. The configurations of the third pad 45A, the fourth pad 55A, the metal layer 73A, and the metal film 71A are the same as the configurations of the first pad 45, the second pad 55, the metal layer 73, and the metal film 71. Omitted.

  The mounting substrate 160 includes a conductive substrate 160s, a first mounting electrode 162, a second mounting electrode 162A, a first mounting electrode insulating layer 161, and a second mounting electrode insulating layer 161A. The first mounting electrode insulating layer 161 and the second mounting electrode insulating layer 161A are provided on the substrate 160s. The first mounting electrode 162 is provided on the first mounting electrode insulating layer 161. The second mounting electrode 162A is provided on the second mounting electrode insulating layer 161A. The first mounting electrode 162 and the second mounting electrode 162A are, for example, metal films.

  The first semiconductor light emitting device 110 is disposed on a part of the substrate 160s. A bonding member 163 is provided between a part of the substrate 160s and the metal film 71.

  The second semiconductor light emitting element 110A is disposed on another part of the substrate 160s. A joining member 163A is provided between another part of the substrate 160s and the metal film 71A.

  In this manner, the semiconductor light emitting devices 110 and 110A are mounted on the mounting substrate 160. The joining members 163 and 163A include, for example, a metal such as solder. The joining members 163 and 163A may include, for example, a conductive or insulating resin (adhesive).

  For example, the first pad 45 and the first mounting electrode 162 are connected by the wiring 152. The fourth pad 55A and the second mounting electrode 162A are connected by the wiring 153. The second pad 55 and the third pad 45A are connected by the wiring 151. That is, two semiconductor light emitting elements are connected in series.

  In the semiconductor light emitting element 110 and the semiconductor light emitting element 110A, since the conductive base is insulated from the semiconductor layer, the potentials of these bases are independent of these semiconductor layers. For example, even when a plurality of semiconductor light emitting elements are mounted on the substrate 160s, normal operation of the semiconductor light emitting elements can be maintained.

  For example, in the above third reference example including an insulating growth substrate (such as a sapphire substrate), a plurality of semiconductor light emitting elements are arranged on a conductive substrate 160s, and these semiconductor light emitting elements are connected in series. Even normal operation can be obtained. However, as already described, the third reference example has a large light loss and low heat dissipation.

  On the other hand, in a general thin film type semiconductor light emitting device, the base is electrically connected to an n-type semiconductor layer or a p-type semiconductor layer. In this case, if a plurality of semiconductor light emitting elements are arranged on the conductive substrate 160s and connected in series, normal operation cannot be obtained.

  On the other hand, in the semiconductor light emitting device according to this embodiment, the base body 70 is insulated from the semiconductor layer. Therefore, even when a plurality of semiconductor light emitting elements are arranged on the conductive substrate 160s and connected in series, normal operation can be obtained. That is, it is possible to obtain a semiconductor light emitting device that can be mounted on the mounting substrate 160 and connected in series while obtaining high heat dissipation and high efficiency characteristics. According to the embodiment, the application of the semiconductor light emitting device can be expanded.

  In the example shown in FIG. 4, when the substrate 160s is insulative, a mounting metal layer is provided on the substrate 160s. The first semiconductor light emitting device 110 and the second semiconductor light emitting device 110A may be disposed on the metal layer. Even in this case, normal operation can be obtained even when connected in series.

FIG. 5A and FIG. 5B are schematic views illustrating another semiconductor light emitting element according to the first embodiment.
FIG. 5B is a plan view seen from the direction of the arrow AA shown in FIG. FIG. 5A is a cross-sectional view taken along line B1-B2 of FIG. In FIG. 5B, a state in which some elements are seen through is indicated by a broken line.

  As shown in FIGS. 5A and 5B, another semiconductor light emitting device 111 according to the present embodiment includes a base body 70, a first semiconductor layer 10, a second semiconductor layer 20, and a third semiconductor. The layer 30, the first conductive layer 51, and the insulating layer 81 are included. Since these configurations are the same as those of the semiconductor light emitting device 110, description thereof is omitted.

  The semiconductor light emitting device 111 further includes a first pad 45 and a second pad 55. The semiconductor light emitting device 111 further includes a second conductive layer 42.

  The first semiconductor layer 10 includes a first semiconductor region 10p and a second semiconductor region 10q. The second semiconductor region 10q is aligned with the first semiconductor region 10p in a direction (for example, the second direction D2) that intersects the first direction D1 (for example, the Z-axis direction).

  The first conductive layer 51 is disposed between the base body 70 and the second semiconductor region 10q. A part of the first conductive layer 51 (first conductive portion 51a) is disposed between the base body 70 and the second semiconductor region 10q. The part of the first conductive layer 51 (first conductive portion 51a) is electrically connected to the second semiconductor region 10q. Also in this case, another part (second conductive portion 51 b) of the first conductive layer 51 is disposed between the second pad 55 and the base body 70.

  At least a part of the second pad 55 of the stacked body 15 including the first semiconductor layer 10, the third semiconductor layer 30, and the second semiconductor layer 20 in a direction intersecting the first direction D1 (for example, the second direction D2). At least partly overlaps.

  A part of the second conductive layer 42 (second conductive portion 42a) is disposed between the base body 70 and the first semiconductor region 10p. The part of the second conductive layer 42 (third conductive portion 42a) is electrically connected to the first semiconductor region 10p. The second conductive layer 42 is a contact electrode connected to the first semiconductor layer 10. The second conductive layer 42 has, for example, a thin line shape. The second conductive layer 42 has a function of spreading current.

  Another portion (fourth conductive portion 42 b) of the second conductive layer 42 is disposed between the first pad 45 and the base body 70. The first pad 45 is electrically connected to the other part (fourth conductive portion 42 b) of the second conductive layer 42. That is, the first pad 45 is electrically connected to the first semiconductor region 10 p of the first semiconductor layer 10 through the second conductive layer 42.

  The second conductive layer 42 is, for example, reflective. The second conductive layer 42 includes, for example, at least one of silver and aluminum. The second conductive layer 42 is in ohmic contact with the first semiconductor region 10p.

  At least a part of the first pad 45 has a first semiconductor layer 10, a third semiconductor layer 30, and a second semiconductor layer in a direction (for example, the second direction D2) that intersects the first direction D1 (for example, the Z-axis direction). It overlaps with at least a part of the laminate 15 including 20.

  Also in this example, a metal layer 73 is provided. The metal layer 73 is provided between the base body 70 and the insulating layer 81.

  That is, in the semiconductor light emitting element 111, the arrangement of the second conductive layer 42 and the first pad 45 is different from those in the semiconductor light emitting element 110.

  Also in the semiconductor light emitting device 111, the first conductive layer 51 and the base 70 are electrically insulated by the insulating layer 81, and the second conductive layer 42 (first semiconductor layer 10) and the base 70 are electrically insulated. The Also in the semiconductor light emitting element 111, the withstand voltage can be improved. Normal operation can also be obtained when a plurality of semiconductor light emitting elements 111 are arranged on a conductive substrate 160s and connected in series. A semiconductor light emitting device that can be connected in series and mounted while obtaining high heat dissipation and high efficiency characteristics can be obtained. Applications of semiconductor light emitting devices can be expanded.

  For each element included in the semiconductor light emitting element 111, the configuration (material, thickness, etc.) described with respect to the semiconductor light emitting element 110 can be applied. For example, the semiconductor light emitting element 111 can be formed by forming the second conductive layer 42 in the process described with reference to FIG.

  As shown in FIG. 5, a part of the first conductive layer 51 (second metal region 51q) overlaps the second conductive layer 42 in the Z-axis direction. Thereby, the light emitted from the semiconductor layer can be efficiently reflected by these conductive layers, and the loss of light can be suppressed.

  In the semiconductor light emitting device 111, the distance t15 between the first conductive layer 51 and the second surface 10b) of the first semiconductor layer 10 is not less than 1.5 μm and not more than 30 μm. The distance t15 is the shortest distance between the first conductive layer 51 and the second surface 10b. When the unevenness 10 dp is provided, the distance t15 corresponds to the distance between the bottom of the unevenness 10 dp and the first conductive layer 51.

(Second Embodiment)
FIG. 6 is a schematic cross-sectional view illustrating a semiconductor light emitting element according to the second embodiment.
6 is a cross-sectional view corresponding to the cross section along line A1-A2 of FIG.
As shown in FIG. 6, the semiconductor light emitting device 120 according to this embodiment also includes the base body 70, the first semiconductor layer 10, the second semiconductor layer 20, the third semiconductor layer 30, the first conductive layer 51, And an insulating layer 81. Since the configuration of the semiconductor layer is the same as that of the semiconductor light emitting device 110, description thereof is omitted.

  Also in the semiconductor light emitting device 120, a first pad 45 and a second pad 55 are provided. The first semiconductor layer 10 is disposed between the first pad 45 and the third semiconductor layer 30. The first pad 45 is electrically connected to the first semiconductor layer 10.

  A part of the first conductive layer 51 (first conductive portion 51 a) is disposed between the second semiconductor layer 20 and the base body 70. Another part (second conductive portion 51 b) of the first conductive layer 51 is disposed between the second pad 55 and the base body 70. The second pad 55 is electrically connected to the other part (second conductive portion 51 b) of the first conductive layer 51. The insulating layer 81 is disposed between the base body 70 and the first conductive layer 51.

  In the semiconductor light emitting device 120, a metal layer 73 is further provided. The metal layer 73 is provided between the first conductive layer 51 and the insulating layer 81.

  That is, a metal layer 73 (for example, a bonding layer) is provided on the conductive substrate 70, and the first conductive layer 51 is provided thereon. The second semiconductor layer 20, the third semiconductor layer 30, and the first semiconductor layer 10 are provided on a part of the first conductive layer 51 (first conductive portion 51a). A first pad 45 is provided on the first semiconductor layer 10. A second pad 55 is provided on another part (second conductive portion 51 b) of the first conductive layer 51.

  Also in the semiconductor light emitting device 120, the first conductive layer 51 and the base 70 are electrically insulated by the insulating layer 81, and the first semiconductor layer 10 and the base 70 are electrically insulated. Also in the semiconductor light emitting device 120, the withstand voltage can be improved. Normal operation can also be obtained when a plurality of semiconductor light emitting elements 120 are arranged on a conductive substrate 160s and connected in series. A semiconductor light emitting device that can be connected in series and mounted while obtaining high heat dissipation and high efficiency characteristics can be obtained. Applications of semiconductor light emitting devices can be expanded.

  For each element included in the semiconductor light emitting device 120, the configuration (material, thickness, etc.) described with respect to the semiconductor light emitting device 110 can be applied. In the semiconductor light emitting device 120, the configuration of the second conductive layer 42 and the first pad 45 described with respect to the semiconductor light emitting device 111 may be applied.

  The semiconductor light emitting device 120 can be formed, for example, by appropriately changing the steps described with reference to FIGS. 3B and 3C.

  For example, in the process illustrated in FIG. 3B, the formation of the second metal region 51q and the insulating layer 81 is omitted. On the other hand, in the process illustrated in FIG. 3C, the insulating layer 81 is provided between the base body 70 and the metal layer 73 in the counter substrate 75. Thereafter, the semiconductor light emitting device 120 is obtained through a bonding process, processing of the semiconductor layer, formation of a pad, division, and the like.

  In the semiconductor light emitting device 120, at least a part of the second pad 55 is in the direction intersecting the first direction D1 (for example, the second direction D2), the first semiconductor layer 10, the third semiconductor layer 30, and the second semiconductor layer 20. It overlaps with at least a part of the laminated body 15 containing.

  In the semiconductor light emitting device 120, the distance t15 between the first pad 45 and the first conductive layer 51 is, for example, not less than 1.5 μm and not more than 30 μm.

  In this example of the semiconductor light emitting device 120, the outer edge 70r of the base body 70 of the first conductive layer 51 is within the XY plane (in the plane intersecting the first direction D1 from the base body 70 toward the second semiconductor layer 20). It is located outside the outer edge 51r. That is. The size of the base body 70 and the size of the first conductive layer 51 are different from each other. The size of the base body 70 is larger than the size of the first conductive layer 51.

  In this example, the outer edge 81r of the insulating layer 81 overlaps the outer edge 70r of the base body 70 in the first direction D1. For example, the insulating layer 81 and the base body 70 are divided in one process, and the size is determined. The outer edge 73r of the metal layer 73 overlaps with the outer edge 51r of the first conductive layer 51 in the first direction D1. For example, the metal layer 73 and the conductive layer 51 are divided in another single process, and the size is determined. By making the size of the base body 70 larger than the size of the first conductive layer 51, for example, the structure including the base body 70 and the structure including the first conductive layer 51 can be easily joined.

  In the example of the semiconductor light emitting device 120, the first metal layer 51 q is not provided in the first conductive layer 51. Thereby, the 1st conductive layer 51 is flat and the level | step difference is suppressed. Thereby, a decrease in the insulating property of the insulating layer 81 due to the step of the first conductive layer 51 is suppressed. A higher withstand voltage can be obtained.

(Third embodiment)
FIG. 7 is a schematic cross-sectional view illustrating a semiconductor light emitting element according to the third embodiment.
FIG. 7 is a cross-sectional view corresponding to the cross section along line A1-A2 of FIG.
As shown in FIG. 7, the semiconductor light emitting device 130 according to the present embodiment includes an insulating layer 81, a base body 70, a first semiconductor layer 10, a second semiconductor layer 20, a third semiconductor layer 30, and a first semiconductor layer. The conductive layer 51, the first pad 45, and the second pad 55 are included.

  The first semiconductor layer 10 is provided between the insulating layer 81 and the first pad 45. The first semiconductor layer 10 includes a first conductivity type region 11 (see FIG. 2). The first semiconductor layer 10 may further include a low impurity concentration region 12 (see FIG. 2). The second semiconductor layer 20 is provided between the first semiconductor layer 10 and the insulating layer 81. The third semiconductor layer 30 is provided between the first semiconductor layer 10 and the second semiconductor layer 20. The structure described regarding the semiconductor light emitting element 110 can be applied to these semiconductor layers.

  The first conductive layer 51 is electrically connected to the second semiconductor layer 20. A part of the first conductive layer 51 (first conductive portion 51 a) is provided between the insulating layer 81 and the second semiconductor layer 20.

  The base body 70 is provided between the part (first conductive portion 51 a) of the first conductive layer 51 and the insulating layer 81.

  Another part (second conductive portion 51 b) of the first conductive layer 51 is disposed between the second pad 55 and the base body 70.

  At least a portion of the second pad 55 is in the first semiconductor layer 10, the third semiconductor layer 30, and the second semiconductor layer 20 in a direction (for example, the second direction D2) intersecting the first direction D1 (for example, the Z-axis direction). It overlaps with at least a part of the laminated body 15 containing.

  In the semiconductor light emitting device 130, at least a part of the second pad 55 is in the direction intersecting the first direction D1 (for example, the second direction D2), for example, the first semiconductor layer 10, the third semiconductor layer 30, and the second semiconductor layer. It overlaps with at least a part of the laminate 15 including 20.

  A distance t15 between the first pad 45 and the first conductive layer 51 is not less than 1.5 μm and not more than 30 μm.

  Thus, the semiconductor light emitting device 130 is a thin film type LED. There is little loss of light and heat dissipation is high.

  In the semiconductor light emitting device 130, the upper surface (second surface 10b) of the first semiconductor layer 10 is a light emitting surface. The surface opposite to the light exit surface is the mounting surface. In the semiconductor light emitting device 130, an insulating layer 81 is provided on the mounting surface. By the insulating layer 81, the potential of the mounting surface is independent of the semiconductor layer. When a high voltage is applied to the mounting surface due to static electricity or the like, the high voltage can be suppressed from being applied to the semiconductor layer. Thereby, the withstand voltage can be improved.

  Further, when the semiconductor light emitting device 130 is mounted on a conductive substrate 160 s or the like, the potential of the substrate 160 s is independent of the semiconductor layer of the semiconductor light emitting device 130. Even when a plurality of semiconductor light emitting elements 130 are arranged on a conductive substrate 160s and connected in series, normal operation can be obtained. A semiconductor light emitting device that can be connected in series and mounted while obtaining high heat dissipation and high efficiency characteristics can be obtained. Applications of semiconductor light emitting devices can be expanded.

  In the semiconductor light emitting device 130, the configuration described with respect to the semiconductor light emitting device 110 can be applied to the insulating layer 81, the base 70, the first conductive layer 51, the first pad 45, and the second pad 55. In the semiconductor light emitting device 130, the second metal region 51q may be provided. A second conductive layer 42 may be provided, and the first pad 45 may be connected to the second conductive layer 42.

  In this example, the semiconductor light emitting device 130 further includes a metal layer 73. The metal layer 73 is provided between the base body 70 and the first conductive layer 51.

  The semiconductor light emitting device 130 further includes a metal film 71. The insulating layer 81 is disposed between the metal film 71 and the base body 70. The metal film 71 is electrically insulated from the base body 70 and the first conductive layer 51.

  For example, when the semiconductor light emitting element 130 is mounted using a metal member such as solder, the metal film 71 is bonded to the metal member. Providing the metal film 71 enables stable mounting with high thermal conductivity. The metal film 71 is provided as necessary, and may be omitted as necessary.

  In this example, the insulating layer 81 is provided not only on the lower surface of the base body 70 but also on the side surface 70 s of the base body 70. That is, the base body 70 has a side surface 70s. The side surface 70s intersects a second direction (for example, the second direction D2) that intersects the first direction D1. The first direction D1 is a Z-axis direction from the base body 70 toward the second semiconductor layer 20 and is parallel to a direction from the second semiconductor layer 20 toward the first semiconductor layer 10. The insulating layer 81 includes a side surface portion 81b. The side surface portion 81b intersects the side surface 70s in the second direction D2. The insulating layer 81 includes a main surface portion 81a. The main surface portion 81a intersects the base body 70 in the first direction D1.

  That is, the outer edge 81r of the insulating layer 81 is outside the outer edge 70r of the base body 70 in a plane (XY plane) that intersects the first direction D1 (the direction from the second semiconductor layer 20 toward the first semiconductor layer 10). Located in.

  By providing the side surface portion 81b, high insulation can be obtained on the side surface 70s of the base body 70. For example, when the semiconductor light emitting device 130 is mounted on the mounting substrate 160 or the like, occurrence of a short circuit can be suppressed.

  The insulating layer 81 includes, for example, silicon oxide. The insulating layer 81 is formed by sputtering, for example.

  The semiconductor light emitting device 130 can be manufactured by appropriately changing the manufacturing method described for the semiconductor light emitting device 130.

  For example, in the manufacturing method described for the semiconductor light emitting device 130, the formation of the second metal region 51q and the insulating layer 81 is omitted, and the steps up to the step shown in FIG. Then, the first pad 45 and the second pad 55 are formed, and the wafer is divided into a predetermined shape. Thereafter, an insulating layer 81 is formed on the back surface and side surfaces of the base body 70.

An example of this process will be described.
FIG. 8A and FIG. 8B are schematic views illustrating the method for manufacturing the semiconductor light emitting element according to the third embodiment.
As shown in FIG. 8A, the divided individual chips 130a are arranged on the support 88b. The chip 130a becomes the semiconductor light emitting element 130, for example.

  The support 88b is supported by the support portion 88a. The support 88b has a film shape, for example. The support 88b has, for example, adhesiveness. For example, a “blue sheet” may be used as the support 88b.

  On the support 88b, the interval between the plurality of chips 130a is larger than the interval before dicing. That is, they are arranged in an expanded state. At this time, the base body 70 is turned upward. That is, for example, the first semiconductor layer 10 side faces the support 88b.

  For example, the material 81mt that becomes the insulating layer 81 is supplied to the chip 130a. For example, a method such as sputtering is used.

  As shown in FIG. 8B, the material 81mt is supplied from a plurality of directions toward the chip 130a. For example, sputtering is performed in four directions. Thereby, in addition to the main surface of the base body 70, the insulating layer 81 (side face portion 81 b) is formed on the four side faces 70 s of the base body 70. For example, a silicon oxide film is formed as the insulating layer 81. The thickness of the silicon oxide film is, for example, about 1 μm (for example, 0.5 μm or more and 3 μm or less). For example, when the insulating layer 81 includes silicon nitride, the thickness of the silicon nitride film is 0.1 μm or more and 20 μm or less.

  By such a process, for example, the semiconductor light emitting device 130 is obtained. For example, when the thickness of the insulating layer 81 is 3 μm, a breakdown voltage exceeding 300 volts can be obtained with a DC voltage.

  The thickness of the insulating layer 81 may be changed according to the film forming conditions (film forming method, film forming temperature, etc.) of the insulating layer 81 so as to obtain a desired withstand voltage.

  Like the semiconductor light emitting device 130, the insulating layer 81 may be provided on a part of the side surface 70s of the base body 70, or may be provided on the entire side surface 70s. The position where the insulating layer 81 is provided can be variously modified.

FIG. 9A to FIG. 9F are schematic cross-sectional views illustrating other semiconductor light emitting elements according to the third embodiment.
These drawings are cross-sectional views corresponding to the cross section along line A1-A2 of FIG.
As shown in FIG. 9A, in the semiconductor light emitting device 131, the insulating layer 81 covers the side surface 70 s of the base body 70 and the side surface 73 s of the metal layer 73. Except this, it is the same as the semiconductor light emitting device 130.

  The side surface 73s of the metal layer 73 intersects a second direction (eg, the second direction D2) that intersects the first direction D1. The side surface portion 81b of the insulating layer 81 intersects the side surface 70s and the side surface 73s in the second direction D2. The side surface portion 81 b of the insulating layer 81 is in contact with at least a part of the insulating film 87. Thereby, high reliability is obtained.

  As shown in FIG. 9B, the semiconductor light emitting device 132 is further provided with an insulating film 85 in the semiconductor light emitting device 131. The rest is the same as the semiconductor light emitting device 131.

  The insulating film 85 is provided between the main surface portion 81 a of the insulating layer 81 and the base body 70. The insulating film 85 may be regarded as a part of the insulating layer 81. That is, in the semiconductor light emitting device 132, the thickness of the bottom portion of the insulating layer 81 (the portion intersecting the base body 70 in the first direction D1) is thicker than the thickness of the side surface portion 81b of the insulating layer 81. The thickness of the bottom is the sum of the thickness of the insulating film 85 and the thickness of the main surface portion 81a. The thickness of the bottom is a length along the first direction D1. The thickness of the side surface portion 81b is a length along the second direction D2. By increasing the thickness of the bottom portion of the insulating layer 81, higher insulating properties can be obtained.

  In the above-described manufacturing method described for the semiconductor light emitting device 130, an insulating film is formed on the surface of the base 70 before the wafer is divided. This insulating film becomes the insulating film 85. The insulating film 85 includes, for example, at least one of silicon oxide and silicon nitride. For the insulating film 85, for example, plasma CVD or the like is used.

  By forming the insulating film 85, the thickness of the insulating layer 81 can be reduced. Thereby, it can suppress that the temperature in formation of the insulating layer 81 (for example, film formation by sputtering) becomes high too much. For example, sticking of the chip 130a and the support 88b can be suppressed. The support 88b can be prevented from being thermally deformed. High productivity can be obtained.

  After forming the insulating film formed as the insulating film 85, it is preferable to remove the insulating film at a position overlapping with the dicing street before dividing. Thereby, it can suppress that a crack arises in this insulating film in a dicing process (chip formation process). High yield is obtained.

  As shown in FIG. 9C, in the semiconductor light emitting device 133, a metal film 71 is further provided in the semiconductor light emitting device 131. The rest is the same as the semiconductor light emitting device 131.

  The metal film 71 can be formed using, for example, a transfer film of a conductive film. Mounting is performed using a metal member such as solder using the metal film 71. Thereby, high heat dissipation is obtained.

  The metal film 71 may include, for example, a laminated film of Ti film (thickness: about 200 nm) / Ni film (thickness: 200 nm). The adhesion with the insulating layer 81 can be improved by the Ti film. The Ti film functions as, for example, a barrier layer for solder. For example, the Ni film forms an alloy with Sn contained in the solder. Thereby, a strong bond is obtained between the solder and the semiconductor light emitting device.

  The area of the metal film 71 is preferably larger than the area of the first conductive layer 51. The metal film 71 is preferably formed so as to cover the first conductive layer 51. Heat generation is large at the position overlapping the first conductive layer 51. By increasing the area of the metal film 71, high heat dissipation can be obtained. Thereby, high efficiency is obtained.

  For example, the wettability between the solder and the metal material is high, and the wettability between the solder and the insulating material is low. For this reason, when the solder contacts the metal film 71, it can be suppressed that the solder contacts the insulating layer 81. Thereby, in the semiconductor light emitting element 133, the portion to which the voltage is applied via solder or the like is limited to the lower surface (mounting surface) portion on which the metal film 71 is provided. Thereby, even when the side surface portion 81b of the insulating layer 81 becomes thin, a high withstand voltage can be obtained. For example, in the insulating layer 81, the quality of the insulating layer 81 may deteriorate at a portion (corner portion) where the main surface portion 81a and the side surface portion 81b are connected. Even in this case, a high withstand voltage can be maintained by limiting the region where the solder contacts with the metal film 71.

  As shown in FIG. 9D, the semiconductor light emitting device 134 is further provided with a metal film 71 in the semiconductor light emitting device 132. Except this, it is the same as the semiconductor light emitting device 132.

  By providing the insulating film 85, even when the insulating layer 81 is thick, the entire thickness of the insulating film can be maintained at the lower surface (mounting surface) of the semiconductor light emitting element 134. Then, the metal film 71 can control the portion in contact with the solder. A higher withstand voltage can be obtained.

  As shown in FIG. 9E, in the semiconductor light emitting device 135, the semiconductor light emitting device 131 is further provided with an insulating film 86. The rest is the same as the semiconductor light emitting device 131.

  In the semiconductor light emitting device 135, a part of the metal layer 73 intersects the second stacked body 15 in a direction intersecting the first direction D1 (for example, the second direction D2). For example, the laminate 15 is provided with a mesa portion.

  The insulating film 86 is provided between the metal layer 73 and the first semiconductor layer 10, between the metal layer 73 and the third semiconductor layer 30, and between the metal layer 73 and the second semiconductor layer 10. The second pad 55 intersects at least a part of the first semiconductor layer 10 in the second direction D2.

  A part of the insulating film 85 overlaps with the second semiconductor layer 20 in the first direction D1. This part of the insulating film 85 is located between the lower surface of the second semiconductor layer 20 and the base body 70.

  In the semiconductor light emitting device 135, for example, the insulating film 87 (passivation film) is formed before bonding. With this configuration, it is possible to suppress leakage at the side portion of the light emitting unit (third semiconductor layer 30). Yield can be improved.

  As shown in FIG. 9F, in the semiconductor light emitting device 136, in the semiconductor light emitting device 131, the side surface 70s of the base body 70 is inclined with respect to the first direction D1. The rest is the same as the semiconductor light emitting device 131.

  In the semiconductor light emitting device 136, the length in the second direction D <b> 2 of the portion near the metal layer 73 in the base 70 is longer than the length in the second direction D <b> 2 in the portion far from the metal layer 73 in the base 70. Thus, by inclining the side surface 70s of the base body 70, the coverage of the insulating layer 81 provided on the side surface 70s is improved. Thereby, insulation tolerance can be made higher.

  Also in the semiconductor light emitting elements 131 to 136, the mounting surface of the semiconductor light emitting element is insulated from the semiconductor layer by the insulating layer 81. As a result, high insulation resistance can be obtained, and normal operation can be obtained even when arranged on a conductive substrate 160s and connected in series. A semiconductor light emitting device that can be connected in series and mounted while obtaining high heat dissipation and high efficiency characteristics can be obtained. Applications of semiconductor light emitting devices can be expanded.

FIG. 10 is a schematic cross-sectional view illustrating another semiconductor light emitting element according to the third embodiment. FIG. 10 is a cross-sectional view corresponding to the cross section along line A1-A2 of FIG.
As shown in FIG. 10, in the semiconductor light emitting device 140 according to this embodiment, the insulating layer 81 is provided on a part of the lower surface of the base body 70. The metal film 71 is omitted. Except this, it is the same as the semiconductor light emitting device 130. In the semiconductor light emitting device 140, a metal film 71 may be provided.

  In the semiconductor light emitting device 140, the base body 70 in a plane (for example, an XY plane) intersecting the first direction D1 (for example, the Z-axis direction and the direction from the second semiconductor layer 20 toward the first semiconductor layer 10). The outer edge 70r of the insulating layer 81 is located outside the outer edge 81r of the insulating layer 81.

  For example, also in the semiconductor light emitting device 140, the surface opposite to the light emitting surface (second surface 10b) is the mounting surface. Also in the semiconductor light emitting device 140, the insulating layer 81 is provided on the mounting surface, and the potential of the mounting surface is independent of the semiconductor layer. When a high voltage is applied to the mounting surface due to static electricity or the like, the high voltage can be suppressed from being applied to the semiconductor layer. Thereby, the withstand voltage can be improved.

  For example, the insulating layer 81 is fixed to the mounting substrate 160 with an adhesive or the like. The base 70 is insulated from the mounting substrate 160 by the insulating layer 81.

(Third embodiment)
FIG. 11 is a schematic cross-sectional view illustrating a part of the semiconductor light emitting element according to the embodiment.
FIG. 11 illustrates the insulating layer 11 (or the insulating layer 11A) according to the above embodiment. As shown in FIG. 11, the insulating layer 11 according to the embodiment includes a first film 81h, a second film 81i, and a third film 81j.

  The second film 81i is provided between the first film 81h and the third film 81j. The first film 81h, the second film 81i, and the third film 81j are arranged along the first direction D1.

The first film 81h includes silicon oxide.
The second film 81i includes at least one of silicon nitride and aluminum oxide.
The third film 81j includes silicon oxide.

For example, when the second film 81 i includes silicon nitride, the insulating layer 81 has a configuration of, for example, silicon oxide / silicon nitride / silicon oxide (for example, SiO ₂ / SiN _x / SiO ₂ ). When the second film 81 i includes aluminum oxide, the insulating layer 81 has a structure of silicon oxide / aluminum oxide / silicon oxide (for example, SiO ₂ / Al ₂ O ₃ / SiO ₂ ). Further, in the insulating layer 81, a film containing at least one of silicon nitride and aluminum oxide may be provided between two silicon oxide films.

  According to the experiments by the inventors of the present application, as the insulating layer, for example, silicon oxide / silicon nitride / silicon oxide and silicon oxide / aluminum oxide / oxide are compared with a single film of silicon oxide or a stacked film of silicon oxide films. It was found that a high withstand voltage can be obtained in a laminated film such as silicon (a laminated film made of different materials).

For example, the withstand voltage in a single SiO ₂ film (thickness of about 4 μm) is 700V to 1100V.

On the other hand, the AC withstand voltage in the laminated film of SiO ₂ (thickness 0.05 μm) / SiN _x (thickness about 4 μm) / SiO ₂ (thickness 0.05 μm) is about 1400V to 2100V. A similar high withstand voltage can be obtained also in a laminated film of silicon oxide / aluminum oxide / silicon oxide.

  For example, according to the Poole-Frenkel effect, the leak current value in the dielectric film when a high voltage is applied depends on the thickness of the dielectric film, the relative dielectric constant of the dielectric, and the barrier height of the dielectric. The barrier height is strongly dependent on the quality of the dielectric. If the quality is low, impurity levels such as subbands are easily formed in the dielectric, and the barrier height is lowered. As a result, a leak current easily flows.

  In silicon oxide, since the barrier height is high, leakage current hardly flows. For this reason, the withstand voltage depends on breakdown. On the other hand, in silicon nitride or aluminum oxide, the barrier height is low, and a leak current tends to flow. For this reason, electric field concentration is suppressed and breakdown is unlikely to occur. Thus, silicon oxide and silicon nitride have different characteristics. Silicon oxide and aluminum oxide have different characteristics.

  In the present embodiment, the first film 81h containing silicon oxide, the second film 81i containing silicon nitride and aluminum oxide, and the third film 81j containing silicon oxide are combined. Thereby, a high withstand voltage can be obtained while suppressing breakdown by an appropriate leak current.

  In the embodiment, the insulating layer 81 may include a first film 81h containing silicon oxide and a second film 81i containing silicon nitride and aluminum oxide, and the third film 81j may be omitted. The insulating layer 81 may include a third film 81j containing silicon oxide and a second film 81i containing silicon nitride and aluminum oxide, and the first film 81h may be omitted.

  Thus, in this embodiment, a higher withstand voltage can be obtained by using the above laminated film containing different materials.

  The configurations of the first film 81h, the second film 81i, and the second film 81j may be applied to at least one of the insulating films 85, 86, and 87.

  In the embodiment, the thickness of the first film 81h is, for example, not less than 0.02 μm and not more than 2 μm. The thickness of the second film 81i is, for example, not less than 0.5 μm and not more than 8 μm. The thickness of the third film 81j is, for example, not less than 0.02 μm and not more than 2 μm. If the thickness of these films is excessively thin, insulation may be insufficient. If the thickness of these films is excessively large, the heat dissipation may be insufficient.

  According to the above embodiment, a semiconductor light emitting device capable of improving the withstand voltage can be provided.

In this specification, “nitride semiconductor” means B _x In _y Al _z Ga _1-xyz N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z ≦ 1) Semiconductors having all compositions in which the composition ratios x, y, and z are changed within the respective ranges are included. Furthermore, in the above chemical formula, those further containing a group V element other than N (nitrogen), those further containing various elements added for controlling various physical properties such as conductivity type, and unintentionally Those further including various elements included are also included in the “nitride semiconductor”.

  In the present specification, “vertical” and “parallel” include not only strictly vertical and strictly parallel, but also include, for example, variations in the manufacturing process, and may be substantially vertical and substantially parallel. It ’s fine.

  The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a first conductive layer, a second conductive layer, a first pad, a second pad, a metal layer, an insulating layer, and a metal included in the semiconductor light emitting device The specific configuration of each element such as a membrane is included in the scope of the present invention as long as a person skilled in the art can implement the present invention in the same manner by selecting appropriately from a known range and obtain the same effect. The

  Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, all semiconductor light-emitting elements that can be implemented by those skilled in the art based on the semiconductor light-emitting elements described above as embodiments of the present invention are included in the scope of the present invention as long as they include the gist of the present invention. Belonging to.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... 1st semiconductor layer, 10A ... 4th semiconductor layer, 10a ... 1st surface, 10b ... 2nd surface, 10dp ... Convex part, 10p ... 1st semiconductor region, 10q ... 2nd semiconductor region, 11 ... 1st electroconductivity 11f ... first semiconductor film, 12 ... low impurity concentration region, 12f ... low impurity concentration film, 15, 15A ... laminated body, 15f ... laminated film, 15fs ... structure, 18 ... substrate, 20 ... second Semiconductor layer, 20A ... fifth semiconductor layer, 20f ... second semiconductor film, 30 ... third semiconductor layer, 30A ... sixth semiconductor layer, 30f ... active film, 31 ... barrier layer, 32 ... well layer, 42 ... second Conductive layer, 42a ... third conductive portion, 42b ... fourth conductive portion, 45 ... first pad, 45A ... third pad, 46 ... electrode, 51 ... first conductive layer, 51A ... conductive layer, 51a ... first conductive Part, 51b ... 2nd conductive part, 51p ... 1st metal area | region, 51b ... 2nd metal area | region, 51qa, 51qb ... part, 51r ... Outer edge, 55 ... 2nd pad, 55A ... 4th pad, 70, 70A ... Base | substrate, 70r ... Outer edge, 70s ... Side, 71, 71A ... Metal film, 71a ... Ni film, 71b ... Ti film, 73, 73A ... Metal layer, 73a, 73b ... Metal film, 73r ... Outer edge, 73s ... Side, 75 ... Counter substrate, 81, 81A: Insulating layer, 81a: Main surface portion, 81b ... Side surface portion, 81e ... First film, 81f ... Second film, 81g ... Third film, 81mt ... Material, 81r ... Outer edge, 85, 86, 87 ... Insulating film, 88a ... support part, 88b ... support, 110, 110A, 111, 120, 130-136, 140 ... semiconductor light emitting element, 130a ... chip, 151, 52, 153 ... wiring, 160 ... mounting substrate, 160s ... substrate, 161 ... insulating film for first mounting electrode, 161A ... insulating film for second mounting electrode, 162 ... first mounting electrode, 162A ... second mounting electrode, 163 163A ... first and second joining members 210 ... light emitting device, AA ... arrow, BL ... barrier layer, D1 ... first direction, D2 ... second direction, WL ... well layer, t15 ... distance

Claims (20)

A conductive substrate;
A first semiconductor layer including a region of a first conductivity type;
A second semiconductor layer of a second conductivity type provided between the first semiconductor layer and the substrate;
A third semiconductor layer provided between the first semiconductor layer and the second semiconductor layer;
A first conductive layer provided between the second semiconductor layer and the base body and electrically connected to the second semiconductor layer;
An insulating layer provided between the base and the first conductive layer, electrically insulating the first conductive layer and the base, and electrically insulating the first semiconductor layer and the base;
A semiconductor light emitting device comprising: A first pad;
A second pad;
Further comprising
The first semiconductor layer is disposed between the first pad and the third semiconductor layer, and the first pad is electrically connected to the first semiconductor layer;
A portion of the first conductive layer is disposed between the second semiconductor layer and the substrate;
Another portion of the first conductive layer is disposed between the second pad and the base body,
The semiconductor light emitting element according to claim 1, wherein the second pad is electrically connected to the another part of the first conductive layer.   The semiconductor light emitting element according to claim 2, further comprising a metal layer provided between the base and the insulating layer. The first conductive layer includes a first metal region and a second metal region,
The first metal region is provided between a part of the second metal region and the second semiconductor layer;
The part of the first conductive layer includes the part of the first metal region and the second metal region,
4. The semiconductor light emitting element according to claim 2, wherein the another part of the first conductive layer includes another part of the second metal region. 5.   The semiconductor light emitting element according to claim 2, further comprising a metal layer provided between the first conductive layer and the insulating layer. In a plane intersecting with a first direction from the base toward the second semiconductor layer, an outer edge of the base is located outside an outer edge of the first conductive layer,
The semiconductor light emitting element according to claim 5, wherein an outer edge of the insulating layer overlaps with the outer edge of the base in the first direction.   At least a part of the second pad includes the first semiconductor layer, the third semiconductor layer, and the second semiconductor layer in a direction crossing a first direction from the base toward the second semiconductor layer. The semiconductor light-emitting device according to claim 2, which overlaps at least a part of the semiconductor light-emitting device.   8. The semiconductor light emitting element according to claim 2, wherein a distance between the first pad and the first conductive layer is 1.5 μm or more and 30 μm or less. A first pad;
A second pad;
A second conductive layer;
Further comprising
The first semiconductor layer includes the first semiconductor region and a second semiconductor region aligned with the first semiconductor region in a direction intersecting the first direction from the base toward the second semiconductor layer,
A portion of the first conductive layer is disposed between the base and the second semiconductor region,
The part of the first conductive layer is electrically connected to the second semiconductor region;
Another part of the first conductive layer is disposed between the second pad and the substrate;
A portion of the second conductive layer is disposed between the base and the first semiconductor region,
The part of the second conductive layer is electrically connected to the first semiconductor region;
Another part of the second conductive layer is disposed between the first pad and the substrate;
The semiconductor light emitting element according to claim 1, wherein the first pad is electrically connected to the another part of the second conductive layer.   At least a part of the first pad includes the first semiconductor layer, the third semiconductor layer, and the second semiconductor layer in a direction crossing a first direction from the base toward the second semiconductor layer. The semiconductor light emitting device according to claim 9, which overlaps at least a part of the semiconductor light emitting device.   At least a part of the second pad includes the first semiconductor layer, the third semiconductor layer, and the second semiconductor layer in a direction crossing a first direction from the base toward the second semiconductor layer. The semiconductor light-emitting device according to claim 9, which overlaps at least a part of the semiconductor light-emitting device. The first semiconductor layer has a first surface on the third semiconductor layer side and a second surface opposite to the first surface;
The semiconductor light emitting element according to any one of claims 9 to 11, wherein a distance between the first conductive layer and the second surface is 1.5 micrometers or more and 30 micrometers or less. An insulating layer;
A first pad;
A first semiconductor layer including a region of a first conductivity type provided between the insulating layer and the first pad;
A second semiconductor layer of a second conductivity type provided between the first semiconductor layer and the insulating layer;
A third semiconductor layer provided between the first semiconductor layer and the second semiconductor layer;
A first conductive layer electrically connected to the second semiconductor layer, wherein a part of the first conductive layer is provided between the insulating layer and the second semiconductor layer; Layers,
A conductive substrate provided between the part of the first conductive layer and the insulating layer;
A second pad, wherein another part of the first conductive layer is disposed between the second pad and the substrate;
A semiconductor light emitting device comprising:   At least a part of the second pad includes the first semiconductor layer, the third semiconductor layer, and the second semiconductor layer in a direction crossing a first direction from the base toward the second semiconductor layer. The semiconductor light emitting element according to claim 13, which overlaps at least a part of the semiconductor light emitting element.   The semiconductor light emitting device according to claim 13 or 14, wherein a distance between the first pad and the first conductive layer is not less than 1.5 micrometers and not more than 30 micrometers. A metal film,
The insulating layer is disposed between the metal film and the substrate;
The semiconductor light emitting element according to claim 13, wherein the metal film is electrically insulated from the base body and the first conductive layer. The base has a side surface that intersects a second direction that intersects a first direction from the second semiconductor layer toward the first semiconductor layer;
17. The semiconductor light emitting element according to claim 13, wherein the insulating layer includes a side surface portion that intersects the side surface in the second direction.   18. The outer edge of the insulating layer is located outside the outer edge of the base body in a plane intersecting a first direction from the second semiconductor layer toward the first semiconductor layer. 18. The semiconductor light-emitting device described in 1. The insulating layer comprises silicon oxide;
19. The semiconductor light emitting element according to claim 1, wherein the insulating layer has a thickness of 3 micrometers or less. The insulating layer includes silicon nitride;
The semiconductor light-emitting element according to claim 1, wherein the insulating layer has a thickness of 20 micrometers or less.

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