JP5951732B2 - Semiconductor light emitting device - Google Patents

Description

Embodiments of the present invention relates to a semiconductor light-emitting element.

  Semiconductor light emitting devices such as light emitting diodes (LEDs) and laser diodes (LDs) have been developed. In a semiconductor light emitting device, a nitride semiconductor layer such as gallium nitride is crystal-grown on a growth substrate. At this time, if the difference in thermal expansion coefficient between the growth substrate and the semiconductor layer is large, the crystal quality may be deteriorated or cracked when the temperature is returned to room temperature after crystal growth, and the quality may be lowered.

JP 2006-210824 A

Embodiments of the present invention provides a high-quality semiconductor light emitting element of.

According to an embodiment of the present invention, there is provided a semiconductor light emitting device including a substrate, a first electrode, a first semiconductor layer, a light emitting layer, a second semiconductor layer, an insulating layer, and a second electrode. The The substrate includes a first region, a second region, and a third region provided between the first region and the second region. The first semiconductor layer includes a first portion provided on the first region and a second portion provided on the second region, and has the first conductivity type. The light emitting layer includes a third portion provided on the first portion and a fourth portion provided on the second portion. The second semiconductor layer includes a fifth portion provided on the third portion and a sixth portion provided on the fourth portion, and has the second conductivity type. The insulating layer is provided on the third region, between the first portion and the second portion, and between the third portion and the fourth portion. Said second electrode is in contact with pre-Symbol said insulating layer between said fifth portion and the sixth portion disposed between the fifth portion and the sixth portion. The first electrode is provided between the first portion and the first region, and between the second portion and the second region, and is in contact with the first portion and the second portion . Wherein the upper surface of the insulating layer, the first of the first width from a region toward the second region is wider than the lower surface of the first width of the second electrode.
According to an embodiment of the present invention, a semiconductor light emitting device is provided that includes a substrate, a first electrode, a first semiconductor layer, a light emitting layer, a second semiconductor layer, an insulating layer, and a second electrode. The The substrate includes a first region, a second region, and a third region provided between the first region and the second region. The first semiconductor layer includes a first portion provided on the first region and a second portion provided on the second region, and has the first conductivity type. The light emitting layer includes a third portion provided on the first portion and a fourth portion provided on the second portion. The second semiconductor layer includes a fifth portion provided on the third portion and a sixth portion provided on the fourth portion, and has the second conductivity type. The insulating layer is provided on the third region, between the first portion and the second portion, and between the third portion and the fourth portion. The second electrode is provided between the fifth portion and the sixth portion, and is in contact with the insulating layer between the fifth portion and the sixth portion. The first electrode is provided between the first portion and the first region, and between the second portion and the second region, and is in contact with the first portion and the second portion. The insulating layer has a recess provided on the lower surface of the insulating layer. At least a portion of the first electrode is along the inner surface of the recess.

1 is a schematic cross-sectional view showing a semiconductor light emitting element according to a first embodiment. 1 is a schematic plan view showing a semiconductor light emitting element according to a first embodiment. 1 is a schematic cross-sectional view showing a semiconductor light emitting element according to a first embodiment. 1 is a schematic cross-sectional view showing a semiconductor light emitting element according to a first embodiment. It is a typical sectional view showing another semiconductor light emitting element concerning a 1st embodiment. It is a flowchart figure which shows the manufacturing method of the semiconductor light-emitting device which concerns on 2nd Embodiment. FIG. 7A to FIG. 7H are schematic cross-sectional views in order of steps showing the method for manufacturing the semiconductor light emitting device according to the second embodiment. It is a typical sectional view showing a semiconductor light emitting element concerning a 3rd embodiment. FIG. 9A to FIG. 9E are schematic plan views showing the semiconductor light emitting elements according to the embodiment. It is a typical sectional view showing a semiconductor light emitting element concerning an embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(First embodiment)
FIG. 1 is a schematic cross-sectional view illustrating the configuration of the semiconductor light emitting element according to the first embodiment. FIG. 2 is a schematic plan view illustrating the configuration of the semiconductor light emitting element according to the first embodiment. 1 is a cross-sectional view taken along line A1-A2 of FIG.

  As shown in FIGS. 1 and 2, the semiconductor light emitting device 110 according to this embodiment includes the first electrode 40, the first semiconductor layer 10, the light emitting layer 30, the second semiconductor layer 20, and the insulating layer 60. And the second electrode 50.

  The first electrode 40 includes a first region 41, a second region 42, and a third region 43. The third region 43 is provided between the first region 41 and the second region 42.

  A direction perpendicular to the main surface of the first electrode 40 is taken as a Z-axis direction. One direction perpendicular to the Z-axis direction is taken as an X-axis direction. A direction perpendicular to the Z-axis direction and the X-axis direction is taken as a Y-axis direction.

  For example, the shape (planar shape) when the semiconductor light emitting element 110 is viewed along the Z-axis direction is a rectangle (for example, a rectangle). One side of the planar shape of the semiconductor light emitting device 110 is, for example, along the X-axis direction. Another side of the planar shape of the semiconductor light emitting device 110 is, for example, along the Y-axis direction.

  As illustrated in FIG. 2, in this example, the third region 43 is provided in a lattice shape in the XY plane. The third region 43 is a region that divides the first region 41 and the second region 42.

  For example, the first direction from the first region 41 toward the second region 42 is parallel to the X-axis direction. However, the embodiment is not limited to this, and the first direction can be an arbitrary direction parallel to the XY plane. That is, the relationship between the first direction from the first region 41 toward the second region 42 and the direction of the side of the semiconductor light emitting element 110 is arbitrary. Hereinafter, the case where the first direction is parallel to the X-axis direction will be described.

  In this example, a plurality of first regions 41 and second regions 42 are provided. The plurality of first regions 41 are arranged in a second direction that is non-parallel to the first direction from the first region 41 toward the second region 42. The plurality of second regions 42 are arranged along the second direction. In this example, the second direction is the Y-axis direction.

  As described above, the plurality of first regions 41 and the plurality of second regions 42 are arranged in a lattice pattern. In the embodiment, the number of the plurality of first regions 41 and the number of the plurality of second regions 42 are arbitrary.

  As illustrated in FIG. 2, the semiconductor light emitting device 110 may further include a pad portion 55. The pad part 55 is electrically connected to the second electrode 50. The second electrode 50 is, for example, a fine wire electrode.

  As illustrated in FIG. 1, the first semiconductor layer 10 has the first conductivity type. The first semiconductor layer 10 includes a first portion p1 and a second portion p2. The first portion p <b> 1 is provided on the first region 41. The second portion p2 is provided on the second region 42.

  The light emitting layer 30 includes a third portion p3 and a fourth portion p4. The third portion p3 is provided on the first portion p1. The fourth portion p4 is provided on the second portion p2.

  The second semiconductor layer 20 is of the second conductivity type. The second semiconductor layer 20 includes a fifth portion p5 and a sixth portion p6. The fifth portion p5 is provided on the third portion p3. The sixth part p6 is provided on the fourth part p4. The second semiconductor layer 20 has a first side surface s1 that faces the sixth portion p6 of the fifth portion p5, and a second side surface s2 that faces the fifth portion p5 of the sixth portion p6. The first side surface s1 faces the second side surface s2 along the first direction. The second side surface s2 faces the first side surface s1 along the first direction.

  The first conductivity type is, for example, p-type, and the second conductivity type is, for example, n-type. However, the embodiment is not limited to this, and the first conductivity type may be n-type and the second conductivity type may be p-type. In the following description, it is assumed that the first conductivity type is p-type and the second conductivity type is n-type.

  The first semiconductor layer 10, the second semiconductor layer 20, and the light emitting layer 30 include a nitride semiconductor. For example, the first semiconductor layer 10 includes p-type GaN. The second semiconductor layer 20 includes n-type GaN. Examples of the first semiconductor layer 10, the second semiconductor layer 20, and the light emitting layer 30 will be described later.

  The insulating layer 60 is provided on the third region 43, between the first portion p1 and the second portion p2, and between the third portion p3 and the fourth portion p4. The insulating layer 60 separates the first portion p1 and the second portion p2 of the first semiconductor layer 10. The insulating layer 60 divides the third portion p3 and the fourth portion p4 of the light emitting layer 30. In this example, the insulating layer 60 is provided in a lattice shape along the third region 43. Thereby, the first semiconductor layer 10 is divided into a lattice shape, and the light emitting layer 30 is also divided into a lattice shape.

For the insulating layer 60, for example, an insulating material such as metal oxide, metal nitride, or metal oxynitride is used. For example, silicon oxide (for example, SiO ₂ ), silicon nitride (SiN), silicon oxynitride (SiON), or the like is used for the insulating layer 60.

  The second electrode 50 includes a seventh portion p7, an eighth portion p8, and a ninth portion p9. The seventh portion p7 is provided on the insulating layer 60. The eighth portion p8 is in contact with the first side surface s1 of the second semiconductor layer 20 (the side surface facing the sixth portion p6 of the fifth portion p5). The ninth portion p9 is in contact with the second side surface s2 of the second semiconductor layer 20 (the side surface facing the fifth portion p5 of the sixth portion p6).

  For example, the eighth portion p8 is in ohmic contact with the first side surface s1, and the ninth portion p9 is in ohmic contact with the second side surface s2. Thus, the second electrode 50 is in ohmic contact with the second semiconductor layer 20 on the side surface of the second semiconductor layer 20.

  In this example, the semiconductor light emitting device 110 further includes a third semiconductor layer 23. The third semiconductor layer 23 includes a tenth portion p10 provided on the fifth portion p5 and an eleventh portion p11 provided on the sixth portion p6. The impurity concentration of the third semiconductor layer 23 is lower than the impurity concentration of the second semiconductor layer 20 (the fifth portion p5 and the sixth portion p6). The third semiconductor layer 23 includes, for example, a GaN layer (i-GaN layer) to which no impurity is added. In this example, the third semiconductor layer 23 has unevenness 23 p provided on the upper surface of the third semiconductor layer 23. The depth of the unevenness of the unevenness 23p is desirably 0.8 times or more and 5 times or less of the peak wavelength of light (emitted light) emitted from the light emitting layer 30. The unevenness 23p allows the light emitted from the light emitting layer 30 to be efficiently extracted out of the device.

  The third semiconductor layer 23 is provided as necessary and may be omitted. An example of the third semiconductor layer 23 will be described later.

  The eighth portion p8 of the second electrode 50 is further in contact with the side surface of the third semiconductor layer 23 facing the eleventh portion p11 of the tenth portion p10. The ninth portion p9 of the second electrode 50 is further in contact with the side surface of the third semiconductor layer 23 facing the tenth portion p10 of the eleventh portion p11.

  That is, a lattice-shaped groove (second groove 20 t) is provided in the second semiconductor layer 20 (and the third semiconductor layer 23) along the lattice-shaped third region 43. The second groove 20t divides the second semiconductor layer 20 (and the third semiconductor layer 23) into a lattice shape. A conductive layer is provided in the second groove 20t, and the second electrode 50 is formed. The second electrode 50 is electrically connected to the side surfaces (first side surface s1 and second side surface s2) of the second semiconductor layer 20 exposed at the inner wall of the second groove 20t.

  On the other hand, the insulating layer 60 electrically insulates the first semiconductor layer 10 and the second electrode 50 and electrically insulates the light emitting layer 30 and the second electrode 50.

  In the semiconductor light emitting device 110, a voltage is applied between the first electrode 40 and the second electrode 50, and a current is supplied to the light emitting layer 30 via the first semiconductor layer 10 and the second semiconductor layer 20 to emit light. Light is emitted from layer 30. The peak wavelength of the emitted light is, for example, not less than 370 nanometers (nm) and not more than 700 nm.

In the semiconductor light emitting device 110, the laminated semiconductor layer 15 including the first semiconductor layer 10, the light emitting layer 30, and the second semiconductor layer 20 is provided. In the case where the third semiconductor layer 23 is provided, the stacked semiconductor layer 15 also includes the third semiconductor layer 23. In the semiconductor light emitting device 110, the stacked semiconductor layer 15 is divided into a plurality of regions in the XY plane. Specifically, the light emitting layer 30 and the first semiconductor layer 10 are divided by the insulating layer 60, and the second semiconductor layer 20 is divided by the second electrode 50 (that is, the second groove 20t). For this reason, the area of each of the plurality of regions of the laminated semiconductor layer 15 is smaller than that in the case where it is not divided.

  For example, when the crystal layer of the stacked semiconductor layer 15 is grown on the growth substrate, excessive stress is applied to the crystal due to a large thermal expansion coefficient between the crystal layer and the growth substrate, Crystallinity deterioration and cracks occur.

  However, in this embodiment, since the laminated semiconductor layer 15 is divided and the size of the semiconductor layer is reduced, even when stress is applied to the semiconductor layer, it is possible to suppress crystallinity deterioration and cracks. According to the embodiment, a high-quality semiconductor light emitting device can be provided. As described above, in the embodiment, a configuration for relieving the residual stress accumulated in the stacked semiconductor layer 15 is introduced. Thereby, generation | occurrence | production of a crack can be suppressed.

  In particular, the difference in thermal expansion coefficient between a nitride semiconductor (for example, GaN) and silicon is relatively large. For this reason, when the nitride semiconductor laminated semiconductor layer 15 is grown on the silicon growth substrate, a particularly large stress is generated. For this reason, when the nitride semiconductor layer is formed on the silicon substrate, deterioration of crystallinity and cracks are more effectively suppressed by providing the configuration of the embodiment.

  In this example, the semiconductor light emitting device 110 further includes a support substrate 70, a first intermediate conductive layer 71, and a second intermediate conductive layer 72. The support substrate 70 is conductive. As the support substrate 70, for example, a conductive silicon substrate or the like is used. A first electrode 40 is provided on the support substrate 70. That is, the first electrode 40 is disposed between the support substrate 70 and the first semiconductor layer 10. The first intermediate conductive layer 71 is provided between the support substrate 70 and the first electrode 40. The second intermediate conductive layer 72 is provided between the support substrate 70 and the first intermediate conductive layer 71. For example, the first intermediate conductive layer 71 is formed on the surface (lower surface) of the first electrode 40. The second intermediate conductive layer 72 is formed on the surface of the support substrate 70. The support substrate 70 is bonded to the first electrode 40 by bonding the first intermediate conductive layer 71 and the second intermediate conductive layer 72 with the first intermediate conductive layer 71 and the second intermediate conductive layer 72 facing each other. Is done.

  The first intermediate conductive layer 71 is, for example, an adhesive metal layer. For the first intermediate conductive layer 71, for example, Ti or a Ti alloy is used. The second intermediate conductive layer 72 is a bonding metal layer. For the second intermediate conductive layer 72, for example, an AnSn alloy or the like is used.

  The semiconductor light emitting device 110 is, for example, a thin film type semiconductor light emitting device. As will be described later, in the semiconductor light emitting device 110, after the semiconductor layer is crystal-grown on the growth substrate, the support substrate is bonded to the semiconductor layer, and then the growth substrate is removed. In such a structure that the thin semiconductor layer is peeled off from the growth substrate by performing such processing, the quality of the crystal is more likely to deteriorate. For example, the semiconductor layer is particularly grown on a silicon growth substrate, and the growth substrate is peeled off. By applying this embodiment to such a configuration, deterioration of crystallinity and cracks are effectively suppressed.

  In this specification, “joining” includes not only the state of being directly fixed, but also the state of being fixed with another element inserted therebetween. Further, “provided on” includes not only the case of being disposed in direct contact but also the case of being disposed with another element interposed therebetween. Further, “opposite” includes not only a state of facing directly but also a state of facing indirectly by inserting another element therebetween. The term “laminated” includes not only the state of being stacked in contact with each other but also the state of being stacked with another layer interposed therebetween.

  There is a configuration in which a plurality of semiconductor light emitting element chips are arranged on a base and their electrodes are connected to each other to form a light emitting device. This configuration is complicated to manufacture. In this case, since the individual semiconductor light emitting element chips are respectively arranged on the base, the distance between the base and the semiconductor layer differs depending on the semiconductor light emitting element chip. The crystal orientation of the semiconductor layer varies depending on the semiconductor light emitting element chip.

  In contrast, in the semiconductor light emitting device 110 according to the embodiment, the laminated semiconductor layer 15 formed on one growth substrate is divided as will be described later. For this reason, the distance between the growth substrate and the semiconductor layer is constant in a plurality of regions. In addition, the crystal orientation of the semiconductor layer is constant in a plurality of regions. For this reason, for example, the distance between the interface between the first semiconductor layer 10 and the light emitting layer 30 and the first electrode 40 is constant.

  For example, as illustrated in FIG. 1, the distance between the interface IF1 between the first part p1 and the third part p3 and the first electrode 40 is the interface IF2 between the second part p2 and the fourth part p4. The distance between the first electrode 40 and the first electrode 40 is the same. For example, the crystal orientation of the first portion p1 is the same as the crystal orientation of the second portion p2. For example, the crystal orientation of the third portion p3 is the same as the crystal orientation of the fourth portion p4. For example, the crystal orientation of the fifth portion p5 is the same as the crystal orientation of the sixth portion p6. As a result, the distance between the separated regions becomes narrower than the width of the insulator layer. According to this configuration, for example, the mounting density of the chips is higher than a configuration in which a plurality of semiconductor light emitting element chips are arranged on the base and the electrodes are connected to each other to form a light emitting device. Furthermore, it is advantageous for cost reduction.

Further, the stacked semiconductor layer 15 (the first semiconductor layer 10, the light emitting layer 30, and the second semiconductor layer 20) is not divided, for example, the first semiconductor layer 10 and the light emitting layer 30 are divided, and the second semiconductor layer 20 is divided. An unstructured configuration is also conceivable. Further, for example, a configuration in which the first semiconductor layer 10 is divided and the light emitting layer 30 and the second semiconductor layer 20 are not divided is also conceivable. However, in the configuration in which any of the layers included in the laminated semiconductor layer 15 is not divided, the stress is not relaxed in the undivided layer, and it is difficult to suppress the generation of cracks.

  In the embodiment, by dividing the stacked semiconductor layer 15 (the first semiconductor layer 10, the light emitting layer 30, and the second semiconductor layer 20), the applied stress is effectively dispersed. Thereby, a high quality semiconductor light emitting element can be provided.

  As illustrated in FIG. 1, the width of the upper surface 60 u of the insulating layer 60 in the first direction (for example, the X-axis direction) is wider than the width of the lower surface 50 l of the second electrode 50 in the first direction. Thereby, the insulation between the first semiconductor layer 10 and the second electrode 50 and the insulation between the light emitting layer 30 and the second electrode 50 are more reliably performed by the insulating layer 60.

  In the semiconductor light emitting device 110, the second electrode 50 can be reflective to the light emitted from the light emitting layer 30. Further, the first electrode 40 can be reflective to the light emitted from the light emitting layer 30. Thereby, the light emitted from the light emitting layer 30 can be effectively extracted outside the device.

  For the first electrode 40, for example, a single layer film of at least one of Ag, Al, and Pd, or a laminated film of two or more films thereof can be used. For example, Ag or an Ag alloy is used for the first electrode 40. For the second electrode 50, for example, a single-layer film of at least one of Ag, Al, and Pd, or a laminated film of two or more films thereof can be used. For example, Ag or an Ag alloy is used for the second electrode 50.

  FIG. 3 is a schematic cross-sectional view illustrating the configuration of the semiconductor light emitting element according to the first embodiment. FIG. 3 illustrates the state when the stacked semiconductor layer 15 is crystal-grown. That is, FIG. 3 illustrates the state of one stage of the manufacturing process of the semiconductor light emitting device 110.

  As shown in FIG. 3, the laminated semiconductor layer 15 is epitaxially grown on the growth substrate 5. For example, a metal-organic chemical vapor deposition (MOCVD) method or a metal-organic vapor phase epitaxy method is used as a method for growing the stacked semiconductor layer 15. it can. The growth substrate 5 and the stacked semiconductor layer 15 are included in the stacked body 16.

For example, silicon (Si) is used for the growth substrate 5. For example, the growth substrate 5 is made of any one of Si, SiO ₂ , quartz, sapphire, GaN, SiC, and GaAs. At this time, the plane orientation of the growth substrate 5 is arbitrary. Hereinafter, an example in which a Si substrate is used as the growth substrate 5 will be described.

  A third semiconductor layer 23 is formed on the growth substrate 5. The third semiconductor layer 23 includes, for example, an AlN layer 25, an AlGaN layer 24, a stacked intermediate layer 22s, and a base layer 20i. The AlN layer 25 is formed on the growth substrate 5.

  The AlN layer 25 is formed by low temperature growth or high temperature growth. In the case of low temperature growth, the formation temperature of the AlN layer 25 is, for example, 400 ° C. or more and 500 ° C. or less. The thickness of the AlN layer 25 in the case of low temperature growth is, for example, 30 nm or more and 100 nm or less. In the case of high temperature growth, the formation temperature of the AlN layer 25 is, for example, 700 ° C. or more and 1200 ° C. or less. The thickness of the AlN layer 25 in the case of high temperature growth is, for example, not less than 100 nm and not more than 300 nm. The AlN layer 25 may include a stacked low-temperature growth layer and a high-temperature growth layer. When the formation temperature of the AlN layer 25 is low, the thickness of the AlN layer 25 is made thinner than when the formation temperature is high. Thereby, it becomes easy to maintain crystal quality.

  The AlGaN layer 24 is formed on the AlN layer 25. The formation temperature of the AlGaN layer 24 is, for example, 800 ° C. or more and 1200 ° C. or less. The thickness of the AlGaN layer 24 is, for example, not less than 300 nm and not more than 2000 nm. The Al composition ratio in the AlGaN layer 24 is, for example, 0.15 or more and less than 1. The AlGaN layer 24 may include a plurality of layers having different compositions. The AlGaN layer 24 may have a continuously changing composition.

The stacked intermediate layer 22 s is formed on the AlGaN layer 24. The stacked intermediate layer 22 s includes a plurality of first layers 21 and a plurality of second layers 22. The plurality of first layers 21 and the plurality of second layers 22 are alternately stacked. For example, GaN is used for the first layer 21. For example, Al _x Ga _1-x N (0 <x ≦ 1) is used for the second layer 22. The thickness of the first layer 21 is, for example, 150 nm or more and 1000 nm or less, and the thickness of the second layer 22 is 10 nm or more and 500 nm or less. At this time, the number of stacked layers (the number of the first layers 21 or the number of the second layers 22) is 2 or more and 5 or less. Further, the thickness of the first layer 21 is, for example, not less than 300 nm and not more than 2000 nm, and the thickness of the second layer 22 is not less than 10 nm and not more than 500 nm. At this time, the number of stacked layers is 1 or more and 3 or less. The total thickness of the stacked intermediate layer 22s is, for example, not less than 320 nm and not more than 7500 nm. The formation temperature of the first layer 21 is, for example, 800 ° C. or more and 1200 ° C. or less, and the formation temperature of the second layer 22 is 500 ° C. or more and 1200 ° C. or less. Regarding the relationship of the thickness of each layer with respect to the number of stacked layers, it is desirable to reduce the thickness of each layer when the number of stacked layers is large from the viewpoint of improving throughput by shortening film formation and suppressing cracks and improving yield. That is, it is desirable to suppress the overall thickness of the laminated intermediate layer 22s.

  The foundation layer 20i is formed on the stacked intermediate layer 22s. For the base layer 20i, for example, GaN (i-GaN) to which no impurity is added is used. The formation temperature of the underlayer 20i is, for example, not less than 800 ° C. and not more than 1200 ° C. The thickness of the foundation layer 20i is, for example, not less than 300 nm and not more than 1500 nm.

  The second semiconductor layer 20 is formed on the base layer 20 i, the light emitting layer 30 is formed on the second semiconductor layer 20, and the first semiconductor layer 10 is formed on the light emitting layer 30.

  For example, the base layer 20 i is in contact with the second semiconductor layer 20. However, in the embodiment, another layer may be provided between the base layer 20 i and the second semiconductor layer 20. For example, the semiconductor light emitting device 110 may further include a stacked film provided between the base layer 20 i and the second semiconductor layer 20. This laminated film includes, for example, a plurality of high band gap energy layers and a plurality of low band gap energy layers that are alternately laminated. The high band gap energy layer is, for example, a GaN layer. The low band gap energy layer is, for example, an InGaN layer. With this laminated film, for example, good crystallinity can be obtained.

  The second semiconductor layer 20 includes, for example, a GaN layer containing n-type impurities. For example, at least one of Si, Ge, Te, and Sn can be used as the n-type impurity. The second semiconductor layer 20 includes, for example, an n-side contact layer.

  The first semiconductor layer 10 includes, for example, a GaN layer containing p-type impurities. As the p-type impurity, at least one of Mg, Zn, and C can be used. The first semiconductor layer 10 includes, for example, a p-side contact layer.

  In the semiconductor light emitting device 110, the third semiconductor layer 23 includes, for example, a base layer 20i. The third semiconductor layer 23 may further include at least a part of the stacked intermediate layer 22s, for example. The third semiconductor layer 23 may further include an AlGaN layer 24 and an AlN layer 25.

FIG. 4 is a schematic cross-sectional view illustrating the configuration of the semiconductor light emitting element according to the first embodiment. FIG. 4 shows one example of the configuration of the light emitting layer 30.
As shown in FIG. 4, the light emitting layer 30 includes a plurality of barrier layers 31 and a well layer 32 provided between the plurality of barrier layers 31. For example, a plurality of barrier layers 31 and a plurality of well layers 32 are alternately stacked along the Z-axis direction.

The well layer 32 includes In _x1 Ga _1-x1 N (0 <x1 <1). The barrier layer 31 includes GaN. That is, the well layer 32 contains In, and the barrier layer 31 does not substantially contain In. The band gap energy in the barrier layer 31 is larger than the band gap energy in the well layer 32.

  The light emitting layer 30 may have a single quantum well (SQW) configuration. At this time, the light emitting layer 30 includes two barrier layers 31 and a well layer 32 provided between the barrier layers 31. Alternatively, the light emitting layer 30 may have a multi quantum well (MQW) configuration. At this time, the light emitting layer 30 includes three or more barrier layers 31 and a well layer 32 provided between the barrier layers 31.

  That is, the light emitting layer 30 includes, for example, (n + 1) barrier layers 31 and n well layers 32 (n is an integer of 2 or more). The (i + 1) -th barrier layer BL (i + 1) is disposed between the i-th barrier layer BLi and the first semiconductor layer 10 (i is an integer not less than 1 and not more than (n−1)). The (i + 1) th well layer WL (i + 1) is disposed between the i-th well layer WLi and the first semiconductor layer 10. The first barrier layer BL1 is provided between the second semiconductor layer 20 and the first well layer WL1. The nth well layer WLn is provided between the nth barrier layer BLn and the (n + 1) th barrier layer BL (n + 1). The (n + 1) th barrier layer BL (n + 1) is provided between the nth well layer WLn and the first semiconductor layer 10.

FIG. 5 is a schematic cross-sectional view illustrating the configuration of another semiconductor light emitting element according to the first embodiment.
FIG. 5 is a cross-sectional view corresponding to the cross section along line A1-A2 of FIG.
As shown in FIG. 5, in the semiconductor light emitting device 111 according to the present embodiment, the insulating layer 60 has a recess 60 d provided on the lower surface 60 l of the insulating layer 60. At least a part of the third region 43 of the first electrode 40 is along the inner surface of the recess 60d. In other words, the third region 43 of the first electrode 40 is provided with a convex portion, and the insulating layer 60 is provided along the convex portion. Other than this, since it can be the same as that of the semiconductor light emitting device 110, the description is omitted.

  In this example, a part of the third region 43 of the first electrode 40 has a concave portion along the inner surface of the concave portion 60d. In this example, a part of the first intermediate conductive layer 71 is embedded in the concave portion of the third region 43 of the first electrode 40. Further, the second intermediate conductive layer 72 is embedded in the remaining space.

  Also in this case, the first semiconductor layer 10 and the light emitting layer 30 are separated by the insulating layer 60. The second semiconductor layer 20 is divided by the second electrode 50 (second groove 20t). Thereby, the laminated semiconductor layer 15 (including the third semiconductor layer 23 in this example) is divided into a plurality of regions. Thereby, deterioration of crystallinity and cracks can be suppressed, and a high-quality semiconductor light emitting device can be provided.

  Also in the semiconductor light emitting device 111, the width of the upper surface 60 u of the insulating layer 60 in the first direction (for example, the X-axis direction) is wider than the width of the lower surface 50 l of the second electrode 50 in the first direction. Thereby, the insulation between the first semiconductor layer 10 and the second electrode 50 and the insulation between the light emitting layer 30 and the second electrode 50 are more reliably performed by the insulating layer 60.

  The width of the insulating layer 60 in the first direction (the direction from the first region 41 to the second region 42) is, for example, not less than 5 micrometers (μm) and not more than 30 μm. It is desirable that the width of the insulating layer 60 in the first direction be 5 μm or more because patterning is easy. When the width of the insulating layer 60 in the first direction is 30 μm or less, the area utilization efficiency of the epitaxial wafer is increased, which is desirable. The width in the first direction of the insulating layer 60 corresponds to the line width of the insulating layer 60. When the insulating layer 60 has a tapered slope (side surface), the width of the insulating layer 60 in the first direction is the first direction of the insulating layer 60 at the center in the thickness direction (Z-axis direction) of the insulating layer 60. The width of

  The width of the second electrode 50 in the first direction is, for example, 3 μm or more and 20 μm or less. It is desirable that the width of the second electrode 50 in the first direction is 3 μm or more because patterning becomes easy. When the width in the first direction of the second electrode 50 is 20 μm or less, the area utilization efficiency of the epitaxial wafer is increased, which is desirable. The width of the second electrode 50 in the first direction corresponds to the line width of the second electrode 50. When the second electrode 50 has a tapered slope (side surface), the width of the second electrode 50 in the first direction is the width of the second electrode 50 in the first direction at the center in the Z-axis direction. Width.

  The width along the first direction of the first region 41 and the width along the second direction of the second region 42 are, for example, 50 μm or more and 500 μm or less. A direction perpendicular to the stacking direction (Z-axis direction) and perpendicular to the first direction from the first region 41 toward the second region 42 is defined as a second direction. At this time, the width of the first region 41 along the first direction is preferably the same as the width of the first region 41 along the second direction. Similarly, the width of the second region 42 along the first direction is preferably the same as the width of the second region 42 along the second direction. However, the width of the first region 41 along the first direction may be changed to the width of the first region 41 along the second direction. Thereby, for example, even when the stress is not uniform in the plane, the occurrence of cracks and the like can be more effectively suppressed.

(Second Embodiment)
The second embodiment relates to a method for manufacturing a semiconductor light emitting device.
Hereinafter, an example of a method for manufacturing the semiconductor light emitting device 111 will be described.

FIG. 6 is a flowchart illustrating the method for manufacturing the semiconductor light emitting element according to the second embodiment.
FIG. 7A to FIG. 7H are schematic cross-sectional views in order of the processes, illustrating the method for manufacturing the semiconductor light emitting element according to the second embodiment.
FIG. 7A to FIG. 7H illustrate the A3-A4 cross section of FIG. 2 with a part thereof omitted.

  As shown in FIGS. 6 and 7A, the laminate 16 is prepared (step S110). The stacked body 16 includes a growth substrate 5, a first conductivity type first semiconductor film 10f, and a second conductivity type second semiconductor film 20f provided between the growth substrate 5 and the first semiconductor film 10f. And a light emitting film 30f provided between the first semiconductor film 10f and the second semiconductor film 20f. In this example, the stacked body 16 further includes a third semiconductor film 23f. The third semiconductor film 23f is provided between the growth substrate 5 and the second semiconductor film 20f.

  The first semiconductor film 10 f becomes the first semiconductor layer 10. The second semiconductor film 20 f becomes the second semiconductor layer 20. The light emitting film 30 f becomes the light emitting layer 30. The third semiconductor film 23 f becomes the third semiconductor layer 23.

  The manufacturing method may further include a step of forming the stacked body 16 (that is, a step of growing the stacked semiconductor layer 15 on the growth substrate 5).

  As shown in FIGS. 6 and 7B, a first trench 15t that divides the first semiconductor film 10f and the light emitting film 30f is formed (step S120). Thereby, the first semiconductor layer 10 and the light emitting layer 30 are formed. The first groove 15 t is provided along a region that becomes the third region 43 of the first electrode 40. The first groove 15t may be further provided at a location where a plurality of elements are separated from each other. In this example, the first trench 15t reaches the second semiconductor film 20f. However, the first trench 15t does not divide the second semiconductor film 20f.

As shown in FIGS. 6 and 7B, the insulating layer 60 is formed on the side surface of the first semiconductor film 10f and the side surface of the light emitting film 30f exposed in the first trench 15t (step S130). ). As the insulating layer 60, for example, a SiO ₂ film having a thickness of 50 nm to 600 nm is formed and processed into a predetermined shape. For example, vapor deposition or sputtering is used to form the insulating layer 60.

For example, after forming a SiO ₂ film on the entire surface of the workpiece, etching is performed using a mask having a predetermined pattern shape. That is, the SiO ₂ film is left in the region where the first semiconductor film 10f and the light emitting film 30f are removed (first groove 15t), and the SiO ₂ film is removed in the region excluding the region. Then, the upper surface of the first semiconductor film 10f (first semiconductor layer 10) is exposed.

  As shown in FIG. 6, the first electrode 40 is formed on the upper surface of the first semiconductor film 10f (first semiconductor layer 10) and on the insulating layer 60 (step S140).

  For example, as shown in FIG. 7C, an Ag film to be the first electrode 40 is formed on the entire top surface of the processed body. The thickness of the Ag film is, for example, 100 nm or more and 400 nm or less. Further, a metal film to be the first intermediate conductive layer 71 is formed on the Ag film. For this metal film, for example, Ti or Ti alloy is used. The thickness of this metal film is, for example, not less than 10 nm and not more than 200 nm. The first intermediate conductive layer 71 functions as a barrier metal.

  As shown in FIG. 6, the conductive support substrate 70 is bonded to the first electrode 40 (step S150).

  For example, a silicon substrate provided with a second intermediate conductive layer 72 (for example, AuSn layer) on the main surface is prepared as the support substrate 70.

  As shown in FIG. 7D, the first electrode 40 and the support substrate 70 are arranged with the first intermediate conductive layer 71 and the second intermediate conductive layer 72 facing each other. Then, the first intermediate conductive layer 71 and the second intermediate conductive layer 72 are brought into contact with each other and heated to join the first electrode 40 and the support substrate 70 together.

  As shown in FIGS. 6 and 7E, the growth substrate 5 is removed (step S160). This removal is performed, for example, by at least one of grinding and etching.

  As shown in FIGS. 6 and 7F, the second semiconductor film 20f is divided to form the second trench 20t that reaches the insulating layer 60 (step S170). The second groove 20t is preferably formed in a forward tapered shape.

  As shown in FIG. 7G, in this example, the unevenness 23p is formed on the surface of the third semiconductor film 23f. For the formation of the unevenness 23p, for example, a wet process using KOH or the like, or an arbitrary dry etching process can be used.

As shown in FIGS. 6 and 7H, the second electrode 50 is formed on the side surfaces (first side surface s1 and second side surface s2) of the second semiconductor film 20f exposed in the second trench 20t. (Step S180). In this example, the second electrode 50 is further provided on the side surface of the third semiconductor layer 23.
Thereby, the semiconductor light emitting element 111 is obtained.

  In addition, the order of said step S110-S180 can be replaced in the technically possible range. At least two of steps S110 to S180 may be performed simultaneously as far as technically possible.

  According to the method for manufacturing a semiconductor light emitting element according to this embodiment, it is possible to suppress the deterioration of crystallinity and cracks, and to provide a method for manufacturing a high quality semiconductor light emitting element.

  In the manufacturing method, the formation of the second electrode 50 (step S180) includes forming the second electrode 50 so that a part of the second electrode 50 is in contact with the insulating layer 60.

  In the present manufacturing method, a silicon substrate can be used as the growth substrate 5. At this time, the first semiconductor film 10f, the second semiconductor film 20f, and the light emitting film 30f include a nitride semiconductor. Thus, when using a material with a large difference in thermal expansion coefficient, deterioration of crystallinity and cracks can be more effectively suppressed by applying this embodiment.

  As described above, this manufacturing method further includes forming the unevenness 23p on the surface of the third semiconductor film 23f after the growth substrate 5 is removed. The third semiconductor film 23 f is included in the stacked body 16. The third semiconductor film 23f is provided between the growth substrate 5 and the second semiconductor film 20f. The impurity concentration of the third semiconductor film 23f is lower than the impurity concentration of the second semiconductor film 20f.

  The first groove 15t divides the first semiconductor film 10f and the light emitting film 30f into a lattice shape. For example, the first groove 15t is formed along the lattice shape of the third region 43 illustrated in FIG. Thereby, the laminated semiconductor layer 15 is divided into a plurality of regions in a lattice shape, and the size of one region of the laminated semiconductor layer 15 can be reduced.

  The second groove 20t extends along the first groove 15t when projected onto a plane (XY plane) parallel to the main surface of the first semiconductor film 10f. Thereby, the second semiconductor film 20f is divided corresponding to the location where the first semiconductor film 10f and the light emitting film 30f are divided.

(Third embodiment)
FIG. 8 is a schematic cross-sectional view illustrating the configuration of the semiconductor light emitting element according to the third embodiment. 8 is a cross-sectional view corresponding to the cross section along line A1-A2 of FIG.
As shown in FIG. 8, in the semiconductor light emitting device 112 according to the present embodiment, the third semiconductor layer 23 is not provided. The second semiconductor layer 20 has unevenness 20 p provided on the upper surface 20 u of the second semiconductor layer 20. Other than this, since it can be the same as that of the semiconductor light emitting device 110, the description is omitted.

  The depth of the unevenness 20p provided in the second semiconductor layer 20 is not less than 0.8 times and not more than 5 times the peak wavelength of light emitted from the light emitting layer 30. High light extraction efficiency is obtained by the unevenness 20p.

  Note that when the base layer 20 i described with reference to FIG. 3 includes a second conductivity type (for example, n-type) impurity, at least a part of the base layer 20 i may be considered to be included in the second semiconductor layer 20. . Further, when the stacked intermediate layer 22 s includes the second conductivity type impurity, it may be considered that at least a part of the stacked intermediate layer 22 s is included in the second semiconductor layer 20.

  The semiconductor light emitting device 112 can also suppress deterioration of crystallinity and cracks, and provide a high quality semiconductor light emitting device.

  In the semiconductor light emitting devices 110 to 112 described above, as illustrated in FIG. 2, the stacked semiconductor layer 15 is divided into 16 4 × 4 regions. However, in the embodiment, the number of divisions of the stacked semiconductor layer 15 is arbitrary.

FIG. 9A to FIG. 9E are schematic plan views illustrating the configuration of the semiconductor light emitting element according to the embodiment.
These drawings show examples of the divided state of the stacked semiconductor layer 15 (that is, examples of patterns of the first region 41, the second region 42, and the third region 43).

  As shown in FIG. 9A, in the semiconductor light emitting device 110a according to the embodiment, the third region 43 has a rectangular outline shape. A first region 41 is provided in the center of the planar shape of the element, a second region 42 is provided in the peripheral portion of the element, and a third region 43 is disposed therebetween. In this example, the laminated semiconductor layer 15 is divided into two regions.

  As shown in FIG. 9B, in the semiconductor light emitting device 110b according to the embodiment, the third region 43 has a rectangular outline and a line segment connecting two opposing sides of the rectangle. In this example, the laminated semiconductor layer 15 is divided into three regions.

  As shown in FIG. 9C, in the semiconductor light emitting device 110c according to the embodiment, the stacked semiconductor layer 15 is divided into four regions. In the semiconductor light emitting devices 110b and 110c, the third region 43 has a line segment region along one direction (for example, the Y-axis direction).

As shown in FIG. 9D, in the semiconductor light emitting device 110d according to the embodiment, the stacked semiconductor layer 15 is divided into 20 regions. In this example, the third region 43 has a lattice shape in two orthogonal directions (for example, the X-axis direction and the Y-axis direction). Further, as in this example, the pitch along the X-axis direction of the line segment extending in the Y-axis direction of the third region 43 is in the Y-axis direction of the line segment extending in the X-axis direction of the third region 43. It may be different from the pitch along.
As shown in FIG. 9E, in the semiconductor light emitting device 110e according to the embodiment, the third region 43 has a partial shape of a hexagonal outline. The shape of the third region 43 may be, for example, a shape corresponding to the crystal orientation of the semiconductor layer. Thereby, more stable characteristics can be obtained.

  In the semiconductor light emitting devices 110a to 110c, the third region 43 does not reach the end face of the device. In the semiconductor light emitting devices 110d and 110e, the third region 43 reaches the end face of the device.

  Thus, in the embodiment, the patterns of the first region 41, the second region 42, and the third region 43 are arbitrary. That is, the divided state of the laminated semiconductor layer 15 is arbitrary. The insulating layer 60 is provided along the third region 43, and the pattern of the insulating layer 60 is also arbitrary. The second electrode 50 is also provided along the third region 43, and the pattern of the second electrode 50 is also arbitrary.

  In the embodiment, the second electrode 50 may have an arbitrary configuration and arrangement depending on the shape, direction, and number of lines to be divided. The second electrode 50 desirably reaches the end face of the semiconductor light emitting device. However, the second electrode 50 can have a closed line or rectangle inside the planar shape of the semiconductor light emitting element, or any other shape.

FIG. 10 is a schematic cross-sectional view illustrating the configuration of the semiconductor light emitting element according to the embodiment.
FIG. 10 is a cross-sectional view corresponding to the cross section along line A1-A2 of FIG.
As shown in FIG. 10, in the semiconductor light emitting device 113 according to the embodiment, the second electrode 50 is formed on the seventh portion p7 provided on the insulating layer 60 and the sixth portion p6 of the fifth portion p5. A part of the second semiconductor layer 20 in addition to the eighth portion p8 in contact with the opposing first side surface s1 and the ninth portion p9 in contact with the second side surface s2 facing the fifth portion p5 of the sixth portion p6. And a portion q1 and a portion q2 that cover the top.

  In this example, the portion q1 covers a part of the fifth portion p5 of the second semiconductor layer 20. The part q2 covers a part of the sixth part p6 of the second semiconductor layer 20. Specifically, the portion q1 covers a part of the tenth portion p10 of the third semiconductor layer 23 provided on the fifth portion p5. The part q2 covers a part of the eleventh part p11 of the third semiconductor layer 23 provided on the sixth part p6. Other than this, since it can be the same as that of the semiconductor light emitting device 110, the description is omitted.

As described above, the second electrode 50 may be further provided on a part of the upper surface of the second semiconductor layer 20 in addition to the side surface of the second semiconductor layer 20.
Also in the semiconductor light emitting device 113, deterioration of crystallinity and cracks can be suppressed, and a high quality semiconductor light emitting device can be provided.

  In a semiconductor light emitting device, a laminated semiconductor layer is formed on a heterogeneous substrate by heteroepitaxial growth. The laminated semiconductor layer is single crystalline. For this reason, in the laminated semiconductor layer, stress is accumulated and cracks are likely to occur. When a crack occurs in the laminated semiconductor layer, a current path that does not pass through the pn junction is generated, so that the efficiency is lowered and the element life is shortened. Furthermore, if the laminated semiconductor layer is partially removed or the surface is processed to have irregularities, the stress state and stress resistance in the laminated semiconductor layer having residual stress become non-uniform. For this reason, when such processing is performed, cracks are more likely to occur.

  In the embodiment, a groove for dividing the stacked semiconductor layer is formed inside the element. Thereby, a residual stress can be relieve | moderated and generation | occurrence | production of a crack can be suppressed. The second electrode 50 is formed by forming a conductive layer on the wall surface of the formed groove. The ohmic contact between the second electrode 50 and the second semiconductor layer 20 is formed on the side surface of the groove. This promotes current diffusion in the light emitting element surface.

  Furthermore, the second electrode 50 can reflect light from the light emitting layer 30 by using Al having high reflectivity, and can efficiently guide the light to the light extraction surface subjected to the uneven processing. According to the embodiment, a highly efficient semiconductor light emitting device including a stress relaxation structure can be provided.

  According to the embodiment, a high-quality semiconductor light emitting device and a method for manufacturing the same can be provided.

In this specification, “nitride semiconductor” means B _x In _y Al _z Ga _1-xyz N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z ≦ 1) Semiconductors having all compositions in which the composition ratios x, y, and z are changed within the respective ranges are included. Furthermore, in the above chemical formula, those further containing a group V element other than N (nitrogen), those further containing various elements added for controlling various physical properties such as conductivity type, and unintentionally Those further including various elements included are also included in the “nitride semiconductor”.

  In the present specification, “vertical” and “parallel” include not only strictly vertical and strictly parallel, but also include, for example, variations in the manufacturing process, and may be substantially vertical and substantially parallel. is good.

  The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a light emitting layer, a first electrode, a second electrode, a supporting substrate, a first intermediate conductive layer, a second intermediate conductive layer, and a growth included in the semiconductor light emitting device With regard to the specific configuration of each element such as a substrate for use, the present invention is similarly implemented by appropriately selecting from a known range and those skilled in the art can similarly obtain the same effect, and are included in the scope of the present invention. Is done.

  Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, on the basis of the semiconductor light-emitting element and its manufacturing method described above as embodiments of the present invention, all semiconductor light-emitting elements that can be implemented by a person skilled in the art with appropriate design changes and manufacturing methods thereof are also included in the present invention. As long as the gist of the present invention is included, it belongs to the scope of the present invention.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 5 ... Growth substrate, 10 ... 1st semiconductor layer, 10f ... 1st semiconductor film, 15 ... Multilayer semiconductor layer, 15t ... 1st groove | channel, 16 ... Laminated body, 20 ... 2nd semiconductor layer, 20f ... 2nd semiconductor film 20i ... Underlayer, 20p ... Uneven, 20t ... Second groove, 20u ... Upper surface, 21 ... First layer, 22 ... Second layer, 22s ... Laminated intermediate layer, 23 ... Third semiconductor layer, 23f ... Third semiconductor 24 ... AlGaN layer, 25 ... AlN layer, 30 ... Light emitting layer, 30f ... Light emitting film, 31 ... Barrier layer, 32 ... Well layer, 40 ... First electrode, 41 ... First region, 42 ... 2nd region, 43 ... 3rd region, 50 ... 2nd electrode, 50l ... lower surface, 55 ... pad part, 60 ... insulating layer, 60d ... recessed part, 60l ... lower surface, 60u ... upper surface, 70 ... support substrate, 71 ... 1st 1 intermediate conductive layer, 72 Second intermediate conductive layer, 110, 110a to 110d, 111 to 113 ... semiconductor light emitting device, 130, 140 ... nitride semiconductor wafer, BL ... barrier layer, IF1, IF2 ... interface, WL ... well layer, p1-p11 ... first 1st to 11th part, q1, q2 ... part, s1 ... first side, s2 ... second side

Claims (14)

A substrate including a first region, a second region, and a third region provided between the first region and the second region;
A first conductivity type first semiconductor layer including: a first portion provided on the first region; and a second portion provided on the second region;
A light emitting layer including a third portion provided on the first portion and a fourth portion provided on the second portion;
A second semiconductor layer of a second conductivity type including a fifth portion provided on the third portion and a sixth portion provided on the fourth portion;
An insulating layer provided between the first portion and the second portion and between the third portion and the fourth portion on the third region;
A second electrode in contact with the insulating layer between said fifth portion and the sixth portion disposed between the front Symbol fifth portion and the sixth portion,
A first electrode provided between the first portion and the first region and between the second portion and the second region, and in contact with the first portion and the second portion ;
With
Wherein the upper surface of the insulating layer, the first width extending from the first region to the second region, the lower surface of the first direction wider semiconductor light-emitting element than the width of the second electrode. A substrate including a first region, a second region, and a third region provided between the first region and the second region;
A first conductivity type first semiconductor layer including: a first portion provided on the first region; and a second portion provided on the second region;
A light emitting layer including a third portion provided on the first portion and a fourth portion provided on the second portion;
A second semiconductor layer of a second conductivity type including a fifth portion provided on the third portion and a sixth portion provided on the fourth portion;
An insulating layer provided between the first portion and the second portion and between the third portion and the fourth portion on the third region;
A second electrode in contact with the insulating layer between said fifth portion and the sixth portion disposed between the front Symbol fifth portion and the sixth portion,
A first electrode provided between the first portion and the first region and between the second portion and the second region, and in contact with the first portion and the second portion ;
With
The insulating layer has a recess provided on the lower surface of the insulating layer;
The even without least the first electrodes in part, a semiconductor light-emitting element along the inner surface of the recess. Wherein the upper surface of the insulating layer, the first of the first width from a region toward the second region, the semiconductor light-emitting of the lower surface of the first direction wider claim 2 than the width of the second electrode element.   A third semiconductor layer including a tenth portion provided on the fifth portion and an eleventh portion provided on the sixth portion, and the impurity concentration of the third semiconductor layer is The semiconductor light emitting element according to claim 1, wherein the impurity concentration is lower than the impurity concentration of the fifth portion and the sixth portion. The third semiconductor layer has irregularities provided on the upper surface of the third semiconductor layer,
5. The semiconductor light emitting element according to claim 4, wherein a depth of the unevenness is 0.8 to 5 times a peak wavelength of light emitted from the light emitting layer. A portion of the second electrode is in ohmic contact with a first side surface of the fifth portion facing the sixth portion ;
6. The semiconductor light emitting element according to claim 1, wherein a part of the second electrode is in ohmic contact with a second side surface of the sixth portion facing the fifth portion .   7. The insulating layer according to claim 1, wherein the insulating layer electrically insulates the first semiconductor layer from the second electrode and electrically insulates the light emitting layer from the second electrode. Semiconductor light emitting device.   The semiconductor light emitting element according to claim 1, wherein the second electrode is reflective to light emitted from the light emitting layer.   The semiconductor light emitting element according to claim 1, wherein the first electrode is reflective to light emitted from the light emitting layer. The second semiconductor layer has irregularities provided on the upper surface of the second semiconductor layer,
3. The semiconductor light emitting element according to claim 1, wherein a depth of the unevenness is 0.8 to 5 times a peak wavelength of light emitted from the light emitting layer. A first intermediate conductive layer provided between the first electrode and the board,
A second intermediate conductive layer provided between the front Kimoto plate and the first intermediate conductive layer,
The semiconductor light emitting device according to claim 1, further comprising: It said first region and said second region is provided in plurality,
Said plurality of first regions, arranged in non-parallel second direction with respect to a direction from said first region to said second region,
It said plurality of second regions, the semiconductor light emitting device according to any one of claims 1 to 11 arranged along the second direction.   The distance between the first electrode and the interface between the first part and the third part is the same as the distance between the first electrode and the interface between the second part and the fourth part. The semiconductor light-emitting device according to claim 1.   The semiconductor light emitting element according to claim 1, wherein a crystal orientation of the first portion is the same as a crystal orientation of the second portion.

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