JP5433798B2 - Semiconductor light emitting device and semiconductor light emitting device - Google Patents

Description

  The present invention relates to a semiconductor light emitting element and a semiconductor light emitting device.

  In the flip-chip type semiconductor light emitting element that extracts light generated from the light emitting layer from the substrate side, the light extraction efficiency can be improved by increasing the reflectance and area of the reflection region on the electrode formation surface.

  For example, when a p-side electrode having both ohmic characteristics and high-efficiency reflection characteristics is used, the reflectance in a region where no electrode is formed is low, which causes a decrease in light extraction efficiency. The light extraction efficiency is improved by increasing the area of the reflection region by devising such as shortening the distance of the n-side electrode.

  When designing an electrode with an emphasis on such light extraction efficiency, high mounting accuracy is required when the semiconductor light emitting element is flip-chip mounted.

  On the other hand, since light-emitting diodes using semiconductor light-emitting elements are required to enhance cost competitiveness by mass production, the time required to mount one element is usually 0.5 seconds or less, and the mounting accuracy is Is very low.

  Patent Document 1 discloses a technique of mounting a flip chip mount type semiconductor light emitting element using metal solder.

JP 2007-324585 A

  The present invention provides a semiconductor light-emitting element and a semiconductor light-emitting device that can be assembled at high speed with high accuracy and have high light extraction efficiency.

According to one embodiment of the present invention, a stacked structure including a first semiconductor layer, a second semiconductor layer, and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer; A first electrode provided on the main surface side of the multilayer structure and connected to the first semiconductor layer, and a second electrode provided on the main surface side of the multilayer structure and connected to the second semiconductor layer Provided on the first semiconductor layer and the second semiconductor layer that are not covered by the first electrode and the second electrode on the main surface side, and on the periphery of the first electrode and the second electrode. A dielectric laminated film formed by laminating dielectric films having different refractive indexes, and upper surfaces of the first electrode and the second electrode not covered by the dielectric laminated film; the upper surface of the dielectric multilayer film in the peripheral portion of the first electrode and the second electrode, and, prior to A conductive film provided on a side surface of the dielectric multilayer film, the semiconductor light-emitting device having a are provided.

  According to another aspect of the present invention, the semiconductor light emitting device further comprising: a first connection member connected to the first electrode; and a second connection member connected to the second electrode; A semiconductor device comprising: a mounting member provided to face the main surface of the semiconductor light emitting element and connected to the first electrode and the second electrode via the first connection member and the second connection member A light emitting device is provided.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor light-emitting device and semiconductor light-emitting device with high light extraction efficiency which can be assembled with high precision and at high speed are provided.

FIG. 5 is a schematic cross-sectional view in order of the processes, illustrating the manufacturing process of the semiconductor light emitting device according to the first embodiment of the invention. 1 is a schematic view illustrating the configuration of a semiconductor light emitting element applied to a manufacturing process of a semiconductor light emitting device according to a first embodiment of the invention. 1 is a schematic cross-sectional view illustrating the configuration of a semiconductor light emitting device manufactured by a manufacturing process of a semiconductor light emitting device according to a first embodiment of the invention. FIG. 3 is a flowchart illustrating the manufacturing process of the semiconductor light emitting device according to the first embodiment of the invention. FIG. 5 is a schematic process cross-sectional view in order of the processes, illustrating a process for manufacturing a semiconductor light emitting element applied to the method for manufacturing a semiconductor light emitting device according to the first embodiment of the invention. FIG. 6 is a schematic process cross-sectional view in order of the processes following FIG. 5. It is a graph which illustrates the characteristic of the semiconductor light-emitting device to which the manufacturing method of the semiconductor light-emitting device concerning the 1st Embodiment of this invention is applied. It is a graph which illustrates the characteristic of the semiconductor light-emitting device to which the manufacturing method of the semiconductor light-emitting device concerning the 1st Embodiment of this invention is applied. It is a schematic cross section which shows the structure of the semiconductor light-emitting device of a comparative example. FIG. 6 is a schematic cross-sectional view illustrating the configuration of another semiconductor light emitting device manufactured by the manufacturing process of the semiconductor light emitting device according to the first embodiment of the invention. It is a schematic diagram which illustrates the structure of another semiconductor light emitting element applied to the manufacturing process of the semiconductor light emitting device according to the first embodiment of the invention. It is process order typical process sectional drawing which illustrates the manufacturing process of another semiconductor light-emitting device applied to the manufacturing method of the semiconductor light-emitting device concerning the 1st Embodiment of this invention. FIG. 13 is a schematic process cross-sectional view in order of the processes following FIG. 12. It is a schematic diagram which illustrates the structure of another semiconductor light emitting element applied to the manufacturing process of the semiconductor light emitting device according to the first embodiment of the invention. It is a schematic diagram which illustrates the structure of another semiconductor light emitting element applied to the manufacturing process of the semiconductor light emitting device according to the first embodiment of the invention. It is a flowchart figure which illustrates the manufacturing process of the semiconductor light-emitting device concerning the 2nd Embodiment of this invention. It is a flowchart figure which illustrates the manufacturing process of the semiconductor light-emitting device concerning the 3rd Embodiment of this invention. It is a flowchart figure which illustrates the manufacturing process of the semiconductor light-emitting device concerning the 4th Embodiment of this invention. It is a flowchart figure which illustrates the manufacturing process of the semiconductor light-emitting device concerning the 5th Embodiment of this invention. It is typical sectional drawing which illustrates the structure of another semiconductor light-emitting device manufactured by the manufacturing method of the semiconductor light-emitting device concerning embodiment of this invention.

Embodiments of the present invention will be described below with reference to the drawings.
Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio coefficient of the size between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratio coefficient may be represented differently depending on the drawing.
Further, in the present specification and each drawing, the same reference numerals are given to the same elements as those described above with reference to the previous drawings, and detailed description thereof will be omitted as appropriate.

(First embodiment)
FIG. 1 is a schematic cross-sectional view in order of the processes, illustrating the manufacturing process of the semiconductor light emitting device according to the first embodiment of the invention.
FIG. 2 is a schematic view illustrating the configuration of a semiconductor light emitting element applied to the manufacturing process of the semiconductor light emitting device according to the first embodiment of the invention.
That is, FIG. 4B is a plan view, and FIG. 4A is a cross-sectional view taken along the line AA ′ in FIG.
FIG. 3 is a schematic cross-sectional view illustrating the configuration of the semiconductor light emitting device manufactured by the manufacturing process of the semiconductor light emitting device according to the first embodiment of the invention.
FIG. 4 is a flowchart illustrating the manufacturing process of the semiconductor light emitting device according to the first embodiment of the invention.

First, the configuration of the semiconductor light emitting device 101 to which the semiconductor light emitting device manufacturing apparatus of this embodiment is applied will be described with reference to FIG.
As shown in FIG. 2A, in the semiconductor light emitting device 101 according to the first embodiment of the present invention, an n-type semiconductor layer (first semiconductor layer) 1 is formed on a substrate 10 made of sapphire, for example. A stacked structure 1s is formed in which the layer 3 and the p-type semiconductor layer (second semiconductor layer) 2 are stacked in this order.

  A p-side electrode (second electrode) 4, an n-side electrode (first electrode) 7, and a dielectric laminated film 11 are provided on the same main surface 1a of the laminated structure 1s.

  That is, the p-side electrode 4 is provided on the p-type semiconductor layer 2. As will be described later, the p-side electrode 4 includes a second metal film (second p-side electrode film) 4b (not shown) serving as a high-efficiency reflective film and a first metal made of a metal that does not necessarily require high-efficiency reflective characteristics. 1 metal film (first p-side electrode film) 4a (not shown).

A part of the p-type semiconductor layer 2 and the light emitting layer 3 is removed by, for example, etching, and an n-side electrode 7 is provided on the exposed n-type semiconductor layer 1.
In the specific example shown in FIG. 2B, the n-side electrode 7 occupies a corner of the rectangular semiconductor light emitting element 101, but the shape of the n-side electrode 7 is not limited to this.

  And on the main surface 1a, the dielectric laminated film 11 is provided on the n-type semiconductor layer 1 and the p-type semiconductor layer 2 which are not covered with the n-side electrode 7 and the p-side electrode 4. The dielectric laminated film 11 is configured by laminating dielectric films having different refractive indexes. As will be described later, the dielectric laminated film 11 functions as a guide at the time of assembly in manufacturing a semiconductor light emitting device using the semiconductor light emitting element 101 in addition to the function of reflecting the light emitted from the light emitting layer 3.

The dielectric laminated film 11 may be provided on at least a part of the periphery of at least one of the n-side electrode 7 and the p-side electrode 4. That is, the dielectric multilayer film 11 may be provided so as to completely surround at least one of the periphery of the n-side electrode 7 and the p-side electrode. It may be provided in a part.
A part of the dielectric laminated film 11 may be provided on at least a part of the n-side electrode 7 and the p-side electrode 4.

That is, in the semiconductor light emitting device 101, since the dielectric laminated film 11 is provided, a step is provided between the n-side electrode 7 and the p-side electrode 4 and the dielectric laminated film 11. That is, in the semiconductor light emitting device 101, the dielectric multilayer film 11 has a protruding portion 11 b that protrudes from the n-side electrode 7 and the p-side electrode 4.
The projecting portion 11 b is erected on at least a part of the periphery of at least one of the n-side electrode 7 and the p-side electrode 4.

  And the recessed part 11c is provided between the protrusion parts 11b by this protrusion part 11b.

  Next, a semiconductor light emitting device having such a semiconductor light emitting element 101 will be described with reference to FIG. 3 is drawn with the semiconductor light emitting device 101 illustrated in FIG. 2 upside down.

  As shown in FIG. 3, the semiconductor light emitting device 201 manufactured by the manufacturing process of the semiconductor light emitting device according to this embodiment includes the semiconductor light emitting element 101, the mounting member 13 on which the semiconductor light emitting element 101 is mounted, Have The mounting member 13 is, for example, a submount or a mounting substrate on which a semiconductor light emitting element is mounted.

  The mounting member 13 and the semiconductor light emitting element 101 are joined by a connection member 14 connected to the electrodes (n-side electrode 4 and p-side electrode 7) of the semiconductor light emitting element 101. The connection member 14 can be made of a conductive material that can be welded to a metal. For example, a material that is solid at room temperature and is in a liquid state at high temperature and has conductivity, for example, solder can be used.

  The connection member 14 includes an n-side connection member 14 a connected to the n-side electrode 4 of the semiconductor light emitting element 101 and a p-side connection member 14 b connected to the p-side electrode 7 of the semiconductor light emitting element 101. The connection member 14 (n-side connection member 14a and p-side connection member 14b) can be provided on an electrode (not shown) provided on the mounting member 13. Note that the n-side connection member 14 a and the p-side connection member 14 b protrude from the main surface of the mounting member 13.

  Thus, the semiconductor light emitting element 101 and the mounting member 13 are electrically connected to the electrodes (not shown) provided on the mounting member 13 and the electrodes of the semiconductor light emitting element 101 (the n-side electrode 4 and the p-side electrode 7). Are fixed.

As shown in FIG. 1, in the method for manufacturing the semiconductor light emitting device according to this embodiment for manufacturing the semiconductor light emitting device 201 having such a configuration, the semiconductor light emitting element 101 and the mounting member 13 are opposed to each other. The connecting member 14 is brought into contact with and bonded to the n-side electrode 7 and the p-side electrode 4 using the protruding portion 11b of the dielectric laminated film 11 as a guide.
The protruding portion 11 b is provided on at least a part of the periphery of at least one of the n-side electrode 7 and the p-side electrode 7. Therefore, in the manufacturing method described above, with the protruding portion 11b as a guide, the connecting member 14 is connected to the n-side electrode 7 and the p-side electrode 4 on which the protruding portion 11b is provided (that is, at least one of the above). ) To join.

This will be described in more detail below.
First, as shown in FIG. 1A, for example, using a collet or the like, the semiconductor light emitting element 101 is sucked by a vacuum chuck and carried above the mounting member 13, and the mounting member 13 and the semiconductor light emitting element 101 are moved to each other. Approximate alignment is performed.

Then, the mounting member 13 and the semiconductor light emitting element 101 are brought into contact with each other in a state of being roughly aligned.
That is, as shown in FIG. 4, the semiconductor light emitting element 101 and the mounting member 13 are brought into contact with each other in a state where the concave portion 11 c and the connection member 14 are roughly aligned (step S <b> 110).

  At this time, the dielectric laminated film 11 provided in the semiconductor light emitting device 101 protrudes from the n-side electrode 7 and the p-side electrode 4, and the respective protruding portions 11 b are the n-side guide portion 12 a and the p-side guide portion. 12b. The n-side guide portion 12a and the p-side guide portion 12b are in contact with the n-side connection member 14a and the p-side connection member 14b of the mounting member 13, and are aligned with each other, so that the n-side guide portion 12a and the p-side guide portion are aligned. The n-side connecting member 14a and the p-side connecting member 14b are designed to be inserted and fitted inside 12b.

That is, the planar shapes of the n-side connecting member 14a and the p-side connecting member 14b are recessed portions of the n-side guide portion 12a and the p-side guide portion 12b so as to enter the n-side guide portion 12a and the p-side guide portion 12b, respectively. The shape is smaller than the shape.
That is, the shape of the connection member 14 in the plane parallel to the main surface 1a is smaller than the shape of the recess 11c in the plane parallel to the main surface 1a.

  The heights of the n-side connecting member 14a and the p-side connecting member 14b are respectively steps of the n-side guide portion 12a and the p-side guide portion 12b (steps between the n-side guide portion 12a and the n-side electrode 7, and It is set higher than each of the step between the p-side guide portion 12b and the p-side electrode 4). That is, the height of the connecting member 14 is higher than the height of the protruding portion 11b (the step between the n-side guide portion 12a and the n-side electrode 7 and the step between the p-side guide portion 12b and the p-side electrode 4). .

  As shown in FIG. 1B, for example, when vibration (for example, ultrasonic vibration) is applied to the semiconductor light emitting element 101 through a collet, the semiconductor light emitting element 101 instantaneously moves in the range of several tens of μm, and the n side The n-side connecting member 14a and the p-side connecting member 14b are inserted and fitted inside the guide portion 12a and the p-side guide portion 12b, and the semiconductor light emitting element 101 is fixed at that position. In the above description, the vibration may be applied to at least one of the semiconductor light emitting element 101 and the mounting member 13. The frequency of the vibration is not particularly limited, but ultrasonic vibration of 20 kHz or higher is desirable.

  That is, as shown in FIG. 4, in the contacted state, vibration is applied to at least one of the semiconductor light emitting element 101 and the mounting member 13, and the connection member 14 is placed in the recess 11 c surrounded by the protrusion 11 b. The connecting member 14 is brought into contact with at least one of the n-side electrode 7 and the p-side electrode 7 (step S120).

  Thereafter, for example, the temperature is raised to a temperature equal to or higher than the melting point of the connection member 14, and the connection member 14 is welded to the p-side electrode 4 and the n-side electrode 7.

That is, after the fitting step, the connection member 14 is welded to at least one of the n-side electrode 7 and the p-side electrode 4 (step S130).
Thus, the semiconductor light emitting device 201 can be manufactured by assembling the semiconductor light emitting element 101 and the mounting member 13 having high light extraction efficiency with high accuracy and at high speed. Further, by using such a manufacturing method, the accuracy is improved, and the light extraction efficiency of the semiconductor light emitting device 201 is increased.

  In addition, what is necessary is just to implement the heating in said step S130 by the property of the connection member 14. FIG. For example, when the connection member 14 is solder, the connection member 14 is melted by heating, and the connection member 14 is welded to at least one of the n-side electrode 7 and the p-side electrode 4.

Further, the above step S130 may be performed depending on the nature of the connection member 14 and the electrical characteristics and reliability required in the semiconductor light emitting device.
That is, after the fitting step in step S120, the connection member 14 and at least one of the n-side electrode 7 and the p-side electrode 4 are electrically connected by contact resistance and reliability that are practically required. Then, the above step S130 can be omitted. Further, after step S120, for example, the semiconductor light emitting element 101 and the mounting member 13 are stored inside another holder or the like, and the connection member 14, the n-side electrode 7 and the p-side electrode 4 are generated by force from the holder. Step S130 can be omitted if at least one of the above is electrically connected with contact resistance and reliability that are practically required.

  In the method of manufacturing a semiconductor light emitting device according to the present embodiment, the range in which the semiconductor light emitting element 101 can be aligned includes the strength of pressing (or contacting) the semiconductor light emitting element 101 with a collet, and the frequency and strength of vibration. It can be adjusted by adjusting the material of the collet itself for amplifying the vibration amplitude.

  According to the manufacturing method of the semiconductor light emitting device according to the present embodiment, it is not necessary to use a gold bump or the like by a ball bonder, and high-precision alignment is possible. Can be small. Thereby, since the area of the p-side electrode 4 can be increased, the light emitting region and the reflective region are expanded, and the light output can be improved.

  Then, on the substrate 10 on which the semiconductor light emitting element 101 is formed, each position guide (n-side guide portion 12a and p-side guide portion 12b) corresponding to each electrode (n-side electrode 4 and p-side electrode 7) is made high. Since the electrodes can be formed with high accuracy, the degree of freedom in designing each electrode is improved, the light extraction efficiency is increased, and the light output is expected to be improved.

  Furthermore, by forming the dielectric laminated film 11 so as to cover the ends of the p-side electrode 4 and the n-side electrode 7, it is possible to prevent the connection member (solder) 14 from coming into contact with the semiconductor layer. (Solder) It is possible to prevent generation of stress or void between the semiconductor layer 14 and the semiconductor layer.

  As described above, the dielectric laminated film 11 of the semiconductor light emitting device 101 can make most of the main surface of the semiconductor layer on which the electrode is formed as a reflective structure, and can be easily used as a position guide. High mounting is possible. As a result, the degree of freedom in electrode design is increased, the light extraction efficiency can be improved by increasing the reflection region, and the cost can be reduced by high-speed mounting. In addition, it is possible to provide a light source with less light emission point deviation in the semiconductor light emitting device. .

Hereinafter, the semiconductor light emitting device 101 applied to the semiconductor manufacturing method of the present embodiment will be described in detail.
First, a specific example of a stacked structure of semiconductor layers formed on the substrate 10 will be described.
The semiconductor light emitting device 101 according to the present embodiment is made of, for example, a nitride semiconductor formed on the substrate 10 made of sapphire.

That is, for example, using a metal organic chemical vapor deposition method, a first AlN buffer layer having a high carbon concentration (carbon concentration: 3 × 10 ¹⁸ cm ^{−3 to} 5 × 10 ²⁰⁾ is formed on the substrate 10 having a sapphire c surface. cm ⁻³ ) of ³ nm to 20 nm, high-purity second AlN buffer layer (carbon concentration 1 × 10 ¹⁶ cm ^{−3 to} 3 × 10 ¹⁸ cm ⁻³ ) of 2 μm, non-doped GaN buffer layer of 3 μm, Si-doped n-type GaN contact 4 μm of the layer (Si concentration 1 × 10 ¹⁸ cm ^{−3 to} 5 × 10 ¹⁸ cm ⁻³ ) and the Si-doped n-type Al _0.10 Ga _0.90 N cladding layer (Si concentration 1 × 10 ¹⁸ cm ⁻³ ) 0.02 [mu] m, Si-doped n-type _Al 0.11 _{Ga 0.89} n barrier layer (Si concentration 1.1~1.5 × ¹⁰ 19 ^{cm -3)} and GaInN light-emitting layer (wavelength 380 nm) and is alternately 0.075μm emitting layer having the multiple quantum well structure formed by periodically laminating a final _Al 0.11 _{Ga 0.89} N barrier layer having a multiple quantum well (Si concentration 1.1~1.5 × ¹⁰ 19 ^{cm -3)} 0.01 μm, Si-doped n-type Al _0.11 Ga _0.89 N layer (Si concentration 0.8 to 1.0 × 10 ¹⁹ cm ⁻³ ) 0.01 μm, non-doped Al _0.11 Ga _0.89 The N spacer layer is 0.02 μm, the Mg doped p-type Al _0.28 Ga _0.72 N clad layer (Mg concentration 1 × 10 ¹⁹ cm ⁻³ ) is 0.02 μm, and the Mg doped p-type GaN contact layer (Mg concentration 1). It is possible to employ a structure in which × 10 ¹⁹ cm ⁻³ ) is 0.1 μm and a high-concentration Mg-doped p-type GaN contact layer (Mg concentration 2 × 10 ²⁰ cm ⁻³ ) is sequentially stacked with a thickness of 0.02 μm. it can.

Here, the n-type semiconductor layer 1 illustrated in FIG. 2A includes a first AlN buffer layer having a high carbon concentration, a high-purity second AlN buffer layer, a non-doped GaN buffer layer, a Si-doped n-type GaN contact layer, and A Si-doped n-type Al _0.10 Ga _0.90 N cladding layer may be included.

The light emitting layer 3 illustrated in FIG. 2A is formed by alternately stacking three periods of the Si-doped n-type Al _0.11 Ga _0.89 N barrier layer) and the GaInN light emitting layer (wavelength 380 nm). And a final Al _0.11 Ga _0.89 N barrier layer of the multiple quantum well.

The p-type semiconductor layer 2 illustrated in FIG. 2A includes the Mg-doped p-type Al _0.28 Ga _0.7a N cladding layer, the Mg-doped p-type GaN contact layer, and the high-concentration Mg-doped p. A type GaN contact layer may be included.

By setting the Mg concentration of the Mg-doped p-type GaN contact layer as high as 1 × 10 ²⁰ cm ⁻³ , ohmic contact characteristics with the p-side electrode can be improved. However, in the case of a semiconductor light emitting diode, unlike the semiconductor laser diode, since the distance between the contact layer and the light emitting layer 4 is short, there is a concern about deterioration of characteristics due to Mg diffusion. Therefore, by utilizing the fact that the contact area between the p-side electrode 4 and the contact layer is wide and the current density during operation is low, the Mg concentration is suppressed to 1 × 10 ¹⁹ cm ⁻³ without significantly impairing electrical characteristics. As a result, Mg diffusion can be prevented and the light emission characteristics can be improved.

The first AlN buffer layer having a high carbon concentration serves to alleviate the difference in crystal type from the substrate, and particularly reduces screw dislocations.
Further, the surface of the high purity second AlN buffer layer is flattened at the atomic level. Therefore, defects in the non-doped GaN buffer layer grown thereon are reduced. For this purpose, the thickness of the high purity second AlN buffer layer is preferably thicker than 1 μm. In order to prevent warping due to distortion, the thickness of the high purity second AlN buffer layer is desirably 4 μm or less. The high-purity second AlN buffer layer is not limited to AlN, and may be Al _x Ga _1-x N (0.8 ≦ x ≦ 1), and can compensate for warpage of the wafer.

  The non-doped GaN buffer layer plays a role of reducing defects by performing three-dimensional island growth on the high purity second AlN buffer layer. In order to flatten the growth surface, the average film thickness of the non-doped GaN buffer layer needs to be 2 μm or more. From the viewpoint of reproducibility and warpage reduction, the total film thickness of the non-doped GaN buffer layer is suitably 4 to 10 μm.

  By employing these buffer layers, defects can be reduced to about 1/10 compared to conventional low-temperature grown AlN buffer layers. With this technique, it is possible to produce a highly efficient semiconductor light-emitting device that emits high-concentration Si into the n-type GaN contact layer and emits light in the ultraviolet band. In addition, light absorption in the buffer layer can be suppressed by reducing crystal defects in the buffer layer.

Next, formation of electrodes on the semiconductor layer in the semiconductor light emitting device 101 will be described.
Hereinafter, the p-side electrode 4 of the semiconductor light emitting device 101 includes a first metal film (first p-side electrode film) 4a made of a metal that does not necessarily require high-efficiency reflection characteristics, and a first metal film (first p-side electrode film). ) A case will be described where a second metal film (second p-side electrode film) 4b provided between 4a and the p-type semiconductor layer 2 and serving as a highly efficient reflective film is provided.

FIG. 5 is a schematic cross-sectional view in order of the processes, illustrating the manufacturing process of the semiconductor light-emitting element applied to the method for manufacturing the semiconductor light-emitting device according to the first embodiment of the invention.
FIG. 6 is a schematic process cross-sectional view in order of the processes following FIG.
First, as illustrated in FIG. 5A, light emission from the p-type semiconductor layer 2 is performed by dry etching using a mask until the n-type contact layer is exposed on the surface in a partial region of the p-type semiconductor layer 2. Layer 3 is removed. At this time, by optimizing the shape of the mask and the dry etching conditions, the step between the p-type semiconductor layer 2 and the n-type semiconductor layer 1 can be processed into a tapered shape with an arbitrary angle. That is, the tapered portion 1t can be provided in the semiconductor layer. Here, an angle formed by the inclined surface of the tapered portion 1t and the layer surface of the semiconductor layer is referred to as a taper angle θ (°). That is, as the taper angle θ is smaller, the tapered portion 1t is inclined more gently. When the taper angle θ is 90 degrees, the stepped portions of the n-type semiconductor layer 1 and the p-type semiconductor layer 2 are stepped. It has a side.

  Next, as shown in FIG. 5B, the n-side electrode 7 having ohmic characteristics is formed. That is, a patterned lift-off resist (not shown) is formed on the exposed n-type contact layer, and, for example, Ti / Al / Ni / Au is used as the n-side electrode 7 for the ohmic contact region by using a vacuum evaporation apparatus. The film is formed with a film thickness of 500 nm, and after the lift-off, sintering is performed in a nitrogen atmosphere at 550 ° C.

  Next, as shown in FIG. 5C, in order to form the p-side electrode 4, a patterned lift-off resist (not shown) is formed on the p-type contact layer, and the second p is formed using a vacuum evaporation apparatus. As the side electrode film 4b, for example, an Ag film is formed with a film thickness of 200 nm, and a sintering process is performed in a nitrogen atmosphere at 350 ° C. after lift-off.

  Next, as shown in FIG. 6A, a patterned lift-off resist (not shown) is formed on the semiconductor layer, and the first p-side electrode film 4b is formed in the region where the Ag film is formed, for example, Pt / Au film is formed with a film thickness of 500 nm. Thereby, the p-side electrode 4 is formed.

Subsequently, as illustrated in FIG. 6B, for example, five pairs of combinations of SiO ₂ films and TiO ₂ films are formed on the semiconductor using a vacuum deposition apparatus.

  Then, as shown in FIG. 6C, a patterned resist (not shown) is formed thereon, and the above dielectric material is exposed so that the p-side electrode 4 and the n-side electrode 7 are exposed by the ammonium fluoride treatment. Then, the dielectric laminated film 11 is formed.

  In this way, by forming the dielectric multilayer film 11, the dielectric multilayer film 11 protrudes from the n-side electrode 7 and the p-side electrode, and at least a part of the peripheral edge of each of the n-side electrode 7 and the p-side electrode 4 The protruding portion 11b provided on the n-side becomes the n-side guide portion 12a and the p-side guide portion 12b.

  Then, it is cut by cleaving or a diamond blade to obtain individual light emitting elements. In this way, the semiconductor light emitting device 101 illustrated in FIG. 2 is formed.

  Thereafter, as described in FIG. 1, the semiconductor light emitting device 201 is manufactured by mounting the semiconductor light emitting element 101 on the mounting member 13.

Further, the semiconductor light emitting device 101 will be described.
As already described, the dielectric multilayer film 11 includes a first dielectric layer (for example, SiO ₂ ) and a second dielectric layer (for example, TiO ₂ ) as two or more types of dielectrics having different refractive indexes. For example, a combination of five laminated films, for example, a laminated film composed of a total of ten dielectric layers can be used. At this time, the thickness of each of the first dielectric layer and the second dielectric layer is λ / (4n) where n is the refractive index and λ is the emission wavelength from the light emitting layer 3. Set to

That is, the dielectric multilayer film 11 includes a first dielectric layer having a first refractive index n _1, and a second dielectric layer having a different second refractive index n ₂ from the first refractive index n ₁ When the emission wavelength of the light emitting layer 3 is λ, the thickness of each of the first dielectric layers is substantially λ / (4n ₁ ), and the second dielectric The thickness of each of the layers is substantially λ / (4n ₂ ).

  In the dielectric laminated film 11, the higher the refractive index ratio of the combined dielectrics, and the greater the number of combinations (number of pairs) of layers having different refractive indexes, the higher the reflectivity, and the margin for the film thickness and wavelength. Also become wider.

FIG. 7 is a graph illustrating characteristics of the semiconductor light emitting element to which the method for manufacturing the semiconductor light emitting device according to the first embodiment of the invention is applied.
That is, this figure exemplifies the simulation result regarding the reflectance of the emitted light perpendicularly incident on the dielectric multilayer film 11 from GaN, and FIG. 10 (a) exemplifies the dependence of the reflectance on the refractive index ratio. FIG. 4B illustrates the dependence of the reflectance on the number of pairs. The horizontal axis in FIG. 6A represents the refractive index ratio of two types of combinations of dielectrics in the dielectric multilayer film 11, and the horizontal axis in FIG. Represents the number of dielectric pairs, and the vertical axis in FIGS. 4A and 4B represents the reflectance.
In this simulation, each parameter is changed using the physical property values of the material of the dielectric multilayer film 11 of the semiconductor light emitting device 101 described above.

As shown in FIGS. 7A and 7B, the reflectance can be a value close to 100% by appropriately selecting the conditions for both the refractive index ratio and the number of pairs.
For example, as shown in FIG. 7A, in order for the reflectance to be 95% or more, the refractive index ratio is desirably 1.4 or more.
Further, as shown in FIG. 7B, it is desirable that the number of pairs is 3 or more for the reflectance to be 95% or more.

  Note that, as the incident angle from GaN to the dielectric laminated film 11 is tilted from the vertical, the reflectivity increases and total reflection occurs at a certain threshold angle.

  From these properties, if the design conditions are selected, it is expected that the light extraction efficiency will be improved by adopting the dielectric laminated film 11 that functions as a reflective film having higher performance than the metallic reflective film. In the semiconductor light emitting device 101 of this specific example, the design reflectance of the dielectric laminated film 11 is 99.7%.

  Since the emitted light incident on the cross section of the semiconductor layer sandwiching the light emitting layer 3 is affected by the film thickness in the normal direction of the dielectric multilayer film 11 formed on the cross section of the semiconductor layer, unless the taper angle is 0 °, This is influenced by the dielectric laminated film 11 shifted in a direction thinner than the designed film thickness. The looser the taper angle, the more the dielectric laminated film in the semiconductor layer cross section functions as designed.

FIG. 8 is a graph illustrating characteristics of the semiconductor light emitting element to which the method for manufacturing the semiconductor light emitting device according to the first embodiment of the invention is applied.
That is, this figure illustrates the calculation result of the relationship between the taper angle and the reflectance of the dielectric multilayer film 11, the horizontal axis represents the taper angle, and the vertical axis represents the reflectance of the dielectric multilayer film 11. Represent. And the figure has illustrated the calculation result using the design conditions already demonstrated regarding the semiconductor light-emitting device 101. FIG.

As shown in FIG. 8, when the taper angle θ is about 40 degrees or less, high reflection characteristics are shown. However, when the taper angle θ is larger than 40 degrees, the film thickness of the dielectric multilayer film 11 is increased. Is too thin to show high reflection characteristics as designed.
Note that the margin of high reflection characteristics with respect to the taper angle becomes wider as the refractive index ratio of the two types of dielectrics to be stacked increases.

  Further, by providing the tapered portion 1t, it is possible to prevent disconnection of the dielectric laminated film 11 in the cross section of the semiconductor layer sandwiching the light emitting layer 3. Further, it functions as a region for changing the angle of emitted light that is not extracted outside by repeated reflection in the semiconductor layer, so that the light extraction efficiency is improved.

  The taper angle θ of the tapered portion 1t can be appropriately determined based on the element area, light emission characteristics, processing accuracy, and the like of the semiconductor light emitting element.

  The dielectric laminated film 11 includes silicon (Si), aluminum (Al), zirconium (Zr), titanium (Ti), niobium (Nb), tantalum (Ta), magnesium (Mg), hafnium (Hf), cerium ( An oxide such as Ce) and zinc (Zn), a nitride, an oxynitride, or the like can be used. The total thickness of the dielectric films to be laminated is preferably 50 nm or more for ensuring insulation and 1000 nm or less for suppressing cracks in the dielectric film.

  And in order to improve the performance as a position guide, it is more preferable to set it as 1000 nm or more and 10000 nm or less from the thickness of the dielectric laminated film 11 being as thick as possible.

  Further, in order to suppress stress between different materials due to heat generation during element operation, the first layer on the semiconductor layer side of the dielectric multilayer film 11 is preferably a material having a linear expansion coefficient close to that of the semiconductor layer. For example, when the semiconductor layer is GaN, it is preferable to use, for example, SiN for the first layer on the semiconductor layer side of the dielectric multilayer film 11.

Since the dielectric laminated film 11 can relieve the stress applied to the inside by laminating different types of dielectrics, even if the total film thickness increases, cracks, cracks, etc. Since the damage to the semiconductor layer is less likely to occur and the stress on the semiconductor layer can be relaxed, the performance as a position guide is improved and the reliability is also improved.
In particular, the stress relaxation effect is promoted by laminating dielectrics having tensile stress and compressive stress.

  And since the dielectric laminated film 11 used as each position guide is provided around the connection member 14, it is possible to prevent the connection member (solder) from being excessively spread during the mounting process by heat treatment. Thereby, the degree of freedom of design such as the area and film thickness of the connection member (solder) 14 is increased, the degree of freedom of wettability with respect to each electrode is increased, and mounting is possible for a short time.

A semiconductor light emitting element to which the manufacturing method of the semiconductor manufacturing apparatus of the present embodiment is applied includes at least an n-type semiconductor layer, a p-type semiconductor layer, and a semiconductor layer including a light emitting layer sandwiched between them. The material is not particularly limited, but for example, a gallium nitride-based compound semiconductor such as Al _x Ga _1-xy In _y N (x ≧ 0, y ≧ 0, x + y ≦ 1) is used. The method for forming these semiconductor layers is not particularly limited. For example, techniques such as metal organic chemical vapor deposition and molecular beam epitaxial growth can be used.

  Further, in the semiconductor light emitting device to which the manufacturing method of the semiconductor manufacturing apparatus of the present embodiment is applied, the substrate material is not particularly limited, but a general substrate such as sapphire, SiC, GaN, GaAs, Si or the like is used. Can be used. The substrate may be finally removed.

  Further, as already described, the p-side electrode 4 is composed of a second p-side electrode film 4b containing at least silver or a silver alloy and a first p-side electrode film 4a made of a metal not containing at least silver or a silver alloy. Can do. The material of the second p-side electrode film 4b may be a silver single layer or an alloy layer containing a metal other than silver or aluminum.

  The reflection efficiency of a normal metal single layer film in the visible light band tends to decrease as the wavelength becomes shorter in the ultraviolet region of 400 nm or less, but silver has a high reflection efficiency even for light in the ultraviolet region of 370 nm to 400 nm. Has characteristics. Therefore, in the case of a semiconductor light emitting device that emits ultraviolet light and the second p-side electrode film 4b is made of silver or a silver alloy, it is desirable that the second p-side electrode film 4b on the semiconductor interface side has a larger silver component ratio. The film thickness of the second p-side electrode film 4b is preferably 100 nm or more in order to ensure light reflection efficiency.

  When silver or a silver alloy is used for the second p-side electrode film 4b, the risk of insulation failure and breakdown voltage failure due to migration from silver or silver alloy decreases as the distance between the second p-side electrode film 4b and the n-side electrode 7 increases. To do. The p-side electrode 4 facing the n-side electrode 7 in the vicinity of the center of the element has a higher light extraction efficiency if it is formed to the end of the p-type contact layer as long as process conditions such as exposure accuracy allow. Considering the current path from the second p-side electrode film 4b to the n-side electrode 7, the current tends to concentrate in the region where the distance between the second p-side electrode film 4b and the n-side electrode 7 is the shortest. In order to relax, it is preferable to design the region having the shortest distance as long as possible among the regions where the second p-side electrode film 4b and the n-side electrode 7 face each other.

  Further, when viewed in plan, the longer the length of the region where the second p-side electrode film 4b and the n-side electrode 7 face each other, the more current paths to the second p-side electrode film 4b and the n-side electrode 7 increase. Electric field concentration is alleviated and deterioration of the second p-side electrode film 4b is suppressed. In consideration of these effects, the area and shape of the second p-side electrode film 4b and the distance between the second p-side electrode film 4b and the n-side electrode 7 can be appropriately determined.

  The first p-side electrode film 4a is made of a metal that does not contain silver, and is in electrical contact with the second p-side electrode film 4b. The material of the first p-side electrode film 4a is not particularly limited, and may be a metal single layer film or multilayer film, a metal alloy layer, a conductive oxide film single layer film or multilayer film, or a combination thereof. May be. The film thickness of the 1st p side electrode film 4a is not specifically limited, For example, it can select between 100 nm and 1000 nm.

  The material of the n-side electrode 7 is not particularly limited, and is composed of a conductive single layer film or multilayer film used as an ohmic electrode of an n-type semiconductor. The film thickness of the n-side electrode 7 is not particularly limited, and can be selected between 5 nm and 1000 nm.

  Separate pads can be provided on the p-side electrode 4 and the n-side electrode 7. The film thickness of the pad is not particularly limited, and can be selected, for example, between 1000 nm and 10000 nm. By forming the pad, it is possible to improve the wettability during welding with the connection member (for example, solder) 14 and to reduce the risk that each electrode causes an excessive alloying reaction with the connection member (for example, solder) 14.

In addition, by using a crystal on a single crystal AlN buffer, high luminous efficiency can be realized even in a wavelength region shorter than 400 nm, where efficiency usually decreases due to crystal defect reduction.
In addition, when an amorphous or polycrystalline AlN layer is provided to alleviate the difference in crystal type on the sapphire substrate, the buffer layer itself becomes a light absorber, so that light as a light emitting element can be obtained. The take-out efficiency will be reduced. On the other hand, the n-type semiconductor layer 1, the light emitting layer 3, and the p-type semiconductor layer 2 are formed on the substrate 10 made of sapphire through the high carbon concentration single crystal AlN buffer layer and the high purity single crystal AlN buffer layer. As a result, the buffer layer is unlikely to be an absorber of light and crystal defects can be greatly reduced, so that the absorber in the crystal can be greatly reduced. In this case, the emitted light can be repeatedly reflected in the crystal many times, and the effect of increasing the reflective region on the electrode formation surface is enhanced. These effects are expected to improve the emission intensity.

FIG. 9 is a schematic cross-sectional view showing the structure of a semiconductor light emitting device of a comparative example.
As shown in FIG. 9, in the semiconductor light emitting device 90 of the comparative example, the dielectric laminated film 11 is not provided. That is, instead of the dielectric laminated film 11, for example, a SiO ₂ film having a thickness of 400 nm is formed as a single-layer dielectric film (not shown). For this reason, no step is provided between the n-side electrode 7 and the p-side electrode 4, and there is no protruding portion serving as a guide portion.

In the semiconductor light emitting device 90 having such a configuration, the electrodes are formed as follows.
First, in order to form the n-side electrode 7, a patterned lift-off resist is formed on the exposed n-type contact layer and becomes an ohmic contact region using a vacuum evaporation apparatus. For example, Ti / Al / Ni / Au The n-side electrode 7 is formed with a film thickness of 500 nm, and sintering is performed in a nitrogen atmosphere at 550 ° C.

  Then, in order to form the p-side electrode 4, a patterned lift-off resist is formed on the semiconductor layer, and an Ag film to be the second p-side electrode film 4 b is formed on the p-type contact layer by using a vacuum deposition apparatus to 200 nm. After the lift-off, a sintering process is performed in a nitrogen atmosphere at 350 ° C. Similarly, a patterned lift-off resist is formed on the semiconductor layer, and the Pt / Au film of the first p-side electrode film 4a is formed to a thickness of 500 nm so as to cover the region where the Ag film of the second p-side electrode film 4b is formed. Form with thickness.

Then, it is cut by cleaving or a diamond blade to form individual light emitting elements.
In this way, the semiconductor light emitting device 90 of the comparative example can be manufactured.

A method of mounting the semiconductor light emitting element 90 having such a configuration on the mounting member 13 is as follows.
In the mounting process to the mounting member 13, first, the semiconductor light emitting element 101 is carried above the mounting member 13 by using a collet or the like, and the connection member (solder) 14 on the mounting member 13 and each electrode are aligned. Then, it is pressed onto the mounting member 13. Thereafter, the mounting member is heated to a temperature equal to or higher than the melting point of the connection member (solder) 14, and the connection member (solder) 14 is welded to the p-side electrode 4 and the n-side electrode 7.

  In the case of this comparative example, since the relative position between the semiconductor light emitting element 90 and the mounting member 13 is determined by the positioning accuracy of the motor that moves the collet, for example, the mounting accuracy is not high. Further, if the speed of carrying the element is increased to increase the tact time, the mounting accuracy is further lowered. In order to cope with this low mounting accuracy, it is necessary to earn a positioning margin by moving the electrodes of the semiconductor light emitting element 101 away from each other or increasing the area of the n-side electrode 7. As a result, the degree of freedom in electrode design is reduced, and it is not always possible to select an optimal electrode structure for light extraction efficiency and light output.

  On the other hand, according to the present embodiment, by using the dielectric laminated film 11 as a position guide, it becomes possible to mount with high accuracy easily, so that the degree of freedom in electrode design is expanded. At the same time, the dielectric laminated film 11 can be used as a highly efficient reflective film. With these effects, light extraction efficiency and light output can be improved.

  As described above, according to the method for manufacturing a semiconductor light emitting device according to the present embodiment, it is possible to provide a method for manufacturing a semiconductor light emitting device with high light extraction efficiency that can be assembled with high accuracy and at high speed.

FIG. 10 is a schematic cross-sectional view illustrating the configuration of another semiconductor light emitting device manufactured by the manufacturing process of the semiconductor light emitting device according to the first embodiment of the invention.
As shown in FIG. 10, in the semiconductor light emitting device 202, the connection member 14 (n-side connection member 14 a and p-side connection member 14 b) covers a part of the dielectric multilayer film 11.

  That is, the semiconductor light emitting device 202 according to this embodiment includes an n-type semiconductor layer (first semiconductor layer) 1, a p-type semiconductor layer (second semiconductor layer) 2, the first semiconductor layer, and the second semiconductor layer. A laminated structure 1s having a light emitting layer 3 provided between and an n-side electrode (first electrode) provided on the main surface 1a of the laminated structure 1s and connected to the first semiconductor layer ) 7, a p-side electrode (second electrode) 4 provided on the main surface 1a of the multilayer structure 1s and connected to the second semiconductor layer 2, and the first surface on the main surface 1a. A plurality of dielectric films having different refractive indexes provided on the first semiconductor layer and the second semiconductor layer that are not covered by the electrode and the second electrode are stacked, and the first electrode and the second electrode are stacked. Projection 11 erected on at least a part of the periphery of at least one of the electrodes A semiconductor light emitting device 101 having a dielectric laminated film 11 having a surface of the semiconductor light emitting device, and a main surface 1a of the semiconductor light emitting device 101. The semiconductor light emitting device 101 is welded to at least one of the first electrode and the second electrode. And a mounting member 13 having a connecting member 14 that covers a part of the protruding portion 11b.

  Thus, by covering a part of the protruding portion 11b of the dielectric multilayer film 11 with the connection member 14 (for example, solder), for example, moisture or the like enters from the interface between the dielectric multilayer film 11 and the connection member 14. Then, it is possible to prevent the electrodes from reaching the n-side electrode 7 and the p-side electrode 4 and deteriorating.

  In order to manufacture such a semiconductor light emitting device 202, in the method of manufacturing a semiconductor light emitting device according to the present embodiment, the welding process in step S130 illustrated in FIG. A step of covering a part with the connecting member 14.

  At this time, the connection member 14 is required to fix the semiconductor light emitting element 101 and the mounting member 13 with a high-precision pattern so that the n-side electrode 7 and the p-side electrode are not electrically short-circuited.

  As in the method of manufacturing the semiconductor light emitting device according to the present embodiment, the protruding portion 11b formed by the dielectric laminated film 11 is used as a guide, that is, the recessed portion 11c formed by the protruding portion 11b and the connection member 14 are fitted together. Assembling the 101 and the mounting member 13 increases the accuracy of the assembly. For this reason, after the semiconductor light emitting element 101 and the mounting member 13 are assembled and fixed, the shape of the connection member 14 is highly accurate. Thereby, a part of the dielectric laminated film 11 can be covered with the connection member 14 with high accuracy.

  That is, in the comparative example in which the dielectric laminated film 11 is not provided, the assembly accuracy is low. Therefore, when the amount of the connecting member 14 is excessive, the n-side electrode 7 and the p-side electrode are electrically short-circuited. End up. Further, when the amount of the connecting member 14 is excessively small, the deterioration of the electrode cannot be prevented.

  Further, even if the dielectric laminated film 11 is provided, in the manufacturing method of the comparative example in which the dielectric laminated film 11 is not assembled as a guide, the assembly accuracy is low. Therefore, when the amount of the connecting member 14 is excessive, the dielectric laminated film 11 is provided. The connecting member 14 flows out and is disposed in a portion other than the region to be covered on the film 11, and the n-side electrode 7 and the p-side electrode 4 are electrically short-circuited. On the other hand, when the amount of the connecting member 14 is too small, the connecting member 14 cannot cover a predetermined region of the dielectric laminated film 11, and the effect of preventing the electrode deterioration described above cannot be obtained. Further, when the accuracy is low and the amount of the connecting member 14 is small, the inside of the recess 11c provided by the dielectric laminated film 11 cannot be sufficiently filled with the connecting member 14, and a gap is generated, and the electrode Deterioration cannot be prevented and reliability is poor.

  On the other hand, as already described, according to the method for manufacturing the semiconductor light emitting device according to the present embodiment, the dielectric multilayer film 11 is used as a position guide at the time of assembly. It is possible to coat a part of the substrate with the connecting member 14 with a predetermined shape with high accuracy. Thereby, a highly reliable semiconductor light emitting device can be realized. The semiconductor light emitting device 202 according to this embodiment has high reliability because the connection member 14 covers a part of the dielectric multilayer film 11 to be coated with a predetermined shape with high accuracy.

FIG. 11 is a schematic view illustrating the configuration of another semiconductor light emitting element applied to the manufacturing process of the semiconductor light emitting device according to the first embodiment of the invention.
FIG. 12 is a schematic process cross-sectional view in order of the processes, illustrating another process for manufacturing a semiconductor light emitting element applied to the method for manufacturing the semiconductor light emitting device according to the first embodiment of the invention.
FIG. 13 is a schematic process cross-sectional view in order of the processes following FIG.
As shown in FIG. 11, in another semiconductor light emitting device 102 applied to the method for manufacturing the semiconductor light emitting device according to the present embodiment, the dielectric stacked film 11, the n-type semiconductor layer 1, and the p-type semiconductor layer 2. A dielectric film 11a is provided between the two. This dielectric film 11a has a higher step coverage than the dielectric laminated film 11, so that even when the cross section of the semiconductor layer sandwiching the light emitting layer 3 is vertical (taper angle θ is 90 °). The cross section can be satisfactorily coated with the dielectric film 11a. Other than this, it is the same as the semiconductor light emitting device 101 already described, and the description is omitted.
Although omitted in FIG. 11, the p-side electrode 4 includes a first p-side electrode film 4 a and a second p-side electrode film 4 b provided between the first p-side electrode film 4 a and the p-type semiconductor layer 2. And having.

Such a semiconductor light emitting device 102 is manufactured as follows.
First, as shown in FIG. 12A, light emission from the p-type semiconductor layer 2 is performed by dry etching using a mask until the n-type contact layer is exposed on the surface in a partial region of the p-type semiconductor layer 2. Layer 3 is removed.

Next, as shown in FIG. 12B, SiO ₂ to be the dielectric film 11a is formed with a film thickness of 200 nm on the semiconductor layer using a thermal CVD apparatus. By using a thermal CVD apparatus, it is possible to form a film having good coverage with respect to a step, and to form the dielectric film 11a with good coverage even with respect to a vertical cross section.

Next, as shown in FIG. 12C, the n-side electrode 7 having ohmic characteristics is formed. That is, a patterned lift-off resist (not shown) is formed on the semiconductor layer, and a part of the exposed SiO ₂ film on the n-type contact layer is removed by an ammonium fluoride treatment. The SiO ₂ film is removed and formed on the exposed n-type contact layer, and an ohmic contact region is formed using a vacuum deposition apparatus. For example, an n-side electrode 7 made of, for example, a Ti / Al / Ni / Au film is formed to a thickness of 500 nm. Thickness is formed, and sintering is performed in a nitrogen atmosphere at 550 ° C.

Next, as shown in FIG. 13A, in order to form the p-side electrode 4, a patterned lift-off resist (not shown) is formed on the semiconductor layer, and the SiO ₂ film on the p-type contact layer is formed. The part is removed by ammonium fluoride treatment. Then, a patterned lift-off resist is formed on the p-type contact layer, and, for example, an Ag film is formed with a film thickness of 200 nm as the second p-side electrode film 4b using a vacuum evaporation apparatus. Sintering is performed in a nitrogen atmosphere.

  Next, as shown in FIG. 13B, a patterned lift-off resist is formed on the semiconductor layer, and the first p-side electrode film 4a is formed in the region where the Ag film is formed, for example, Pt / Au The film is formed with a thickness of 500 nm, and the p-side electrode 4 is formed.

Subsequently, a patterned lift-off resist (not shown) is formed on the semiconductor layer, and, for example, five pairs of combinations of SiO ₂ films and TiO ₂ films are formed on the semiconductor layer by using a vacuum deposition apparatus. Then, the dielectric laminated film 11 is formed by lift-off. Each film thickness is expressed as λ / (4n) where n is the refractive index and λ is the wavelength of light emitted from the light emitting layer 3.

  In this way, by forming the dielectric multilayer film 11, the p-side guide portion 12b for the p-side electrode 4 and the p-side guide portion 12a for the p-side electrode 7 used at the time of mounting can be formed. it can.

  As described above, the semiconductor light emitting device 102 is provided with the dielectric film 11a having a higher step coverage than the dielectric laminated film 11, for example, formed by the thermal CVD method. Even if the step is steep, the dielectric film 11a can be formed thereon with good coverage. For this reason, since it is not necessary to process the level | step difference of the semiconductor layer cross section which pinches | interposes the light emitting layer 3 in a taper shape, a semiconductor layer processing process with fewer processes can be employ | adopted.

  Further, by protecting the p-type contact layer and the n-type contact layer with the dielectric film 11a before forming the n-side electrode 7 and the p-side electrode 4, the interface between the electrode and the semiconductor layer in these electrode forming steps. Contamination adhering to the substrate can be greatly reduced, so that reliability, yield, electrical characteristics, and optical characteristics can be improved.

  By forming the dielectric film 11a, there is almost no influence on the reflectivity of the dielectric multilayer film 11 and the dielectric film 11a. In the dielectric multilayer film 11, a plurality of pairs of dielectrics having different refractive indexes may be laminated. For example, the design reflectivity is sufficiently increased. In the semiconductor light emitting device 102 of this specific example, the design reflectance of the region where the dielectric film 11a and the dielectric laminated film 11 are overlapped is 99.5%.

FIG. 14 is a schematic view illustrating the configuration of another semiconductor light emitting element applied to the manufacturing process of the semiconductor light emitting device according to the first embodiment of the invention.
As shown in FIG. 14, in another semiconductor light emitting device 103 applied to the method for manufacturing a semiconductor light emitting device according to this embodiment, the p-side electrode 4 includes a first p-side electrode film 4 a and a first p-side electrode. A second p-side electrode film 4b provided between the film 4a and the p-type semiconductor layer 2, and a third p-side electrode between the first p-side electrode film 4a and the second p-side electrode film 4b. A film 4c is provided. Other than this, it is the same as the semiconductor light emitting device 101 already described, and the description is omitted.
In the third p-side electrode film 4c, the material contained in the first p-side electrode film 4a and the solder of the connecting member 14 at the time of mounting diffuses into the second p-side electrode film 4b, or the first p-side electrode film 4a. And the material included in the connection member 14 and the material included in the second p-side electrode film 4b have a function of preventing the reaction. The third p-side electrode film 4c is electrically connected to the first p-side electrode film 4a and the second p-side electrode film 4b.

A material that does not react with silver or does not actively diffuse into silver is used for the third p-side electrode film 4c.
As a material used for the third p-side electrode film 4c, a refractory metal that can be used as a diffusion preventing layer, for example, vanadium (V), chromium (Cr), iron (Fe), cobalt (Co), nickel (Ni) Niobium (Nb), Molybdenum (Mo), Ruthenium (Ru), Rhodium (Rh), Tantalum (Ta), Tungsten (W), Rhenium (Re), Osmium (Os), Iridium (Ir), Platinum (Pt) And a single layer film or a laminated film.

  More preferably, as a metal that has a high work function and can easily obtain ohmic properties with the p-GaN contact layer, iron (Fe), cobalt ( Co), nickel (Ni), rhodium (Rh), tungsten (W), rhenium (Re), osmium (Os), iridium (Ir), and platinum (Pt).

  The film thickness of the third p-side electrode film 4c is preferably in the range of 5 nm to 200 nm so that the film state can be maintained in the case of a single layer film. In the case of a laminated film, it is not particularly limited, and can be selected, for example, from 10 nm to 10000 nm.

  By providing the third p-side electrode film 4c as the diffusion preventing layer, it becomes possible to mount at a higher temperature, so that the mounting speed can be increased and the cost competitiveness can be increased.

  In the semiconductor light emitting device 103, the dielectric film 11a described in the semiconductor light emitting device 102 may be provided.

FIG. 15 is a schematic view illustrating the configuration of another semiconductor light emitting element applied to the manufacturing process of the semiconductor light emitting device according to the first embodiment of the invention.
As shown in FIG. 15, in another semiconductor light emitting element 104 applied to the method for manufacturing the semiconductor light emitting device according to the present embodiment, the p-side electrode 4 and the n-side electrode that are not covered with the dielectric multilayer film 11. 7, the upper surface of the dielectric laminated film 11 around the p-side electrode 4 and the n-side electrode 7 (on the side opposite to the semiconductor layer of the dielectric laminated film 11), and the dielectric laminated film 11. A guide portion conductive film 12m is provided on the side surface. Other than this, it is the same as the semiconductor light emitting device 101 already described, and the description is omitted.
In the peripheral portion of the n-side electrode 7, an n-side guide portion 12a is formed by the dielectric laminated film 11 and the guide portion conductive film 12m. Further, in the peripheral portion of the p-side electrode 4, the p-side guide portion 12 b is formed by the dielectric multilayer film 11 and the guide portion conductive film 12 m. That is, the recess 11c is formed by the guide portion conductive film 12m provided on the side surface of the dielectric multilayer film 11, and the recess 11c and the connection member 14 are fitted together to assemble the semiconductor light emitting element 104 and the mounting member 13. .
As described above, even when the guide conductive film 12m is provided on a part of the protrusion of the dielectric multilayer film 11, the connection member 14 is connected to the n-side electrode 7 and the protrusion 11b of the dielectric multilayer film 11 as a guide. The at least one of the p-side electrodes 4 can be contacted and bonded.

  The guide portion conductive film 12m is formed, for example, by forming a dielectric laminate film 11 and then forming a patterned lift-off resist on the semiconductor layer to form the guide portion conductive film 12m. For example, a Ti / Pt / Au film Can be formed with a film thickness of 500 nm.

  In the n-side guide portion 12a and the p-side guide portion 12b, the guide portion conductive film 12m is provided so as to cover a part of the upper surface and the side surface of the dielectric multilayer film 11, so that the n-side guide portion 12a and It is possible to prevent each guide portion from being damaged by an impact when the p-side guide portion 12b and the connection member 14 (for example, solder) are in contact with each other or by an applied vibration.

  In order to easily form the guide portion conductive film 12m on the side surface of the dielectric multilayer film 11, the cross section of the dielectric multilayer film 11 is preferably tapered.

  By protecting the dielectric laminated film 11 serving as the n-side guide portion 12a and the p-side guide portion 12b with the guide portion conductive film 12m, it becomes possible to use vibration under stronger conditions, and the semiconductor light emitting element 104 has a wider range. Can be moved, the mounting speed can be further increased, and the cost competitiveness can be further increased.

(Second Embodiment)
FIG. 16 is a flowchart illustrating the manufacturing process of the semiconductor light emitting device according to the second embodiment of the invention.
As shown in FIG. 16, the method for manufacturing a semiconductor light emitting device according to the second embodiment of the present invention further includes the following steps before step S <b> 110 illustrated in FIG. 4.

That is, first, the first semiconductor layer (n-type semiconductor layer 1), the light emitting layer 3, and the second semiconductor layer (p-type semiconductor layer 2) are stacked on the substrate 10 (step S210).
Then, the second semiconductor layer and a part of the light emitting layer are removed to expose the first semiconductor layer (step S220).
Then, a first electrode (n-side electrode 7) is formed on the exposed first semiconductor layer (step S230).
Then, a second metal film (p-side electrode 4) is formed on the second semiconductor layer (step S240).
A plurality of types of dielectric films having different refractive indexes are alternately stacked on the exposed first semiconductor layer and the second semiconductor layer that are not covered with the first metal film and the second metal film, The dielectric laminated film 11 is formed (Step S250).
In the above steps S210 to S250, for example, the method described with reference to FIGS. 5 and 6 can be used.

  Thus, according to the manufacturing method of the semiconductor light emitting device according to the present embodiment, the dielectric multilayer film 11 serving as the guide portion can be formed, and the semiconductor light emitting element and the mounting member 13 can be assembled using the dielectric laminated film 11. Therefore, it is possible to provide a method of manufacturing a semiconductor light emitting device that can be assembled with high accuracy and at high speed and has high light extraction efficiency.

  In the above, steps S210 to S250 can be interchanged as much as technically possible, and can be performed simultaneously. For example, the steps S230 and S240 for forming the n-side electrode 7 and the p-side electrode 4 can be interchanged and can be performed simultaneously.

(Third embodiment)
FIG. 17 is a flowchart illustrating the manufacturing process of the semiconductor light emitting device according to the third embodiment of the invention.
As shown in FIG. 17, the method for manufacturing a semiconductor light emitting device according to the third embodiment of the present invention further includes the following steps before step S <b> 110 illustrated in FIG. 4.

That is, the first semiconductor layer (n-type semiconductor layer 1), the light emitting layer 3, and the second semiconductor layer (p-type semiconductor layer 2) are stacked on the substrate 10 (step S310).
Then, the second semiconductor layer and a part of the light emitting layer are removed to expose the first semiconductor layer (step S320).
Then, dielectric films having different refractive indexes are alternately laminated on the exposed part of the first semiconductor layer and the part of the second semiconductor layer, and the dielectric laminated film 11 is formed (step S330).
Then, the first electrode (n-side electrode 7) is formed on the first semiconductor layer not covered with the dielectric multilayer film 11 (step S340).
Then, the second electrode (p-side electrode 4) is formed on the second semiconductor layer not covered with the dielectric multilayer film 11 (step S350).
In each of the above steps S310 to S350, for example, the method described with reference to FIGS. 5 and 6 can be modified and used.

(Fourth embodiment)
FIG. 18 is a flowchart illustrating the manufacturing process of the semiconductor light emitting device according to the fourth embodiment of the invention.
As shown in FIG. 18, in the method for manufacturing the semiconductor light emitting device according to the fourth embodiment of the present invention, after the first semiconductor layer is exposed, before the dielectric stacked film 11 is formed, The dielectric film 11a described is provided.

That is, as shown in FIG. 18, the uncovered portion between the step of exposing the first semiconductor layer (step S220) and the step of forming the dielectric laminated film (step S250). A dielectric having higher coverage with respect to the first semiconductor layer and the second semiconductor layer than the dielectric stacked film 11 on a part of the first semiconductor layer and a part of the second semiconductor layer. The body film 11a is formed (step S225).
In this specific example, step S225 is performed between the step of exposing the first semiconductor layer (step S220) and the step of forming the first electrode (step S230). In this case, the order of step S230 to step S250 can be interchanged, and can be performed simultaneously.

  In the above steps S210 to S250, for example, the method described with reference to FIGS. 12 and 13 can be used.

(Fifth embodiment)
FIG. 19 is a flowchart illustrating the manufacturing process of the semiconductor light emitting device according to the fifth embodiment of the invention.
As shown in FIG. 19, also in the method for manufacturing the semiconductor light emitting device according to the fifth embodiment of the present invention, after the first semiconductor layer is exposed, before the dielectric stacked film 11 is formed, The dielectric film 11a described is provided.

That is, as shown in FIG. 19, the exposed first first layer is exposed between the step of exposing the first semiconductor layer (step S320) and the step of forming the dielectric stacked film (step S330). A dielectric film having a higher covering property on the first semiconductor layer and the second semiconductor layer than on the dielectric stacked film 11 on a part of the semiconductor layer and on a part of the second semiconductor layer. 11a is formed (step S325).
In the above description, the order of steps S330 to S350 can be interchanged and can be performed simultaneously.

  Also in the method for manufacturing a semiconductor light emitting device according to the third to fifth embodiments, the dielectric laminated film 11 having the protruding portion 11b serving as the guide portion is formed, and the semiconductor light emitting element and the mounting member are used by using the dielectric laminated film 11 13 can be assembled, and a semiconductor light emitting device manufacturing method with high light extraction efficiency that can be assembled at high speed with high accuracy can be provided.

  In the method for manufacturing a semiconductor light emitting device according to the second to fifth embodiments, the step of exposing the first semiconductor layer (step S220 or step S320) includes the step of exposing the stacked structure 1s to the stacked structure 1s. A step of forming the tapered portion 1t inclined with respect to the layer surface can be included. Thereby, the coverage of the dielectric multilayer film 11 formed thereon is improved, and the reflection performance of the dielectric multilayer film 11 can be enhanced by this step, and a semiconductor light emitting device with higher light extraction efficiency can be obtained. can get.

  In the method for manufacturing a semiconductor light emitting device according to the first to fifth embodiments, the shape in a plane parallel to the surface of the mounting substrate on the mounting substrate is surrounded by the protruding portion 11b. A step of forming a connection member 14 smaller than the shape of at least one of the side electrode 7 and the p-side electrode 4 can be further included. Thereby, the connection member 14 having a predetermined shape can be formed, and the semiconductor light emitting element and the mounting member 13 can be assembled with high accuracy. At this time, the height of the connection member 14 can be made higher than the height of the protrusion 11b.

FIG. 20 is a schematic cross-sectional view illustrating the structure of another semiconductor light emitting device manufactured by the method for manufacturing a semiconductor light emitting device according to the embodiment of the invention.
The semiconductor light emitting device 301 of this specific example is a white LED in which any one of the semiconductor light emitting elements according to the above embodiment is combined with a phosphor. That is, the semiconductor light emitting device 301 according to this embodiment includes any one of the above semiconductor light emitting elements and a phosphor layer irradiated with light emitted from the semiconductor light emitting elements.
In the following description, the semiconductor light emitting element 101 and a phosphor are combined.

  As shown in FIG. 20, in the semiconductor light emitting device 301 according to the present embodiment, the reflective film 23 is provided on the inner surface of the container 22 made of ceramic or the like. Separately provided. The reflective film 23 is made of, for example, aluminum. Among these, the semiconductor light emitting element 101 is installed via the submount 24 on the reflective film 23 provided on the bottom of the container 22. This submount 24 is the mounting member 13.

  As already described, the semiconductor light emitting element 101 and the submount 24 (mounting member 13) are connected and fixed by the connecting member 14 (for example, solder).

  For fixing the semiconductor light emitting element 101, the submount 24, and the reflective film 23, adhesion using an adhesive, solder, or the like can be used.

  Electrodes patterned so as to insulate the p-side electrode 4 and the n-side electrode 7 of the semiconductor light-emitting element 101 are formed on the surface of the submount 24 on the semiconductor light-emitting element side. A bonding wire 26 is connected to the electrode (not shown). This connection is made at a portion between the reflection film 23 on the inner side surface and the reflection film 23 on the bottom surface.

  A first phosphor layer 211 containing a red phosphor is provided so as to cover the semiconductor light emitting element 101 and the bonding wire 26, and blue, green or yellow phosphors are provided on the first phosphor layer 211. The 2nd fluorescent substance layer 212 containing is formed. A lid portion 27 made of silicon resin is provided on the phosphor layer.

The first phosphor layer 211 includes a resin and a red phosphor dispersed in the resin.
As the red phosphor, for example, Y ₂ O ₃ , YVO ₄ , Y ₂ (P, V) O ₄ can be used as a base material, and trivalent Eu (Eu ³⁺ ) is used as an activator. Include. That is, Y ₂ O ₃ : Eu ³⁺ , YVO ₄ : Eu ^3+, etc. can be used as the red phosphor. The concentration of Eu ³⁺ can be 1% to 10% in terms of molar concentration. As a base material of the red phosphor, LaOS, Y ₂ (P, V) O ₄ or the like can be used in addition to Y ₂ O ₃ and YVO ₄ . In addition to Eu ³⁺ , Mn ⁴⁺ or the like can be used. In particular, by adding a small amount of Bi together with trivalent Eu to the YVO ₄ matrix, absorption at 380 nm increases, so that the luminous efficiency can be further increased. Further, as the resin, for example, silicon resin or the like can be used.

  The second phosphor layer 212 includes a resin and at least one of blue, green, and yellow phosphors dispersed in the resin. For example, a phosphor combining a blue phosphor and a green phosphor may be used, or a phosphor combining a blue phosphor and a yellow phosphor may be used, and a blue phosphor, a green phosphor and a yellow phosphor may be used. You may use the fluorescent substance which combined the fluorescent substance.

As the blue phosphor, for example, (Sr, Ca) ₁₀ (PO ₄ ) ₆ Cl ₂ : Eu ²⁺ , BaMg ₂ Al ₁₆ O ₂₇ : Eu ^2+, or the like can be used.
As the green phosphor, for example, Y ₂ SiO ₅ : Ce ³⁺ , Tb ³⁺ having trivalent Tb as the emission center can be used. In this case, energy is transferred from Ce ions to Tb ions, so that the excitation efficiency is improved. For example, Sr ₄ Al ₁₄ O ₂₅ : Eu ²⁺ can be used as the green phosphor.
For example, Y ₃ Al ₅ : Ce ³⁺ can be used as the yellow phosphor.
Further, as the resin, for example, a silicon resin or the like can be used.
In particular, trivalent Tb exhibits sharp light emission near 550 nm where the visibility is maximized. Therefore, when combined with sharp red light emission of trivalent Eu, the light emission efficiency is significantly improved.

  According to the semiconductor light emitting device 301 according to the present embodiment, the 380 nm ultraviolet light generated from the semiconductor light emitting element 101 is emitted to the substrate 10 side of the semiconductor light emitting element 101, and also uses reflection at the reflective film 23. The phosphors included in each phosphor layer can be excited efficiently.

For example, the phosphor having the emission center of trivalent Eu contained in the first phosphor layer 211 is converted into light having a narrow wavelength distribution around 620 nm, and red visible light can be obtained efficiently. .
In addition, the blue, green, and yellow phosphors included in the second phosphor layer 212 are efficiently excited, and blue, green, and yellow visible light can be efficiently obtained.
As these mixed colors, white light and various other colors can be obtained with high efficiency and good color rendering.

Next, a method for manufacturing the semiconductor light emitting device 301 according to this embodiment will be described.
In addition, since the method demonstrated previously can be used for the process of manufacturing the semiconductor light-emitting device 101, below, the process after the semiconductor light-emitting device 101 is completed is demonstrated.

  First, a metal film to be the reflection film 23 is formed on the inner surface of the container 22 by, for example, sputtering, and this metal film is patterned to leave the reflection film 23 on the inner surface and the bottom surface of the container 22 respectively.

  Next, the semiconductor light emitting device 101 is fixed on the submount 24 (mounting member 13) by the method described in the first embodiment, and the submount 24 is placed on the reflective film 23 on the bottom surface of the container 22. Install and fix. For these fixings, adhesion with an adhesive or soldering can be used.

  Next, an n-side electrode and a p-side electrode (not shown) on the submount 24 are connected to electrodes (not shown) provided on the container 22 side by bonding wires 26.

  Furthermore, a first phosphor layer 211 containing a red phosphor is formed so as to cover the semiconductor light emitting element 101 and the bonding wire 26, and a second phosphor containing a blue, green or yellow phosphor on the first phosphor layer 211. The phosphor layer 212 is formed.

  Each of the methods for forming the phosphor layer is a method in which each phosphor is dispersed in a resin raw material mixed solution, and the resin is cured by heat treatment to cure the resin. In addition, the resin raw material mixture containing each phosphor is dropped and allowed to stand for a while and then cured, so that the fine particles of each phosphor settle and each fluorescent material is deposited under the first and second phosphor layers 211 and 212. The fine particles of the body can be unevenly distributed, and the luminous efficiency of each phosphor can be appropriately controlled. Thereafter, the lid 27 is provided on the phosphor layer, and the semiconductor light emitting device 301 according to this embodiment, that is, a white LED is manufactured.

In this specification, “nitride semiconductor” means B _x In _y Al _z Ga _1-xyz N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z ≦ 1) Semiconductors having all compositions in which the composition ratios x, y, and z are changed within the respective ranges are included. Furthermore, in the above chemical formula, those further including a group V element other than N (nitrogen) and those further including any of various dopants added for controlling the conductivity type are also referred to as “nitride semiconductors”. Shall be included.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, those skilled in the art appropriately select the shape, size, material, arrangement relationship, etc. of each element such as a semiconductor multilayer film, metal film, dielectric film, etc. constituting the semiconductor light emitting element from a well-known range. As long as the present invention can be carried out in the same manner and the same effect can be obtained, it is included in the scope of the present invention.
Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, on the basis of the semiconductor light-emitting device manufacturing method and semiconductor light-emitting device described above as embodiments of the present invention, all semiconductor light-emitting device manufacturing methods and semiconductor light-emitting devices that can be implemented with appropriate design modifications by those skilled in the art As long as the gist of the present invention is included, it belongs to the scope of the present invention.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

1 n-type semiconductor layer (first semiconductor layer)
DESCRIPTION OF SYMBOLS 1a Main surface 1s Laminated structure 1t Tapered part 2 p-type semiconductor layer (2nd semiconductor layer)
3 Light emitting layer 4 P-side electrode (second electrode)
4a First p-side electrode film 4b Second p-side electrode film 4c Third p-side electrode film 7 N-side electrode (first electrode)
DESCRIPTION OF SYMBOLS 10 Board | substrate 11 Dielectric laminated film 11a Dielectric film 11b Protrusion part 11c Recessed part 12a n side guide part 12b p side guide part 12m guide part conductive film 13 mounting member 14 connection member (solder)
14a n-side connection member 14b p-side connection member 22 container 23 reflective film 24 submount 26 bonding wire 27 lid 90, 101, 102, 103, 104 semiconductor light emitting device 201, 202, 301 semiconductor light emitting device 211, 212 phosphor layer

Claims (6)

A stacked structure including a first semiconductor layer, a second semiconductor layer, and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer;
A first electrode provided on a main surface side of the multilayer structure and connected to the first semiconductor layer;
A second electrode provided on the main surface side of the multilayer structure and connected to the second semiconductor layer;
On the main surface side, provided on the first semiconductor layer and the second semiconductor layer that are not covered by the first electrode and the second electrode, provided on the periphery of the first electrode and the second electrode. A dielectric laminated film formed by laminating dielectric films having different portions and different refractive indexes;
The upper surfaces of the first electrode and the second electrode that are not covered with the dielectric multilayer film , the upper surface of the dielectric multilayer film in the periphery of the first electrode and the second electrode, and the dielectric multilayer film A conductive film provided on the side surface of
A semiconductor light emitting device comprising:   2. The semiconductor light emitting element according to claim 1, wherein a portion of the dielectric laminated film provided on the peripheral edge of the first electrode and the second electrode is a protrusion of the dielectric.   The semiconductor light emitting element according to claim 1, wherein a side surface of the multilayer structure is tapered. A first connecting member connected to the first electrode;
A second connecting member connected to the second electrode;
The semiconductor light-emitting device according to claim 1, further comprising: The first connecting member covers at least a part of the dielectric laminated film in the peripheral portion of the first electrode,
5. The semiconductor light emitting element according to claim 4, wherein the second connection member covers at least a part of the dielectric laminated film in a peripheral portion of the second electrode. A semiconductor light emitting device according to claim 4 or 5,
A mounting member provided facing the main surface of the semiconductor light emitting element, and connected to the first electrode and the second electrode via the first connection member and the second connection member;
A semiconductor light emitting device comprising:

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