TWI687916B - Circuit arrangement for controlling backlight source and operation method thereof - Google Patents

Abstract

A circuit arrangement for controlling a backlight source and an operation method thereof are provided. The circuit arrangement includes a generator. The generator receives a sync signal, and generates a pulse width modulation signal synchronous with the sync signal to control the backlight source. The sync signal indicates a frequency of a video including a series of image frames. The sync signal includes a sync period corresponding to a frame of the video. The pulse width modulation signal includes a first waveform pattern in a first sub-period of the sync period and a second waveform pattern in a second sub-period of the sync period. Each of the first waveform pattern and the second waveform pattern includes at least one active pulse. The first waveform pattern is substantially identical to the second waveform pattern.

Description

Circuit device for controlling backlight and operation method thereof

The invention relates to a display device, and in particular to a circuit device for controlling a backlight and an operation method thereof.

FIG. 1 is a schematic diagram illustrating the waveform of the backlight control signal BL1 when the conventional backlight device uses an asynchronous method to control/drive the backlight source. The vertical axis shown in FIG. 1 represents voltage, and the horizontal axis represents time. Figure 1 shows that Vsync represents a vertical synchronization signal, and DE represents a data enable signal. The video processing circuit (not shown) can transmit the vertical synchronization signal Vsync and the data enable signal DE to the panel driving circuit (not shown), so as to control the panel driving circuit to drive the liquid crystal display panel (not shown). The vertical synchronization signal Vsync defines a plurality of video frame periods (video frame), such as the video frame periods F1, F2, F3, and F4 shown in FIG. 1. As shown in FIG. 1, the backlight control signal BL1 of the conventional backlight device has no relation to the phase (or timing) of F1, F2, F3 and F4 during the video frame, that is, the conventional backlight device uses an asynchronous method to control/drive the backlight (Not shown). The LCD panel with asynchronous backlight may have the problem of motion blur.

FIG. 2A is a schematic diagram illustrating the waveform of the backlight control signal BL2 when the conventional backlight device uses a synchronous method to control/drive the backlight source. The vertical axis shown in FIG. 2A represents voltage, and the horizontal axis represents time. In FIG. 2A, Vsync represents a vertical synchronization signal, and DE represents a data enable signal. The vertical synchronization signal Vsync defines a plurality of video frame periods, such as the video frame periods F1, F2, F3, and F4 shown in FIG. 2A. As shown in FIG. 2A, according to the vertical synchronization signal Vsync, the pulse phase (or timing) of the backlight control signal BL2 of the conventional backlight device can be synchronized with the video frame period F1, F2, F3, and F4, that is, the conventional backlight device uses synchronization Way to control/drive the backlight (not shown). When the backlight control signal BL2 is at a high level, the backlight source provides backlight. When the backlight control signal BL2 is at a low level, the backlight source does not provide backlight. The pulse widths PW2 of the backlight control signal BL2 in the video frames F1, F2, F3, and F4 are the same as each other, and these pulse widths PW2 can be adjusted according to usage requirements.

FIG. 2B is a schematic diagram illustrating the waveform of the backlight control signal BL2 when another conventional backlight device uses a synchronous method to control/drive the backlight source. The vertical axis shown in FIG. 2B represents voltage, and the horizontal axis represents time. The vertical synchronization signal Vsync and the data enable signal DE shown in FIG. 2B can refer to the related description in FIG. 2A, so they will not be described again. According to the data enable signal DE, as shown in FIG. 2B, the phase (or timing) of the backlight control signal BL2 of the conventional backlight device can be synchronized with the video frame periods F1, F2, F3, and F4, that is, the conventional backlight device is synchronized Control/drive backlight (not shown). The pulse widths PW2 of the backlight control signal BL2 in the video frames F1, F2, F3, and F4 are equal to each other, and these pulse widths PW2 can be adjusted according to usage requirements. In any case, in the actual application environment, the period length of the vertical synchronization signal Vsync (the period length of the data enable signal DE) may not be fixed, that is, the lengths of F1, F2, F3, and F4 during the video frame may be different from each other ( (As shown in Figure 2A and Figure 2B). For a liquid crystal display panel using a synchronous backlight, because the period length of the vertical synchronization signal Vsync is not fixed, the conventional backlight device may have a problem of backlight flicker.

It should be noted that the content of the "prior art" paragraph is used to help understand the present invention. Part of the content (or the entire content) disclosed in the "Prior Art" paragraph may not be the conventional technology known to those with ordinary knowledge in the technical field. The content disclosed in the "Prior Art" paragraph does not mean that the content has been known by those with ordinary knowledge in the technical field before the application of the present invention.

The invention provides a circuit device for controlling a backlight source and an operation method thereof to improve the problem of backlight flicker.

Embodiments of the present invention provide a circuit device for controlling a backlight source. The circuit arrangement includes a generator. The generator is used to receive a synchronization signal (sync signal) and generate a pulse width modulation (PWM) signal synchronized with the synchronization signal to control the backlight source. The synchronization signal indicates the frequency of the video, and the video includes a series of image frames. The synchronization signal includes a synchronization period corresponding to a frame of the video. The pulse width modulation signal includes a first waveform pattern in a first sub-period of the synchronization period and a second waveform pattern in a second sub-period of the synchronization period. Each of the first waveform pattern and the second waveform pattern includes at least one active pulse. The first waveform pattern is substantially the same as the second waveform pattern.

Embodiments of the present invention provide an operation method of a circuit device for controlling a backlight. The operation method includes: receiving a synchronization signal by a generator, wherein the synchronization signal indicates a frequency of a video, and the video includes a series of image frames; and generating, by the generator, a pulse width synchronized with the synchronization signal Modulate the signal to control the backlight. The synchronization signal includes a synchronization period corresponding to a frame of the video, and the pulse width modulation signal includes a first waveform pattern in a first sub-period of the synchronization period and the synchronization period The second waveform pattern in the second sub-period, each of the first waveform pattern and the second waveform pattern includes at least one effective pulse, and the first waveform pattern and the second waveform pattern basically the same.

Embodiments of the present invention provide a circuit device for controlling a backlight. The circuit arrangement includes a generator. The generator is used to receive the synchronization signal and generate a pulse width modulation signal synchronized with the synchronization signal to control the backlight source. The synchronization signal indicates the frequency of the video, which contains a series of image frames. The synchronization signal includes a synchronization period corresponding to a frame of the video. The pulse width modulation signal includes a plurality of repeated waveform patterns in the first sub-period and the second sub-period of the synchronization period. Each of the plurality of repeating waveform patterns includes at least one effective pulse.

Embodiments of the present invention provide a circuit device for controlling a backlight. The circuit arrangement includes a generator. The generator is used to receive the synchronization signal and generate a pulse width modulation signal synchronized with the synchronization signal to control the backlight source. The synchronization signal indicates the frequency of the video, which contains a series of image frames. The synchronization signal includes a synchronization period corresponding to a frame of the video. The generator divides the synchronization period into at least a first sub-period and a second sub-period. The pulse width modulation signal includes a first waveform pattern in the first sub-period of the synchronization period and a second waveform pattern in the second sub-period of the synchronization period. Each of the first waveform pattern and the second waveform pattern includes at least one effective pulse.

Embodiments of the present invention provide a circuit device for controlling a backlight. The circuit arrangement includes a generator. The generator is used to receive the synchronization signal and generate a pulse width modulation signal synchronized with the synchronization signal to control the backlight source. The synchronization signal indicates the frequency of the video. The video contains a series of image frames. The synchronization signal includes a first synchronization period corresponding to the first frame of the video and a second synchronization period corresponding to the second frame of the video. The first synchronization period is longer than the second synchronization period in time. The pulse width modulation signal includes a first waveform pattern in a first sub-period of the first synchronization period, a second waveform pattern in a second sub-period of the first synchronization period, and a The third waveform pattern in the second synchronization period. Each of the first waveform pattern, the second waveform pattern, and the third waveform pattern includes at least one effective pulse, respectively. The first waveform pattern is substantially the same as the second waveform pattern.

Based on the above, the circuit device for controlling the backlight and the operation method thereof according to the embodiments of the present invention divide a synchronization period into at least a first sub-period and a second sub-period. The first waveform pattern in the first sub-period and the second waveform pattern in the second sub-period respectively include at least one effective pulse. The first waveform pattern is substantially the same as the second waveform pattern. If the length of the synchronization period is too long, the first waveform pattern and the second waveform pattern can bring a frequency doubling effect and make it difficult for human eyes to perceive flicker. Therefore, the circuit device and its operation method can improve the problem of backlight flicker.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

The term "coupling (or connection)" used in the entire specification of the case (including the scope of patent application) may refer to any direct or indirect connection means. For example, if it is described that the first device is coupled (or connected) to the second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be connected to another device or a certain device. Connection means indirectly connected to the second device. The terms "first" and "second" mentioned in the entire specification of the case (including the scope of patent application) are used to name the element, or to distinguish between different embodiments or ranges, not to limit the number of elements The upper or lower limit is not used to limit the order of components. In addition, wherever possible, elements/components/steps using the same reference numbers in the drawings and embodiments represent the same or similar parts. Elements/components/steps that use the same reference numbers or use the same terminology in different embodiments may refer to related descriptions with each other.

FIG. 3 is a schematic diagram of a circuit block of a display device 300 according to an embodiment of the invention. The display device 300 includes a display panel 330, a panel driving circuit 320, and a video processing circuit. According to design requirements, the video processing circuit is, for example, a scaler circuit 310 and/or other video signal processing circuits. The scaler circuit 310 (video processing circuit) can transmit the clock signal, the synchronization signal and the video data to the panel driving circuit 320, so as to control the panel driving circuit to drive the display panel 330. According to design requirements, the synchronization signal may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and/or other synchronization signals. The vertical synchronization signal may define multiple video frame (video frame) periods. In other words, the synchronization signal may indicate the frequency (or period) of video, where the video contains a series of image frames. According to design requirements, the display panel 330 may be a liquid crystal display (Liquid Crystal Display, LCD) panel or other types of display panels. The scaler circuit 310, the panel driving circuit 320, and the display panel 330 are conventional components, so they are not described here.

In the embodiment shown in FIG. 3, the display device 300 further includes a backlight 350 and a circuit device for controlling the backlight 350. In the embodiment shown in FIG. 3, the circuit device includes a generator 340, for example. The generator 340 may receive the synchronization signal from a video processing circuit (eg, scaler circuit 310). According to the synchronization signal, the generator 340 may control/drive the backlight 350 in a synchronization manner. The generator 340 may perform full-area backlight control or partition-area backlight control on the backlight 350. The backlight 350 may provide the backlight 351 to the display panel 330. According to design requirements, the backlight 350 may be a direct type backlight module or an edge type backlight module. Since the generator 340 controls/drives the backlight 350 using a synchronization method, the problem of motion blur can be effectively improved.

In the embodiment shown in FIG. 3, the generator 340 includes a pulse width modulation (pulse width modulation, hereinafter referred to as PWM) control circuit 341 and a backlight driving circuit 342. The PWM control circuit 341 is coupled to a video processing circuit (such as the scaler circuit 310) to receive synchronization signals (such as vertical synchronization signals, data enable signals, and/or other synchronization signals). The PWM control circuit 341 can generate the PWM signal BL3. The backlight driving circuit 342 is coupled to the PWM control circuit 341 to receive the PWM signal BL3. According to the PWM signal BL3, the backlight driving circuit 342 can drive the backlight 350 of the display panel 330. The PWM control circuit 341 can perform full-area backlight control or partition-area backlight control on the backlight 350.

FIG. 4 is a schematic flowchart of an operation method of a circuit device for controlling a backlight according to an embodiment of the invention. Please refer to Figures 3 and 4. In step S410, the PWM control circuit 341 receives a synchronization signal (such as a vertical synchronization signal, a data enable signal, and/or other synchronization signals) from a video processing circuit (such as the scaler circuit 310), where the synchronization signal defines multiple During the video frame. In step S420, the PWM control circuit 341 divides each of these video frame periods into at least a first period and a second period, where the lengths of the first periods of different video frame periods are the same as each other.

FIG. 5 is a schematic diagram illustrating the waveform of the PWM signal BL3 shown in FIG. 3 according to an embodiment of the present invention. The vertical axis shown in FIG. 5 represents voltage, and the horizontal axis represents time. The embodiment shown in FIG. 5 assumes that the PWM control circuit 341 receives a vertical synchronization signal Vsync (video synchronization information) from a video processing circuit (such as the scaler circuit 310). Please refer to Figure 3, Figure 4 and Figure 5. The vertical synchronization signal Vsync defines a plurality of video frame periods, such as the video frame periods F5, F6, F7 and F8 shown in FIG. 5. In another embodiment, the PWM control circuit 341 receives the data enable signal DE (synchronization signal) from the video processing circuit (eg, the scaler circuit 310). The data enable signal DE may also define multiple video frame periods, such as the video frame periods F5, F6, F7, and F8 shown in FIG. 5.

In step S420, the PWM control circuit 341 divides each of these video frame periods into at least a first period and a second period. According to design requirements, the first period includes part or all of the data period during the video frame, and the second period includes part or all of the blank period during the video frame.

For example, according to the data enable signal DE in the synchronization signal, the video frame period F5 is divided into at least a first period P51 and a second period P52, and the video frame period F6 is divided into at least a first period P61 and a second period During the period P62, the video frame period F7 is divided into at least the first period P71 and the second period P72, and the video frame period F8 is divided into at least the first period P81 and the second period P82. However, the lengths of the first periods P51, P61, P71, and P81 of the video frame periods F5 to F8 are the same as each other. The first period P51 includes the data period of the video frame period F5, and the second period P52 includes the blank period of the video frame period F5. The first period P61 includes the data period of the video frame period F6, and the second period P62 includes the blank period of the video frame period F6. The first period P71 includes the data period of the video frame period F7, and the second period P72 includes the blank period of the video frame period F7. The first period P81 includes the data period of the video frame period F8, and the second period P82 includes the blank period of the video frame period F8.

In step S430, the PWM control circuit 341 generates the PWM signal BL3. The frequency of the PWM signal BL3 in the first period is different from the frequency of the PWM signal BL3 in the second period, but the duty ratio of the PWM signal BL3 in the first period is the same as the operation of the PWM signal BL3 in the second period ratio. For example, the frequency of the PWM signal BL3 in the first period P51 is different from the frequency of the PWM signal BL3 in the second period P52, but the operation of each duty cycle of the PWM signal BL3 in the first period P51 The ratio is the same as the duty ratio of each duty cycle of the PWM signal BL3 in the second period P52.

In the embodiment shown in FIG. 5, the frequency of the PWM signal BL3 in the first period is smaller than the frequency of the PWM signal BL3 in the second period. For example, the frequency of the PWM signal BL3 in the first period P51 is smaller than the frequency of the PWM signal BL3 in the second period P52.

The backlight driving circuit 342 is coupled to the PWM control circuit 341 to receive the PWM signal BL3. In step S440, the backlight driving circuit 342 drives the backlight 350 of the display panel 330 according to the PWM signal BL3, so that the backlight 350 provides the backlight 351 to the display panel 330.

Based on the above, the generator 340 and its operating method described in this embodiment divide each video frame period into at least a first period and a second period. The lengths of these first periods during different video frames are the same as each other. If the length of the video frame period changes, the length of the second period will also change, but the length of the first period will not change. The frequency of the PWM signal BL3 in the first period is different from the frequency of the PWM signal BL3 in the second period, but the duty ratio of the PWM signal BL3 in the first period is the same as the duty ratio of the PWM signal BL3 in the second period. Therefore, by driving/controlling the backlight 350 to provide the compensated light energy (backlight 351) during the second period, the average backlight brightness in F5 to F8 during different video frames can be nearly uniform. In other words, the generator 340 and its operation method can improve the problem of backlight flicker.

FIG. 6 is a circuit block diagram illustrating the PWM control circuit 341 shown in FIG. 3 according to an embodiment of the present invention. In the embodiment shown in FIG. 6, the PWM control circuit 341 includes a period defining circuit 610, a first PWM signal generating circuit 620, a second PWM signal generating circuit 630, and a superposition circuit 640. The period definition circuit 610 is coupled to a video processing circuit (eg, scaler circuit 310) to receive a synchronization signal (eg, vertical synchronization signal Vsync) from the video processing circuit. According to the timing of the vertical synchronization signal Vsync, the period definition circuit 610 can generate the first enable signal 611 and the second enable signal 612. The first enable signal 611 may define the first period, and the second enable signal 612 may define the second period.

For example, FIG. 7 is a schematic diagram illustrating the waveform of the signal shown in FIG. 6 according to an embodiment of the invention. The vertical axis shown in FIG. 7 represents voltage, and the horizontal axis represents time. The vertical synchronization signal Vsync defines a plurality of video frame periods, such as the video frame periods F9 and F10 shown in FIG. 7. The video frame period F9 is divided into at least a first period P91 and a second period P92, and the video frame period F10 is divided into at least a first period P101 and a second period P102. The first enable signal 611 may define the first period P91 and the first period P101, and the second enable signal 612 may define the second period P92 and the second period P102. However, the lengths of these first periods P91 and P101 are the same as each other. If the length of the video frame period changes, the lengths of the second periods P92 and P102 will also change accordingly, but the lengths of the first period P91 and P101 will not change accordingly.

Please refer to Figures 6 and 7. The first PWM signal generation circuit 620 is coupled to the period definition circuit 610 to receive the first enable signal 611. The first PWM signal generating circuit 620 may generate the first PWM signal 621 according to the first enable signal 611 in the first period. The first PWM signal generation circuit 620 may determine the operation ratio of the first PWM signal 621 in the first period according to the operation ratio parameter DR. The embodiment shown in FIG. 7 will assume that the work ratio is 50%. In other embodiments, the work ratio may be adjusted according to usage requirements. The first PWM signal generating circuit 620 can also determine the phase of the first PWM signal 621 in the first period according to the delay parameter DL. The first PWM signal generating circuit 620 may be any type of PWM signal generating circuit/element. For example, the first PWM signal generating circuit 620 may be a PWM signal generating circuit well known in the art or other PWM signal generating circuits.

In the embodiment shown in FIG. 7, when the first enable signal 611 is at a low level, the first PWM signal generating circuit 620 is disabled. When the first enable signal 611 is at a high level, the first PWM signal generating circuit 620 is enabled. Therefore, the first PWM signal generating circuit 620 can generate the first PWM signal 621 during the first period P91 and P101. The first PWM signal generating circuit 620 may set the operating ratio of the first PWM signal 621 in the first period P91 and P101 to 50% according to the operating ratio parameter DR. The first PWM signal generating circuit 620 may also determine the delay time TD of the pulse of the first PWM signal 621 in the first period P91 and P101 according to the delay parameter DL, that is, determine the first period P91 and P101 The phase of the first PWM signal 621 in.

The second PWM signal generation circuit 630 is coupled to the period definition circuit 610 to receive the second enable signal 612. The second PWM signal generating circuit 630 may generate the second PWM signal 631 according to the second enable signal 612 during the second period. The second PWM signal generating circuit 630 may determine the duty ratio of the second PWM signal 631 in the second period according to the same duty ratio parameter DR. In the embodiment shown in FIG. 7, when the second enable signal 612 is at a low level, the second PWM signal generating circuit 630 is disabled. When the second enable signal 612 is at a high level, the second PWM signal generating circuit 630 is enabled. Therefore, the second PWM signal generating circuit 630 can generate the second PWM signal 631 during the second period P92 and P102. The second PWM signal generating circuit 630 may set the working ratio of the second PWM signal 631 in the second period P92 and P102 to 50% according to the working ratio parameter DR. The frequency of the second PWM signal 631 in the second periods P92 and P102 is different from the frequency of the first PWM signal 621 in the first periods P91 and P101. The second PWM signal generating circuit 630 may be any type of PWM signal generating circuit/element. For example, the second PWM signal generating circuit 630 may be a PWM signal generating circuit well known in the art or other PWM signal generating circuits.

The superposition circuit 640 is coupled to the first PWM signal generation circuit 620 to receive the first PWM signal 621. The superposition circuit 640 is coupled to the second PWM signal generation circuit 630 to receive the second PWM signal 631. The superimposing circuit 640 can superimpose the first PWM signal 621 and the second PWM signal 631 to obtain the PWM signal BL3, as shown in FIG. 7.

FIG. 8 is a circuit block diagram illustrating the PWM control circuit 341 shown in FIG. 3 according to another embodiment of the present invention. In the embodiment shown in FIG. 8, the PWM control circuit 341 includes a low-pass filter 710, a period definition circuit 610, a first PWM signal generation circuit 620, a second PWM signal generation circuit 630 and a superposition circuit 640. The period definition circuit 610, the first PWM signal generation circuit 620, the second PWM signal generation circuit 630, and the superposition circuit 640 shown in FIG. 8 can be analogized with reference to the related descriptions of FIG. 6 and FIG.

In the embodiment shown in FIG. 8, the low-pass filter 710 is coupled to the video processing circuit (for example, the scaler circuit 310) to receive the synchronization signal (for example, the vertical synchronization signal Vsync) from the video processing circuit. The low-pass filter 710 may output the smoothed signal 711 to the period definition circuit 610. 9 is a schematic diagram illustrating waveforms of the vertical synchronization signal Vsync and the smoothed signal 711 shown in FIG. 8 according to an embodiment of the present invention. As shown in FIG. 9, the low-pass filter 710 can smooth the vertical synchronization signal Vsync, and generate a smoothed signal 711. The period definition circuit 610 is coupled to the low-pass filter 710 to receive the smoothed signal 711. The period definition circuit 610 can generate the first enable signal 611 and the second enable signal 612 according to the timing of the smoothed signal 711.

The generator 340 and its operation method described in the above embodiments use a synchronous manner to control/drive the backlight 350, so the problem of motion blur can be effectively improved. The generator 340 and its operation method can be applied to backlight control of variable vertical synchronization signals or fixed vertical synchronization signals. The generator 340 and its operating method can divide each video frame period into at least a first period and a second period. The lengths of these first periods during different video frames are the same as each other. If the length of the video frame period changes, the length of the second period will also change, but the length of the first period will not change. The frequency of the PWM signal BL3 in the first period is different from the frequency of the PWM signal BL3 in the second period, but the duty ratio of the PWM signal BL3 in the first period is the same as the duty ratio of the PWM signal BL3 in the second period. Therefore, by driving/controlling the backlight 350 to provide the compensated light energy (backlight 351) during the second period, the average backlight brightness during different video frames can be close to uniform. In other words, the generator 340 and its operation method can improve the problem of backlight flicker.

10 is a schematic flowchart of an operation method of a circuit device for controlling a backlight according to another embodiment of the invention. Please refer to FIGS. 3 and 10. In step S1010, the generator 340 receives the synchronization signal (including the vertical synchronization signal Vsync, the data enable signal DE, and/or other synchronization signals). The synchronization signal may indicate the frequency of a video, where the video contains a series of image frames. The synchronization signal includes a sync period corresponding to one frame of the video.

In step S1020, the generator 340 may generate a pulse width modulation (PWM) signal BL3 synchronized with the synchronization signal to control the backlight 350. The generator 340 may divide the synchronization period into at least a first sub-period and a second sub-period. The PWM signal BL3 includes a first waveform pattern in the first sub-period of the synchronization period and a second waveform pattern in the second sub-period of the synchronization period. Each of the first waveform pattern and the second waveform pattern includes at least one active pulse. The first waveform pattern is substantially the same as the second waveform pattern.

In another embodiment, the PWM signal BL3 includes a plurality of repeating waveform patterns in the first and second sub-periods of the synchronization period, wherein each of the plurality of repeating waveform patterns includes at least One valid pulse.

In yet another embodiment, the synchronization signal includes a first synchronization period corresponding to the first frame of the video and a second synchronization period corresponding to the second frame of the video. The first synchronization period is longer than the second synchronization period in time. The pulse width modulation signal includes a first waveform pattern in a first sub-period of the first synchronization period, a second waveform pattern in a second sub-period of the first synchronization period, and a The third waveform pattern in the second synchronization period. Each of the first waveform pattern, the second waveform pattern, and the third waveform pattern includes at least one effective pulse, respectively. The first waveform pattern is substantially the same as the second waveform pattern.

In step S1030, the generator 340 drives the backlight 350 of the display panel 330 according to the PWM signal BL3, so that the backlight 350 provides the backlight 351 to the display panel 330. For the step S1030 shown in FIG. 10, reference may be made to the related description of the step S440 shown in FIG.

In this embodiment, the PWM control circuit 341 of the generator 340 can receive the synchronization signal from the scaler circuit 310 (video processing circuit). The PWM control circuit 341 checks the frequency (or period) of the synchronization signal. When the frequency of the synchronization signal is lower than the threshold frequency (or when the period of the synchronization signal is greater than the threshold period), the PWM control circuit 341 multiplies the frequency of the synchronization signal to generate a multiplied synchronization signal. The threshold frequency can be determined according to design requirements. When the frequency of the synchronization signal is higher than the threshold frequency, the PWM control circuit 341 uses the synchronization signal as the frequency-multiplied synchronization signal. The PWM control circuit 341 can generate the PWM signal BL3 according to the multiplied synchronization signal. The backlight driving circuit 342 is coupled to the PWM control circuit 341 to receive the PWM signal BL3. The backlight driving circuit 342 drives the backlight 350 of the display panel 330 according to the PWM signal BL3.

The PWM control circuit 341 can check the length of the synchronization period. When the length of the synchronization period exceeds the rated length of time, the PWM control circuit 341 divides the synchronization period into at least the first sub-period and the second sub-period. The rated time length can be set according to design requirements. The duty ratio of the PWM signal BL3 in the first sub-period is the same as the duty ratio of the PWM signal BL3 in the second sub-period. The frequency of the PWM signal BL3 in the first sub-period is the same as the frequency of the PWM signal BL3 in the second sub-period.

FIG. 11 is a schematic diagram illustrating the waveform of the PWM signal BL3 shown in FIG. 3 according to still another embodiment of the present invention. The vertical axis shown in FIG. 11 represents voltage, and the horizontal axis represents time. Please refer to FIG. 3, FIG. 10 and FIG. 11. In step S1010, the PWM control circuit 341 receives a synchronization signal (for example, a vertical synchronization signal Vsync1 or a data enable signal DE) from a video processing circuit (for example, the scaler circuit 310). The vertical synchronization signal Vsync1 shown in FIG. 12 may indicate the frequency (or period) of the video, where the video contains a series of image frames (for example, a series of image frames), such as the video frames F11, F12, F13, and F14 shown in FIG. , F15 and F16. The synchronization signal includes a sync period corresponding to one frame of the video. For example, the video frame F16 corresponds to a synchronization period Psync1.

The PWM control circuit 341 can check the length of the synchronization period (for example, the synchronization period Psync1 shown in FIG. 11 ). Here, the synchronization period Psync1 corresponding to the video frame F16 is used as an illustrative example. The synchronization period corresponding to the remaining video frames (for example, the video frames F11, F12, F13, F14, and F15 shown in FIG. 11) can be inferred by referring to the relevant description of the synchronization period Psync1, and thus will not be repeated. If the synchronization period Psync1 is too long (that is, the frequency of the PWM signal BL3 may be too low), the human eye may perceive the flicker of the backlight 350. Therefore, when the time length of the synchronization period Psync1 exceeds the rated time length, the PWM control circuit 341 may divide the synchronization period Psync1 into at least a first sub-period SP11 and a second sub-period SP12.

In step S1020, the PWM control circuit 341 may generate a PWM signal BL3 synchronized with the synchronization signal (for example, the vertical synchronization signal Vsync1 or the data enable signal DE) to control the backlight 350. Among them, the duty ratio of the PWM signal BL3 in the first sub-period SP11 is the same as the duty ratio of the PWM signal BL3 in the second sub-period SP12, and the frequency of the PWM signal BL3 in the first sub-period SP11 is the same as that in the second sub-period SP11 The frequency of the PWM signal BL3 in the period SP12. In step S1030, the backlight driving circuit 342 drives the backlight 350 of the display panel 330 according to the PWM signal BL3, so that the backlight 350 provides the backlight 351 to the display panel 330.

When the time length of Psync1 during synchronization exceeds the rated time length, the PWM control circuit 341 can apply a frequency doubling operation to the PWM signal BL3 in Psync1 during synchronization, so that it is difficult for human eyes to perceive the flicker of the backlight 350. Therefore, the generator 340 and its operation method can improve the problem of backlight flicker.

FIG. 12 is a circuit block diagram illustrating the PWM control circuit 341 shown in FIG. 3 according to another embodiment of the present invention. In the embodiment shown in FIG. 12, the PWM control circuit 341 includes a frequency checking circuit 1210 and a PWM signal generating circuit 1220. The frequency checking circuit 1210 is coupled to a video processing circuit (eg, scaler circuit 310) to receive a synchronization signal (eg, vertical synchronization signal Vsync1) from the video processing circuit. The frequency checking circuit 1210 checks the frequency of the vertical synchronization signal Vsync1.

Please refer to FIG. 11 and FIG. 12. When the frequency of the vertical synchronization signal Vsync1 is higher than the threshold frequency (or when the period of the vertical synchronization signal Vsync1 is less than the threshold period), the frequency checking circuit 1210 uses the vertical synchronization signal Vsync1 as the multiplied-frequency synchronization signal Vsync2. For example, in the video frame F11, the frequency of the multiplied synchronization signal Vsync2 is the same as the frequency of the vertical synchronization signal Vsync1. The threshold frequency can be determined according to design requirements. When the frequency of the vertical synchronizing signal Vsync1 is lower than the threshold frequency (or when the period of the vertical synchronizing signal Vsync1 is greater than the threshold period), the frequency checking circuit 1210 multiplies the frequency of the vertical synchronizing signal Vsync1 to generate frequency-doubled synchronization Signal Vsync2. Referring to the embodiment shown in FIG. 11, in the synchronization period Psync1, the frequency of the multiplied synchronization signal Vsync2 is twice the frequency of the vertical synchronization signal Vsync1. In any case, the magnification of the frequency doubling operation can be determined according to design requirements.

The PWM signal generating circuit 1220 is coupled to the frequency checking circuit 1210 to receive the multiplied synchronization signal. The PWM signal generating circuit 1220 generates the PWM signal BL3 to the backlight driving circuit 342 according to the frequency-multiplied synchronization signal Vsync2. Wherein, the PWM signal generating circuit 1220 determines the working ratio of the PWM signal according to the working ratio parameter DR. This work ratio parameter DR can be adjusted according to actual use requirements. In addition, the PWM signal generating circuit 1220 can also determine the delay time TD according to the delay parameter DL, that is, determine the phase of the PWM signal BL3. The PWM signal generating circuit 1220 may be any type of PWM signal generating circuit/component. For example, the PWM signal generating circuit 1220 may be a PWM signal generating circuit or other PWM signal generating circuits well known in the art.

FIG. 13 is a schematic diagram illustrating the waveform of the PWM signal BL3 shown in FIG. 3 according to yet another embodiment of the present invention. The vertical axis shown in FIG. 13 represents voltage, and the horizontal axis represents time. The embodiment shown in FIG. 13 assumes that the PWM control circuit 341 receives the vertical synchronization signal Vsync1 (video synchronization information) from the video processing circuit (for example, the scaler circuit 310). The vertical synchronization signal Vsync1, frequency-multiplied synchronization signal Vsync2, delay time TD, video frame F11, video frame F12, video frame F13, video frame F14, video frame F15, video frame F16, synchronization period Psync1, first For the sub-period SP11 and the second sub-period SP12, reference may be made to the related description in FIG. 11, so no further description is required.

The PWM control circuit 341 divides the first sub-period SP11 into at least a third sub-period SP111 and a fourth sub-period SP112 according to the frequency-doubled synchronization signal Vsync2. By analogy, the second sub-period SP12 is divided into at least sub-period SP121 and sub-period SP122. The remaining video frames F11, F12, F13, F14, and F15 shown in FIG. 11 are also divided into multiple sub-periods. These sub-periods of the video frames F11, F12, F13, F14, and F15 shown in FIG. 11 can refer to the video frame period F5, the first period P51, the second period P52, the video frame period F6, the first period P61 shown in FIG. 5, The related descriptions of the second period P62, the video frame period F7, the first period P71, the second period P72, the video frame period F8, the first period P81 and the second period P82 can be deduced by analogy.

FIG. 14 is a circuit block diagram illustrating the PWM control circuit 341 shown in FIG. 3 according to yet another embodiment of the present invention. Please refer to FIGS. 13 and 14. In the embodiment shown in FIG. 14, the PWM control circuit 341 includes a frequency check circuit 1210, a period definition circuit 610, a first PWM signal generation circuit 620, a second PWM signal generation circuit 630, and a superposition circuit 640. The frequency checking circuit 1210 is coupled to a video processing circuit (eg, scaler circuit 310) to receive a synchronization signal (eg, vertical synchronization signal Vsync1) from the video processing circuit. The frequency checking circuit 1210 checks the frequency of the vertical synchronization signal Vsync1, and outputs the frequency-doubled synchronization signal Vsync2. The frequency check circuit 1210 shown in FIG. 14 and the frequency-doubled synchronization signal Vsync2 can be analogized with reference to the relevant descriptions of the frequency check circuit 1210 shown in FIG. 12 and the frequency-doubled synchronization signal Vsync2, so they will not be repeated here.

The period definition circuit 610 is coupled to the frequency checking circuit 1210 to receive the frequency-doubled synchronization signal Vsync2. According to the timing of the frequency-doubled synchronization signal Vsync2, the period definition circuit 610 can generate a first enable signal 611 and a second enable signal 612, wherein the first enable signal 611 defines the third sub-period SP111 And the sub-period SP121, and the second enable signal 612 defines the fourth sub-period SP112 and the sub-period SP122. The period definition circuit 610, the first enable signal 611, and the second enable signal 612 shown in FIG. 14 can refer to the period definition circuit 610, the first enable signal 611, and the second enable signal 612 shown in FIGS. 6 and 7. Relevant descriptions can be deduced by analogy.

The first PWM signal generation circuit 620 is coupled to the period definition circuit 610 to receive the first enable signal 611. The first PWM signal generating circuit 620 may generate the first PWM signal 621 according to the first enable signal 611 in the third sub-period SP111 and the sub-period SP121, and determine the first PWM signal 621 according to the operating ratio parameter DR The working ratio of the first PWM signal 621 in the three sub-periods SP111 and the sub-periods SP121. The first PWM signal generating circuit 620 can also determine the delay time TD of the pulse of the first PWM signal 621 in the third sub-period SP111 according to the delay parameter DL, that is, determine the phase of the first PWM signal 621. The first PWM signal generating circuit 620 and the first PWM signal 621 shown in FIG. 14 can be analogized with reference to the relevant descriptions of the first PWM signal generating circuit 620 and the first PWM signal 621 shown in FIGS.

The second PWM signal generation circuit 630 is coupled to the period definition circuit 610 to receive the second enable signal 612. The second PWM signal generating circuit 630 generates the second PWM signal 631 according to the second enable signal 612 in the fourth sub-period SP112 and the sub-period SP122, and determines the fourth sub-period SP112 according to the duty ratio parameter DR The duty ratio of the second PWM signal 631 in the sub-period SP122. The frequency of the second PWM signal 631 is different from the frequency of the first PWM signal 621. The second PWM signal generating circuit 630 and the second PWM signal 631 shown in FIG. 14 can be analogized with reference to the relevant descriptions of the second PWM signal generating circuit 630 and the second PWM signal 631 shown in FIGS. 6 and 7, and thus will not be repeated.

The superposition circuit 640 is coupled to the first PWM signal generation circuit 620 to receive the first PWM signal 621. The superposition circuit 640 is coupled to the second PWM signal generating circuit 630 to receive the second PWM signal 631. The superposition circuit 640 superposes the first PWM signal 621 and the second PWM signal 631 to obtain the PWM signal BL3. The superimposing circuit 640 and the PWM signal BL3 shown in FIG. 14 can be inferred by referring to the relevant description of the superimposing circuit 640 and the PWM signal BL3 shown in FIGS. 6 and 7, and thus will not be repeated.

FIG. 15 is a schematic diagram illustrating the waveform of the PWM signal BL3 shown in FIG. 3 according to another embodiment of the present invention. The vertical axis shown in FIG. 15 represents voltage, and the horizontal axis represents time. The embodiment shown in FIG. 15 assumes that the PWM control circuit 341 receives the vertical synchronization signal Vsync1 (video synchronization information) from the video processing circuit (for example, the scaler circuit 310). The vertical synchronization signal Vsync1, frequency-multiplied synchronization signal Vsync2, video frame F11, video frame F12, video frame F13, video frame F14, video frame F15, video frame F16, synchronization period Psync1, the first sub-period SP11 and For the second sub-period SP12, reference may be made to the relevant descriptions in FIG. 11 and/or FIG. 13, so details are not described here.

In the embodiment shown in FIG. 15, the PWM signal BL3 has one pulse each in the first period and the last period in the sub-period, and the PWM signal BL3 has no pulse in the middle period in the sub-period. For example, the PWM signal BL3 has one pulse each in the first period and the last period in the third sub-period SP111, and the PWM signal BL3 has no pulse in the middle period in the third sub-period SP111, as shown in FIG. 15 Show. For other sub-periods (for example, sub-period SP121), reference may be made to the relevant description of the third sub-period SP111, so no further description is required.

According to different design requirements, the above generator 340, PWM control circuit 341, backlight drive circuit 342, frequency check circuit 1210, PWM signal generation circuit 1220, period definition circuit 610, first PWM signal generation circuit 620, second PWM signal generation The circuit 630 and/or the blocks of the superposition circuit 640 can be implemented in hardware, firmware, software (program), or a combination of multiple of the foregoing.

In terms of hardware, the generator 340, PWM control circuit 341, backlight drive circuit 342, frequency check circuit 1210, PWM signal generation circuit 1220, period definition circuit 610, first PWM signal generation circuit 620, second PWM signal The blocks of the generating circuit 630 and/or the superimposing circuit 640 can be implemented as a logic circuit on an integrated circuit. The above generator 340, PWM control circuit 341, backlight driving circuit 342, frequency checking circuit 1210, PWM signal generating circuit 1220, period definition circuit 610, first PWM signal generating circuit 620, second PWM signal generating circuit 630 and/or The related functions of the superposition circuit 640 can be implemented as hardware using hardware description languages (for example, Verilog HDL or VHDL) or other suitable programming languages. For example, the above generator 340, PWM control circuit 341, backlight drive circuit 342, frequency check circuit 1210, PWM signal generation circuit 1220, period definition circuit 610, first PWM signal generation circuit 620, second PWM signal generation circuit 630 And/or related functions of the superposition circuit 640 can be implemented in one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASIC), digital signal processors ( digital signal processor (DSP), Field Programmable Gate Array (FPGA) and/or various logic blocks, modules and circuits in other processing units.

In the form of software and/or firmware, the above generator 340, PWM control circuit 341, backlight drive circuit 342, frequency check circuit 1210, PWM signal generation circuit 1220, period definition circuit 610, first PWM signal generation circuit 620 2. The related functions of the second PWM signal generating circuit 630 and/or the superposition circuit 640 can be implemented as programming codes. For example, the above-mentioned generator 340, PWM control circuit 341, backlight driving circuit 342, frequency check circuit 1210, PWM signal generation can be realized by using general programming languages (such as C, C++ or combined languages) or other suitable programming languages The circuit 1220, the period definition circuit 610, the first PWM signal generation circuit 620, the second PWM signal generation circuit 630, and/or the superposition circuit 640. The programming code may be recorded/stored in a recording medium, for example, the recording medium includes a read only memory (Read Only Memory, ROM), a storage device, and/or a random access memory (Random Access Memory, RAM) . A computer, a central processing unit (CPU), a controller, a microcontroller, or a microprocessor can read and execute the programming code from the recording medium to achieve related functions. As the recording medium, "non-transitory computer readable medium" can be used. For example, a tape, disk, card, semiconductor memory, or Programming logic circuits, etc. Moreover, the program can also be provided to the computer (or CPU) via any transmission medium (communication network, broadcast wave, etc.). The communication network is, for example, the Internet, wired communication, wireless communication, or other communication media.

In summary, the circuit device for controlling the backlight and the operation method thereof according to the embodiments of the present invention can divide a synchronization period Psync1 into at least a first sub-period SP11 and a second sub-period SP12. The first waveform pattern of the PWM signal BL3 in the first sub-period SP11 and the second waveform pattern of the PWM signal BL3 in the second sub-period SP12 each include at least one effective pulse. The first waveform pattern in the first sub-period SP11 is substantially the same as the second waveform pattern in the second sub-period SP12. If the length of the Psync1 during the synchronization period is too long, the first waveform pattern and the second waveform pattern can bring a frequency doubling effect, making it difficult for human eyes to perceive the flicker of the backlight 350. Therefore, the circuit device and its operation method can improve the problem of backlight flicker.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

300: display device 310: Scaler circuit 320: panel drive circuit 330: Display panel 340: Generator 341: Pulse width modulation control circuit 342: backlight drive circuit 350: backlight 351: Backlight 610: Period definition circuit 611: First enable signal 612: Second enable signal 620: First pulse width modulation signal generating circuit 621: first enable signal 630: Second pulse width modulation signal generating circuit 631: Second enable signal 640: Stacked circuit 710: Low-pass filter 711: Smoothed signal 1210: Frequency check circuit 1220: Pulse width modulation signal generating circuit BL1, BL2: backlight control signal BL3: Pulse width modulation control signal DE: data enable signal DL: Delay parameter DR: work ratio parameter F1, F2, F4, F4, F5, F6, F7, F8, F9, F10: during video frames F11, F12, F13, F14, F15, F16: video frames P51, P61, P71, P81, P91, P101: the first period P52, P62, P72, P82, P92, P102: the second period PW2: pulse width Psync1: During synchronization S410～S440, S1010～S1030: Steps SP11: First sub-period SP12: Second sub-period TD: delay time Vsync1: vertical sync signal Vsync2: Frequency-multiplied synchronization signal SP111: The third sub-period SP112: Fourth sub-period SP121, SP122: Sub-period

FIG. 1 is a schematic diagram illustrating the waveform of a backlight control signal when the conventional backlight device uses an asynchronous method to control/drive the backlight source. FIG. 2A is a schematic diagram illustrating the waveform of the backlight control signal when the conventional backlight device uses a synchronous method to control/drive the backlight source. FIG. 2B is a schematic diagram illustrating the waveform of the backlight control signal when another conventional backlight device uses a synchronous method to control/drive the backlight source. 3 is a schematic diagram of a circuit block of a display device according to an embodiment of the invention. FIG. 4 is a schematic flowchart of an operation method of a circuit device for controlling a backlight according to an embodiment of the invention. FIG. 5 is a schematic diagram illustrating the waveform of the pulse width modulation signal shown in FIG. 3 according to an embodiment of the invention. FIG. 6 is a circuit block diagram illustrating the pulse width modulation control circuit shown in FIG. 3 according to an embodiment of the invention. 7 is a schematic diagram illustrating the waveform of the signal shown in FIG. 6 according to an embodiment of the invention. FIG. 8 is a circuit block diagram illustrating the pulse width modulation control circuit shown in FIG. 3 according to another embodiment of the present invention. 9 is a schematic diagram illustrating the waveforms of the vertical synchronization signal and the smoothed signal shown in FIG. 8 according to an embodiment of the invention. 10 is a schematic flowchart of an operation method of a circuit device for controlling a backlight according to another embodiment of the invention. FIG. 11 is a schematic diagram illustrating the waveform of the PWM signal shown in FIG. 3 according to still another embodiment of the present invention. FIG. 12 is a circuit block diagram illustrating the PWM control circuit shown in FIG. 3 according to still another embodiment of the present invention. FIG. 13 is a schematic diagram illustrating the PWM signal shown in FIG. 3 according to yet another embodiment of the present invention. 14 is a schematic block diagram of a PWM control circuit shown in FIG. 3 according to yet another embodiment of the present invention. 15 is a schematic diagram illustrating the waveform of the PWM signal shown in FIG. 3 according to another embodiment of the present invention.

BL3: Pulse width modulation control signal

DE: data enable signal

F11, F12, F13, F14, F15, F16: video frames

Psync1: During synchronization

SP11: First sub-period

SP12: Second sub-period

TD: delay time

Vsync1: vertical sync signal

Vsync2: Frequency-multiplied synchronization signal

Claims (23)

A circuit device for controlling a backlight source includes: a generator for receiving a synchronization signal and generating a pulse width modulation signal synchronized with the synchronization signal to control the backlight source, the synchronization signal indicating a video signal Frequency, the video includes a series of image frames, where the synchronization signal includes a synchronization period corresponding to a frame of the video, and the pulse width modulation signal includes a first of a first sub-period of the synchronization period A waveform pattern and a second waveform pattern in a second sub-period of the synchronization period, each of the first waveform pattern and the second waveform pattern includes at least one effective pulse, and the first waveform pattern and The second waveform pattern is basically the same. The circuit device as described in item 1 of the patent application scope, wherein the generator includes: a pulse width modulation control circuit for receiving the synchronization signal from a video processing circuit, wherein the pulse width modulation control circuit checks the synchronization The frequency of the signal. When the frequency of the synchronization signal is lower than a threshold frequency, the pulse width modulation control circuit multiplies the frequency of the synchronization signal to generate a multiplied synchronization signal. When the frequency of the synchronization signal is higher than At the threshold frequency, the pulse width modulation control circuit uses the synchronization signal as the multiplied frequency synchronization signal, and the pulse width modulation control circuit generates the pulse width modulation signal according to the multiplied frequency synchronization signal; and a backlight The driving circuit is coupled to the pulse width modulation control circuit to receive the pulse width modulation signal, and is used to drive the backlight of a display panel according to the pulse width modulation signal. The circuit device according to item 2 of the patent application scope, wherein the video processing circuit includes a scaler circuit, and the synchronization signal includes a vertical synchronization signal. The circuit device according to item 2 of the patent application scope, wherein the pulse width modulation control circuit checks the length of the synchronization period, and when the length of the synchronization period exceeds a rated length of time, the pulse width modulation control circuit The synchronization period is divided into at least the first sub-period and the second sub-period, the duty ratio of the pulse width modulation signal in the first sub-period is the same as the pulse width modulation in the second sub-period Signal-to-work ratio. The circuit device according to item 4 of the patent application scope, wherein the frequency of the pulse width modulation signal in the first sub-period is the same as the frequency of the pulse width modulation signal in the second sub-period. The circuit device as described in item 2 of the patent application scope, wherein the pulse width modulation control circuit includes: a frequency checking circuit for receiving the synchronization signal from the video processing circuit, wherein the frequency checking circuit checks the synchronization signal Frequency, when the frequency of the synchronization signal is lower than the threshold frequency, the frequency checking circuit multiplies the frequency of the synchronization signal to generate the multiplied synchronization signal, and when the frequency of the synchronization signal is higher than the threshold frequency At this time, the frequency checking circuit uses the synchronization signal as the multiplied frequency synchronization signal; and a pulse width modulation signal generating circuit coupled to the frequency checking circuit to receive the multiplied frequency synchronization signal for use in accordance with the multiplied frequency Frequency synchronization signal to generate the pulse width modulation signal to the backlight driving circuit, and determine a working ratio of the pulse width modulation signal according to a working ratio parameter. The circuit device according to item 2 of the patent application scope, wherein the pulse width modulation control circuit divides the first sub-period into at least a third sub-period and a fourth sub-period according to the frequency-doubled synchronization signal. The circuit device as described in item 7 of the patent application range, wherein the pulse width modulation signal has pulses in each of a first period and a tail period of the third sub-period, and the pulse width modulation signal is in the third There is no pulse in one of the sub-periods. The circuit device as described in item 7 of the patent application range, wherein the pulse width modulation control circuit includes: a frequency checking circuit for receiving the synchronization signal from the video processing circuit, wherein the frequency checking circuit checks the synchronization signal The frequency, when the frequency of the synchronization signal is lower than the threshold frequency, the frequency checking circuit multiplies the frequency of the synchronization signal to generate the multiplied synchronization signal, and when the frequency of the synchronization signal is higher than At the threshold frequency, the frequency checking circuit uses the synchronization signal as the frequency-multiplied synchronization signal; a period defining circuit coupled to the frequency checking circuit to receive the frequency-doubled synchronization signal, and according to the frequency-doubled synchronization signal To generate a first enable signal and a second enable signal, wherein the first enable signal defines the third sub-period, and the second enable signal defines the fourth sub-period; a first pulse A wide modulation signal generating circuit, coupled to the period definition circuit to receive the first enable signal, for generating a first pulse width modulation signal according to the first enable signal in the third sub-period, And a duty ratio of the first pulse width modulation signal in the third sub-period is determined according to a duty ratio parameter; a second pulse width modulation signal generation circuit is coupled to the period definition circuit to receive the The second enable signal is used to generate a second pulse width modulation signal in the fourth sub-period according to the second enable signal and to determine the second pulse in the fourth sub-period according to the duty ratio parameter An operating ratio of the second pulse width modulation signal, wherein the frequency of the second pulse width modulation signal is different from the frequency of the first pulse width modulation signal; and a superposition circuit, coupled to the first pulse width The modulation signal generation circuit receives the first pulse width modulation signal, and is coupled to the second pulse width modulation signal generation circuit to receive the second pulse width modulation signal, wherein the overlapping circuit overlaps the first The pulse width modulation signal and the second pulse width modulation signal obtain the pulse width modulation signal. The circuit device according to item 9 of the patent application scope, wherein the first pulse width modulation signal generating circuit further determines the phase of the first pulse width modulation signal in the third sub-period according to a delay parameter. An operation method of a circuit device for controlling a backlight source includes: a synchronization signal is received by a generator, wherein the synchronization signal indicates a frequency of a video, the video includes a series of image frames; and the generator generates and A pulse width modulation signal synchronized by the synchronization signal to control the backlight, wherein the synchronization signal includes a synchronization period corresponding to a frame of the video, and the pulse width modulation signal includes a first period during the synchronization period A first waveform pattern in the sub-period and a second waveform pattern in a second sub-period in the synchronization period, each of the first waveform pattern and the second waveform pattern includes at least one effective pulse, And the first waveform pattern is basically the same as the second waveform pattern. The operation method as described in item 11 of the patent application scope, wherein the step of generating the PWM signal includes: checking the frequency of the synchronization signal; when the frequency of the synchronization signal is lower than a threshold frequency, the synchronization signal The frequency is multiplied to generate a multiplied synchronization signal; when the frequency of the synchronization signal is higher than the threshold frequency, the synchronization signal is used as the multiplied synchronization signal; the pulse width is generated according to the multiplied synchronization signal A modulation signal; and a backlight driving circuit drives the backlight of a display panel according to the pulse width modulation signal. The operation method as described in item 12 of the patent application scope, wherein the synchronization signal includes a vertical synchronization signal. The operation method as described in item 12 of the patent application scope, wherein the step of checking the frequency of the synchronization signal includes: checking a length of time during the synchronization period; when the length of the synchronization period exceeds a rated length of time, the The synchronization period is divided into at least the first sub-period and the second sub-period, wherein the duty ratio of the pulse width modulation signal in the first sub-period is the same as that of the pulse width modulation signal in the second sub-period Work ratio. The operation method as described in item 14 of the patent application range, wherein the frequency of the pulse width modulation signal in the first sub-period is the same as the frequency of the pulse width modulation signal in the second sub-period. The operation method as described in item 12 of the patent application scope, wherein the step of generating the pulse width modulated signal includes: generating a pulse width modulated signal to the pulse width modulated signal by a pulse width modulated signal generating circuit according to the multiplied synchronization signal A backlight driving circuit; and the pulse width modulation signal generating circuit determines a duty ratio of the pulse width modulation signal according to a duty ratio parameter. The operation method as described in item 12 of the patent application scope further includes: dividing the first sub-period into at least a third sub-period and a fourth sub-period according to the frequency-doubled synchronization signal. The operation method as described in item 17 of the patent application range, wherein the pulse width modulation signal has pulses in each of a first period and a tail period of the third sub-period, and the pulse width modulation signal is in the third There is no pulse in one of the sub-periods. The operation method as described in Item 17 of the patent application scope, wherein the step of generating the pulse width modulated signal includes: generating a first enabling signal and a first enabling signal according to the timing of the multiplied synchronization signal by a period definition circuit Two enable signals, wherein the first enable signal defines the third sub-period, and the second enable signal defines the fourth sub-period; a first pulse width modulation signal generating circuit according to the first enable Signal to generate a first pulse width modulation signal in the third sub-period, and to determine a working ratio of the first pulse width modulation signal in the third sub-period according to a duty ratio parameter; The second pulse width modulation signal generating circuit generates a second pulse width modulation signal in the fourth sub-period according to the second enable signal, and determines the value in the fourth sub-period according to the duty ratio parameter An operating ratio of the second pulse width modulation signal, wherein the frequency of the second pulse width modulation signal is different from the frequency of the first pulse width modulation signal; and the first pulse width is superimposed by a superimposing circuit The modulation signal and the second pulse width modulation signal to obtain the pulse width modulation signal. The operation method as described in Item 19 of the patent application range, wherein the first pulse width modulation signal generating circuit further determines the phase of the first pulse width modulation signal in the third sub-period according to a delay parameter. A circuit device for controlling a backlight source includes: a generator for receiving a synchronization signal and generating a pulse width modulation signal synchronized with the synchronization signal to control the backlight source, the synchronization signal indicating a video signal Frequency, the video includes a series of image frames, where the synchronization signal includes a synchronization period corresponding to a frame of the video, and the pulse width modulation signal includes a first sub-period and a second sub-period during the synchronization period The plurality of repeating waveform patterns in the period, and each of the plurality of repeating waveform patterns include at least one effective pulse. A circuit device for controlling a backlight source includes: a generator for receiving a synchronization signal and generating a pulse width modulation signal synchronized with the synchronization signal to control the backlight source, the synchronization signal indicating a video signal Frequency, the video includes a series of image frames, wherein the synchronization signal includes a synchronization period corresponding to a frame of the video, the generator divides the synchronization period into at least a first sub-period and a second sub-period, the pulse The wide modulation signal includes a first waveform pattern in the first sub-period of the synchronization period and a second waveform pattern in the second sub-period of the synchronization period, and the first waveform pattern and the first Each of the two waveform patterns includes at least one effective pulse. A circuit device for controlling a backlight source includes: a generator for receiving a synchronization signal and generating a pulse width modulation signal synchronized with the synchronization signal to control the backlight source, the synchronization signal indicating a video signal Frequency, the video contains a series of image frames, where the synchronization signal includes a first synchronization period corresponding to a first frame of the video and a second synchronization period corresponding to a second frame of the video, at time The first synchronization period is longer than the second synchronization period, the pulse width modulation signal includes a first waveform pattern in a first sub-period of the first synchronization period, and a second waveform pattern in the first synchronization period A second waveform pattern in the sub-period and a third waveform pattern in the second synchronization period, each of the first waveform pattern, the second waveform pattern, and the third waveform pattern includes at least one effective The pulse and the first waveform pattern are substantially the same as the second waveform pattern.

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