CN113035136B - Signal processing method for maintaining relative relationship of signals and electronic device thereof - Google Patents
Signal processing method for maintaining relative relationship of signals and electronic device thereof Download PDFInfo
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- 238000003672 processing method Methods 0.000 title claims abstract description 12
- 230000001360 synchronised effect Effects 0.000 claims abstract description 6
- 230000000737 periodic effect Effects 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 7
- 238000013459 approach Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 12
- 230000010363 phase shift Effects 0.000 description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 5
- 230000010355 oscillation Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3406—Control of illumination source
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
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Abstract
The disclosure provides a signal processing method for maintaining relative relationship of signals and an electronic device thereof. The signal processing method includes detecting that a current input period of a vertical synchronization signal changes from a previous input period. Judging whether the frequency difference between the pulse width modulation signal and the vertical synchronous signal is in a receiving interval, and when the frequency difference is not in the receiving interval, performing a frequency adjusting stage to adjust the period of the pulse width modulation signal to be close to the current input period. Selectively performing a phase adjustment stage to adjust the phase of the PWM signal to the phase of the vertical synchronization signal. The relative phase relationship between the PWM signal and the vertical synchronization signal is maintained.
Description
Technical Field
The present disclosure relates to signal synchronization technologies, and more particularly, to a signal processing method for maintaining a relative relationship between signals and an electronic device thereof.
Background
The Pulse Width Modulation (PWM) signal is a signal for controlling the backlight switch, and when the PWM signal is at a high level, a small deviation may occur in the display of the panel due to the current pumping of the power supply, and the deviation is not easily perceived by human eyes. However, when the boundary of the deviation shifts with the phase difference of the pwm signal, the water wave phenomenon of rolling up or down may be perceived by human eyes.
On the other hand, in the digital tv, the pwm signal generated by the pwm control circuit is transmitted to different panels, and the different panels have corresponding panel characteristics, which limits the pwm signal adjustment. Moreover, the brightness degree of the digital television is to adjust the ratio of the bright band and the dark band by using the pulse width modulation signal, so that human eyes can feel the brightness change of the picture due to the persistence of vision, because the ratio of the bright band of the pulse width modulation signal changes along with the period of the pulse width modulation signal, the time of the bright band is correspondingly increased when the period is increased, and if a large period change occurs, human eyes can feel that the picture is instantly brightened, and the picture is considered to flicker (flicker).
Accordingly, the output image of the digital tv has a corresponding backlight adjustment, the phase and frequency tracking speed is very important during the adjustment process, and when the pwm control circuit cannot know the period of the vertical synchronization signal in advance, a transient frequency difference and phase change may occur, which may cause a ripple phenomenon or flicker on the panel.
Disclosure of Invention
In view of the above, the present disclosure provides a signal processing method for maintaining a relative relationship between signals, comprising: detecting that a current input period and a previous input period of a vertical synchronization signal are changed; judging whether a frequency difference value between a pulse width modulation signal and a vertical synchronous signal is in a receiving interval, and when the frequency difference value is not in the receiving interval, performing a frequency adjustment stage to adjust the period of the pulse width modulation signal to be close to the current input period; judging whether the phase of the pulse width modulation signal is to be adjusted, and when the phase of the pulse width modulation signal is to be adjusted, performing a phase adjustment stage to adjust the phase of the pulse width modulation signal to the phase of the vertical synchronous signal; and maintaining the relative phase relationship between the PWM signal and the vertical synchronization signal.
The present disclosure further provides an electronic device for maintaining a relative relationship between signals, which includes a display control circuit, a pwm control circuit, and a processor electrically connected to and controlling the display control circuit and the pwm control circuit. The display control circuit is electrically connected with a display device and used for outputting a vertical synchronizing signal. The pulse width modulation control circuit is electrically connected with the display control circuit and the display device respectively, receives the vertical synchronizing signal, judges whether a frequency difference value between a pulse width modulation signal and the vertical synchronizing signal is in a receiving interval when the current input period and the previous input period of the vertical synchronizing signal change, and performs a frequency adjusting stage to adjust the period of the pulse width modulation signal to be close to the current input period when the frequency difference value is not in the receiving interval; the pulse width modulation control circuit judges whether the phase of the pulse width modulation signal is to be adjusted or not, and when the phase of the pulse width modulation signal is to be adjusted, the pulse width modulation control circuit carries out a phase adjustment stage to adjust the phase of the pulse width modulation signal to the phase of the vertical synchronous signal; the pulse width modulation control circuit maintains the relative phase relationship between the pulse width modulation signal and the vertical synchronizing signal.
According to some embodiments, the change is that the difference between the current input period and the previous input period exceeds a predetermined threshold.
According to some embodiments, in the frequency adjustment phase, the period of the pwm signal is adjusted in stages to be close to the current input period, and each stage is adjusted by a step value.
According to some embodiments, the amplitude of the periodic variation of the pwm signal is inversely proportional to the time required for the phase of the pwm signal to adjust to the phase of the vertical synchronization signal.
According to some embodiments, when maintaining the relative phase relationship between the pwm signal and the vertical synchronization signal, the relative phase relationship between the pwm signal and the vertical synchronization signal may be maintained to be equal to the phase relationship between the vertical synchronization signal or the relative phase relationship between the pwm signal and the vertical synchronization signal may be maintained to be different by a target phase difference.
In summary, under the premise of not generating the moire phenomenon and the panel flicker, the present disclosure adjusts the frequency of the pwm signal to be the same as the vertical synchronization signal by the frequency adjustment and the phase adjustment according to the characteristics of different display devices, and stably maintains a certain phase relationship, so as to effectively maintain the optimal relative relationship between the pwm signal and the vertical synchronization signal.
Drawings
Fig. 1 is a block schematic diagram of an electronic device according to an embodiment of the present disclosure.
Fig. 2 is a schematic flow chart diagram of a signal processing method according to an embodiment of the present disclosure.
Fig. 3a is a schematic diagram of a relationship between a vertical synchronization signal and a pwm signal before and after a frequency change according to an embodiment of the present disclosure.
Fig. 3b is a schematic diagram of a relationship between a vertical synchronization signal and a pwm signal before and after a frequency change according to another embodiment of the present disclosure.
Fig. 4 is a graph of the amplitude of the periodic variation of the pwm signal versus the time to adjust the phase according to an embodiment of the present disclosure.
Fig. 5 is a graph of the relationship between the period variation of the vertical synchronization signal and the pwm signal and the corresponding phase shift according to an embodiment of the present disclosure.
Fig. 6 is a graph of the relationship between the period variation of the vertical synchronization signal and the pwm signal and the corresponding phase shift according to another embodiment of the present disclosure.
Description of the symbols
10 electronic device
12 processor
14 display control circuit
16 pulse width modulation control circuit
20 display device
S10-S20
PWM pulse width modulation signal
Vsync vertical synchronization signal
Area on left side of A
Area on the right side of B
C middle region
Range of I1-I5
Detailed Description
The signal processing method for maintaining the relative relationship of the signals is suitable for an electronic device connected with a display device, and utilizes a pulse width modulation control circuit to process pulse width modulation signals. The method and the device can ensure that the phase positions of the pulse width modulation signal and the vertical synchronous signal do not change slowly all the time so as to reduce the risk of water ripple and ensure that the periodic variation amplitude of the pulse width modulation signal cannot be too large so as to avoid panel flicker.
Fig. 1 is a block diagram of an electronic device according to an embodiment of the disclosure, and referring to fig. 1, an electronic device 10 includes a processor 12, a display control circuit 14, and a pwm control circuit 16. The processor 12 is electrically connected to the display control circuit 14 and the pwm control circuit 16 to control the operations of the display control circuit 14 and the pwm control circuit 16, respectively, and the display control circuit 14 and the pwm control circuit 16 are electrically connected to a display device 20, respectively, and the display control circuit 14 outputs the vertical synchronization signal Vsync to the pwm control circuit 16. In detail, the processor 12 generates a Duty Cycle (Duty Cycle) signal for controlling brightness to the PWM control circuit 16, so as to drive the PWM control circuit 16 to generate a Pulse Width Modulation (PWM) signal PWM to the display device 20, so that the display device 20 controls the on/off timing of the backlight module of the display device 20 according to the PWM signal PWM, and the PWM control circuit 16 also receives the vertical synchronization signal Vsync output from the display control circuit 14. In order to deal with the frame frequency variation of the received vertical synchronization signal Vsync, the PWM control circuit 16 adjusts the PWM signal PWM according to the period and phase of the vertical synchronization signal Vsync outputted from the display control circuit 14.
In one embodiment, the electronic device 10 is a system on a chip (SoC), such that the processor 12, the display control circuit 14 and the pwm control circuit 16 are all built in the SoC.
Fig. 2 is a flowchart of a signal processing method according to an embodiment of the disclosure, please refer to fig. 1 and fig. 2, in which the pwm control circuit 16 continuously determines whether the period of the vertical synchronization signal Vsync from the display control circuit 14 changes, as shown in step S10, when the pwm control circuit 16 detects that the current input period and the previous input period of the vertical synchronization signal Vsync change, the adjustment mechanism is activated, and steps S12 to S20 are performed in sequence. In one embodiment, the change detected by the pwm control circuit 16 is that a difference between a current input period and a previous input period of the vertical synchronization signal Vsync exceeds a predetermined threshold.
In step S12, the PWM control circuit 16 determines whether the frequency difference between the PWM signal PWM and the vertical synchronization signal Vsync is within a receiving interval, which is a period before and after the frequency of the vertical synchronization signal Vsync. When the frequency difference is within the acceptance interval, it indicates that the frequency of the PWM signal PWM is close to or the same as the frequency of the vertical synchronization signal Vsync, and the next step is performed without any frequency adjustment (step S16). When the PWM control circuit 16 determines that the frequency difference is not within the receiving interval, as shown in step S14, the PWM control circuit 16 performs a frequency adjustment phase on the PWM signal PWM to adjust the period of the PWM signal PWM to be close to the current input period of the vertical synchronization signal Vsync. In the frequency adjustment phase of step S14, the PWM control circuit 16 adjusts the period of the PWM signal PWM to approach the current input period in a stepwise manner, and each step adjusts a step value, which may be 1 millisecond (ms), for example, and increases the period of the PWM signal PWM by 1 ms each time until the period of the PWM signal PWM approaches the current input period if the period of the PWM signal PWM is to be increased.
In step S16, the PWM control circuit 16 determines whether to adjust the phase of the PWM signal PWM, and if it is not necessary to adjust the phase of the PWM signal PWM, the current phase is regarded as the new target phase, and the next step is performed (step S20). When the phase of the pulse width modulation signal PWM is to be adjusted, a phase adjustment stage is performed as shown in step S18, and the pulse width modulation control circuit 16 adjusts the phase of the pulse width modulation signal PWM to the phase of the vertical synchronization signal Vsync.
Finally, as shown in step S20, the PWM control circuit 16 maintains the relative phase relationship between the PWM signal PWM and the vertical synchronization signal Vsync regardless of whether the phase of the PWM signal PWM is adjusted. In other words, regardless of the adjusted target phase or the unadjusted target phase, for a slight fluctuation of the vertical synchronization signal Vsync, the pulse width modulation control circuit 16 slightly changes the frequency of the pulse width modulation signal PWM to maintain the relative phase relationship between the pulse width modulation signal PWM and the vertical synchronization signal Vsync. In one embodiment, the relative phase relationship between the PWM signal PWM and the vertical synchronization signal Vsync is maintained in two ways, one is that the PWM control circuit 16 maintains the relative phase relationship that the phase of the PWM signal PWM is equal to the phase of the vertical synchronization signal Vsync, and the other is that the PWM control circuit 16 maintains the relative phase relationship that the phase of the PWM signal PWM and the phase of the vertical synchronization signal Vsync differ from each other by a target phase difference.
Since different display devices 20 have different panel characteristics and compatibility, this factor will affect the PWM control circuit 16 to determine whether to adjust the phase of the PWM signal PWM. As shown in fig. 1 and 3a, since the PWM signal PWM and the vertical synchronization signal Vsync must be aligned, when the frame frequency changes, the PWM control circuit 16 needs to adjust the phase of the PWM signal PWM to the phase of the vertical synchronization signal Vsync, so that the PWM signal PWM and the vertical synchronization signal Vsync are aligned and the start positions are the same. If the display device 20 can accept that the PWM signal PWM and the vertical synchronization signal Vsync are not necessarily aligned according to the panel characteristics and compatibility, as shown in FIG. 1 and FIG. 3b, when the frame frequency changes, a phase difference exists between two adjacent pulses of the PWM signal PWM
In this case, the PWM control circuit 16 may directly use the current phase of the pulse as the new target phase, and it is not necessary to adjust the phase of the PWM signal PWM again.
In one embodiment, the amplitude of the periodic variation of the pulse width modulation signal PWM is inversely proportional to the time required for the phase of the pulse width modulation signal PWM to be adjusted to the phase of the vertical synchronization signal Vsync. Fig. 4 is a graph of the relationship between the amplitude of the periodic variation of the PWM signal and the time for adjusting the phase according to an embodiment of the present disclosure, please refer to fig. 4, in which the graph shows the phase difference after the frequency adjustment is completed, and the amplitude of the periodic variation acceptable according to the PWM signal PWM is inversely proportional to the time required for adjusting the phase of the PWM signal PWM. In the range of the left area a, the amplitude of the period change of the PWM signal PWM is selected to be very small, that is, the period of the PWM signal PWM is very close to the period of the vertical synchronization signal Vsync, the phase change is very slow, and the ripple phenomenon after the time is lengthened is not easily observed. In the range of the right area B, the amplitude of the periodic variation of the PWM signal PWM may be relatively large, and the phase amplitude that can be adjusted at one time is relatively large, and the phase variation of the PWM signal PWM and the vertical synchronization signal Vsync is very fast, so that the water ripple phenomenon is not easily observed. However, if the phase changes slowly but not very slowly within the range of the middle region C, this is where the ripple phenomenon is observed. Therefore, the risk of the occurrence of the water ripple phenomenon can be minimized by compensating the phase of the PWM signal PWM at an extremely fast speed or an extremely slow speed without causing panel flicker.
In view of the above, since different display devices have different panel characteristics, each display device has a corresponding relationship graph of the cycle variation amplitude of the pwm signal corresponding to the adjustment phase time, and the selection of the most suitable adjustment method and parameters for each display device can stabilize the relative relationship between the pwm signal and the vertical synchronization signal without causing panel flicker and water ripple.
Fig. 5 is a graph of the relationship between the period variation of the vertical synchronization signal and the PWM signal and the corresponding phase shift diagram according to an embodiment of the present disclosure, in which the vertical synchronization signal Vsync must be aligned with the start point of the PWM signal PWM, as shown in fig. 3a, and the amplitude of the period variation of the PWM signal PWM is limited. Referring to fig. 1 and 5, when the frame frequency of the vertical synchronization signal Vsync changes from 60Hz to 50Hz, the pwm control circuit 16 detects that the current input period and the previous input period of the vertical synchronization signal Vsync change, and if the frequency is too far away, it does not make much sense to adjust the phase, so the frequency is adjusted first. If the range I1 is located, the PWM control circuit 16 starts to adjust the frequency of the PWM signal PWM to make the period of the PWM signal PWM close to the current input period of the vertical synchronization signal Vsync, and the phase of the PWM signal PWM at this time has a large phase change as seen from the corresponding phase shift diagram. After adjusting the frequency, the PWM control circuit 16 analyzes the phase difference between the current PWM signal PWM and the vertical synchronization signal Vsync to determine which side the phase of the PWM signal PWM is adjusted according to the magnitude of the phase difference, for example, in the position of the range I2, after the frequency of the PWM signal PWM approaches the vertical synchronization signal Vsync, the PWM control circuit 16 starts to adjust the phase of the PWM signal PWM, and it can be seen from the corresponding phase offset diagram that the phase of the PWM signal PWM is gradually increased. After the phase adjustment, the PWM signal PWM will maintain a fixed relative phase relationship with the slight fluctuation of the vertical synchronization signal Vsync, for example, the position of the range I3, if the vertical synchronization signal Vsync still has slight oscillation, the PWM control circuit 16 will correspondingly fine-tune the period of the PWM signal PWM, and it can be seen from the phase offset diagram that the phase of the PWM signal PWM is substantially maintained at 0.
Fig. 6 is a graph of the relationship between the period variation of the vertical synchronization signal and the PWM signal and the corresponding phase shift diagram according to another embodiment of the present disclosure, in which the vertical synchronization signal Vsync may not be aligned with the start point of the PWM signal PWM, as shown in fig. 3 b. Referring to fig. 1 and 6, when the frame frequency of the vertical synchronization signal Vsync changes from 60Hz to 50Hz, the PWM control circuit 16 detects that the current input period of the vertical synchronization signal Vsync changes from the previous input period, and adjusts the frequency difference at the fastest speed when the period of the PWM signal PWM is not close to the vertical synchronization signal Vsync. If the range I4 is located, the PWM control circuit 16 starts to adjust the frequency of the PWM signal PWM to make the period of the PWM signal PWM close to the current input period of the vertical synchronization signal Vsync, and the phase of the PWM signal PWM at this time has a large phase change as seen from the corresponding phase shift diagram. After adjusting the frequency, the PWM control circuit 16 fixes the current phase of the PWM signal PWM to be the latest target phase, and each subsequent phase adjustment is performed with the target phase as the final position, such as the position in the range I5, after the frequency of the PWM signal PWM approaches the vertical synchronization signal Vsync, if the vertical synchronization signal Vsync still has slight oscillation, the PWM control circuit 16 will keep the phase of the PWM signal PWM at a certain fixed value (target phase) according to the fine adjustment period of the PWM signal PWM, as can be seen from the corresponding phase offset diagram. Therefore, after the frequency adjustment is completed, the current phase difference can be fixed as the target phase difference, and then only the small-amplitude variation of the vertical synchronization signal Vsync needs to be compensated, so that the target phase difference can be maintained at a certain magnitude, and the relative phase relationship between the pulse width modulation signal PWM and the vertical synchronization signal Vsync is maintained.
Therefore, on the premise of not generating the ripple phenomenon and the panel flicker, the present disclosure adjusts the frequency of the pwm signal to be the same as the vertical synchronization signal by using the frequency adjustment and phase adjustment methods according to the characteristics of different display devices, and stably maintains a certain phase relationship, so that the optimal relative relationship between the pwm signal and the vertical synchronization signal can be effectively maintained.
The above-described embodiments are merely illustrative of the technical ideas and features of the present disclosure, and the purpose thereof is to enable those skilled in the art to understand the disclosure and implement the same, and not to limit the claims of the present disclosure, i.e., all equivalent changes and modifications made according to the concepts disclosed in the present disclosure should be covered by the claims of the present disclosure.
Claims (10)
1. A signal processing method for maintaining relative relationship of signals comprises:
detecting that a current input period and a previous input period of a vertical synchronization signal change;
judging whether the frequency difference between a pulse width modulation signal and the vertical synchronizing signal is in a receiving interval, when the frequency difference is not in the receiving interval, carrying out a frequency adjusting stage to adjust the period of the pulse width modulation signal to be close to the current input period, and when the frequency difference is in the receiving interval, directly carrying out the following steps;
judging whether to adjust the phase of the pulse width modulation signal, and when the phase of the pulse width modulation signal is to be adjusted, performing a phase adjustment stage to adjust the phase of the pulse width modulation signal to the phase of the vertical synchronization signal; and
maintaining the relative phase relationship between the PWM signal and the vertical synchronization signal.
2. The method of claim 1, wherein the change is that a difference between the current input period and the previous input period exceeds a predetermined threshold.
3. The method as claimed in claim 1, wherein in the frequency adjustment stage, the period of the pwm signal is adjusted in stages to approach the current input period, and each stage is adjusted by a step value.
4. The signal processing method of claim 1, wherein the amplitude of the periodic variation of the pwm signal is inversely proportional to the time required for the phase of the pwm signal to be adjusted to the phase of the vertical synchronization signal.
5. The signal processing method according to claim 1, wherein in the step of maintaining the relative phase relationship between the pulse width modulation signal and the vertical synchronization signal, the relative phase relationship is maintained in which the phase of the pulse width modulation signal is equal to the phase of the vertical synchronization signal, or the relative phase relationship is maintained in which the phase of the pulse width modulation signal and the vertical synchronization signal differs by a target phase difference.
6. An electronic device for maintaining relative relationship of signals, comprising:
the display control circuit is electrically connected with a display device and outputs a vertical synchronous signal;
a pulse width modulation control circuit, which is electrically connected with the display control circuit and the display device respectively, receives the vertical synchronizing signal, and when the current input period and the previous input period of the vertical synchronizing signal change, the pulse width modulation control circuit judges whether the frequency difference value between a pulse width modulation signal and the vertical synchronizing signal is in a receiving interval, when the frequency difference value is not in the receiving interval, the pulse width modulation control circuit carries out a frequency adjusting stage to adjust the period of the pulse width modulation signal to be close to the current input period, and when the frequency difference value is in the receiving interval, the following steps are directly carried out; the PWM control circuit judges whether to adjust the phase of the PWM signal, and when the phase of the PWM signal is to be adjusted, the PWM control circuit carries out a phase adjustment stage to adjust the phase of the PWM signal to the phase of the vertical synchronization signal; the pulse width modulation control circuit maintains the relative phase relation between the pulse width modulation signal and the vertical synchronizing signal; and
and the processor is electrically connected with the display control circuit and the pulse width modulation control circuit so as to control the display control circuit and the pulse width modulation control circuit.
7. The electronic device of claim 6, wherein the change is that a difference between the current input period and the previous input period exceeds a predetermined threshold.
8. The electronic device of claim 6, wherein in the frequency adjustment phase, the period of the PWM signal is adjusted in stages to approach the current input period, and each stage is adjusted by a step value.
9. The electronic device according to claim 6, wherein the amplitude of the periodic variation of the PWM signal is inversely proportional to the time required for the phase of the PWM signal to be adjusted to the phase of the vertical synchronization signal.
10. The electronic device of claim 6, wherein the PWM control circuit maintains the relative phase relationship in which the phase of the PWM signal is equal to the phase of the vertical synchronization signal, or the PWM control circuit maintains the relative phase relationship in which the phase of the PWM signal is different from the phase of the vertical synchronization signal by a target phase difference.
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| KR101308479B1 (en) * | 2010-12-31 | 2013-09-16 | 엘지디스플레이 주식회사 | Method and circuit for synchronizing input and output synchronization signals, backlight driver of liquid crystal display device using the same, and method for driving the backlight driver |
| WO2012165172A1 (en) * | 2011-06-03 | 2012-12-06 | コニカミノルタアドバンストレイヤー株式会社 | Probe system and method for using same |
| TWI441142B (en) * | 2012-06-26 | 2014-06-11 | Amtran Technology Co Ltd | Liquid crystal display device capable of reducing ghost images and related method thereof |
| KR102034049B1 (en) * | 2012-12-27 | 2019-10-18 | 엘지디스플레이 주식회사 | Backlight driver of liquid crystal display device and method for driving the same |
| CN103093727B (en) * | 2013-01-23 | 2015-11-18 | 深圳创维－Rgb电子有限公司 | Backlight control signal method of adjustment and device |
| US10692443B2 (en) * | 2017-11-30 | 2020-06-23 | Novatek Microelectronics Corp. | Synchronous backlight device and operation method thereof |
| US10665177B2 (en) * | 2017-11-30 | 2020-05-26 | Novatek Microelectronics Corp. | Circuit arrangement for controlling backlight source and operation method thereof |
| CN111081191B (en) * | 2018-10-18 | 2021-06-15 | 联咏科技股份有限公司 | Circuit device for controlling backlight source and operation method thereof |
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