CN103390389A - Liquid crystal display device, panel drive device and control circuit - Google Patents
Liquid crystal display device, panel drive device and control circuit Download PDFInfo
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- CN103390389A CN103390389A CN2012101456277A CN201210145627A CN103390389A CN 103390389 A CN103390389 A CN 103390389A CN 2012101456277 A CN2012101456277 A CN 2012101456277A CN 201210145627 A CN201210145627 A CN 201210145627A CN 103390389 A CN103390389 A CN 103390389A
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Abstract
Disclosed are a liquid crystal display device capable of reducing fixed-frequency noise signals, a panel drive device and a control circuit. The liquid crystal display device comprises the control circuit, a backlight module, a panel and a drive circuit. The control circuit comprises a main board, a power panel and a time control unit. The main board receives an image signal and generates a pulse width modulation signal and a low-voltage differential signal with picture refreshing frequency, and the frequency of the pulse width modulation signal is odd times the 1/2 of the picture refreshing frequency. The power panel is electrically connected with the main board to receive the pulse width modulation signal and output control current to the backlight module according to the pulse width modulation signal to adjust luminance. The time control unit is electrically connected with the main board to receive the low-voltage differential signal and output a sequence signal to the drive circuit according to the picture refreshing frequency to drive the panel.
Description
Technical field
The present invention relates to a kind of device and circuit, particularly relate to a kind of liquid crystal indicator, board driving mchanism and control circuit.
Background technology
Existing a kind of liquid crystal indicator (not shown), by a Low Voltage Differential Signal LVDS(Low-voltage differential signal) decide picture refreshing frequency (Frame rate), and by a pulse width modulation (PWM) (Pulse-width modulation) signal, decide the brightness of its picture.
But existing liquid crystal indicator has following shortcoming: shown picture can be subject to determining the frequency noise and disturb, and more commonly, because this Low Voltage Differential Signal LVDS is different from the frequency of pulse width modulating signal PWM, the situation that interferes with each other is often arranged.As shown in Figure 1,, because this Low Voltage Differential Signal LVDS is a continuous signal, when this Low Voltage Differential Signal LVDS is disturbed by certain frequency noise, cause the light and shade of display cycle property on shown picture to change.It seems via human eye, become the band of a rule.
Summary of the invention
The object of the present invention is to provide a kind of liquid crystal display, board driving mchanism and control circuit of determining the frequency noise of subduing.
Liquid crystal indicator of the present invention comprises a control circuit, a panel, a backlight module and one drive circuit.This control circuit has a mainboard, a power panel and a time control module.
This mainboard is used for receiving a signal of video signal, and produce a Low Voltage Differential Signal with the picture refreshing frequency and a pulse width modulating signal, the frequency of this pulse width modulating signal is 1/2nd odd-multiple of this picture refreshing frequency, and has a dutycycle.This power panel is electrically connected to this mainboard and also exports accordingly the control electric current of relevant this dutycycle of size to receive this pulse width modulating signal.This time control unit is electrically connected to this mainboard to receive this Low Voltage Differential Signal, and according to this picture refreshing frequency, produces a clock signal.
This backlight module is electrically connected on this power panel to receive this control electric current, and is subjected to the control of this control electric current to adjust luminous brightness.This driving circuit is electrically connected on this time control unit to receive this clock signal, and is subjected to the control of this clock signal to drive this panel.
Board driving mchanism of the present invention is applicable to drive a panel, and comprises a control circuit, a backlight module and one drive circuit.This control circuit comprises a mainboard, a power panel and a time control module.
This mainboard is used for receiving a signal of video signal, and produce a Low Voltage Differential Signal with the picture refreshing frequency and a pulse width modulating signal, the frequency of this pulse width modulating signal is 1/2nd odd-multiple of this picture refreshing frequency, and has a dutycycle.This power panel is electrically connected to this mainboard and also exports accordingly the control electric current of relevant this dutycycle of size to receive this pulse width modulating signal.This time control unit is electrically connected to this mainboard to receive this Low Voltage Differential Signal, and according to this picture refreshing frequency, produces a clock signal.
This backlight module is electrically connected on this power panel to receive this control electric current, and is subjected to the control of this control electric current to adjust luminous brightness.This driving circuit is electrically connected on this time control unit to receive this clock signal, and is subjected to the control of this clock signal to drive this panel.
Control circuit of the present invention is applied to a liquid crystal indicator, this liquid crystal indicator comprises a backlight module, a panel, and one drive circuit, this backlight module is controlled electric current according to one and is adjusted luminosity, this driving circuit is subjected to the control of a clock signal to drive this panel, and this control circuit comprises a mainboard, a power panel and a time control module.
This mainboard is used for receiving a signal of video signal, and produce a Low Voltage Differential Signal with the picture refreshing frequency and a pulse width modulating signal, the frequency of this pulse width modulating signal is 1/2nd odd-multiple of this picture refreshing frequency, and has a dutycycle.This power panel is electrically connected to this mainboard and also exports accordingly the control electric current of relevant this dutycycle of size to receive this pulse width modulating signal.This time control unit is electrically connected to this mainboard to receive this Low Voltage Differential Signal, and according to this picture refreshing frequency, produces a clock signal.
This mainboard comprises a scalar processor and a phase-locked loop.This scalar processor, receive this signal of video signal and from this signal of video signal, capture a clock pulse information that is relevant to this picture refreshing frequency, and produce this Low Voltage Differential Signal and a frequency according to this clock pulse information and equal the reference signal of this picture refreshing frequency.This phase-locked loop, receive an adjustment signal with a multiple setting value, and be electrically connected on this scalar processor to receive this reference signal, and according to the frequency of this multiple setting value and this reference signal, produce this pulse width modulating signal, wherein, this multiple setting value odd-multiple of equaling 1/2nd.
This phase-locked loop has a frequency eliminator, a frequency plot detector, a low-pass filter and a voltage controlled oscillator.This frequency eliminator, receive this pulse width modulating signal and this adjustment signal, and computing according to this produces a feedback signal, and the frequency of this feedback signal is that the frequency of this pulse width modulating signal is divided by this multiple setting value; This frequency plot detector, be electrically connected on this scalar processor and this frequency eliminator to receive this reference signal and this feedback signal, and this reference signal and this feedback signal are carried out frequency plot relatively, produces a comparative result; This low-pass filter is electrically connected on this frequency plot detector to receive this comparative result, and filtering high frequency composition is controlled voltage to obtain one; This voltage controlled oscillator, be electrically connected on this low-pass filter to receive this control voltage, and produce according to this this pulse width modulating signal, and the frequency of this pulse width modulating signal is by this control Control of Voltage.
Beneficial effect of the present invention is: the frequency setting by adjusting this pulse width modulating signal, make in every two continuous pictures, and the interference that this Low Voltage Differential Signal is subject to is the anti-phase noise of subduing on picture.
Description of drawings
Fig. 1 is the schematic diagram that the existing shown picture of a liquid crystal indicator is interfered.
Fig. 2 is the system block diagrams of the preferred embodiment of liquid crystal indicator of the present invention.
Fig. 3 is a Low Voltage Differential Signal LVDS of this preferred embodiment and the oscillogram of a pulse width modulating signal PWM.
Fig. 4 is the shown picture view of this preferred embodiment, illustrates and disturb the situation that reduces when the dutycycle of this pulse width modulating signal is 50%.
Fig. 5 is the schematic diagram that the shown picture of this preferred embodiment is interfered, and illustrates and disturb the situation that reduces when this dutycycle is not 50%.
Fig. 6 is the system block diagrams of a phase-locked loop of this preferred embodiment.
Embodiment
The present invention is described in detail below in conjunction with drawings and Examples.
Consult Fig. 2, the present invention has the preferred embodiment of subduing the liquid crystal indicator of determining frequency noise function and comprises a panel drive unit 6 and a panel 3.This board driving mchanism 6 comprises a control circuit 2, a backlight module 4 and one drive circuit 5.
This control circuit 2 comprises a mainboard 21, a power panel 22 and a time control module 23.
This mainboard 21 receives a signal of video signal (coming from a signal source, for example the display card of computer), and produces a LVDS of the Low Voltage Differential Signal with the picture refreshing frequency and a pulse width modulating signal PWM with a dutycycle.This power panel 22 is electrically connected to this mainboard 21, also exports accordingly the control electric current of relevant this dutycycle of size to receive this pulse width modulating signal PWM.This time control unit 23 is electrically connected to this mainboard 21 to receive this Low Voltage Differential Signal LVDS, and according to this picture refreshing frequency, produces a clock signal.
This backlight module 4 is electrically connected on this power panel 22 to receive this control electric current, and is subjected to the control of this control electric current to adjust luminous brightness.This driving circuit 5 is electrically connected on this time control unit 23 to receive this clock signal, and is subjected to the control of this clock signal to drive this panel 3.
The problem that interferes with each other in order to solve this Low Voltage Differential Signal LVDS and pulse width modulating signal PWM, the frequency of this pulse width modulating signal PWM is set to 1/2nd odd-multiple (frequency of pulse width modulating signal PWM=(2n+1) * these picture refreshing frequency/2, n is integer) of this picture refreshing frequency.Consult Fig. 3 and Fig. 4, this Low Voltage Differential Signal LVDS switches between a picture data level T1 and a vertical synchronization (Vertical synchronous) pulse level T2, when being in picture data level T1, this driving circuit 5 drives this panel 3 to show a picture 01; When being in vertical sync pulse level T2, represent that this picture 01 demonstration finishes and prepare to show next picture 02, so the frequency of vertical sync pulse level T2 equals the picture refreshing frequency.The dutycycle of pulse width modulating signal PWM shown in figure take 50% is as example, it is anti-phase that the suffered pulse width modulating signal PWM of this moment picture 01 and picture 02 disturbs, the interference that shows on panel 3 is due to the persistence of vision of human eye, continuous two pictures 01,02 stack and average after, look like a uniform bias light (as shown in 03), and do not have a periodic band of the rule.
When the dutycycle of pulse width modulating signal PWM was not 50%, setting its frequency also had the effect of subduing interference for 1/2nd odd-multiple of this picture refreshing frequency.As shown in Figure 5, continuous two pictures 01,02 stack and average after, looking like frequency is the light line (as shown in 03) of twice.
Consult Fig. 2, but the frequency nationality of this pulse width modulating signal PWM adds namely a phase-locked loop 24 to reach more accurate frequency setting by these mainboard 21 adjustment.This moment, this mainboard 21 had a scalar processor 211 and a phase-locked loop 24.This scalar processor 211 receives these signal of video signal and from this signal of video signal, captures a clock pulse information that is relevant to this picture refreshing frequency, and produces this Low Voltage Differential Signal LVDS and a frequency according to this clock pulse information and equal the reference signal of this picture refreshing frequency.This phase-locked loop 24 receives an adjustment signal with a multiple setting value, and be electrically connected on this scalar processor 211 to receive this reference signal, and according to the frequency of this multiple setting value and this reference signal, produce this pulse width modulating signal PWM, wherein, this multiple setting value odd-multiple of equaling 1/2nd.
As shown in Figure 6, this phase-locked loop 24 has a frequency eliminator 244, a frequency plot detector 241, a low-pass filter 242 and a voltage controlled oscillator 243.This frequency eliminator 244 receives this pulse width modulating signal PWM and this adjusts signal, and computing according to this produces a feedback signal, and the frequency of this feedback signal is that the frequency of this pulse width modulating signal PWM is divided by this multiple setting value.This frequency plot detector 241 is electrically connected on this scalar processor 211 and this frequency eliminator 244 to receive this reference signal and this feedback signal, and this reference signal and this feedback signal are carried out frequency plot relatively, produces a comparative result.This low-pass filter 242 is electrically connected on this frequency plot detector 241 to receive this comparative result, and filtering high frequency composition is controlled voltage to obtain one.This voltage controlled oscillator 243 is electrically connected on this low-pass filter 242 to receive this control voltage, and produces according to this this pulse width modulating signal PWM, and the frequency of this pulse width modulating signal PWM is by this control Control of Voltage.
In sum, above-described embodiment has the following advantages:
1. utilize the frequency setting of this pulse width modulating signal PWM to solve the problem of determining the interference of frequency noise.No matter disturb and where occur in liquid crystal indicator, as long as making the frequency of this pulse width modulating signal PWM is 1/2nd odd-multiple of this picture refreshing frequency, just can be by the reverse-phase of undesired signal, reduce the noise that shows on panel 3, so really can reach the present invention's purpose.
2. directly utilize phase-locked loop 24 to adjust frequency, and need not consuming timely on the mainboard 21 of wiring complexity to carry out debug.
As described above, be only preferred embodiment of the present invention, and when not limiting scope of the invention process with this, i.e. all simple equivalences of doing according to the claims in the present invention book and description change and modify, and all still belong to the scope of patent of the present invention.
Claims (10)
1. control circuit, be applied to a liquid crystal indicator, this liquid crystal indicator comprises a backlight module, a panel, and one drive circuit, this backlight module is controlled electric current according to one and is adjusted luminosity, this driving circuit is subjected to the control of a clock signal to drive this panel, it is characterized in that this control circuit comprises:
One mainboard, be used for receiving a signal of video signal, and produce a Low Voltage Differential Signal with the picture refreshing frequency and a pulse width modulating signal, the frequency of this pulse width modulating signal is 1/2nd odd-multiple of this picture refreshing frequency, and this pulse width modulating signal has a dutycycle; And
One power panel, be electrically connected to this mainboard and also export accordingly the control electric current of relevant this dutycycle of size to receive this pulse width modulating signal; And
One time control module, be electrically connected to this mainboard to receive this Low Voltage Differential Signal, and according to this picture refreshing frequency, produce this clock signal.
2. control circuit according to claim 1 is characterized in that this mainboard comprises:
One scalar processor, receive this signal of video signal and from this signal of video signal, capture a clock pulse information that is relevant to this picture refreshing frequency, and produce this Low Voltage Differential Signal and a frequency according to this clock pulse information and equal the reference signal of this picture refreshing frequency; And
One phase-locked loop, receive an adjustment signal with a multiple setting value, and be electrically connected on this scalar processor to receive this reference signal, and according to the frequency of this multiple setting value and this reference signal, produce this pulse width modulating signal, wherein, this multiple setting value odd-multiple of equaling 1/2nd.
3. control circuit according to claim 2 is characterized in that this phase-locked loop has:
One frequency eliminator, receive this pulse width modulating signal and this adjustment signal, and computing according to this produces a feedback signal, and the frequency of this feedback signal is that the frequency of this pulse width modulating signal is divided by this multiple setting value;
One frequency plot detector, be electrically connected on this scalar processor and this frequency eliminator to receive this reference signal and this feedback signal, and this reference signal and this feedback signal are carried out frequency plot relatively, produces a comparative result;
One low-pass filter, be electrically connected on this frequency plot detector to receive this comparative result, and filtering high frequency composition is controlled voltage to obtain one; And
One voltage controlled oscillator, be electrically connected on this low-pass filter to receive this control voltage, and produce according to this this pulse width modulating signal, and the frequency of this pulse width modulating signal is by this control Control of Voltage.
4. liquid crystal indicator is characterized in that comprising:
one control circuit, comprise a mainboard, one power panel and a time control module, this mainboard is used for receiving a signal of video signal, and produce a Low Voltage Differential Signal with the picture refreshing frequency and a pulse width modulating signal, the frequency of this pulse width modulating signal is 1/2nd odd-multiple of this picture refreshing frequency, and has a dutycycle, this power panel is electrically connected to this mainboard and also exports accordingly the control electric current of relevant this dutycycle of size to receive this pulse width modulating signal, this time control unit is electrically connected to this mainboard to receive this Low Voltage Differential Signal, and according to this picture refreshing frequency, produce a clock signal,
One backlight module, be electrically connected on this power panel to receive this control electric current, and be subjected to the control of this control electric current to adjust luminous brightness;
One panel; And
One drive circuit, be electrically connected on this time control unit to receive this clock signal, and be subjected to the control of this clock signal to drive this panel.
5. liquid crystal indicator according to claim 4 is characterized in that this mainboard comprises:
One scalar processor, receive this signal of video signal and from this signal of video signal, capture a clock pulse information that is relevant to this picture refreshing frequency, and produce this Low Voltage Differential Signal and a frequency according to this clock pulse information and equal the reference signal of this picture refreshing frequency; And
One phase-locked loop, receive an adjustment signal with a multiple setting value, and be electrically connected on this scalar processor to receive this reference signal, and according to the frequency of this multiple setting value and this reference signal, produce this pulse width modulating signal, wherein, this multiple setting value odd-multiple of equaling 1/2nd.
6. liquid crystal indicator according to claim 5 is characterized in that this phase-locked loop has:
One frequency eliminator, receive this pulse width modulating signal and this adjustment signal, and computing according to this produces a feedback signal, and the frequency of this feedback signal is that the frequency of this pulse width modulating signal is divided by this multiple setting value;
One frequency plot detector, be electrically connected on this scalar processor and this frequency eliminator to receive this reference signal and this feedback signal, and this reference signal and this feedback signal are carried out frequency plot relatively, produces a comparative result;
One low-pass filter, be electrically connected on this frequency plot detector to receive this comparative result, and filtering high frequency composition is controlled voltage to obtain one; And
One voltage controlled oscillator, be electrically connected on this low-pass filter to receive this control voltage, and produce according to this this pulse width modulating signal, and the frequency of this pulse width modulating signal is by this control Control of Voltage.
7. a board driving mchanism, be applicable to drive a panel, it is characterized in that this board driving mchanism comprises:
One control circuit comprises:
One mainboard, be used for receiving a signal of video signal, and produce a Low Voltage Differential Signal with the picture refreshing frequency and a pulse width modulating signal, the frequency of this pulse width modulating signal is 1/2nd odd-multiple of this picture refreshing frequency, and this pulse width modulating signal has a dutycycle;
One power panel, be electrically connected to this mainboard and also export accordingly the control electric current of relevant this dutycycle of size to receive this pulse width modulating signal; And
One time control module, be electrically connected to this mainboard to receive this Low Voltage Differential Signal, and according to this picture refreshing frequency, produce a clock signal;
One backlight module, be electrically connected on this power panel to receive this control electric current, and be subjected to the control of this control electric current to adjust luminous brightness; And
One drive circuit, be electrically connected on this time control unit to receive this clock signal, and be subjected to the control of this clock signal to drive this panel.
8. board driving mchanism according to claim 7 is characterized in that this mainboard comprises:
One scalar processor, receive this signal of video signal and from this signal of video signal, capture a clock pulse information that is relevant to this picture refreshing frequency, and produce this Low Voltage Differential Signal and a frequency according to this clock pulse information and equal the reference signal of this picture refreshing frequency; And
One phase-locked loop, receive an adjustment signal with a multiple setting value, and be electrically connected on this scalar processor to receive this reference signal, and according to the frequency of this multiple setting value and this reference signal, produce this pulse width modulating signal, wherein, this multiple setting value odd-multiple of equaling 1/2nd.
9. board driving mchanism according to claim 8 is characterized in that this phase-locked loop has:
One frequency eliminator, receive this pulse width modulating signal and this adjustment signal, and computing according to this produces a feedback signal, and the frequency of this feedback signal is that the frequency of this pulse width modulating signal is divided by this multiple setting value;
One frequency plot detector, be electrically connected on this scalar processor and this frequency eliminator to receive this reference signal and this feedback signal, and this reference signal and this feedback signal are carried out frequency plot relatively, produces a comparative result;
One low-pass filter, be electrically connected on this frequency plot detector to receive this comparative result, and filtering high frequency composition is controlled voltage to obtain one; And
One voltage controlled oscillator, be electrically connected on this low-pass filter to receive this control voltage, and produce according to this this pulse width modulating signal, and the frequency of this pulse width modulating signal is by this control Control of Voltage.
10. board driving mchanism according to claim 7, is characterized in that this dutycycle is set as 50%.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012101456277A CN103390389A (en) | 2012-05-09 | 2012-05-09 | Liquid crystal display device, panel drive device and control circuit |
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| CN2012101456277A CN103390389A (en) | 2012-05-09 | 2012-05-09 | Liquid crystal display device, panel drive device and control circuit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2015096111A1 (en) * | 2013-12-23 | 2015-07-02 | 深圳市华星光电技术有限公司 | Liquid crystal display and method for adjusting brightness and contrast of liquid crystal display |
| CN109387978A (en) * | 2017-08-03 | 2019-02-26 | 苹果公司 | Local display back light system and method |
| WO2021238361A1 (en) * | 2020-05-26 | 2021-12-02 | 海信视像科技股份有限公司 | Display device and display control method |
| CN113948040A (en) * | 2021-11-22 | 2022-01-18 | 合肥视涯技术有限公司 | Display panel |
| CN114730051A (en) * | 2020-08-18 | 2022-07-08 | 华为技术有限公司 | Optical module, communication device and PoE device |
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| TW200639773A (en) * | 2005-01-25 | 2006-11-16 | Matsushita Electric Ind Co Ltd | Backlight control device and display apparatus |
| TWM373542U (en) * | 2009-07-28 | 2010-02-01 | Chunghwa Picture Tubes Ltd | Circuit architecture for filtering backlight light source noise |
| CN102103842A (en) * | 2009-12-17 | 2011-06-22 | 乐金显示有限公司 | Liquid crystal display and method of updating software |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2015096111A1 (en) * | 2013-12-23 | 2015-07-02 | 深圳市华星光电技术有限公司 | Liquid crystal display and method for adjusting brightness and contrast of liquid crystal display |
| CN109387978A (en) * | 2017-08-03 | 2019-02-26 | 苹果公司 | Local display back light system and method |
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| WO2021238361A1 (en) * | 2020-05-26 | 2021-12-02 | 海信视像科技股份有限公司 | Display device and display control method |
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| CN114730051A (en) * | 2020-08-18 | 2022-07-08 | 华为技术有限公司 | Optical module, communication device and PoE device |
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| CN113948040A (en) * | 2021-11-22 | 2022-01-18 | 合肥视涯技术有限公司 | Display panel |
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Application publication date: 20131113 |