CN111081191A

CN111081191A - Circuit device for controlling backlight source and operation method thereof

Info

Publication number: CN111081191A
Application number: CN201811396640.3A
Authority: CN
Inventors: 吴忠文; 林文祈; 林俊谊
Original assignee: Novatek Microelectronics Corp
Current assignee: Novatek Microelectronics Corp
Priority date: 2018-10-18
Filing date: 2018-11-22
Publication date: 2020-04-28
Anticipated expiration: 2038-11-22
Also published as: CN111540316A; CN111540316B; TW202016920A; CN111081191B; TWI687916B

Abstract

The embodiment of the invention provides a circuit device for controlling a backlight source and an operation method thereof. The circuit arrangement comprises a generator. The generator is used for receiving the synchronous signal and generating a pulse width modulation signal synchronous with the synchronous signal so as to control the backlight source. The synchronization signal indicates the frequency of the video, which in turn comprises a series of image frames. The synchronization signal includes a synchronization period corresponding to one frame of the video. The pulse width modulation signal includes a first waveform pattern in a first sub-period of the synchronization period and a second waveform pattern in a second sub-period of the synchronization period. Each of the first and second waveform patterns includes at least one effective pulse, respectively. The first wave pattern is substantially the same as the second wave pattern.

Description

Circuit device for controlling backlight source and operation method thereof

Technical Field

The present disclosure relates to display devices, and particularly to a circuit device for controlling a backlight and a method for operating the same.

Background

Fig. 1 is a waveform diagram illustrating a backlight control signal BL1 when a conventional backlight apparatus controls/drives a backlight in an asynchronous manner. The vertical axis in fig. 1 represents voltage, and the horizontal axis represents time. Vsync in fig. 1 indicates a vertical synchronization signal, and DE indicates a data enable signal. The video processing circuit (not shown) may transmit the vertical synchronization signal Vsync and the data enable signal DE to the panel driving circuit (not shown) so as to control the panel driving circuit to drive the liquid crystal display panel (not shown). The vertical synchronization signal Vsync defines a plurality of video frame periods (video frames), such as the video frame periods F1, F2, F3, and F4 shown in fig. 1. As shown in fig. 1, the backlight control signal BL1 of the conventional backlight device is independent of the phases (or timings) of the video frame periods F1, F2, F3 and F4, i.e., the conventional backlight device controls/drives the backlight source (not shown) in an asynchronous manner. The lcd panel using the asynchronous backlight may have a problem of image sticking (Motion Blur).

Fig. 2A is a waveform diagram illustrating a backlight control signal BL2 when a conventional backlight device employs a synchronization method to control/drive a backlight source. The vertical axis in fig. 2A represents voltage, and the horizontal axis represents time. Vsync shown in fig. 2A denotes a vertical synchronization signal, and DE denotes a data enable signal. The vertical synchronization signal Vsync defines a plurality of video frame periods, such as the video frame periods F1, F2, F3, and F4 shown in fig. 2A. As shown in fig. 2A, the pulse phase (or timing) of the backlight control signal BL2 of the conventional backlight device can be synchronized with the video frame periods F1, F2, F3 and F4 according to the vertical synchronization signal Vsync, that is, the conventional backlight device controls/drives the backlight source (not shown) in a synchronized manner. When the backlight control signal BL2 is high, the backlight provides backlight. When the backlight control signal BL2 is low, the backlight source does not provide backlight. The pulse widths PW2 of the backlight control signal BL2 in the video frame periods F1, F2, F3 and F4 are the same, and these pulse widths PW2 can be adjusted according to the usage requirement.

Fig. 2B is a waveform diagram illustrating a backlight control signal BL2 when another conventional backlight device employs a synchronization method to control/drive the backlight source. The vertical axis in fig. 2B represents voltage, and the horizontal axis represents time. The vertical synchronization signal Vsync and the data enable signal DE shown in fig. 2B can be referred to the related description of fig. 2A, and thus are not described again. According to the data enable signal DE, as shown in fig. 2B, the phase (or timing) of the backlight control signal BL2 of the conventional backlight device can be synchronized with the video frame periods F1, F2, F3 and F4, i.e. the conventional backlight device controls/drives the backlight source (not shown) in a synchronized manner. The pulse widths PW2 of the backlight control signal BL2 in F1, F2, F3, and F4 are equal to each other during the video frame, and these pulse widths PW2 can be adjusted according to the use requirement. In any case, in practical applications, the period length of the vertical synchronization signal Vsync (the period length of the data enable signal DE) may not be fixed, that is, the lengths of the video frame periods F1, F2, F3, and F4 may be different from each other (as shown in fig. 2A and 2B). For the liquid crystal display panel using the synchronous backlight, since the period length of the vertical synchronization signal Vsync is not fixed, the conventional backlight device may have a problem of backlight flicker.

Disclosure of Invention

The invention provides a circuit device for controlling a backlight source and an operation method thereof, which aim to solve the problem of backlight flicker.

Embodiments of the present invention provide a circuit arrangement for controlling a backlight source. The circuit arrangement comprises a generator. The generator is used for receiving a synchronization signal (sync signal) and generating a Pulse Width Modulation (PWM) signal synchronized with the sync signal to control the backlight source. The synchronization signal indicates the frequency of a video (video) that contains a series of image frames. The synchronization signal includes one synchronization period (sync period) corresponding to one frame (frame) of the video. The pulse width modulation signal includes a first waveform pattern (waveform pattern) in a first sub-period of the synchronization period and a second waveform pattern in a second sub-period of the synchronization period. Each of the first and second waveform patterns includes at least one active pulse (active pulse), respectively. The first wave pattern is substantially the same as the second wave pattern.

Embodiments of the present invention provide a method of operating a circuit arrangement for controlling a backlight. The operation method comprises the following steps: receiving, by a generator, a synchronization signal, wherein the synchronization signal indicates a frequency of a video, and the video includes a series of image frames; and generating a pulse width modulation signal synchronous with the synchronous signal by the generator so as to control the backlight source. Wherein the synchronization signal includes a synchronization period corresponding to one frame of the video, the pwm signal includes a first waveform pattern in a first sub-period of the synchronization period and a second waveform pattern in a second sub-period of the synchronization period, each of the first waveform pattern and the second waveform pattern respectively includes at least one effective pulse, and the first waveform pattern is substantially the same as the second waveform pattern.

The embodiment of the invention provides a circuit device for controlling a backlight source. The circuit arrangement comprises a generator. The generator is used for receiving the synchronous signal and generating a pulse width modulation signal synchronous with the synchronous signal so as to control the backlight source. The synchronization signal indicates a frequency of a video, the video including a series of image frames. The synchronization signal includes a synchronization period corresponding to one frame of the video. The pulse width modulation signal comprises a plurality of repeated waveform patterns in a first sub-period and a second sub-period of the synchronous period. Each of the plurality of repeating waveform patterns includes at least one active pulse.

The embodiment of the invention provides a circuit device for controlling a backlight source. The circuit arrangement comprises a generator. The generator is used for receiving the synchronous signal and generating a pulse width modulation signal synchronous with the synchronous signal so as to control the backlight source. The synchronization signal indicates a frequency of a video, the video including a series of image frames. The synchronization signal includes a synchronization period corresponding to one frame of the video. The generator divides the synchronization period into at least a first sub-period and a second sub-period. The pulse width modulation signal includes a first waveform pattern in the first sub-period of the synchronization period and a second waveform pattern in the second sub-period of the synchronization period. Each of the first and second waveform patterns includes at least one effective pulse, respectively.

The embodiment of the invention provides a circuit device for controlling a backlight source. The circuit arrangement comprises a generator. The generator is used for receiving the synchronous signal and generating a pulse width modulation signal synchronous with the synchronous signal so as to control the backlight source. The synchronization signal indicates the frequency of the video. The video includes a series of image frames. The synchronization signal includes a first synchronization period corresponding to a first frame of the video and a second synchronization period corresponding to a second frame of the video. The first synchronization period is longer in time than the second synchronization period. The pwm signal includes a first waveform pattern in a first sub-period of the first synchronization period, a second waveform pattern in a second sub-period of the first synchronization period, and a third waveform pattern in the second synchronization period. Each of the first, second, and third waveform patterns includes at least one effective pulse, respectively. The first wave pattern is substantially the same as the second wave pattern.

In view of the above, the circuit device for controlling a backlight source and the operating method thereof according to the embodiments of the invention divide a synchronization period into at least a first sub-period and a second sub-period. The first waveform pattern of the first sub-period and the second waveform pattern of the second sub-period include at least one effective pulse, respectively. The first wave pattern is substantially the same as the second wave pattern. If the length of the synchronization period is too long, the first waveform pattern and the second waveform pattern may bring about a frequency doubling effect to make human eyes not easily perceive flicker, so the circuit device and the operation method thereof may improve the problem of backlight flicker.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a schematic diagram illustrating waveforms of backlight control signals when a conventional backlight device controls/drives a backlight source in an asynchronous manner;

fig. 2A is a schematic diagram illustrating waveforms of backlight control signals when a conventional backlight device controls/drives a backlight source in a synchronous manner;

FIG. 2B is a diagram illustrating waveforms of backlight control signals when another conventional backlight device employs a synchronous method to control/drive the backlight sources;

FIG. 3 is a circuit block diagram of a display device according to an embodiment of the invention;

FIG. 4 is a flowchart illustrating a method of operating a circuit arrangement for controlling a backlight according to an embodiment of the present invention;

FIG. 5 is a waveform diagram illustrating the PWM signal of FIG. 3 according to an embodiment of the present invention;

FIG. 6 is a block diagram of a PWM control circuit of FIG. 3 according to an embodiment of the present invention;

FIG. 7 is a waveform diagram illustrating signals of FIG. 6 according to one embodiment of the present invention;

FIG. 8 is a block diagram of a PWM control circuit of FIG. 3 according to another embodiment of the present invention;

FIG. 9 is a schematic diagram illustrating waveforms of the vertical synchronization signal and the smoothed signal shown in FIG. 8 according to an embodiment of the invention;

FIG. 10 is a flowchart illustrating a method of operating a circuit arrangement for controlling a backlight according to another embodiment of the present invention;

FIG. 11 is a schematic diagram illustrating waveforms of the PWM signal shown in FIG. 3 according to a further embodiment of the present invention;

FIG. 12 is a block diagram of a PWM control circuit of FIG. 3 according to a further embodiment of the present invention;

FIG. 13 is a schematic diagram illustrating waveforms of the PWM signal of FIG. 3 according to yet another embodiment of the present invention;

FIG. 14 is a block diagram of a PWM control circuit of FIG. 3 according to another embodiment of the present invention;

fig. 15 is a schematic diagram illustrating waveforms of the PWM signal shown in fig. 3 according to another embodiment of the present invention.

Description of the reference numerals

300: display device

310: scaler circuit

320: panel driving circuit

330: display panel

340: generator

341: pulse width modulation control circuit

342: backlight driving circuit

350: back light source

351: back light

610: period definition circuit

611: first enable signal

612: second enable signal

620: first pulse width modulation signal generating circuit

621: first enable signal

630: second pulse width modulation signal generating circuit

631: second enable signal

640: superposition circuit

710: low-pass filter

711: smoothed signal

1210: frequency checking circuit

1220: pulse width modulation signal generating circuit

BL1, BL 2: backlight control signal

BL 3: pulse width modulation control signal

DE: data enable signal

DL: delay parameter

DR: duty ratio parameter

F1, F2, F4, F4, F5, F6, F7, F8, F9, F10: during video frames

F11, F12, F13, F14, F15, F16: video frame

P51, P61, P71, P81, P91, P101: the first period

P52, P62, P72, P82, P92, P102: the second period

PW 2: pulse width

Psync 1: during synchronization

S410 to S440, S1010 to S1030: step (ii) of

SP 11: the first sub-period

SP 12: the second sub-period

TD: delay time

Vsync 1: vertical synchronization signal

Vsync 2: multiplied synchronous signals

SP 111: the third sub-period

SP 112: the fourth sub period

SP121, SP 122: sub period

Detailed Description

The term "coupled" as used throughout this specification, including the claims, may refer to any direct or indirect connection. For example, if a first device couples (or connects) to a second device, it should be construed that the first device may be directly connected to the second device or the first device may be indirectly connected to the second device through some other device or some connection means. Further, wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts. Elements/components/steps in different embodiments using the same reference numerals or using the same terms may be referred to one another in relation to the description.

Fig. 3 is a circuit block diagram of a display device 300 according to an embodiment of the invention. The display device 300 includes a display panel 330, a panel driving circuit 320, and a video processing circuit. Such as a scaler circuit 310 and/or other video signal processing circuits, depending on design requirements. The scaler circuit 310 (video processing circuit) may transmit the clock signal, the synchronization signal and the video data to the panel driving circuit 320 so that the panel driving circuit may drive the display panel 330. The synchronization signal may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and/or other synchronization signals according to design requirements. The vertical synchronization signal may define a plurality of video frame (video frame) periods. In other words, the synchronization signal may indicate the frequency (or period) of a video (video), wherein the video comprises a series of image frames (a series of image frames). The Display panel 330 may be a Liquid Crystal Display (LCD) panel or other types of Display panels according to design requirements. The scaler circuit 310, the panel driving circuit 320 and the display panel 330 are conventional components and therefore will not be described herein.

In the embodiment shown in fig. 3, display device 300 further includes a backlight 350 and circuitry for controlling backlight 350. In the embodiment shown in fig. 3, the circuit arrangement comprises, for example, a generator 340. The generator 340 may receive the synchronization signal from a video processing circuit, such as the scaler circuit 310. In accordance with the synchronization signal, generator 340 may control/drive backlight 350 in a synchronized manner. Generator 340 may perform either full-zone backlight control or zoned backlight control on backlight 350. Backlight 350 may provide backlight 351 to display panel 330. The backlight 350 may be a direct-type backlight module or an edge-type backlight module according to design requirements. Since the generator 340 controls/drives the backlight 350 in a synchronous manner, the problem of Motion Blur can be effectively improved.

In the embodiment shown in fig. 3, the generator 340 includes a Pulse Width Modulation (PWM) control circuit 341 and a backlight driving circuit 342. The PWM control circuit 341 is coupled to the video processing circuit (e.g., the scaler circuit 310) to receive a synchronization signal (e.g., a vertical synchronization signal, a data enable signal, and/or other synchronization signals). The PWM control circuit 341 may generate a PWM signal BL 3. The backlight driving circuit 342 is coupled to the PWM control circuit 341 to receive the PWM signal BL 3. According to the PWM signal BL3, the backlight driving circuit 342 may drive the backlight 350 of the display panel 330. PWM control circuit 341 may perform either full-zone backlight control or zoned backlight control on backlight 350.

Fig. 4 is a flowchart illustrating an operation method of a circuit apparatus for controlling a backlight according to an embodiment of the invention. Please refer to fig. 3 and fig. 4. In step S410, the PWM control circuit 341 receives a synchronization signal (e.g., a vertical synchronization signal, a data enable signal, and/or other synchronization signals) from a video processing circuit (e.g., the scaler circuit 310), wherein the synchronization signal defines a plurality of video frame periods. In step S420, the PWM control circuit 341 divides each of the video frame periods into at least a first period and a second period, wherein the lengths of the first periods in different video frame periods are the same as each other.

Fig. 5 is a waveform diagram illustrating the PWM signal BL3 shown in fig. 3 according to an embodiment of the invention. The vertical axis in fig. 5 represents voltage, and the horizontal axis represents time. The example of implementation shown in fig. 5 assumes that PWM control circuit 341 receives a vertical synchronization signal Vsync (video synchronization information) from a video processing circuit (e.g., scaler circuit 310). Please refer to fig. 3, fig. 4 and fig. 5. The vertical synchronization signal Vsync defines a plurality of video frame periods, such as the video frame periods F5, F6, F7, and F8 shown in fig. 5. In another embodiment, PWM control circuit 341 receives data enable signal DE (synchronization signal) from a video processing circuit (e.g., scaler circuit 310). The data enable signal DE may also define a plurality of video frame periods, such as the video frame periods F5, F6, F7, and F8 shown in fig. 5.

In step S420, the PWM control circuit 341 divides each of the video frame periods into at least a first period and a second period. The first period may comprise part or all of a data period during a video frame, and the second period may comprise part or all of a blanking period during a video frame, as desired by design.

For example, according to the data enable signal DE in the synchronization signal, the video frame period F5 is divided into at least a first period P51 and a second period P52, the video frame period F6 is divided into at least a first period P61 and a second period P62, the video frame period F7 is divided into at least a first period P71 and a second period P72, and the video frame period F8 is divided into at least a first period P81 and a second period P82. Wherein, the lengths of the first periods P51, P61, P71 and P81 of the video frame periods F5-F8 are the same. The first period P51 includes a data period of the video frame period F5, and the second period P52 includes a blank period of the video frame period F5. The first period P61 includes a data period of the video frame period F6, and the second period P62 includes a blank period of the video frame period F6. The first period P71 includes a data period of the video frame period F7, and the second period P72 includes a blank period of the video frame period F7. The first period P81 includes a data period of the video frame period F8, and the second period P82 includes a blank period of the video frame period F8.

In step S430, the PWM control circuit 341 generates a PWM signal BL 3. The frequency of the PWM signal BL3 in the first period is different from the frequency of the PWM signal BL3 in the second period, but the duty ratio (dutypatio) of the PWM signal BL3 in the first period is the same as the duty ratio of the PWM signal BL3 in the second period. For example, the frequency of the PWM signal BL3 in the first period P51 is different from the frequency of the PWM signal BL3 in the second period P52, but the Duty ratio of each Duty cycle of the PWM signal BL3 in the first period P51 is the same as the Duty ratio of each Duty cycle of the PWM signal BL3 in the second period P52.

In the embodiment shown in fig. 5, the frequency of the PWM signal BL3 in the first period is smaller than the frequency of the PWM signal BL3 in the second period. For example, the frequency of the PWM signal BL3 in the first period P51 is smaller than the frequency of the PWM signal BL3 in the second period P52.

The backlight driving circuit 342 is coupled to the PWM control circuit 341 to receive the PWM signal BL 3. In step S440, the backlight driving circuit 342 drives the backlight 350 of the display panel 330 according to the PWM signal BL3, so that the backlight 350 provides the backlight 351 to the display panel 330.

Based on the above, the generator 340 and the operation method thereof according to the present embodiment divide each video frame period into at least a first period and a second period. The lengths of these first periods during different video frames are the same as each other. If the length of the video frame period varies, the length of the second period varies, but the length of the first period does not vary. The frequency of the PWM signal BL3 in the first period is different from the frequency of the PWM signal BL3 in the second period, but the duty ratio of the PWM signal BL3 in the first period is the same as the duty ratio of the PWM signal BL3 in the second period. Therefore, by driving/controlling the backlight 350 to provide the compensating light energy (backlight 351) during the second period, the average backlight luminance in F5 to F8 can be made to be approximately uniform during different video frames. In other words, the generator 340 and the operation method thereof can improve the problem of backlight flickering.

Fig. 6 is a circuit block diagram illustrating the PWM control circuit 341 shown in fig. 3 according to an embodiment of the invention. In the embodiment shown in fig. 6, the PWM control circuit 341 includes a period definition circuit 610, a first PWM signal generation circuit 620, a second PWM signal generation circuit 630, and a superposition circuit 640. The period definition circuit 610 is coupled to the video processing circuit (e.g., the scaler circuit 310) to receive a synchronization signal (e.g., a vertical synchronization signal Vsync) from the video processing circuit. The period definition circuit 610 may generate a first enable signal 611 and a second enable signal 612 according to the timing of the vertical synchronization signal Vsync. The first enable signal 611 may define the first period, and the second enable signal 612 may define the second period.

For example, fig. 7 is a waveform diagram illustrating the signals shown in fig. 6 according to an embodiment of the invention. The vertical axis in fig. 7 represents voltage, and the horizontal axis represents time. The vertical synchronization signal Vsync defines a plurality of video frame periods, such as the video frame periods F9 and F10 shown in fig. 7. The video frame period F9 is divided into at least a first period P91 and a second period P92, and the video frame period F10 is divided into at least a first period P101 and a second period P102. The first enable signal 611 may define the first period P91 and the first period P101, and the second enable signal 612 may define the second period P92 and the second period P102. Wherein the lengths of the first periods P91 and P101 are the same as each other. If the length of the video frame period varies, the lengths of the second periods P92 and P102 also vary, but the lengths of the first periods P91 and P101 do not vary.

Please refer to fig. 6 and 7. The first PWM signal generating circuit 620 is coupled to the period definition circuit 610 to receive the first enable signal 611. The first PWM signal generating circuit 620 may generate the first PWM signal 621 in the first period according to the first enable signal 611. The first PWM signal generation circuit 620 may determine the duty ratio of the first PWM signal 621 in the first period according to the duty ratio parameter DR. The embodiment shown in fig. 7 will assume that the duty ratio is 50%, and in other embodiments the duty ratio may be adjusted according to the usage requirements. The first PWM signal generating circuit 620 may further determine the phase of the first PWM signal 621 in the first period according to the delay parameter DL. The first PWM signal generation circuit 620 may be any type of PWM signal generation circuit/element. For example, the first PWM signal generating circuit 620 may be a PWM signal generating circuit or other PWM signal generating circuit known in the art.

In the embodiment shown in fig. 7, when the first enable signal 611 is at a low level, the first PWM signal generation circuit 620 is disabled. When the first enable signal 611 is at a high level, the first PWM signal generating circuit 620 is enabled (enable). Therefore, the first PWM signal generating circuit 620 can generate the first PWM signal 621 in the first periods P91 and P101. The first PWM signal generation circuit 620 may set the duty ratio of the first PWM signal 621 in the first periods P91 and P101 to 50% according to the duty ratio parameter DR. The first PWM signal generating circuit 620 may further determine the delay time TD of the pulse of the first PWM signal 621 in the first periods P91 and P101 according to the delay parameter DL, i.e. determine the phase of the first PWM signal 621 in the first periods P91 and P101.

The second PWM signal generating circuit 630 is coupled to the period definition circuit 610 for receiving the second enable signal 612. The second PWM signal generating circuit 630 may generate the second PWM signal 631 in the second period according to the second enable signal 612. The second PWM signal generation circuit 630 may determine the duty ratio of the second PWM signal 631 during the second period according to the same duty ratio parameter DR. In the embodiment shown in fig. 7, when the second enable signal 612 is at a low level, the second PWM signal generating circuit 630 is disabled. When the second enable signal 612 is at a high level, the second PWM signal generating circuit 630 is enabled. Therefore, the second PWM signal generating circuit 630 can generate the second PWM signal 631 during the second periods P92 and P102. The second PWM signal generation circuit 630 may set the duty ratio of the second PWM signal 631 in the second periods P92 and P102 to 50% according to the duty ratio parameter DR. The frequency of the second PWM signal 631 in the second periods P92 and P102 is different from the frequency of the first PWM signal 621 in the first periods P91 and P101. The second PWM signal generation circuit 630 may be any type of PWM signal generation circuit/element. For example, the second PWM signal generation circuit 630 may be a PWM signal generation circuit or other PWM signal generation circuit known in the art.

The superimposing circuit 640 is coupled to the first PWM signal generating circuit 620 to receive the first PWM signal 621. The superimposing circuit 640 is coupled to the second PWM signal generating circuit 630 to receive the second PWM signal 631. The superimposing circuit 640 may superimpose the first PWM signal 621 and the second PWM signal 631 to obtain a PWM signal BL3, as shown in fig. 7.

Fig. 8 is a circuit block diagram illustrating the PWM control circuit 341 in fig. 3 according to another embodiment of the invention. In the embodiment shown in fig. 8, the PWM control circuit 341 includes a low pass filter 710, a period definition circuit 610, a first PWM signal generation circuit 620, a second PWM signal generation circuit 630, and a superposition circuit 640. The period definition circuit 610, the first PWM signal generation circuit 620, the second PWM signal generation circuit 630 and the overlap circuit 640 shown in fig. 8 can be analogized with reference to the related descriptions of fig. 6 and fig. 7, and therefore, the description thereof is omitted.

In the embodiment shown in fig. 8, the low pass filter 710 is coupled to the video processing circuit (e.g., the scaler circuit 310) to receive a synchronization signal (e.g., a vertical synchronization signal Vsync) from the video processing circuit. The low pass filter 710 may output a smoothed signal 711 to the period definition circuit 610. Fig. 9 is a schematic diagram illustrating waveforms of the vertical synchronization signal Vsync and the smoothed signal 711 shown in fig. 8 according to an embodiment of the invention. As shown in fig. 9, the low pass filter 710 may smooth the vertical synchronization signal Vsync to generate a smoothed signal 711. The period definition circuit 610 is coupled to the low pass filter 710 to receive the smoothed signal 711. The period definition circuit 610 may generate the first enable signal 611 and the second enable signal 612 according to the timing of the smoothed signal 711.

The generator 340 and the operation method thereof according to the above embodiments use a synchronous manner to control/drive the backlight 350, so that the problem of Motion Blur can be effectively improved. The generator 340 and the operation method thereof may be applied to backlight control of a variable vertical synchronization signal or a fixed vertical synchronization signal. The generator 340 and the method of operating the same may divide each video frame period into at least a first period and a second period. The lengths of these first periods during different video frames are the same as each other. If the length of the video frame period varies, the length of the second period varies, but the length of the first period does not vary. The frequency of the PWM signal BL3 in the first period is different from the frequency of the PWM signal BL3 in the second period, but the duty ratio of the PWM signal BL3 in the first period is the same as the duty ratio of the PWM signal BL3 in the second period. Thus, by driving/controlling backlight 350 to provide compensating light energy (backlight 351) during the second period, the average backlight brightness during different video frames may be made to be approximately uniform. In other words, the generator 340 and the operation method thereof can improve the problem of backlight flickering.

Fig. 10 is a flowchart illustrating an operation method of a circuit apparatus for controlling a backlight according to another embodiment of the invention. Please refer to fig. 3 and fig. 10. In step S1010, the generator 340 receives a synchronization signal (including a vertical synchronization signal Vsync, a data enable signal DE, and/or other synchronization signals). The synchronization signal may indicate a frequency of a video (video), wherein the video comprises a series of image frames. The synchronization signal includes a synchronization period (sync period) corresponding to one frame of video.

In step S1020, the generator 340 may generate a Pulse Width Modulation (PWM) signal BL3 synchronized with the synchronization signal to control the backlight 350. The generator 340 may divide the synchronization period into at least a first sub-period and a second sub-period. The PWM signal BL3 includes a first waveform pattern (waveformpeak) in a first sub-period of the synchronization period and a second waveform pattern in a second sub-period of the synchronization period. Each of the first and second waveform patterns includes at least one active pulse (active pulse), respectively. The first wave pattern is substantially the same as the second wave pattern.

In another embodiment, the PWM signal BL3 includes a plurality of repeating waveform patterns in a first sub-period and a second sub-period of the synchronization period, wherein each of the plurality of repeating waveform patterns includes at least one valid pulse.

In yet another embodiment, the synchronization signal includes a first synchronization period corresponding to a first frame of the video and a second synchronization period corresponding to a second frame of the video. The first synchronization period is longer in time than the second synchronization period. The pulse width modulation signal includes a first waveform pattern in a first sub-period of the first synchronization period, a second waveform pattern in a second sub-period of the first synchronization period, and a third waveform pattern in the second synchronization period. Each of the first, second, and third waveform patterns includes at least one effective pulse, respectively. The first wave pattern is substantially the same as the second wave pattern.

In step S1030, the generator 340 drives the backlight 350 of the display panel 330 according to the PWM signal BL3, so that the backlight 350 provides the backlight 351 to the display panel 330. Step S1030 shown in fig. 10 can refer to the related description of step S440 shown in fig. 4, and therefore is not described herein again.

In the present embodiment, the PWM control circuit 341 of the generator 340 may receive the synchronization signal from the scaler circuit 310 (video processing circuit). The PWM control circuit 341 checks the frequency (or period) of the synchronization signal. When the frequency of the synchronization signal is lower than a threshold frequency (or when the period of the synchronization signal is greater than a threshold period), the PWM control circuit 341 multiplies the frequency of the synchronization signal to generate a multiplied synchronization signal. The threshold frequency may be determined according to design requirements. When the frequency of the synchronization signal is higher than the threshold frequency, the PWM control circuit 341 takes the synchronization signal as the frequency-multiplied synchronization signal. The PWM control circuit 341 may generate the PWM signal BL3 according to the multiplied synchronization signal. The backlight driving circuit 342 is coupled to the PWM control circuit 341 to receive the PWM signal BL 3. The backlight driving circuit 342 drives the backlight 350 of the display panel 330 according to the PWM signal BL 3.

The PWM control circuit 341 may check the time length of the synchronization period. When the time length of the synchronization period exceeds the rated time length, the PWM control circuit 341 divides the synchronization period into at least the first sub-period and the second sub-period. The nominal time length may be set according to design requirements. The duty ratio of the PWM signal BL3 in the first sub-period is the same as the duty ratio of the PWM signal BL3 in the second sub-period. The frequency of the PWM signal BL3 in the first sub-period is the same as the frequency of the PWM signal BL3 in the second sub-period.

Fig. 11 is a waveform diagram illustrating the PWM signal BL3 shown in fig. 3 according to a further embodiment of the present invention. In fig. 11, the vertical axis represents voltage and the horizontal axis represents time. Please refer to fig. 3, fig. 10 and fig. 11. In step S1010, the PWM control circuit 341 receives a synchronization signal (e.g., the vertical synchronization signal Vsync1 or the data enable signal DE) from a video processing circuit (e.g., the scaler circuit 310). The vertical synchronization signal Vsync1 of fig. 12 may indicate the frequency (or period) of a video including a series of image frames (a series of image frames), such as the video frames F11, F12, F13, F14, F15, and F16 of fig. 11. The synchronization signal includes a synchronization period (sync period) corresponding to one frame of video. For example, the video frame F16 corresponds to a sync period Psync 1.

The PWM control circuit 341 may check the time length of the synchronization period (e.g., the synchronization period Psync1 shown in fig. 11). The synchronization period Psync1 corresponding to the video frame F16 is used as an example. The synchronization periods corresponding to the remaining video frames (e.g., the video frames F11, F12, F13, F14, and F15 shown in fig. 11) can be analogized by referring to the description of the synchronization period Psync1, and thus are not described again. If the sync period Psync1 is too long (i.e., the frequency of the PWM signal BL3 may be too low), human eyes may perceive flickering of the backlight 350. Therefore, when the time length of the synchronization period Psync1 exceeds the rated time length, the PWM control circuit 341 may divide the synchronization period Psync1 into at least a first sub-period SP11 and a second sub-period SP 12.

In step S1020, the PWM control circuit 341 may generate a PWM signal BL3 synchronized with the synchronization signal (e.g., the vertical synchronization signal Vsync1 or the data enable signal DE) to control the backlight 350. Here, the duty ratio of the PWM signal BL3 in the first sub-period SP11 is the same as the duty ratio of the PWM signal BL3 in the second sub-period SP12, and the frequency of the PWM signal BL3 in the first sub-period SP11 is the same as the frequency of the PWM signal BL3 in the second sub-period SP 12. In step S1030, the backlight driving circuit 342 drives the backlight 350 of the display panel 330 according to the PWM signal BL3, so that the backlight 350 provides the backlight 351 to the display panel 330.

When the time length of the synchronization period Psync1 exceeds the rated time length, the PWM control circuit 341 may apply a frequency doubling operation to the PWM signal BL3 in the synchronization period Psync1, so that human eyes may not perceive flicker of the backlight 350. Therefore, the generator 340 and the operation method thereof can improve the problem of backlight flicker.

Fig. 12 is a circuit block diagram illustrating the PWM control circuit 341 shown in fig. 3 according to a further embodiment of the present invention. In the embodiment shown in fig. 12, the PWM control circuit 341 includes a frequency check circuit 1210 and a PWM signal generation circuit 1220. The frequency check circuit 1210 is coupled to the video processing circuit (e.g., the scaler circuit 310) to receive a synchronization signal (e.g., the vertical synchronization signal Vsync1) from the video processing circuit. The frequency check circuit 1210 checks the frequency of the vertical synchronization signal Vsync 1.

Please refer to fig. 11 and 12. When the frequency of the vertical synchronization signal Vsync1 is higher than a threshold frequency (or when the period of the vertical synchronization signal Vsync1 is smaller than a threshold period), the frequency check circuit 1210 uses the vertical synchronization signal Vsync1 as the multiplied synchronization signal Vsync 2. For example, in the video frame F11, the frequency of the doubled synchronization signal Vsync2 is the same as the frequency of the vertical synchronization signal Vsync 1. The threshold frequency may be determined according to design requirements. When the frequency of the vertical synchronization signal Vsync1 is lower than the threshold frequency (or when the period of the vertical synchronization signal Vsync1 is greater than the threshold period), the frequency check circuit 1210 multiplies the frequency of the vertical synchronization signal Vsync1 to generate a multiplied synchronization signal Vsync 2. Referring to fig. 11, in the synchronization period Psync1, the frequency of the multiplied synchronization signal Vsync2 is twice the frequency of the vertical synchronization signal Vsync 1. In any case, the multiplying power of the frequency doubling operation can be determined according to design requirements.

The PWM signal generation circuit 1220 is coupled to the frequency check circuit 1210 to receive the multiplied synchronization signal. The PWM signal generating circuit 1220 generates a PWM signal BL3 to the backlight driving circuit 342 according to the frequency-multiplied synchronizing signal Vsync 2. The PWM signal generating circuit 1220 determines the duty ratio of the PWM signal according to the duty ratio parameter DR. The duty ratio parameter DR may be adjusted according to actual usage requirements. In addition, the PWM signal generating circuit 1220 may determine the delay time TD according to the delay parameter DL, that is, determine the phase of the PWM signal BL 3. The PWM signal generation circuit 1220 may be any type of PWM signal generation circuit/element. For example, the PWM signal generating circuit 1220 may be a PWM signal generating circuit known in the art or other PWM signal generating circuits.

Fig. 13 is a schematic diagram illustrating a waveform of the PWM signal BL3 shown in fig. 3 according to yet another embodiment of the present invention. In fig. 13, the vertical axis represents voltage and the horizontal axis represents time. The example of implementation shown in fig. 13 assumes that PWM control circuit 341 receives vertical synchronization signal Vsync1 (video synchronization information) from a video processing circuit (e.g., scaler circuit 310). The vertical synchronization signal Vsync1, the frequency-doubled synchronization signal Vsync2, the delay time TD, the video frame F11, the video frame F12, the video frame F13, the video frame F14, the video frame F15, the video frame F16, the synchronization period Psync1, the first sub-period SP11, and the second sub-period SP12 shown in fig. 13 may refer to the description of fig. 11, and thus, are not repeated.

The PWM control circuit 341 divides the first sub-period SP11 into at least a third sub-period SP111 and a fourth sub-period SP112 according to the multiplied synchronizing signal Vsync 2. Similarly, the second sub-period SP12 is divided into at least a sub-period SP121 and a sub-period SP 122. The remaining video frames F11, F12, F13, F14, and F15 shown in fig. 11 are also each divided into a plurality of sub-periods. The sub-periods of the video frames F11, F12, F13, F14 and F15 shown in fig. 11 can be analogized by referring to the related descriptions of the video frame period F5, the first period P51, the second period P52, the video frame period F6, the first period P61, the second period P62, the video frame period F7, the first period P71, the second period P72, the video frame period F8, the first period P81 and the second period P82 shown in fig. 5, and thus the description is omitted.

Fig. 14 is a circuit block diagram illustrating the PWM control circuit 341 shown in fig. 3 according to yet another embodiment of the present invention. Please refer to fig. 13 and 14. In the embodiment shown in fig. 14, the PWM control circuit 341 includes a frequency checking circuit 1210, a period defining circuit 610, a first PWM signal generating circuit 620, a second PWM signal generating circuit 630, and a superimposing circuit 640. The frequency check circuit 1210 is coupled to the video processing circuit (e.g., the scaler circuit 310) to receive a synchronization signal (e.g., the vertical synchronization signal Vsync1) from the video processing circuit. The frequency check circuit 1210 checks the frequency of the vertical synchronization signal Vsync1, and outputs a multiplied synchronization signal Vsync 2. The frequency check circuit 1210 and the multiplied synchronizing signal Vsync2 shown in fig. 14 can be analogized by referring to the related descriptions of the frequency check circuit 1210 and the multiplied synchronizing signal Vsync2 shown in fig. 12, and thus, the description thereof is omitted.

The period definition circuit 610 is coupled to the frequency check circuit 1210 to receive the multiplied synchronizing signal Vsync 2. According to the timing of the multiplied synchronization signal Vsync2, the period definition circuit 610 may generate a first enable signal 611 and a second enable signal 612, wherein the first enable signal 611 defines the third sub-period SP111 and the sub-period SP121, and the second enable signal 612 defines the fourth sub-period SP112 and the sub-period SP 122. The period definition circuit 610, the first enable signal 611, and the second enable signal 612 shown in fig. 14 can be analogized with the related descriptions of the period definition circuit 610, the first enable signal 611, and the second enable signal 612 shown in fig. 6 and fig. 7, and therefore, the description thereof is omitted.

The first PWM signal generating circuit 620 is coupled to the period definition circuit 610 to receive the first enable signal 611. The first PWM signal generating circuit 620 may generate the first PWM signal 621 in the third sub-period SP111 and the sub-period SP121 according to the first enable signal 611, and determine the duty ratio of the first PWM signal 621 in the third sub-period SP111 and the sub-period SP121 according to a duty ratio parameter DR. The first PWM signal generating circuit 620 may further determine the delay time TD of the pulse of the first PWM signal 621 in the third sub-period SP111 according to the delay parameter DL, that is, determine the phase of the first PWM signal 621. The first PWM signal generating circuit 620 and the first PWM signal 621 shown in fig. 14 can be analogized by referring to the related descriptions of the first PWM signal generating circuit 620 and the first PWM signal 621 shown in fig. 6 and fig. 7, and therefore, the description thereof is omitted.

The second PWM signal generating circuit 630 is coupled to the period definition circuit 610 for receiving the second enable signal 612. The second PWM signal generating circuit 630 generates the second PWM signal 631 in the fourth sub-period SP112 and the sub-period SP122 according to the second enable signal 612, and determines the duty ratio of the second PWM signal 631 in the fourth sub-period SP112 and the sub-period SP122 according to the duty ratio parameter DR. The frequency of the second PWM signal 631 is different from the frequency of the first PWM signal 621. The second PWM signal generating circuit 630 and the second PWM signal 631 shown in fig. 14 can be analogized by referring to the related descriptions of the second PWM signal generating circuit 630 and the second PWM signal 631 shown in fig. 6 and fig. 7, and therefore, the descriptions thereof are omitted.

The superimposing circuit 640 is coupled to the first PWM signal generating circuit 620 to receive the first PWM signal 621. The superimposing circuit 640 is coupled to the second PWM signal generating circuit 630 to receive the second PWM signal 631. The superimposing circuit 640 superimposes the first PWM signal 621 and the second PWM signal 631 to obtain the PWM signal BL 3. The superimposing circuit 640 and the PWM signal BL3 shown in fig. 14 can be analogized with the related descriptions of the superimposing circuit 640 and the PWM signal BL3 shown in fig. 6 and fig. 7, and therefore, the description thereof is omitted.

Fig. 15 is a schematic diagram illustrating a waveform of the PWM signal BL3 shown in fig. 3 according to another embodiment of the present invention. In fig. 15, the vertical axis represents voltage and the horizontal axis represents time. The example of implementation shown in fig. 15 assumes that PWM control circuit 341 receives vertical synchronization signal Vsync1 (video synchronization information) from a video processing circuit (e.g., scaler circuit 310). The vertical synchronization signal Vsync1, the frequency-doubled synchronization signal Vsync2, the video frame F11, the video frame F12, the video frame F13, the video frame F14, the video frame F15, the video frame F16, the synchronization period Psync1, the first sub-period SP11, and the second sub-period SP12 shown in fig. 15 may refer to the description of fig. 11 and/or fig. 13, and thus, the description thereof is omitted.

In the embodiment shown in fig. 15, the PWM signal BL3 has one pulse each during the leading and trailing ones of the sub-periods, and the PWM signal BL3 has no pulse during the middle one of the sub-periods. For example, the PWM signal BL3 has one pulse each in the leading period and the trailing period in the third sub-period SP111, and the PWM signal BL3 has no pulse in the middle period in the third sub-period SP111, as shown in fig. 15. The other sub-periods (for example, the sub-period SP121) can be analogized by referring to the description of the third sub-period SP111, and thus, the description thereof is omitted.

According to different design requirements, the generator 340, the PWM control circuit 341, the backlight driving circuit 342, the frequency checking circuit 1210, the PWM signal generating circuit 1220, the period definition circuit 610, the first PWM signal generating circuit 620, the second PWM signal generating circuit 630 and/or the superimposing circuit 640 may be implemented in hardware (hardware), firmware (firmware), software (software, i.e., program) or a combination of multiple ones of the foregoing.

In terms of hardware, the above-mentioned blocks of the generator 340, the PWM control circuit 341, the backlight driving circuit 342, the frequency checking circuit 1210, the PWM signal generating circuit 1220, the period definition circuit 610, the first PWM signal generating circuit 620, the second PWM signal generating circuit 630 and/or the superimposing circuit 640 may be implemented as logic circuits on an integrated circuit (integrated circuit). The related functions of the generator 340, the PWM control circuit 341, the backlight driving circuit 342, the frequency checking circuit 1210, the PWM signal generating circuit 1220, the period defining circuit 610, the first PWM signal generating circuit 620, the second PWM signal generating circuit 630 and/or the superimposing circuit 640 may be implemented as hardware using hardware description languages (for example, Verilog HDL or VHDL) or other suitable programming languages. For example, the related functions of the generator 340, the PWM control circuit 341, the backlight driving circuit 342, the frequency checking circuit 1210, the PWM signal generating circuit 1220, the period definition circuit 610, the first PWM signal generating circuit 620, the second PWM signal generating circuit 630 and/or the superimposing circuit 640 may be implemented in various logic blocks, modules and circuits in one or more controllers, microcontrollers, microprocessors, Application-specific integrated circuits (ASICs), Digital Signal Processors (DSPs), Field Programmable Gate Arrays (FPGAs) and/or other processing units.

In software and/or firmware, the related functions of the generator 340, the PWM control circuit 341, the backlight driving circuit 342, the frequency checking circuit 1210, the PWM signal generating circuit 1220, the period defining circuit 610, the first PWM signal generating circuit 620, the second PWM signal generating circuit 630 and/or the superimposing circuit 640 may be implemented as programming codes. For example, the generator 340, the PWM control circuit 341, the backlight driving circuit 342, the frequency checking circuit 1210, the PWM signal generating circuit 1220, the period defining circuit 610, the first PWM signal generating circuit 620, the second PWM signal generating circuit 630, and/or the superimposing circuit 640 are implemented by using a general programming language (e.g., C, C + + or a combination language) or other suitable programming languages. The program code may be recorded/stored in a recording medium including, for example, a Read Only Memory (ROM), a storage device, and/or a Random Access Memory (RAM). A computer, a Central Processing Unit (CPU), a controller, a microcontroller, or a microprocessor can read and execute the programming codes from the recording medium to achieve related functions. As the recording medium, a non-transitory computer readable medium (non-transitory medium) may be used, and for example, a tape (tape), a disk (disk), a card (card), a semiconductor memory, a programmable logic circuit, or the like may be used. The program may be supplied to the computer (or CPU) via any transmission medium (communication network, broadcast wave, or the like). Such as the Internet, wired communication, wireless communication, or other communication media.

In summary, the circuit device for controlling a backlight and the operating method thereof according to the embodiments of the invention can divide a synchronization period Psync1 into at least a first sub-period SP11 and a second sub-period SP 12. The first waveform pattern of the PWM signal BL3 in the first sub-period SP11 and the second waveform pattern of the PWM signal BL3 in the second sub-period SP12 respectively include at least one effective pulse. The first waveform pattern in the first sub-period SP11 is substantially the same as the second waveform pattern in the second sub-period SP 12. If the length of the sync period Psync1 is too long, the first waveform pattern and the second waveform pattern may bring about a frequency doubling effect to make the human eye less aware of the flicker of the backlight 350. Therefore, the circuit device and the operation method thereof can improve the problem of backlight flicker.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A circuit arrangement for controlling a backlight, the circuit arrangement comprising:

a generator for receiving a synchronization signal and generating a pulse width modulation signal synchronized with the synchronization signal to control the backlight, the synchronization signal indicating a frequency of a video, the video comprising a series of image frames, wherein

The synchronization signal includes a synchronization period corresponding to a frame of the video,

the pulse width modulation signal includes a first waveform pattern in a first sub-period of the synchronization period and a second waveform pattern in a second sub-period of the synchronization period,

each of the first and second waveform patterns comprises at least one effective pulse, respectively, an

The first wave pattern is substantially the same as the second wave pattern.

2. The circuit arrangement of claim 1, wherein the generator comprises:

a pulse width modulation control circuit for receiving the synchronization signal from a video processing circuit, wherein the pulse width modulation control circuit checks a frequency of the synchronization signal, the pulse width modulation control circuit multiplies the frequency of the synchronization signal to generate a multiplied synchronization signal when the frequency of the synchronization signal is lower than a threshold frequency, the pulse width modulation control circuit treats the synchronization signal as the multiplied synchronization signal when the frequency of the synchronization signal is higher than the threshold frequency, and the pulse width modulation control circuit generates the pulse width modulation signal according to the multiplied synchronization signal; and

a backlight driving circuit coupled to the pwm control circuit for receiving the pwm signal and driving the backlight of the display panel according to the pwm signal.

3. The circuit arrangement of claim 2, wherein the video processing circuit comprises a scaler circuit and the synchronization signal comprises a vertical synchronization signal.

4. The circuit arrangement as claimed in claim 2, wherein the pwm control circuit checks the time length of the synchronization period, and when the time length of the synchronization period exceeds a rated time length, the pwm control circuit divides the synchronization period into at least the first sub-period and the second sub-period, and the duty ratio of the pwm signal in the first sub-period is the same as the duty ratio of the pwm signal in the second sub-period.

5. The circuit device as claimed in claim 4, wherein the frequency of the PWM signal in the first sub-period is the same as the frequency of the PWM signal in the second sub-period.

6. The circuit arrangement of claim 2, wherein the pwm control circuit comprises:

a frequency check circuit to receive the synchronization signal from the video processing circuit, wherein the frequency check circuit checks a frequency of the synchronization signal, the frequency check circuit multiplies the frequency of the synchronization signal to generate the multiplied synchronization signal when the frequency of the synchronization signal is lower than the threshold frequency, and the frequency check circuit treats the synchronization signal as the multiplied synchronization signal when the frequency of the synchronization signal is higher than the threshold frequency; and

a PWM signal generating circuit coupled to the frequency checking circuit for receiving the frequency multiplied synchronous signal, generating the PWM signal to the backlight driving circuit according to the frequency multiplied synchronous signal, and determining a duty ratio of the PWM signal according to a duty ratio parameter.

7. The circuit device according to claim 2, wherein the pwm control circuit divides the first sub-period into at least a third sub-period and a fourth sub-period according to the multiplied synchronization signal.

8. The circuit device as claimed in claim 7, wherein the pulse width modulation signal has pulses in a leading period and a trailing period of the third sub-period, respectively, and the pulse width modulation signal has no pulses in a middle period of the third sub-period.

9. The circuit arrangement of claim 7, wherein the pulse width modulation control circuit comprises:

a frequency check circuit to receive the synchronization signal from the video processing circuit, wherein the frequency check circuit checks the frequency of the synchronization signal, the frequency check circuit multiplies the frequency of the synchronization signal to generate the multiplied synchronization signal when the frequency of the synchronization signal is lower than the threshold frequency, and the frequency check circuit treats the synchronization signal as the multiplied synchronization signal when the frequency of the synchronization signal is higher than the threshold frequency;

a period defining circuit, coupled to the frequency checking circuit, for receiving the frequency-multiplied synchronizing signal and generating a first enable signal and a second enable signal according to a timing of the frequency-multiplied synchronizing signal, wherein the first enable signal defines the third sub-period and the second enable signal defines the fourth sub-period;

a first PWM signal generating circuit coupled to the period definition circuit for receiving the first enable signal, generating a first PWM signal in the third sub-period according to the first enable signal, and determining an duty ratio of the first PWM signal in the third sub-period according to a duty ratio parameter;

a second pwm signal generating circuit, coupled to the period definition circuit to receive the second enable signal, for generating a second pwm signal in the fourth sub-period according to the second enable signal, and determining a duty ratio of the second pwm signal in the fourth sub-period according to the duty ratio parameter, wherein a frequency of the second pwm signal is different from a frequency of the first pwm signal; and

and a superposition circuit coupled to the first pwm signal generating circuit for receiving the first pwm signal, and coupled to the second pwm signal generating circuit for receiving the second pwm signal, wherein the superposition circuit superposes the first pwm signal and the second pwm signal to obtain the pwm signal.

10. The circuit device as claimed in claim 9, wherein the first pwm signal generating circuit further determines the phase of the first pwm signal in the third sub-period according to a delay parameter.

11. A method of operating a circuit arrangement for controlling a backlight, the method comprising:

receiving, by a generator, a synchronization signal, wherein the synchronization signal indicates a frequency of a video, the video including a series of image frames; and

generating a pulse width modulation signal synchronized with the synchronization signal by the generator to control the backlight source, wherein

The first wave pattern is substantially the same as the second wave pattern.

12. The operating method of claim 11, wherein the step of generating the pulse width modulated signal comprises:

checking the frequency of the synchronization signal;

when the frequency of the synchronization signal is below a threshold frequency, frequency-multiplying the frequency of the synchronization signal to generate a frequency-multiplied synchronization signal;

when the frequency of the synchronization signal is higher than the threshold frequency, taking the synchronization signal as the frequency-multiplied synchronization signal;

generating the pulse width modulation signal according to the frequency-multiplied synchronous signal; and

and driving the backlight source of the display panel by a backlight driving circuit according to the pulse width modulation signal.

13. The method of claim 12, wherein the synchronization signal comprises a vertical synchronization signal.

14. The method of claim 12, wherein the step of checking the frequency of the synchronization signal comprises:

checking a time length of the synchronization period;

when the time length of the synchronous period exceeds the rated time length, the synchronous period is divided into at least the first sub-period and the second sub-period, wherein the duty ratio of the pulse width modulation signal in the first sub-period is the same as the duty ratio of the pulse width modulation signal in the second sub-period.

15. The operating method according to claim 14, wherein the frequency of the pwm signal in the first sub-period is the same as the frequency of the pwm signal in the second sub-period.

16. The operating method of claim 12, wherein the step of generating the pulse width modulated signal comprises:

generating the pulse width modulation signal to the backlight driving circuit by a pulse width modulation signal generating circuit according to the frequency-multiplied synchronous signal; and

the duty ratio of the PWM signal is determined by the PWM signal generating circuit according to the duty ratio parameter.

17. The method of claim 12, further comprising:

the first sub-period is divided into at least a third sub-period and a fourth sub-period according to the frequency multiplied synchronization signal.

18. The operating method as claimed in claim 17, wherein the pwm signal has pulses during a leading period and a trailing period of the third sub-period, respectively, and the pwm signal has no pulses during a middle period of the third sub-period.

19. The operating method of claim 17, wherein the step of generating the pulse width modulated signal comprises:

generating a first enable signal and a second enable signal by a period definition circuit according to the timing sequence of the frequency-multiplied synchronizing signal, wherein the first enable signal defines the third sub-period and the second enable signal defines the fourth sub-period;

generating a first pulse width modulation signal in the third sub-period by a first pulse width modulation signal generating circuit according to the first enabling signal, and determining the duty ratio of the first pulse width modulation signal in the third sub-period according to a duty ratio parameter;

generating a second pulse width modulation signal in the fourth sub-period by a second pulse width modulation signal generation circuit according to the second enable signal, and determining the duty ratio of the second pulse width modulation signal in the fourth sub-period according to the duty ratio parameter, wherein the frequency of the second pulse width modulation signal is different from the frequency of the first pulse width modulation signal; and

and superposing the first pulse width modulation signal and the second pulse width modulation signal by a superposition circuit to obtain the pulse width modulation signal.

20. The operating method as claimed in claim 19, wherein the first pwm signal generating circuit further determines the phase of the first pwm signal in the third sub-period according to a delay parameter.

21. A circuit arrangement for controlling a backlight, the circuit arrangement comprising:

the PWM signal includes a plurality of repeating waveform patterns in a first sub-period and a second sub-period of the synchronization period, and

each of the plurality of repeating waveform patterns includes at least one active pulse.

22. A circuit arrangement for controlling a backlight, the circuit arrangement comprising:

the generator divides the synchronization period into at least a first sub-period and a second sub-period,

the pulse width modulation signal includes a first waveform pattern in the first sub-period of the synchronization period and a second waveform pattern in the second sub-period of the synchronization period, and

each of the first and second waveform patterns includes at least one effective pulse, respectively.

23. A circuit arrangement for controlling a backlight, the circuit arrangement comprising:

The synchronization signal comprises a first synchronization period corresponding to a first frame of the video and a second synchronization period corresponding to a second frame of the video,

the first synchronization period is longer in time than the second synchronization period,

the pulse width modulation signal includes a first waveform pattern in a first sub-period of the first synchronization period, a second waveform pattern in a second sub-period of the first synchronization period, and a third waveform pattern in the second synchronization period,

each of the first, second and third waveform patterns includes at least one effective pulse, respectively, an

The first wave pattern is substantially the same as the second wave pattern.