TWI684250B - Packaging substrate, manufacturing method thereof and semiconductor device - Google Patents

Abstract

The present invention provides a package substrate, a method of manufacturing the same, and a semiconductor device. In a package substrate in which a molded body is embedded and holds a conductor pattern, when the conductor pattern is removed from the molded body or a positional deviation is generated, it can be easily transported 3. Operation during the mounting of semiconductor components. The conductor pattern (1) is composed of a lower conductive layer (6) and an upper conductive layer (7). The outer shapes of the lower conductive layer (6) and the upper conductive layer (7) in plan view are formed so that either one is larger than the other. A barrier layer (11) that prevents the conductor pattern (1) from coming off the molded body (2) is formed on any one of the upper and lower surfaces of the molded body (2). The barrier layer (11) is formed to cover a part of the lower conductive layer (6) or the upper conductive layer (7) exposed from the molded body (2). Thereby, the conductive pattern (1) is blocked by the barrier layer (11), and it can be prevented from falling off from the molded body (2), so that the operation of packaging the substrate can be easily performed.

Description

Packaging substrate, manufacturing method thereof and semiconductor device

The present invention relates to a package substrate in which a conductor pattern is embedded and held in a molded body, a manufacturing method thereof, and a semiconductor device. The conductor pattern is exposed from above and below the molded body. Furthermore, the semiconductor device mounts the semiconductor element on the package substrate and is sealed by the sealing body.

For the purpose of reducing the weight of the package substrate, Patent Document 1 discloses a package substrate in which a conductor pattern is embedded and held in a molded body, which is known. The electrode package of Patent Document 1 includes a conductive pattern layer and an electrode layer integrally formed on the conductive pattern layer in a layered manner (hereinafter, the integrally formed conductive pattern layer and electrode layer are referred to as a pattern electrode layer.) . The pattern electrode layer is sealed in a plate-shaped resin (molded body), the conductive pattern layer is exposed on one surface of the plate-shaped resin, and the electrode layer is exposed on the other surface. In the manufacture of the electrode package, first, a resist layer corresponding to the conductive pattern layer is formed on a metal substrate made of stainless steel, and then the conductive pattern layer is formed by electroforming. Next, a resist layer corresponding to the electrode layer is formed on the resist layer and the conductive pattern layer, and then the electrode layer is formed by lamination by electroforming. Next, the two resist layers are removed, and the resin is applied and hardened to embed the pattern electrode layer, thereby sealing it in the plate-shaped resin. Finally, the surface of the plate-shaped resin is cut and peeled from the patterned electrode layer and the plate-shaped resin to remove the metal substrate, thereby manufacturing an electrode package in which the conductive pattern layer and the electrode layer are exposed on the upper and lower surfaces, respectively.

If, like the electrode package of Patent Document 1, it replaces the metal used in electroforming The use of a plate-shaped resin to hold the patterned electrode layer on the substrate makes it possible to reduce the weight of the entire electrode package and reduce the cost of the semiconductor device manufacturer when transporting the electrode package. In addition, when manufacturing a semiconductor device using an electrode package, the manufacturer can eliminate the procedure of removing the metal substrate, and can also contribute to a reduction in the manufacturing cost of the semiconductor device.

Patent Document 1: Japanese Patent Laid-Open No. 2005-244033 (Paragraph 0014, Fig. 1)

In the electrode package of Patent Document 1, since the patterned electrode layer is held by a thin plate-shaped resin, the electrode package is likely to be deformed such as deflection and twisting during transportation or mounting of a semiconductor element. Furthermore, if the electrode package is deformed, there is a possibility that peeling may occur at the boundary surface between the pattern electrode layer and the plate-shaped resin. Furthermore, there is a possibility that the patterned electrode layer may come off from the plate-shaped resin or may be displaced. Careful processing is carried out so as not to cause deflection or twisting of the electrode package, which can prevent the pattern electrode layer from falling off, etc. However, in this case, operations during transportation and mounting of semiconductor elements become cumbersome.

An object of the present invention is to provide a package substrate, a method for manufacturing the same, and a semiconductor device: in a package substrate in which a conductor pattern is embedded and held in a molded body, the conductor pattern is eliminated from the molded body or the positional deviation occurs Defects make it easy to carry out operations during transportation and when mounting semiconductor elements.

The present invention is directed to a package substrate in which the conductor pattern 1 is buried and held in the molded body 2 in a state where the upper and lower surfaces are exposed. It is characterized in that the conductor pattern 1 is composed of a lower conductive layer 6 and an upper conductive layer 7 laminated on the lower conductive layer 6. The outer shapes of the lower conductive layer 6 and the upper conductive layer 7 in plan view are formed so that either one is larger than the other. Moreover, on the molded body 2 A barrier layer 11 that prevents the conductive pattern 1 from falling off the molded body 2 is formed on either the surface or the lower surface.

The barrier layer 11 is formed to cover a part of the lower conductive layer 6 or the upper conductive layer 7 of the conductor pattern 1 exposed from the molded body 2.

The outer shape of the lower conductive layer 6 is formed larger than the outer shape of the upper conductive layer 7, and the barrier layer 11 is formed on the lower surface of the molded body 2.

The outer shape of the upper conductive layer 7 is formed to be larger than the outer shape of the lower conductive layer 6, and the barrier layer 11 is formed on the upper surface of the molded body 2.

The conductor pattern 1 is formed by electroforming, and the lower resist 18 and the upper resist 21 for forming the lower conductive layer 6 and the upper conductive layer 7 also serve as the molded body 2 in which the conductor pattern 1 is buried and held.

The barrier layer 11 is formed of a photo-curable solder resist ink layer 26.

In addition, the present invention is a method of manufacturing a package substrate in which a conductor pattern 1 composed of a lower conductive layer 6 and an upper conductive layer 7 laminated on the lower conductive layer 6 is buried and held in a molded body 2 to make the conductor pattern 1 is exposed on the upper and lower surfaces of the molded body 2, and either the upper surface or the lower surface of the molded body 2 is formed with a barrier layer 11 that prevents the conductive pattern 1 from falling off from the molded body 2. It is characterized by including an electroforming step in which the lower resist 18 is formed on the surface of the flat electroforming master mold 15 and the electroforming master mold 15 is not covered by the lower resist 18 Forming a lower conductive layer 6 on the surface; a secondary electroforming step in which an upper resist 21 is formed on the surface of the lower conductive layer 6 or the lower conductive layer 6 and the lower resist 18, The lower conductive layer 6 covered by the body 21 or the surface layer of the lower conductive layer 6 and the lower resist 18 forms an upper conductive layer 7; and a barrier layer forming step in which the molding of the conductor pattern 1 is buried and held The barrier layer 11 is formed on either the upper surface or the lower surface of the body 2. In the barrier layer forming step, in the molded body 2 Either the upper or lower surface of the photocurable solder resist ink layer 26 is formed, and a part of the exposed portion of the lower conductive layer 6 or the upper conductive layer 7 exposed from the molded body 2 is covered by photolithography The barrier layer 11 is formed.

After the secondary electroforming step, a molding step is performed to form a molded body 2 in which the conductor pattern 1 is buried and held. In the molding step, the lower resist and the upper resist 18, 21 formed in the primary and secondary electroforming steps are removed, and the space after removing the lower resist and the upper resist 18, 21 , The softened molding resin 22 is filled and hardened to form the molded body 2.

In a plan view, the outer shape of the lower conductive layer 6 is formed larger than the outer shape of the upper conductive layer 7, and the barrier layer 11 is formed on the lower surface of the molded body 2. Between the molding step and the barrier layer forming step, a master mold removing step of peeling and removing the electroformed master mold 15 from the conductor pattern 1 and the molded body 2 is included.

In the plan view, the outer shape of the upper conductive layer 7 is formed larger than the outer shape of the lower conductive layer 6, and the barrier layer 11 is formed on the upper surface of the molded body 2. After the barrier layer forming step, a master mold removing step of peeling and removing the electroformed master mold 15 from the conductor pattern 1 and the molded body 2 is included.

The lower and upper resists 18, 21 formed in the primary and secondary electroforming steps remain, and the two resists 18, 21 also serve as the molded body 2 in which the conductor pattern 1 is buried and held.

Furthermore, the present invention is a semiconductor device in which a semiconductor element S is mounted on the above-mentioned package substrate. The conductor pattern 1 includes an external electrode 4. After the electrode 31 included in the semiconductor element S and the external electrode 4 are electrically connected, the semiconductor element S is sealed with the sealing body 30.

In the package substrate of the present invention, the conductor pattern 1 is composed of the lower conductive layer 6 and the upper conductive layer 7 laminated on the lower conductive layer 6, and the lower conductive layer 6 and the upper conductive in plan view The outer shape of the layer 7 is formed so that either one is larger than the other. In addition, on either the upper surface or the lower surface of the molded body 2, a barrier layer 11 that prevents the conductive pattern 1 from falling off from the molded body 2 is formed. In this way, if the barrier layer 11 is formed on either one of the upper surface or the lower surface of the molded body 2 of the molded body 2, even when the package substrate is deformed such as deflection, torsion, etc. during transportation or assembly of the semiconductor element It is also possible to use the barrier layer 11 to prevent the conductor pattern 1 from falling out of the molded body 2. Therefore, it is possible to obtain a package substrate that can eliminate the drop of the conductor pattern 1 from the molded body 2 or the positional deviation, and can easily perform the operation at the time of transportation or the mounting of the semiconductor element. In addition, according to the provision of the barrier layer 11, the resistance against deformation such as deflection and torsion is increased, so that the deformation of the package substrate can be suppressed.

If the barrier layer 11 is formed to cover a part of the lower conductive layer 6 or the upper conductive layer 7 of the conductor pattern 1 exposed from the molded body 2, the portion of the lower conductive layer 6 or the upper conductive covered by the barrier layer 11 The layer 7 is blocked by the barrier layer 11 and can restrict the movement of the conductor pattern 1 to the side where the barrier layer 11 is formed.

If the outer shape of the lower conductive layer 6 is formed larger than the outer shape of the upper conductive layer 7 and the barrier layer 11 is formed on the lower surface of the molded body 2, the barrier layer 11 restricts the conductor pattern 1 from being exposed to the lower conductive layer 6 The lower side moves, and the conductor pattern 1 can be prevented from falling off from the molded body 2.

If the outer shape of the upper conductive layer 7 is formed to be larger than the outer shape of the lower conductive layer 6, and the barrier layer 11 is formed on the upper surface of the molded body 2, the upper surface of the conductive pattern 1 exposed to the upper conductive layer 7 is restricted by the barrier layer 11 Side movement, the conductor pattern 1 can be prevented from falling off from the molded body 2.

If the lower resist and upper resist used to form the lower conductive layer 6 and the upper conductive layer 7 The etching bodies 18 and 21 also serve as the molded body 2, and the two resists 18 and 21 can be used as the molded body 2 in which the conductor pattern 1 is buried and held. Therefore, it is possible to obtain a package substrate provided with the barrier layer 11 without separately embedding and holding the conductor pattern 1 in the molded body 2, and it is possible to reduce the manufacturing cost of the package substrate.

If the barrier layer 11 is formed of a photocurable solder resist ink layer 26, the barrier layer 11 of a desired pattern can be easily formed by photolithography, and the manufacturing cost of a package substrate provided with the barrier layer 11 can be further reduced. Furthermore, since the solder resist ink layer 26 has a higher structural strength than a general-purpose photoresist based on a phenolic resin-based polymer, it is possible to suppress breakage of the barrier layer 11 such as cracks and notches, and to effectively prevent the conductor pattern 1 It falls off from the molded body 2 or shifts in position.

The manufacturing method of the present invention includes a primary electroforming step, a secondary electroforming step, and a barrier layer forming step to form a package substrate. In addition, in the barrier layer forming step, the solder resist ink layer 26 is formed on either the upper or lower side of the molded body 2, and the lower conductive layer 6 or the upper conductive layer exposed from the molded body 2 is formed by photolithography The barrier layer 11 is formed so that a part of the exposed portion of 7 is covered. In this way, each process such as exposure, development, and drying can be performed using the same equipment as the primary and secondary electroforming steps, and since the barrier layer 11 of a desired pattern can be easily formed, the package substrate provided with the barrier layer 11 can be reduced Manufacturing costs.

In the molding step after the secondary electroforming step, the lower resist and the upper resist 18, 21 formed in the primary and secondary electroforming steps are removed, and the lower resist 18 and the upper resist are removed The space after the etching body 21 is filled with the softened molding resin 22 and then hardened to form the molded body 2 in which the conductor pattern 1 is buried and held. In this way, by forming the molded body 2 using the molded resin 22 having desired mechanical strength and material characteristics, the most suitable encapsulation base can be used The molded body 2 for the use of the board embeds and holds the conductor pattern 1. Therefore, when heat resistance is required for the package substrate, for example, by using polybutylene terephthalate, polyethylene, or the like for the mold resin 22, a package substrate excellent in heat resistance can be obtained. In addition, by setting the molded resin 22 to the same or the same system resin material as the sealing body 30 that seals the semiconductor element S mounted on the package substrate, it is possible to fix the molding body 2 and the sealing body 30 The state is stable, and the thermal expansion coefficients of the two 2 and 30 can be made substantially the same, thereby preventing peeling at the boundary surface between the molded body 2 and the sealing body 30.

In the plan view, the outer shape of the lower conductive layer 6 is formed larger than the outer shape of the upper conductive layer 7, and the barrier layer 11 is formed on the lower surface of the molded body 2. In addition, between the molding step and the barrier layer forming step, a master mold removing step of peeling and removing the electroformed master mold 15 from the conductor pattern 1 and the molded body 2 is included. In this way, since the conductive pattern 1 and the molded body 2 are formed on the electroformed master mold 15, the exposed surface of the lower conductive layer 6 and the lower surface of the molded body 2 after removing the electroformed master mold 15 can be smoothed surface. Therefore, it is not necessary to perform a polishing process or the like as a pre-processing for performing the barrier layer forming step, so that the manufacturing cost of the package substrate can be reduced.

In the plan view, the outer shape of the upper conductive layer 7 is formed to be larger than the outer shape of the lower conductive layer 6, and the barrier layer 11 is formed on the upper surface of the molded body 2. In addition, after the barrier layer forming step, a master mold removing step of peeling and removing the electroformed master mold 15 from the conductor pattern 1 and the molded body 2 is included. In this way, since the electroforming master mold 15 is peeled off and removed in the final step after passing through the barrier layer forming step, during the manufacturing process of the package substrate, the electrical conductor can be manufactured while being reliably supported by the electroforming master mold 15 The pattern 1 and the molded body 2 can manufacture a package substrate in a stable state.

Retain the lower resist 18 and the upper formed in the primary and secondary electroforming steps The resist 21, and the two resists 18, 21 also serve as the molded body 2 in which the conductor pattern 1 is buried and held. In this way, it is not necessary to separately form the molded body 2, and the step of forming the molded body 2 can be omitted, and accordingly the manufacturing cost of the package substrate can be further reduced.

In the above-described semiconductor device on which the semiconductor element S is mounted on the package substrate, after the external electrode 4 included in the conductor pattern 1 and the electrode 31 included in the semiconductor element S are electrically connected, the semiconductor element S is sealed with the sealing body 30. In this way, during the connection operation between the external electrode 4 and the electrode 31 and the sealing operation by the sealing body 30, even if the package substrate is deformed by bending or twisting, the conductor pattern 1 will not be removed from the molded body 2 The detachment or positional deviation can easily perform the operation of the package substrate during the above-mentioned work. Furthermore, it is possible to reduce the defective product formation rate at the time of manufacturing the semiconductor device, and to improve the productivity of the semiconductor device.

1‧‧‧Conductor pattern

3‧‧‧Molded body

4‧‧‧External electrode

6‧‧‧Lower conductive layer (first electroformed layer)

7‧‧‧ Upper conductive layer (second electroformed layer)

11‧‧‧ Barrier layer

15‧‧‧Electric casting master

18‧‧‧ Lower resist (first resist)

21‧‧‧upper resist (second resist)

22‧‧‧Moulded resin

26‧‧‧ Solder resist ink layer

30‧‧‧sealing body

31‧‧‧electrode

S‧‧‧Semiconductor components

W‧‧‧Metal wire

FIG. 1 is a longitudinal sectional side view of a package substrate according to a first embodiment of the present invention.

2 is a partial plan view of the package substrate of the first embodiment.

3 is an explanatory diagram showing a primary electroforming step in the method for manufacturing a package substrate of the first embodiment.

4 is an explanatory diagram showing a secondary electroforming step in the method of manufacturing a package substrate of the first embodiment.

5 is an explanatory diagram showing a molding step and a master mold removal step in the method of manufacturing a package substrate of the first embodiment.

FIG. 6 shows a step of forming a barrier layer in the manufacturing step of the package substrate of the first embodiment Illustration.

7 is a longitudinal sectional side view of the semiconductor device of the first embodiment.

8 is a perspective view of the semiconductor device of the first embodiment.

9 is an explanatory diagram showing the method of manufacturing the semiconductor device according to the first embodiment.

10 is a partial plan view for explaining the method of manufacturing the semiconductor device of the first embodiment.

11 is a longitudinal sectional side view of a package substrate according to a second embodiment of the present invention.

FIG. 12 is an explanatory diagram showing a master mold removing step and a barrier layer forming step in the method of manufacturing a package substrate according to the second embodiment.

13 is a longitudinal side view of a package substrate according to a third embodiment of the present invention.

14 is an explanatory diagram showing a primary electroforming step in the method of manufacturing a package substrate of the third embodiment.

15 is an explanatory diagram showing a secondary electroforming step in the method of manufacturing a package substrate of the third embodiment.

16 is an explanatory diagram showing a molding step, a barrier layer forming step, and a master mold removing step in the method of manufacturing a package substrate of the third embodiment.

17 is a longitudinal sectional side view of a package substrate according to a fourth embodiment of the present invention.

FIG. 18 is an explanatory diagram showing the steps of forming the barrier layer and the removal of the master mold in the method of manufacturing the package substrate of the fourth embodiment.

(First embodiment)

1 to 10 show the package substrate of the present invention, its manufacturing method, and semiconductor device The first embodiment. As shown in FIGS. 1 and 2, the conductive pattern 1 of the package substrate is buried and held in the molded body 2, and the conductive pattern 1 is formed by electroforming and exposed above and below the molded body 2. The conductor pattern 1 is composed of a mounting pad 3 on which the semiconductor element S is mounted, and six external electrodes 4 arranged on both sides of the mounting pad 3 as a set of unit patterns. The molded body 2 is arranged in a matrix Multiple unit patterns.

The conductor pattern 1 is composed of a first electroformed layer (lower conductive layer) 6 formed on a conductive electroforming master mold 15 such as stainless steel or aluminum during electroforming, and a first electroformed layer formed on the first electroformed layer 6 The second electroformed layer (upper conductive layer) 7 is configured, and the outer shape of the first electroformed layer 6 is formed to be larger than the outer shape of the second electroformed layer 7. The second electroformed layer 7 is composed of a base layer 8 and a surface layer 9 that attempts to improve the adhesion of solder or metal wires W. The base layer 8 of the first electroformed layer 6 and the second electroformed layer 7 can be formed of nickel, nickel-cobalt alloy, or copper. In addition, the surface layer 9 of the second electroformed layer 7 can be formed of a precious metal, and can be formed of gold, gold-palladium alloy, or the like. The second electroformed layer 7 constitutes the mounting surface of the semiconductor element S on the mounting pad 3 and the external electrode 4.

When peeling occurs at the boundary surface between the conductor pattern 1 embedded in the molded body 2 and the molded body 2, the conductive pattern 1 is blocked by the molded body 2 due to the first electroformed layer 6, and It does not move toward the upper surface side of the second electroformed layer 7 exposed (toward the upper side as viewed in FIG. 1 ). However, since there is no means for restricting the movement of the conductor pattern 1 toward the lower side of the exposed surface of the first electroformed layer 6 (downwardly as viewed in FIG. 1 ), the conductor pattern 1 falls off from the molded body 2 or there is a position Worry about deviation. In this way, in order to prevent the conductor pattern 1 from falling off from the molded body 2 or from being displaced, a barrier layer 11 is formed on the lower surface of the molded body 2.

The barrier layer 11 is formed to cover a part of the first electroformed layer 6 exposed from the molded body 2. Specifically, a window 12 exposing the first electroformed layer 6 is opened in the barrier layer 11, The window 12 is formed to be smaller than the outer shape of the first electroformed layer 6 constituting the mounting pad 3 and the external electrode 4. As a result, the outer edge of the first electroformed layer 6 is blocked by the peripheral edge of the window 12 of the barrier layer 11, and the movement of the conductive pattern 1 in the direction of separation (falling off) from the molded body 2 is restricted. The barrier layer 11 is formed by a photolithography method using a photo-curable solder resist ink layer 26. On the surface of the first electroformed layer 6 opposed to the window 12, a surface layer 13 that attempts to improve the adhesion of solder or metal wires W is formed. The surface layer 13 can be formed of a precious metal, and can be formed of gold, gold-palladium alloy, or the like.

3 to 6 show a method of manufacturing the package substrate of this embodiment. The package substrate passes through the primary electroforming steps shown in FIGS. 3(a) to 3(d), the secondary electroforming steps shown in FIGS. 4(a) to 4(d), and FIGS. 5(a) to 5 It is formed by the molding process shown in (b), the master mold removal process shown in FIG. 5(c), and the barrier layer forming process shown in FIGS. 6(a) to 6(c). The manufacturing of the package substrate is performed using a conductive flat-plate stainless steel electroforming master mold 15.

In one electroforming step, as shown in FIG. 3(a), a first photoresist layer 16 is formed on the electroforming mother mold 15, and then on the first photoresist layer 16, it is placed and closely attached to the The first pattern film 17 of the light transmission hole corresponding to the first electroformed layer 6. Next, ultraviolet light is irradiated with an ultraviolet light lamp to perform exposure, and each process of development and drying is performed to dissolve and remove the unexposed portion, thereby forming the first and the third on the electroforming master mold 15 as shown in FIG. 3(b). A first resist (lower resist) 18 corresponding to an electroformed layer 6. In addition, as the first photoresist layer 16, a photoresist layer formed by laminating one or more alkali-developed and negatively developed photosensitive resist dry films by hot pressing against a predetermined height is used. For example, a general-purpose resist using phenol resin as a base polymer can be used.

Next, as shown in FIG. 3(c), a first electroformed layer is formed by electrodepositing nickel as an electroformed metal on the electroformed master mold 15 other than the first resist 18 by electroforming 6. After forming the first electroformed layer 6, the surface of the first resist 18 and the first electroformed layer 6 By polishing the surface, the surfaces of the first resist 18 and the first electroformed layer 6 become one surface as shown in FIG. 3(d).

In the secondary electroforming step, as shown in FIG. 4(a), a second photoresist layer 19 is formed on the first electroformed layer 6 and the first resist 18, and then on the second photoresist layer 19 Above, the second pattern film 20 having light-transmitting holes corresponding to the second electroformed layer 7 is placed and closely adhered to, wherein the outer shape of the second electroformed layer 7 is smaller than that of the first electroformed layer 6 . Next, the ultraviolet light is irradiated with ultraviolet light to expose, and each process of development and drying is carried out to dissolve and remove the unexposed portion, thereby forming the first electroformed layer 6 and the first as shown in FIG. 4(b). A second resist (upper resist) 21 corresponding to the second electroformed layer 7 is formed on the resist 18. In addition, the second photoresist layer 19 is the same as the first photoresist layer 16, and is formed by laminating one or more alkali-developed and negatively-developed photosensitive resist dry films by hot pressing with a predetermined height. Photoresist layer. For example, a general-purpose resist using phenol resin as a base polymer can be used.

Next, as shown in FIG. 4(c), by electroforming nickel as an electroforming metal on the first electroforming layer 6 other than the second resist 21, a second electrode is formed by lamination The base layer 8 of the casting layer 7. Thereafter, by polishing the surfaces of the second resist 21 and the base layer 8, as shown in FIG. 4( d ), the surfaces of the second resist 21 and the second electroformed layer 7 become one surface. In addition, in the case where the thickness dimension of the base layer 8 is smaller than the thickness dimension of the second resist 21, the polishing step can also be omitted. After the polishing step, gold is electrodeposited on the base layer 8 to form a surface layer 9 of the second electroformed layer 7 (see FIG. 1 ).

In the molding step, as shown in FIG. 5(a), the first resist 18 and the second resist 21 formed in the primary and secondary electroforming steps are dissolved and removed, and both are removed 18, The space after 21 is filled with molding resin 22 made of softened thermoplastic epoxy resin, and then made It is hardened to form the molded body 2 as shown in FIG. 5(b). When the molding resin 22 is filled, a metal mold is arranged so as to face the electroforming mother mold 15 and the space after removing both resists 18 and 21 is used as a cavity, and then the molding resin is filled between the conductor patterns 1 22 and harden it, but this is not shown. A Teflon sheet is attached to the contact surface of the metal mold that contacts the molding resin 22. Thereby, when the metal mold is removed, it is possible to prevent the mold resin 22 from adhering to the metal mold. In addition, the upper surface of the molded body 2 and the upper surface of the second electroformed layer 7 can be formed as one surface, and the molding resin 22 can be prevented from hardening on the upper surface of the second electroformed layer 7. If the molding resin 22 is attached to the upper surface of the second electroformed layer 7, the surface of the molded body 2 and the second electroformed layer 7 may be removed by grinding after hardening.

In the master mold removal step, the electroformed master mold 15 is forcibly peeled off from the conductor pattern 1 (first electroformed layer 6) and the molded body 2 (molded resin 22). Thereby, a package substrate in which the conductor pattern 1 shown in FIG. 5(c) is buried and held in the molded body 2 is obtained.

In the barrier layer forming step, as shown in FIG. 6(a), the packaging substrate obtained in the master mold removal step is turned upside down to form a solder resist ink layer on the first electroformed layer 6 and the molded body 2 26, and a third pattern film 27 is placed on and closely attached to the solder resist ink layer 26, and the third pattern film 27 has a window 12 corresponding to the outer shape of the first electroformed layer 6 which is slightly smaller than the outer shape Light hole. Next, the ultraviolet light is irradiated with an ultraviolet light to expose, and each process of development and drying is carried out to dissolve and remove the unexposed portion, thereby forming the first electroforming layer 6 and molding as shown in FIG. 6(b) A barrier layer 11 is formed on the body 2, and a window 12 is formed on the barrier layer 11. In addition, the solder resist ink layer 26 is a solder resist ink layer formed by laminating one or more alkali-developed dry films of photosensitive solder resist with negative development by hot pressing against a predetermined height. Finally, the exposed surface of the first electroformed layer 6 opposite to the window 12 is formed of gold by electroless plating The surface layer 13 is then inverted upside down to obtain a package substrate provided with the barrier layer 11 shown in FIG. 6(c).

7 and 8 show a semiconductor device in which a semiconductor element S is mounted on a package substrate. As shown in FIG. 7, the semiconductor device is formed by sealing the semiconductor element S mounted on the unit pattern of the conductor pattern 1 included in the package substrate with a sealing body 30 made of epoxy resin. The semiconductor element S is mounted on the surface of the package substrate on the opposite side of the barrier layer 11 and is adhesively fixed to the mounting pad 3, and the electrode 31 and the external electrode formed on the upper surface of the semiconductor element S are formed with a metal wire W 4 Electrically connected to be mounted on the package substrate. The sealing body 30 hermetically seals the semiconductor elements S, the metal wires W, and the like. The entire semiconductor device is formed in a quadrangular block shape, and the surface formed on the surface of the first electroformed layer 6 is exposed from the window 12 opposite to the bottom surface side. Layer 13 (refer to FIG. 8).

9 and 10 show a method of manufacturing the semiconductor device of this embodiment. As shown in FIG. 9(a), the semiconductor element S is bonded and mounted on the mounting pad 3, and then as shown in FIG. 9(b), the metal element W made of gold is used to mount the semiconductor element S on the semiconductor element S using a wire bonding device Electrode 31 and the corresponding external electrode 4 are connected. At this time, since the surface layer 9 improves the adhesiveness of the metal wire W, it is possible to reduce the defective product formation rate during the manufacturing process. In addition, the connection between the electrode 31 and the external electrode 4 is not limited to wire bonding using the metal wire W, and can be electrically connected by flip chip bonding using solder or the like.

Next, as shown in FIG. 9(c), the mounting portion of the semiconductor element S on the packaging substrate is sealed with a thermoplastic epoxy resin, thereby forming a sealing body 30 on the packaging substrate. Specifically, using the package substrate as a master mold, a mold metal mold (male mold) is mounted on the upper side of the package substrate to form a cavity, and the softened thermoplastic epoxy resin is pressed into the cavity and hardened. by In this way, an aggregate of semiconductor devices in a form in which a plurality of semiconductor elements S are sealed by the sealing body 30 is obtained, wherein the semiconductor elements S are mounted with a unit pattern formed in a matrix on the package substrate. Finally, the semiconductor device shown in FIG. 7 is obtained by cutting along a dividing line indicated by a chain line in FIG. 9(c) and FIG. 10.

As described above, in the package substrate of the present embodiment, since the barrier layer 11 is formed to cover the outer edge portion of the first electroformed layer 6 exposed from the molded body 2, the peripheral edge portion of the window 12 can be used The barrier layer 11 blocks the first electroformed layer 6 and restricts the movement of the conductor pattern 1.

Since the outer shape of the first electroformed layer 6 is formed to be larger than the outer shape of the second electroformed layer 7, and the barrier layer 11 is formed on the lower surface of the molded body 2, the conductive body that is not restricted by the molded body 2 is moved The movement of the volume pattern 1 to the lower surface side where the first electroformed layer 6 is exposed can be restricted by the barrier layer 11. Therefore, the barrier layer 11 can prevent the conductor pattern 1 from falling off from the molded body 2. Furthermore, when the second electroformed layer 7 is formed by electroforming, only the electroformed layer on the first electroformed layer 6 of the electrode on the cathode side can be grown. Compared with the case of the second electroformed layer 7 having a large external shape, the consumption of the metal electrode on the anode side when forming the second electroformed layer 7 can be reduced, and the electroforming time can be shortened, and accordingly the package can be reduced. The manufacturing cost of the substrate.

Further, in the method for manufacturing a package substrate of this embodiment, in the molding step after the secondary electroforming step, the first resist 18 and the second resist formed in the primary and secondary electroforming steps are removed The body 21 is filled with the softened molding resin 22 after removing the spaces of the two resists 18 and 21, and then hardened, thereby forming the molded body 2 in which the conductor pattern 1 is buried and held. According to this manufacturing method, by using a mold having desired mechanical strength and material properties The molded body 2 is formed by forming the resin 22, and the conductive body pattern 1 can be embedded and held by the molded body 2 most suitable for the use of the package substrate. Therefore, when heat resistance is required for the package substrate, for example, by using polybutylene terephthalate, polyethylene, or the like for the mold resin 22, a package substrate excellent in heat resistance can be obtained. In addition, by setting the molding resin 22 to the same or the same system of resin material as the sealing body 30 that seals the semiconductor element S mounted on the package substrate, the fixed state between the molding body 2 and the sealing body 30 can be stabilized In addition, since the thermal expansion coefficients of the two 2 and 30 can be made substantially the same, peeling can be prevented at the boundary surface between the molded body 2 and the sealing body 30.

Moreover, the outer shape of the first electroformed layer 6 is formed to be larger than the outer shape of the second electroformed layer 7, and between the molding step and the barrier layer forming step, it is peeled off from the conductor pattern 1 and the molded body 2 and The master mold removing step of removing the electroformed master mold 15. According to this manufacturing method, since the conductor pattern 1 and the molded body 2 are formed on the electroformed master mold 15, the exposed surface of the first electroformed layer 6 and the molded body 2 can be exposed after the electroformed master mold 15 is removed The following becomes a smooth face. Therefore, as a pre-treatment for performing the barrier layer forming step, it is not necessary to perform a polishing treatment or the like, and the manufacturing cost of the package substrate can be reduced.

(Second Embodiment) FIGS. 11 and 12 show a second embodiment of the package substrate of the present invention. This embodiment is different from the first embodiment in that the molding step in the manufacturing process of the package substrate is omitted. That is, as shown in FIG. 11, the first resist 18 and the second resist 21 used to form the first electroformed layer 6 and the second electroformed layer 7 are used to bury and hold the conductor pattern 1的模体2。 The molded body 2. In addition, as shown in FIG. 12( a ), on the upper surface of the electroformed master mold 15, in order to facilitate the peeling in the master mold removal step described later, a thin-film nickel layer 15 a and a copper layer 15 b are laminated in advance. Others are the same as the first embodiment, so that the same components are marked Note the same symbols and omit their description.

The package substrate of this embodiment is formed in FIGS. 4(a) to 4(a) through a master mold removal step shown in FIG. 12(b) and a barrier layer forming step shown in FIGS. 12(c) to 12(e). d) The package substrate in the manufacturing process after the completion of the secondary electroforming step shown (see FIG. 12(a)). In the master mold removal step, after the electroforming master mold 15 and the nickel layer 15a previously formed on the electrocast master mold 15 are forcibly peeled off, the copper layer 15b is removed (etched). Thereby, a package substrate in which the conductor pattern 1 shown in FIG. 12(b) is buried and held in the molded body 2 composed of the first resist 18 and the second resist 21 is obtained. In this way, by finally removing the copper layer 15b, it is possible to facilitate the peeling of the electroformed master mold 15 in the master mold removal step, and it is possible to suppress breakage of both resists 18 and 21.

In the barrier layer forming step, as shown in FIG. 12(c), the packaging substrate obtained in the master mold removing step is turned upside down to form a solder mask on the first electroformed layer 6 and the first resist 18 An ink layer 26, and a third pattern film 27 is placed on and closely attached to the solder resist ink layer 26, and the third pattern film 27 has a window that is one circle smaller than the outer shape of the first electroformed layer 6 12 corresponds to the light transmission hole. Next, the ultraviolet light is irradiated with an ultraviolet light to expose, and each process of development and drying is carried out to dissolve and remove the unexposed portion, thereby, as shown in FIG. 12(d), the first electroformed layer 6 and the first A barrier layer 11 is formed on the resist 18, and a window 12 is formed on the barrier layer 11. Finally, on the surface of the first electroformed layer 6 opposite to the window 12, a surface layer 13 made of gold was formed by electroless plating, and turned upside down, thereby obtaining a barrier as shown in FIG. 12(e) The package substrate of layer 11. The semiconductor device on which the semiconductor element S is mounted on the package substrate of this embodiment is the same as the first embodiment, and therefore its description is omitted.

As described above, in the package substrate of this embodiment, the first resist Since the 18 and the second resist 21 also serve as the molded body 2, the two resists 18 and 21 can be used as the molded body 2 in which the conductor pattern 1 is buried and held. Therefore, it is possible to obtain a package substrate provided with the barrier layer 11 without separately embedding and holding the conductor pattern 1 in the molded body 2. Furthermore, in the method of manufacturing a package substrate of this embodiment, the first resist 18 and the second resist 21 formed in the primary and secondary electroforming steps are retained, and the two resists 18 and 21 also serve as embedding By holding the molded body 2 of the conductor pattern 1, the step of forming the molded body 2 can be omitted, and accordingly the manufacturing cost of the package substrate can be reduced.

In the second embodiment described above, the negative photoresist dry film is used for the first photoresist 16 and the second photoresist layers 19, but it can be improved by using the dry film for negative photoresist soldering. The structural strength of the molded body 2 composed of the first resist 18 and the second resist 21 can effectively prevent the molded body 2 from being damaged.

In this embodiment, since the surface layer 9 is formed after the step of grinding the surface of the second resist 21 and the base layer 8 of the second electroformed layer 7, as shown in FIG. 11, the surface layer 9 is molded from The state in which the upper surface of the body 2 protrudes is formed. In addition, when the thickness dimension of the base layer 8 is formed to be smaller than the thickness dimension of the second resist 21 and the polishing step is omitted, the upper surface of the surface layer 9 can be taken as the same surface as the upper surface of the molded body 2, Alternatively, it may be located below the upper surface of the molded body 2.

(Third Embodiment) FIGS. 13 to 16 show a third embodiment of the package substrate of the present invention. In the present embodiment, the second electroformed layer having a larger external shape is formed in that the size relationship between the outer shapes of the first electroformed layer 6 and the second electroformed layer 7 is oppositely formed, and concomitantly with this. The 7-side molded body 2 is different from the first embodiment in that the barrier layer 11 is formed on the upper surface. The outer shape of the second electroformed layer 7 constituting the conductor pattern 1 is formed The outer shape of the electroformed layer 6 is large, and the first electroformed layer 6 is composed of a base layer 8 and a surface layer 9. A surface layer 13 is formed on the surface of the second electroformed layer 7 opposed to the window 12 opening to the barrier layer 11. In the present embodiment, the first electroformed layer 6 of the conductor pattern 1 constitutes the mounting surface side of the semiconductor element S of the mounting pad 3 and the external electrode 4. Others are the same as in the first embodiment, so that the same components are denoted by the same symbols and their descriptions are omitted.

14 to 16 show a method of manufacturing the package substrate of this embodiment. The package substrate passes through the primary electroforming steps shown in FIGS. 14(a) to 14(d), the secondary electroforming steps shown in FIGS. 15(a) to 15(d), FIGS. 16(a) and 16 It is formed by the molding step shown in (b), the barrier layer forming step shown in FIGS. 16(c) and 16(d), and the master mold removal step shown in FIG. 16(e). In one electroforming step, as shown in FIG. 14(a), the first photoresist 16 is formed on the top of the electroforming master mold 15, and then the first pattern is placed on the first photoresist layer 16 and closely adheres to the first pattern Film 17, the first pattern film 17 has a light transmission hole corresponding to the first electroformed layer 6. Next, ultraviolet light is irradiated with an ultraviolet light lamp to perform exposure, and each process of development and drying is carried out to dissolve and remove the unexposed part, thereby forming the first and third A first resist 18 corresponding to an electroformed layer 6.

Next, as shown in FIG. 14(c), gold is electrodeposited on the electroforming master mold 15 other than the first resist 18 to form the surface layer 9 of the first electroforming layer 6, and by using electroforming In this method, nickel, which is an electroformed metal, is electrodeposited on the surface layer 9, and the base layer 8 is laminated to form a first electroformed layer 6 (see FIG. 13). After forming the first electroformed layer 6, by grinding the surfaces of the first resist 18 and the first electroformed layer 6 (base layer 8), as shown in FIG. 14(d), the first resist 18 and The surface of the first electroformed layer 6 becomes one surface.

In the secondary electroforming step, as shown in FIG. 15(a), in the first electroforming layer 6 And a second photoresist layer 19 is formed on the top of the first resist 18, and then a second pattern film 20 is placed on the second photoresist layer 19 and closely adhered to the second pattern film 20 The second electroformed layer 7 having a large outer shape of the first electroformed layer 6 corresponds to the light transmission hole. Next, ultraviolet light is irradiated with an ultraviolet light lamp to perform exposure, and each process of development and drying is carried out to dissolve and remove the unexposed portion, thereby forming a layer on the first resist 18 as shown in FIG. 15(b). The second resist 21 corresponding to the second electroformed layer 7.

Next, as shown in FIG. 15(c), nickel as an electroformed metal is electrodeposited on the first electroformed layer 6 and the first resist 18 other than the second resist 21 by using an electroforming method, To form the second electroformed layer 7. After forming the second electroformed layer 7, the surfaces of the second resist 21 and the second electroformed layer 7 are polished to make the second resist 21 and the second electroformed as shown in FIG. 15(d) The surface of the layer 7 becomes one surface.

In the molding step, as shown in FIG. 16(a), the first resist 18 and the second resist 21 formed in the primary and secondary electroforming steps are dissolved and removed, and both are removed 18, The space after 21 is filled with a molded resin 22 made of a softened thermoplastic epoxy resin, and then hardened to form a molded body 2 as shown in FIG. 16(b).

In the barrier layer forming step, as shown in FIG. 16(c), a solder resist ink layer 26 is formed on the second electroformed layer 7 and the molded body 2, and then placed on the solder resist ink layer 26 and Adjacent to the third pattern film 27, the third pattern film 27 has a light transmission hole corresponding to the window 12 whose outer shape is smaller than that of the second electroformed layer 7 by one turn. Next, the ultraviolet light is irradiated with an ultraviolet light to expose, and each process of development and drying is carried out to dissolve and remove the unexposed portion, thereby forming the second electroformed layer 7 and molding as shown in FIG. 16(d) A barrier layer 11 is formed on the body 2, and a window 12 is formed on the barrier layer 11. After that, on the surface of the second electroformed layer 7 opposite to the window 12, The surface layer 13 made of gold is formed by electroless plating.

In the master mold removal step, the electroformed master mold 15 is forcibly peeled off from the conductor pattern 1 (second electroformed layer 7) and the molded body 2 (molded resin 22) to remove ) Shows the packaging substrate of the barrier layer 11.

In the manufacturing of the semiconductor device of the present embodiment, the packaging substrate is turned upside down, the first electroformed layer 6 is positioned on the top, and then the semiconductor element S is mounted on the mounting pad 3, and the metal wire W made of gold is used. The electrode 31 and the corresponding external electrode 4 are connected by a wire bonding device. In addition, the mounting portion of the semiconductor element 2 on the package substrate is sealed with a thermoplastic epoxy resin, thereby forming a sealing body 30 on the package substrate.

As described above, in the package substrate of the present embodiment, since the barrier layer 11 is formed to cover the outer edge of the second electroformed layer 7 exposed from the molded body 2, the peripheral edge of the window 12 can be used The barrier layer 11 blocks the second electroformed layer 7 and restricts the movement of the conductor pattern 1.

Since the outer shape of the second electroformed layer 7 is formed to be larger than the outer shape of the first electroformed layer 6, and the barrier layer 11 is formed on the upper surface of the molded body 2, the conductive body that is not restricted by the molded body 2 is moved The movement of the body pattern 1 to the upper surface side where the second electroformed layer 7 is exposed can be restricted by the barrier layer 11, so that the barrier layer 11 can prevent the conductor pattern 1 from falling out of the molded body 2.

In addition, the method of manufacturing the package substrate of the present embodiment includes the step of removing the electroforming master mold 15 from the conductor pattern 1 and the molded body 2 after the barrier layer forming step and removing the electroforming master mold 15. According to this manufacturing method, since the electroforming master mold 15 is peeled off and removed in the final step after passing through the barrier layer forming step, it is possible to reliably support the electroforming master mold 15 in the state of manufacturing the package substrate The conductor pattern 1 and the molded body 2 are manufactured so that It is enough to manufacture a package substrate in a stable state.

(Fourth Embodiment) FIGS. 17 and 18 show a fourth embodiment of the package substrate of the present invention. This embodiment is different from the third embodiment in that the molding step in the manufacturing process of the package substrate is omitted. That is, as shown in FIG. 18, the first resist 18 and the second resist 21 used to form the first electroformed layer 6 and the second electroformed layer 7 are used to bury and hold the conductor pattern 1的模体2。 The molded body 2. In addition, in the manufacture of the package substrate, as in the second embodiment, the electroformed master mold 15 having the thin-film nickel layer 15 a and the copper layer 15 b on the upper area layer is used. Others are the same as the third embodiment, so that the same components are denoted by the same symbols and their descriptions are omitted.

After the secondary electroforming steps shown in FIG. 15(a) to FIG. 15(d) are completed, the package substrate of this embodiment passes through the barrier layer forming steps and diagrams shown in FIGS. 18(a) and 18(b). It is formed by the master mold removal step shown in 18(c). In the barrier layer forming step, as shown in FIG. 18(a), a solder resist ink layer 26 is formed on the second electroformed layer 7 and the second resist 21, and then the solder resist ink layer 26 is loaded on The third pattern film 27 is placed close to the third pattern film 27, and the third pattern film 27 has a light transmission hole corresponding to the window 12 whose outer shape is smaller than that of the second electroformed layer 7 by one turn. Next, ultraviolet light is irradiated with an ultraviolet light lamp to perform exposure, and each process of development and drying is performed to dissolve and remove the unexposed portion, thereby forming the second electroformed layer 7 and the second as shown in FIG. 18(b) A barrier layer 11 is formed on the resist 21, and a window 12 is formed on the barrier layer 11. After that, a surface layer 13 made of gold is formed on the surface of the second electroformed layer 7 facing the window 12 through electroless plating.

In the master mold removal step, after the electroforming master mold 15 and the nickel layer 15a previously formed on the electrocast master mold 15 are forcibly peeled off, the copper layer 15b is removed (etched), thereby obtaining The package substrate of the barrier layer 11 shown in 18(c).

In the above-described embodiment, the negative photoresist dry film is used for the first photoresist layer 16 and the second photoresist layer 19, but it is the same as the previous second embodiment, by using the negative photoresist The soldered dry film can increase the structural strength of the molded body 2 composed of the first resist 18 and the second resist 21, and can effectively prevent the molded body 2 from being damaged.

The semiconductor device on which the semiconductor element S is mounted on the package substrate of this embodiment is the same as that of the third embodiment, and its description is omitted.

As described above, in the package substrates of the above-described embodiments, one of the outer shapes of the first electroformed layer 6 and the second electroformed layer 7 constituting the conductor pattern 1 in plan view is formed larger than the other. On either outer surface of the molded body 2, a barrier layer 11 is formed to prevent the conductor pattern 1 from falling off from the molded body 2, so that the package substrate is deformed such as deflection, torsion, etc. even during transportation and mounting of the semiconductor element In the case of, the barrier layer 11 can prevent the conductor pattern 1 from falling out of the molded body 2. Therefore, it is possible to obtain a package substrate in which the conductor pattern 1 is eliminated from the molded body 2 or the positional deviation occurs, and the operation at the time of transportation or the mounting of the semiconductor element can be easily performed. In addition, according to the provision of the barrier layer 11, the resistance against deformation such as deflection and torsion is increased, so that the deformation of the package substrate can be suppressed.

Since the barrier layer 11 is formed of the photocurable solder resist film layer 26, the barrier layer 11 of a desired pattern can be easily formed by photolithography, and the manufacturing cost of the package substrate provided with the barrier layer 11 can be further reduced. In addition, since the solder resist ink layer 26 has a higher structural strength than a general-purpose photoresist using a phenol resin as a base polymer, it is possible to suppress breakage of the barrier layer 11 such as cracks and notches, and to effectively prevent the conductor pattern 1 Drop off from the molded body 2, or a positional deviation occurs.

In addition, the method for manufacturing a package substrate of each of the above embodiments includes The primary electroforming step, the secondary electroforming step, and the barrier layer forming step form a package substrate provided with the barrier layer 11. In addition, in the barrier layer forming step, the solder resist ink layer 26 is formed on any outer surface of the molded body 2, and the barrier layer 11 of a predetermined pattern is formed by photolithography. According to this manufacturing method, each process such as exposure, development, and drying can be performed using the same equipment as the primary and secondary electroforming barriers, and the barrier layer 11 of a predetermined pattern can be easily formed, so that the package substrate provided with the barrier layer 11 can be reduced Manufacturing costs.

In addition, in the semiconductor device in which the semiconductor element S is mounted on the package substrate of each of the embodiments described above, the external electrode 4 included in the conductor pattern 1 and the electrode 31 included in the semiconductor element S are connected by the metal wire W, and then sealed The body 30 seals the semiconductor element S and the metal wire W. According to this semiconductor device, in the connection operation between the external electrode 4 and the electrode 31 by the metal wire W and the sealing operation by the sealing body 30, if the package substrate is deformed by bending or twisting, the conductor pattern 1 is also The package substrate during the above-mentioned operation can be easily performed without falling off from the molded body 2 or being displaced. In addition, it is possible to reduce the defective product formation rate at the time of manufacturing the semiconductor device, and to improve the productivity of the semiconductor device.

In the first and third embodiments described above, similar to the second and fourth embodiments, the package substrate can be manufactured using the electroforming master mold 15 in which the thin-film nickel layer 15a and the copper layer 15b are laminated. In this case, the peelability of the electroformed master mold 15 during the master mold removal step can be improved. Furthermore, in the second and fourth embodiments, similar to the first and third embodiments, the package substrate can be manufactured using the electroformed master mold 15 that does not include the nickel layer 15a and the copper layer 15b.

”形狀、局部圓環狀、或者分割為多個，總之，若不以較大型成的一側的外形形狀突出，則能夠採用任意的形狀。導電體圖案1也可以在具備安裝墊3以及外部電極4以外，還具備片狀引線(tab lead)、引線腳(lead pin)等。構成第一電鑄層6和第二電鑄層7的金屬材料、構成模制樹脂22和密封體30的樹脂材料、構成第一光阻層16和第二光阻層19、以及防焊油墨層26的基礎聚合物的樹脂材料等不限定於上述實施方式中舉出的材料。並且，模制體2也可以使用防焊油墨，並且，除樹脂材料以外能夠由陶瓷等具有介電性的材料形成。窗12的開口形狀不限定於上述實施方式中舉出的形狀，能夠阻止導電體圖案1的脫落即可。半導體元件S也能夠構裝在封裝基板的形成有阻隔層11的一面側。 In the above embodiments, the conductor pattern 1 is formed by electroforming, but it can be formed by etching. The outer shapes of the first electroformed layer 6 and the second electroformed layer 7 are each formed as a flat plate-shaped layer, but the outer shape of the electroformed layer on the smaller side may be a four-frame shape or a round frame shape ,"

"The shape, partial ring shape, or division into multiples. In short, any shape can be adopted without protruding from the outer shape of the larger side. The conductor pattern 1 may be provided with the mounting pad 3 and the outside. In addition to the electrode 4, tab leads, lead pins, etc. are provided. The metal material constituting the first electroformed layer 6 and the second electroformed layer 7, the mold resin 22 and the sealing body 30 The resin material, the resin material that constitutes the base polymer of the first photoresist layer 16 and the second photoresist layer 19, and the solder resist ink layer 26 are not limited to the materials mentioned in the above embodiment. Furthermore, the molded body 2 Solder resist ink can also be used, and it can be formed of a dielectric material such as ceramics other than the resin material. The opening shape of the window 12 is not limited to the shape mentioned in the above embodiment, and can prevent the conductor pattern 1 from coming off The semiconductor element S can also be mounted on the side of the package substrate on which the barrier layer 11 is formed.

1‧‧‧Conductor pattern

2‧‧‧Molded body

3‧‧‧Installation pad

4‧‧‧External electrode

6‧‧‧Lower conductive layer

7‧‧‧ Upper conductive layer

8‧‧‧ grassroots

9‧‧‧Surface layer

11‧‧‧ Barrier layer

12‧‧‧window

Claims (17)

A packaging substrate in which a conductor pattern (1) is buried and held in a molded body (2) with its upper and lower surfaces exposed; characterized in that the conductor pattern (1) includes a mounting pad (3) and external electrodes (4), and is composed of a lower conductive layer (6) and an upper conductive layer (7) formed on the lower conductive layer (6); the outer shape of the lower conductive layer (6) and the upper conductive layer (7) when viewed from above Either one is larger than the other; on either side of the molded body (2), a barrier layer (11) is formed to prevent the conductor pattern (1) from falling off the molded body (2); A surface layer (13) is formed on the surface of the package substrate where the barrier layer (11) is exposed. The package substrate as described in item 1 of the patent application scope, wherein the barrier layer (11) is formed as a lower conductive layer (6) or an upper conductive layer (1) of the conductive pattern (1) exposed from the molded body (2) 7) Part of the coverage. The package substrate as described in item 1 of the patent application scope, wherein the outer shape of the lower conductive layer (6) is formed to be larger than the outer shape of the upper conductive layer (7), and a barrier is formed under the molded body (2) Floor (11). The package substrate as described in item 2 of the patent application scope, wherein the outer shape of the lower conductive layer (6) is formed to be larger than the outer shape of the upper conductive layer (7), and a barrier is formed under the molded body (2) Floor (11). The package substrate as described in item 1 of the patent application scope, wherein the outer shape of the upper conductive layer (7) is formed larger than the outer shape of the lower conductive layer (6), A barrier layer (11) is formed on the molded body (2). The package substrate as described in item 2 of the patent application scope, wherein the outer shape of the upper conductive layer (7) is formed to be larger than the outer shape of the lower conductive layer (6), and a barrier is formed on the upper surface of the molded body (2) Floor (11). The package substrate as described in any one of items 1 to 6 of the patent application range, characterized in that the conductor pattern (1) is formed by electroforming to form a lower conductive layer (6) and an upper conductive layer (7) The lower resist (18) and the upper resist (21) also serve as a molded body (2) in which the conductor pattern (1) is buried and held. The package substrate as described in any one of claims 1 to 6, wherein the barrier layer (11) is formed of a photocurable solder resist ink layer (26). The package substrate as described in item 7 of the patent application range is characterized in that the barrier layer (11) is formed of a photocurable solder resist ink layer (26). The package substrate as described in item 1 of the patent application scope, wherein a surface layer (13) is formed on at least the surface of the mounting pad (3) exposed from the barrier layer (11). A method for manufacturing a packaging substrate, in which a conductive body formed by a lower conductive layer (6) and a build-up layer formed on the lower conductive layer (6) is embedded and held in a molded body (2) with a mounting pad (3) and an external electrode (4) The conductor pattern (1) composed of the layer (7) exposes the conductor pattern (1) on the upper and lower surfaces of the molded body (2), and is formed on either side of the upper or lower surface of the molded body (2) The barrier layer (11) from which the conductor pattern (1) is detached from the molded body (2), and the method of manufacturing the package substrate described above, characterized in that it includes: An electroforming step, in which a lower resist (18) is formed on the surface of a flat electroforming master mold (15), and an electroforming master mold (not covered by the lower resist (18)) 15) The lower conductive layer (6) is formed on the surface; and a secondary electroforming step in which an upper resistance is formed on the surface of the lower conductive layer (6) or the lower conductive layer (6) and the lower resist (18) Etching body (21), and forming an upper conductive layer (7) on the lower conductive layer (6) or the lower conductive layer (6) and the surface area layer of the lower resist (18) not covered by the upper resist (21) And a barrier layer forming step in which a barrier layer (11) is formed on either side of the upper or lower surface of the molded body (2) in which the conductor pattern (1) is buried and held, in the barrier layer forming step , Forming a photo-curable solder resist ink layer (26) on either the upper or lower side of the molded body (2), and applying a photolithography method to the lower conductive layer (6) exposed from the molded body (2) Alternatively, a barrier layer (11) is formed so as to cover a part of the exposed portion of the upper conductive layer (7), and a surface layer (13) is formed on the surface of the package substrate exposed from the barrier layer (11). The method for manufacturing a package substrate as described in item 11 of the patent application scope, in which a molding step is performed after the secondary electroforming step to form a molded body (2) in which the conductor pattern (1) is buried and held, in the mold In the manufacturing process, the lower resist and the upper resist (18, 21) formed in the primary and secondary electroforming steps are removed, and after removing the lower resist and the upper resist (18, 21) The space is filled with softened molding resin (22) and then hardened to form a molded body (2). The method for manufacturing a package substrate as described in item 12 of the patent application scope, wherein, in a plan view, the outer shape of the lower conductive layer (6) is formed to be higher than that of the upper conductive layer (7) The shape is large, and a barrier layer (11) is formed under the molded body (2), between the molding step and the barrier layer forming step, including peeling off from the conductor pattern (1) and the molded body (2) and The step of removing the electroforming master (15). The method for manufacturing a package substrate as described in item 11 or 12 of the patent application scope, in which the outer shape of the upper conductive layer (7) is formed to be larger than the outer shape of the lower conductive layer (6) when viewed from above A barrier layer (11) is formed on the molded body (2), including after the barrier layer forming step, peeling off and removing the mother of the electroforming master mold (15) from the conductor pattern (1) and the molded body (2) Mold removal step. The method for manufacturing a packaging substrate as described in item 11 of the patent application scope, in which the lower resist and the upper resist (18, 21) formed in the primary and secondary electroforming steps are retained, and the two resists (18, 21) Also serves as a molded body (2) to bury and hold the conductor pattern (1). The method for manufacturing a package substrate as described in item 11 of the patent application scope, wherein a surface layer (13) is formed on at least the surface of the mounting pad (3) exposed from the barrier layer (11). A semiconductor device comprising a semiconductor element (S) as described in any one of claims 1 to 10 of the patent application range. The semiconductor device is characterized in that the conductor pattern (1) is provided with an external electrode (4 ), after electrically connecting the electrode (31) and external electrode (4) included in the semiconductor element (S), the semiconductor element (S) is sealed with the sealing body (30).

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