JP2014022582A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Semiconductor device manufacturing method and semiconductor device Download PDF

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JP2014022582A
JP2014022582A JP2012160218A JP2012160218A JP2014022582A JP 2014022582 A JP2014022582 A JP 2014022582A JP 2012160218 A JP2012160218 A JP 2012160218A JP 2012160218 A JP2012160218 A JP 2012160218A JP 2014022582 A JP2014022582 A JP 2014022582A
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resist pattern
lead
layer
substrate
semiconductor device
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Hiroshi Nakagawa
宏史 中川
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Maxell Holdings Ltd
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Hitachi Maxell Ltd
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
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    • H01L2224/49171—Fan-out arrangements
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can form surface layers on necessary places on a die pad and leads with good accuracy and good efficiency; and provide a semiconductor device obtained by the manufacturing method.SOLUTION: A semiconductor device manufacturing method comprises: forming on one surface side of a substrate 20, a resist pattern layer 25 having resist bodies 25a corresponding to parts except formation places of leads 3; subsequently forming a lead part 13 on a surface of the substrate 20 exposed from the resist pattern layer 25; subsequently forming on the resist pattern layer 25 and on the lead part 13, a resist pattern layer 36 having resist bodies 36a corresponding to parts except a formation place of a surface layer 12; forming the leads 3 by forming the surface layer 12 by lamination on a part of the surface of the lead part 13, which is exposed from the resist pattern layer 36; subsequently removing the resist pattern layer 25 and the resist pattern layer 36 from the substrate 20; subsequently electrically connecting a semiconductor element 2 and the surface layer 12 of the leads 3; forming a resin encapsulated body 7 by molding the semiconductor element 2 and the leads 3 with an encapsulation resin 38; and subsequently removing the substrate 20.

Description

本発明は、底部に電極等の金属部が露出する状態でパッケージングされた半導体装置の製造法、及びその製造方法によって製造される半導体装置に関する。   The present invention relates to a method for manufacturing a semiconductor device packaged with a metal portion such as an electrode exposed at the bottom, and a semiconductor device manufactured by the manufacturing method.

ダイパッドやリードとなる金属部が形成された半導体装置用基板を準備し、この金属部上に半導体素子を搭載して配線等の処理後、半導体素子や配線のある金属部の表面側を封止樹脂で封止し、金属部が底部に一部露出した構成とされる半導体装置は、その高さを低くして省スペース化が図れる他、露出した金属部を通じて半導体素子で生じた熱を外部に放出でき、放熱の面で優れるといった特長を有しており、チップサイズなど超小型の半導体装置の分野で注目を集めている。こうした半導体装置は、主に、導電性を有する母型基板上にダイパッドやリードとなる金属部をメッキ（電鋳）により半導体装置の所望個数分まとめて形成し、半導体素子が搭載され配線等の処理を経た金属部の表面側を封止樹脂で封止した後、母型基板のみを除去し、一体にまとまった状態の多数の半導体装置を個別に切り分ける、といった製造過程を経て製造されており、このような半導体装置の製造方法としては、特許文献１に開示されている。   Prepare a semiconductor device substrate on which a metal part to be a die pad or lead is formed, mount a semiconductor element on this metal part, and after processing the wiring, seal the surface side of the metal part with the semiconductor element and wiring A semiconductor device that is sealed with resin and has a metal part partially exposed to the bottom can save space by reducing its height, and heat generated in the semiconductor element through the exposed metal part can be externally applied. It has a feature of being excellent in heat dissipation and attracting attention in the field of ultra-small semiconductor devices such as chip size. In such a semiconductor device, a metal part to be a die pad or a lead is formed by plating (electroforming) collectively on a conductive base substrate, and a semiconductor element is mounted and wiring or the like is mainly formed. It is manufactured through a manufacturing process such as sealing the surface side of the processed metal part with a sealing resin, then removing only the base substrate and individually cutting a large number of integrated semiconductor devices. A method for manufacturing such a semiconductor device is disclosed in Patent Document 1.

特開２００４−２１４２６５号公報JP 2004-214265 A

従来の半導体装置の製造方法は、前記特許文献に示される工程となっており、母型基板上への金属部の電鋳による形成にあたり、母型基板における金属部の非配置部分にレジスト層をあらかじめ形成して、金属部が適切な位置に形成されるようにしていた。この金属部には、電鋳に適したニッケル等の金属が使用されており、導電性や配線用ワイヤの接合性を高めるために、金属部表面には金・銀・パラジウム等といった貴金属からなるメッキを施して表面層を形成していた。しかしながら、この表面層は、配線用ワイヤが接合される箇所に形成されていれば良く、レジストから露出する金属部表面全面に形成することは、生産面・コスト面で無駄となっていた。   A conventional method for manufacturing a semiconductor device is a process shown in the above-mentioned patent document. In forming a metal part on a mother board by electroforming, a resist layer is formed on a non-arranged part of the metal part on the mother board. It was formed in advance so that the metal part was formed at an appropriate position. The metal part is made of a metal such as nickel suitable for electroforming, and the surface of the metal part is made of a noble metal such as gold, silver, palladium, etc. in order to improve the electrical conductivity and the bonding property of the wiring wire. A surface layer was formed by plating. However, the surface layer only needs to be formed at a location where the wiring wire is joined, and forming the entire surface of the metal part exposed from the resist is useless in terms of production and cost.

本発明は、前記課題を解消するためになされたもので、ダイパッドやリードとなる金属部の必要な箇所に表面層を精度・効率良く形成できる半導体装置の製造方法、及びその製造方法によって得られる半導体装置を提供することを目的とする。   The present invention has been made to solve the above-described problems, and is obtained by a method of manufacturing a semiconductor device capable of forming a surface layer accurately and efficiently at a necessary portion of a metal part to be a die pad or a lead, and the manufacturing method thereof. An object is to provide a semiconductor device.

本発明の半導体装置の製造方法は、半導体素子２と、半導体素子２と電気的に接続されるリード３とが樹脂封止体７により封止されている半導体装置の製造方法であって、基板２０の一面側にリード３の形成箇所を除く部分に対応するレジスト体２５ａを有するレジストパターン層２５を形成する工程と、レジストパターン層２５から露出する基板２０の表面にリード部１３を形成した後、レジストパターン層２５及びリード部１３上に表面層１２の形成箇所を除く部分に対応するレジスト体３６ａを有するレジストパターン層３６を形成し、レジストパターン層３６から露出するリード部１３の表面の一部分に表面層１２を積層形成して前記リード３を形成する工程と、基板２０よりレジストパターン層２５及びレジストパターン層３６を除去する工程と、半導体素子２と前記リード３の表面層１２とを電気的に接続する工程と、半導体素子２とリード３とを封止樹脂３８でモールドして樹脂封止体７を形成する工程と、基板２０を除去する工程とを有することを特徴とする。   The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which a semiconductor element 2 and leads 3 electrically connected to the semiconductor element 2 are sealed with a resin sealing body 7. After forming the lead pattern 13 on the surface of the substrate 20 exposed from the resist pattern layer 25, a step of forming a resist pattern layer 25 having a resist body 25 a corresponding to a portion excluding a portion where the lead 3 is formed on one surface side of the substrate 20. A part of the surface of the lead part 13 exposed from the resist pattern layer 36 is formed on the resist pattern layer 25 and the lead part 13 by forming a resist pattern layer 36 having a resist body 36a corresponding to a part other than the part where the surface layer 12 is formed. Forming the lead 3 by laminating the surface layer 12 on the substrate, and the resist pattern layer 25 and the resist pattern layer 36 from the substrate 20 The step of leaving, the step of electrically connecting the semiconductor element 2 and the surface layer 12 of the lead 3, and the semiconductor element 2 and the lead 3 are molded with a sealing resin 38 to form the resin sealing body 7. It has the process and the process of removing the board | substrate 20. It is characterized by the above-mentioned.

また、レジストパターン層２５から露出する基板２０の表面にリード部１３を形成する前に、裏面層１１を形成することを特徴とする。   Further, the back layer 11 is formed before the lead portion 13 is formed on the surface of the substrate 20 exposed from the resist pattern layer 25.

また、レジストパターン層２５から露出する基板２０の表面にリード部１３を形成した後、レジストパターン層２５及びリード部１３上に直描装置３５を用いてレジストパターン層３６を形成し、レジストパターン層３６から露出するリード部１３の表面に表面層１２を形成することを特徴とする。   Further, after forming the lead portion 13 on the surface of the substrate 20 exposed from the resist pattern layer 25, a resist pattern layer 36 is formed on the resist pattern layer 25 and the lead portion 13 using the direct drawing device 35, and the resist pattern layer The surface layer 12 is formed on the surface of the lead portion 13 exposed from the surface 36.

樹脂封止体７には半導体素子２及びリード３を複数個封止し、基板２０を除去した後、樹脂封止体７を切断線Ｘに沿って個々の半導体装置に切断してあって、隣接する半導体装置のリード３を連接形成し、切断線Ｘが連接形成したリード３の中央部分に沿っていることを特徴とする。   A plurality of semiconductor elements 2 and leads 3 are encapsulated in the resin encapsulant 7, and after removing the substrate 20, the resin encapsulant 7 is cut into individual semiconductor devices along the cutting line X. The leads 3 of adjacent semiconductor devices are connected and formed, and the cutting line X is along the central portion of the connected leads 3.

リード３の表面層１２が切断線Ｘ上を避けた位置に形成することを特徴とする。   The surface layer 12 of the lead 3 is formed at a position avoiding the cutting line X.

また、本発明の半導体装置は、上記半導体装置の製造方法によって得られる半導体装置であって、隅部に位置するリード３が樹脂封止体７の正面、背面、側面、及び裏面から露出していることを特徴とする。   The semiconductor device of the present invention is a semiconductor device obtained by the above-described method for manufacturing a semiconductor device, wherein the leads 3 located at the corners are exposed from the front, back, side, and back of the resin sealing body 7. It is characterized by being.

また、リード３の表面層１２が樹脂封止体７から露出されないように樹脂封止体７の内部に位置することを特徴とする。   Further, the surface layer 12 of the lead 3 is located inside the resin sealing body 7 so as not to be exposed from the resin sealing body 7.

本発明によれば、リード３を構成するリード部１３、表面層１２を連続しためっき工程の中で積層形成するので、量産性に優れた生産が可能となる。しかも、表面層１２は、リード部１３の表面全面ではなく、ワイヤ３が結線させる箇所に部分的に形成するので、表面層１２の形成を必要最小限に抑えることができ、コスト削減に寄与できる。   According to the present invention, since the lead portion 13 and the surface layer 12 constituting the lead 3 are laminated and formed in a continuous plating process, production with excellent mass productivity is possible. In addition, since the surface layer 12 is partially formed not at the entire surface of the lead portion 13 but at the place where the wire 3 is connected, the formation of the surface layer 12 can be suppressed to the minimum necessary, which can contribute to cost reduction. .

本発明の第１実施形態に係る半導体装置の断面図である。1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. 本発明の第１実施形態に係る半導体装置の平面図である。1 is a plan view of a semiconductor device according to a first embodiment of the present invention. 本発明の第１実施形態に係る半導体装置の製造方法を説明するための図である。It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第１実施形態に係る半導体装置の製造方法を説明するための図である。It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第１実施形態に係る半導体装置の製造方法を説明するための図である。It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第２実施形態に係る半導体装置の平面図である。It is a top view of the semiconductor device concerning a 2nd embodiment of the present invention. 本発明の第２実施形態に係る半導体装置の製造方法を説明するための図である。It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. 本発明の第２実施形態の変形例に係る半導体装置の平面図である。It is a top view of the semiconductor device which concerns on the modification of 2nd Embodiment of this invention.

図１乃至図５に本発明に係る半導体装置１の構成および製造方法の第１実施形態を示す。図１は、本発明の第１実施形態に係る半導体装置１の断面図であり、図２は、本発明の第１実施形態に係る半導体装置１の平面図である。各図において、２は半導体素子であって、ダイパッド４上に接着されて搭載されている。５は半導体素子２上に形成された電極であり、上記ダイパッド４と独立して並設されたリード３と金や銅等の導電性のワイヤ６により結線され、電気的に接続されている。上記半導体素子２の搭載部分は熱硬化性エポキシ樹脂等の封止樹脂にて封止されており、上記ダイパッド４とリード３の各裏面が封止樹脂と同一平面で露出した樹脂封止体７が構成されている。   FIG. 1 to FIG. 5 show a first embodiment of the configuration and manufacturing method of a semiconductor device 1 according to the present invention. FIG. 1 is a cross-sectional view of the semiconductor device 1 according to the first embodiment of the present invention, and FIG. 2 is a plan view of the semiconductor device 1 according to the first embodiment of the present invention. In each figure, reference numeral 2 denotes a semiconductor element which is mounted on the die pad 4 while being adhered. Reference numeral 5 denotes an electrode formed on the semiconductor element 2, which is connected and electrically connected by a lead 3 provided in parallel with the die pad 4 and a conductive wire 6 such as gold or copper. The mounting portion of the semiconductor element 2 is sealed with a sealing resin such as a thermosetting epoxy resin, and the resin sealing body 7 in which the back surfaces of the die pad 4 and the lead 3 are exposed in the same plane as the sealing resin. Is configured.

図１の部分拡大図に示すように、ダイパッド４とリード３は、それぞれニッケル・銅・これらの合金等の電鋳金属により構成されるダイパッド部１４、リード部１３を有し、ダイパッド部１４とリード部１３のそれぞれの裏面側には、金・銀・パラジウム・スズ・ハンダ等の導電性に優れた裏面層１１が０．０１〜１μｍ程度の厚さで形成されている。また、ダイパッド部１４とリード部１３のそれぞれの表面側には、ワイヤ３との結線力向上のために、金・銀・パラジウム・白金等の表面層１２が０．０１〜１μｍ程度の厚さで形成されている。この表面層１２は、ダイパッド部１４上には形成しなくても良い。   As shown in the partially enlarged view of FIG. 1, the die pad 4 and the lead 3 each have a die pad portion 14 and a lead portion 13 made of electroformed metal such as nickel, copper, and an alloy thereof. On the back surface side of each lead portion 13, a back surface layer 11 having excellent conductivity such as gold, silver, palladium, tin, and solder is formed with a thickness of about 0.01 to 1 μm. Further, on each surface side of the die pad portion 14 and the lead portion 13, a surface layer 12 of gold, silver, palladium, platinum or the like has a thickness of about 0.01 to 1 μm in order to improve the connection force with the wire 3. It is formed with. The surface layer 12 may not be formed on the die pad portion 14.

図３乃至図５は、上記半導体装置の製造方法を工程ごとに示しており、例えば、ステンレスやアルミ、銅等の導電性の金属板からなる基板２０に約５０μｍ厚のアルカリタイプの感光性フィルムレジストを熱圧着等の方法でラミネートする等して、レジスト層２１を形成し、図３（ａ）に示すごとく、基板２０の一面側のレジスト層２１上に所定パターン２２を有するパターンフィルム２３（ガラスマスク）を配した状態で紫外線ランプ２４の紫外線照射による露光を行った後、現像処理を行うことで、図３（ｂ）に示すような、基板２０の一面側にレジスト体２５ａを有するレジストパターン層２５を得る。   3 to 5 show the method of manufacturing the semiconductor device for each process. For example, an alkali-type photosensitive film having a thickness of about 50 μm is formed on a substrate 20 made of a conductive metal plate such as stainless steel, aluminum, or copper. A resist layer 21 is formed by laminating a resist by a method such as thermocompression bonding. As shown in FIG. 3A, a pattern film 23 (having a predetermined pattern 22 on the resist layer 21 on one surface side of the substrate 20 is formed. A resist having a resist body 25a on one surface side of the substrate 20 as shown in FIG. 3B by performing development processing after exposure by ultraviolet irradiation of the ultraviolet lamp 24 in a state where a glass mask is disposed. The pattern layer 25 is obtained.

次いで、図３（ｃ）に示すごとく、基板２０の一面側にめっきを施すことにより、ダイパッド４及びリード３を形成する。   Next, as shown in FIG. 3C, the die pad 4 and the lead 3 are formed by plating one surface side of the substrate 20.

このダイパッド４及びリード３の形成工程について具体的に説明すると、まず、図４（ａ）に示すごとく、基板２０の一面側のレジストパターン層２５で覆われていない露出面に対し、必要に応じて化学エッチングによる表面酸化被膜除去や薬品による周知の化学処理等の表面活性化処理を行った後、基板２０のレジストパターン層２５により規定された露出面に０．０５〜１μｍ厚で金をめっき成長させて、裏面層１１となる第１金属層３１を形成する。本実施形態の場合、微細パターン部の金メッキ処理において、金メッキの成長不良や付着不良の発生を事前に防止する目的で、上記化学エッチング等の化学処理を行い、基板２０上の不活性膜を除去する工程を付加しているが、基板２０の材質、メッキする金属の選択によっては、この工程は省略可能である。   The process of forming the die pad 4 and the leads 3 will be described in detail. First, as shown in FIG. 4A, the exposed surface not covered with the resist pattern layer 25 on the one surface side of the substrate 20 is first formed as necessary. After performing surface activation treatment such as removal of the surface oxide film by chemical etching or well-known chemical treatment with chemicals, gold is plated on the exposed surface defined by the resist pattern layer 25 of the substrate 20 to a thickness of 0.05 to 1 μm. The first metal layer 31 to be the back layer 11 is formed by growing. In the case of this embodiment, in the gold plating process of the fine pattern part, the chemical process such as the above chemical etching is performed to remove the inactive film on the substrate 20 in order to prevent the gold plating growth failure and the adhesion failure in advance. However, depending on the selection of the material of the substrate 20 and the metal to be plated, this step can be omitted.

次いで、図４（ｂ）に示すごとく、ニッケルや銅，ニッケル−コバルト等の合金等から選択される金属、本実施形態の場合は、ニッケルを上記第１金属層３１上面にめっき（電鋳）することで、ダイパッド部１４とリード部１３となる第２金属層３２を積層形成する。なお、本工程において、第２金属層３２をレジストパターン層２６の厚みを越えて（例えば６０〜８０μｍ厚で）形成することで、ダイパッド４及びリード３の上端部周縁に庇状の張出部を形成することができる。   Next, as shown in FIG. 4B, a metal selected from an alloy such as nickel, copper, nickel-cobalt, or the like, in this embodiment, nickel is plated on the upper surface of the first metal layer 31 (electroforming). Thus, the die pad portion 14 and the second metal layer 32 to be the lead portion 13 are stacked. In this step, the second metal layer 32 is formed beyond the thickness of the resist pattern layer 26 (for example, with a thickness of 60 to 80 μm), so that a flange-like overhanging portion is formed on the periphery of the upper end portion of the die pad 4 and the lead 3. Can be formed.

次いで、図４（ｃ）に示すごとく、第２金属層３２及びレジストパターン層２５上にレジスト層３４を形成した後、直描装置３５を用いてレジスト層３４に紫外線を照射し、露光・現像処理を行うことで、図４（ｄ）に示すように、第２金属層３２上に第３金属層３３の形成箇所に対応するレジスト体３６ａを有するレジストパターン層３６が得られる。   Next, as shown in FIG. 4C, after a resist layer 34 is formed on the second metal layer 32 and the resist pattern layer 25, the resist layer 34 is irradiated with ultraviolet rays using a direct drawing device 35, and is exposed and developed. By performing the treatment, as shown in FIG. 4D, a resist pattern layer 36 having a resist body 36a corresponding to the formation location of the third metal layer 33 on the second metal layer 32 is obtained.

次いで、図４（ｅ）に示すごとく、少なくともリード部１３となる第２金属層３２の表面に後述のワイヤボンディング時の結着力を向上させるために、表面層１２となる第３金属層３３を０．０１〜３．０μｍ厚でめっき成長させ、レジストパターン層３６を除去することで、ダイパッド４及びリード３を形成する。ここで、表面層１２となる第３金属層３３を銀とした場合は、厚さは１．０〜２．５μｍが好ましい。また、本実施形態のように、ダイパッド部１４とリード部１３となる第２金属層３２をニッケルとし、この第２金属層３２上に表面層１２となる第３金属層３３として銀をめっき成長させる場合は、第２金属層３２と第３金属層３３との結着力を向上するために、ニッケルの第２金属層３２上に金やパラジウムなどをめっき形成したうえで、銀の第３金属層３３をめっき成長させるのが好ましい。また、レジストパターン層３６を除去する際には、レジストパターン層２５も一緒に除去するようにすると良い。このように、第３金属層３３は、第２金属層３２の露出する表面全面ではなく、ワイヤボンディングされる箇所に形成されていれば良く、第２金属層３２の表面に銀を部分めっきすることで、第３金属層３３を形成する。ここで、第２金属層３２をニッケル、第３金属層３３を銀とする場合、ニッケルと銀は相性が悪いため、銀めっきの成長不良や付着不良が生じるおそれがあるが、第３金属層３３を形成する前に、第２金属層３２の表面上に金や銀、銅などによるストライクメッキを施すことで、係る不良の発生を防止することができる。   Next, as shown in FIG. 4E, a third metal layer 33 to be the surface layer 12 is formed on at least the surface of the second metal layer 32 to be the lead portion 13 in order to improve the binding force at the time of wire bonding described later. The die pad 4 and the leads 3 are formed by plating growth with a thickness of 0.01 to 3.0 μm and removing the resist pattern layer 36. Here, when the 3rd metal layer 33 used as the surface layer 12 is made into silver, thickness is preferable 1.0-2.5 micrometers. Further, as in the present embodiment, the second metal layer 32 that becomes the die pad portion 14 and the lead portion 13 is made of nickel, and silver is plated and grown as the third metal layer 33 that becomes the surface layer 12 on the second metal layer 32. In order to improve the binding force between the second metal layer 32 and the third metal layer 33, gold or palladium is plated on the second metal layer 32 of nickel, and then the third metal of silver is formed. Layer 33 is preferably plated. When removing the resist pattern layer 36, the resist pattern layer 25 may be removed together. As described above, the third metal layer 33 may be formed not on the entire exposed surface of the second metal layer 32 but on the portion to be wire-bonded, and silver is partially plated on the surface of the second metal layer 32. Thus, the third metal layer 33 is formed. Here, when the second metal layer 32 is nickel and the third metal layer 33 is silver, since the compatibility between nickel and silver is poor, there is a risk that growth failure or adhesion failure of silver plating may occur. By forming strike plating with gold, silver, copper or the like on the surface of the second metal layer 32 before forming 33, the occurrence of such defects can be prevented.

各金属層を形成後、基板２０よりレジストパターン層２５を除去することにより、図３（ｄ）に示すごとく、基板２０上にダイパッド４及びリード３が形成された半導体装置用基板を得ることができる。なお、レジストパターン層２５・３６の除去方法としては、アルカリ溶液による膨潤除去の方法等が考えられる。また、レジストパターン層２５の除去は、レジストパターン層３６の除去と同時に行っても良い。   After forming each metal layer, the resist pattern layer 25 is removed from the substrate 20 to obtain a semiconductor device substrate in which the die pad 4 and the leads 3 are formed on the substrate 20 as shown in FIG. it can. As a method for removing the resist pattern layers 25 and 36, a method for removing swelling with an alkaline solution or the like can be considered. Further, the removal of the resist pattern layer 25 may be performed simultaneously with the removal of the resist pattern layer 36.

次いで、図５（ａ）に示すごとく、半導体素子２をダイボンディングによりダイパッド４上に接着して搭載するとともに、図５（ｂ）に示すごとく、金や銅等の導電性のワイヤ６を用いて超音波ボンディング装置等により上記半導体素子２上の電極５とこれに対応するリード３とを結線する。なお、係る結線において、電極５部分はボールボンディング、リード３部分はウェッジボンディングが好ましい。このように、リード３においては、ワイヤ６の結線箇所に表面層１２が形成されていることにより、結線力が一層向上し、結線ミスを低減できる。   Next, as shown in FIG. 5A, the semiconductor element 2 is mounted on the die pad 4 by die bonding, and a conductive wire 6 such as gold or copper is used as shown in FIG. 5B. Then, the electrode 5 on the semiconductor element 2 and the corresponding lead 3 are connected by an ultrasonic bonding apparatus or the like. In this connection, the electrode 5 portion is preferably ball bonding and the lead 3 portion is preferably wedge bonding. Thus, in the lead 3, since the surface layer 12 is formed at the connection location of the wire 6, the connection force is further improved and connection errors can be reduced.

次いで、基板２０上の半導体素子２搭載部分を、図５（ｃ）に示すごとく、熱硬化性エポキシ樹脂等の封止樹脂３８でモールドし、基板２０上に樹脂封止体７を形成する。具体的には、基板２０の一面側をモールド金型（上型）に装着するとともに、モールド金型内に封止樹脂３８をキャビティにより圧入するもので、基板２０上に並列して形成した、複数組の半導体素子２搭載部分が封止樹脂３８により連続して封止された状態の樹脂封止体７が形成される。この場合、基板２０自体が樹脂モールド時における下型の機能を果たす。なお、モールド時に複数の基板２０を並列に配置して、ライナを通して封止樹脂３８を各基板２０と上金型との間に圧入するようにすれば、効率良く多数の樹脂封止を行うことが可能である。   Next, as shown in FIG. 5C, the portion where the semiconductor element 2 is mounted on the substrate 20 is molded with a sealing resin 38 such as a thermosetting epoxy resin to form the resin sealing body 7 on the substrate 20. Specifically, one side of the substrate 20 is mounted on a mold (upper mold), and a sealing resin 38 is press-fitted into the mold by a cavity, and is formed in parallel on the substrate 20. The resin sealing body 7 is formed in a state in which a plurality of sets of semiconductor element 2 mounting portions are continuously sealed with the sealing resin 38. In this case, the substrate 20 itself functions as a lower mold during resin molding. If a plurality of substrates 20 are arranged in parallel at the time of molding and the sealing resin 38 is press-fitted between each substrate 20 and the upper mold through a liner, a large number of resins can be efficiently sealed. Is possible.

ここで、上記のごとく、ダイパッド４及びリード３の上端部に張出部を形成しておけば、封止樹脂３８による封止状態において、封止樹脂３８はくい込み状に位置した状態で硬化するため、この喰い付き効果により、後工程の樹脂封止体７からの基板２０の除去時において、基板２０を引き剥がし除去する際、ダイパッド４及びリード３は樹脂封止体７側に確実に残留し、基板２０とともにくっついて引き離されることはなく、ズレや欠落等が効果的に防止でき、製造工程時の歩留まりが向上できる。さらに、完成した半導体装置自体の信頼性も向上する。   Here, as described above, if the overhanging portion is formed at the upper ends of the die pad 4 and the lead 3, the sealing resin 38 is cured in a state of being bitten in the sealing state by the sealing resin 38. Therefore, due to this biting effect, when the substrate 20 is removed from the resin sealing body 7 in the subsequent process, when the substrate 20 is peeled off and removed, the die pad 4 and the lead 3 are reliably left on the resin sealing body 7 side. However, they are not stuck together with the substrate 20 and can be effectively prevented from being displaced or missing, and the yield during the manufacturing process can be improved. Furthermore, the reliability of the completed semiconductor device itself is also improved.

次いで、図５（ｄ）に示すごとく、樹脂封止体７から基板２０を除去することにより、樹脂封止体７の底面には、複数組のダイパッド４とリード３の各裏面が露出するとともに、ダイパッド４とリード３の各裏面と樹脂封止体７の底面は略同一平面となっている。すなわち、ダイパッド４とリード３における裏面層１１が樹脂封止体７の底面と略同一平面で露出する状態となっている。上記基板２０を除去する方法としては、樹脂封止体７から基板２０を引き剥がすことによる剥離除去する方法の他、例えば、基板２０を構成する材質に応じて、樹脂封止体７側への影響のない溶剤等により基板２０を溶解することによる溶解除去する方法も含まれるものである。   Next, as shown in FIG. 5 (d), by removing the substrate 20 from the resin sealing body 7, the back surfaces of the plurality of sets of die pads 4 and leads 3 are exposed on the bottom surface of the resin sealing body 7. The back surfaces of the die pad 4 and the lead 3 and the bottom surface of the resin sealing body 7 are substantially on the same plane. That is, the back surface layer 11 of the die pad 4 and the lead 3 is in a state exposed in substantially the same plane as the bottom surface of the resin sealing body 7. As a method of removing the substrate 20, in addition to a method of peeling and removing by peeling the substrate 20 from the resin sealing body 7, for example, depending on the material constituting the substrate 20, A method of dissolving and removing the substrate 20 by dissolving the substrate 20 with a solvent having no influence is also included.

次いで、図５（ｅ）に示すごとく、樹脂封止体を切断線Ｘ−Ｘに沿って１つの半導体素子２毎に切断して切り離すダイシング工程を経て、個々の樹脂封止体７、すなわち、半導体装置が完成するものである。   Next, as shown in FIG. 5 (e), through a dicing process in which the resin sealing body is cut for each semiconductor element 2 along the cutting line XX, the individual resin sealing bodies 7, that is, A semiconductor device is completed.

このような半導体装置の製造方法によれば、ダイシングによる切り離し工程が終了した時点で、各半導体装置の裏面から露出する全てのリード３には、導電性、はんだ性に優れた金属からなる裏面層１１が形成されているため、その後のバレルメッキ等の工程に移ることなく、すぐにこの状態で実装することができる。また、ダイパッド４及びリード３を構成する裏面層１１（第１金属層３１）、ダイパッド部１４・リード部１３（第２金属層３２）、表面層１２（第３金属層３３）を連続しためっき・電鋳工程の中で積層形成するため、量産性にも優れている。そして、少なくともリード３においては、表面層１２を部分的に形成、つまり、ワイヤ３が結線させる箇所に形成すれば、表面層１２としての金属材の使用を最小限に抑えることができ、生産性・コスト性に無駄のない製造が可能となる。しかも、表面層１２は、直描装置３５を用いて形成したレジストパターン層３６上にめっきを施すことで形成しているので、表面層１２をリード部１３上に精度良く警醒することが可能となる。   According to such a method of manufacturing a semiconductor device, when all the leads 3 exposed from the back surface of each semiconductor device are finished at the time of the dicing separation process, the back surface layer made of metal having excellent conductivity and solderability is provided. 11 is formed, it can be immediately mounted in this state without moving to subsequent steps such as barrel plating. Further, the back surface layer 11 (first metal layer 31), the die pad part 14 / lead part 13 (second metal layer 32), and the surface layer 12 (third metal layer 33) constituting the die pad 4 and the lead 3 are continuously plated. -It is excellent in mass productivity because it is laminated in the electroforming process. At least in the lead 3, if the surface layer 12 is partially formed, that is, formed at a place where the wire 3 is connected, the use of a metal material as the surface layer 12 can be minimized, and the productivity is increased.・ Manufacturing that is cost effective is possible. Moreover, since the surface layer 12 is formed by plating on the resist pattern layer 36 formed using the direct drawing device 35, the surface layer 12 can be alerted to the lead portion 13 with high accuracy. Become.

図６及び図７に本発明に係る半導体装置１の構成および製造方法の第２実施形態を示す。図６は、本発明の第２実施形態に係る半導体装置１の平面図である。第１実施形態では、リード３の裏面が樹脂封止体７の底面から露出しているのに対し、本実施形態では、樹脂封止体７の側面からも露出している点が異なる。係る構成のように、リード３が裏面だけでなく側面からも樹脂封止体７から露出されてリード３の露出面積が増えるため、例えば、はんだを用いて半導体装置をプリント基板上に載置する際に、リード３とはんだとの接触面積が大きくなり、プリント基板への半導体装置の搭載をより確実にすることができる。また、係る構成をとるために、後述のようにリード３を連接形成し、このリード３の中央部分を切断しているものであり、このようにリード３を連接形成することで、基板２０上におけるリード３の配置を接近させることができるため、１つの基板２０からの取り数を増やすことができ、量産化、コスト低減に繋がる。   6 and 7 show a second embodiment of the configuration and manufacturing method of the semiconductor device 1 according to the present invention. FIG. 6 is a plan view of the semiconductor device 1 according to the second embodiment of the present invention. In the first embodiment, the back surface of the lead 3 is exposed from the bottom surface of the resin sealing body 7, whereas in the present embodiment, the lead 3 is also exposed from the side surface of the resin sealing body 7. Since the lead 3 is exposed from the resin sealing body 7 not only from the back surface but also from the side surface as in this configuration, the exposed area of the lead 3 is increased. For example, the semiconductor device is placed on the printed board using solder. At this time, the contact area between the lead 3 and the solder is increased, so that the semiconductor device can be more reliably mounted on the printed circuit board. Further, in order to take such a configuration, the leads 3 are connected and formed as will be described later, and the central portion of the leads 3 is cut. Thus, the leads 3 are connected and formed on the substrate 20. Since the arrangement of the leads 3 can be made closer to each other, the number of pieces taken from one substrate 20 can be increased, leading to mass production and cost reduction.

図７に本実施形態に係る半導体装置の製造方法を工程ごとに示す。まず、第１実施形態と同様に、基板２０にレジスト層を形成し、露光・現像処理を行って、基板２０上にダイパッド４とリード３の形成箇所に対応するレジストパターン層２５を形成する。なお、ここでのレジストパターン層２５は、図７（ａ）に示すように、リード３を中央部分で切断して個々の半導体装置側に切り離すようにするため、隣接する各半導体装置のリード３を連接形成できるようになっている。   FIG. 7 shows a method for manufacturing a semiconductor device according to this embodiment for each process. First, as in the first embodiment, a resist layer is formed on the substrate 20, and exposure / development processing is performed to form a resist pattern layer 25 corresponding to the formation positions of the die pad 4 and the leads 3 on the substrate 20. Here, as shown in FIG. 7A, the resist pattern layer 25 is formed by cutting the lead 3 at the central portion so as to be separated to the individual semiconductor device side. Can be connected.

次いで、レジストパターン層２５から露出する基板２０の表面に前処理を行った後、第１金属層３１（裏面層１１）、第２金属層３２（ダイパッド部１４、リード部１３）、第３金属層３３（表面層１２）を形成し、基板２０よりレジストパターン層６を除去することで、図７（ｂ）に示すように、基板２０上にダイパッド４及びリード３が形成された半導体装置用基板を得ることができる。第３金属層３３は、直描装置によるレジストパターンニングとめっきにより第２金属層３２上のワイヤボンディングする箇所に部分的に形成される。   Next, after the pretreatment is performed on the surface of the substrate 20 exposed from the resist pattern layer 25, the first metal layer 31 (back surface layer 11), the second metal layer 32 (die pad portion 14, lead portion 13), and the third metal By forming the layer 33 (surface layer 12) and removing the resist pattern layer 6 from the substrate 20, the die pad 4 and the leads 3 are formed on the substrate 20 as shown in FIG. 7B. A substrate can be obtained. The third metal layer 33 is partially formed at a location where wire bonding is performed on the second metal layer 32 by resist patterning and plating using a direct drawing apparatus.

次いで、ダイパッド４への半導体素子２の搭載、半導体素子２とリード３との結線、樹脂封止、基板除去と各工程を経ることで、図７（ｃ）に示すように、樹脂封止体７を形成する。   Next, through steps of mounting the semiconductor element 2 on the die pad 4, connecting the semiconductor element 2 and the lead 3, resin sealing, and removing the substrate, as shown in FIG. 7 is formed.

次いで、図７（ｄ）に示すごとく、樹脂封止体７を切断線Ｘ−Ｘに沿ってダイシングして、１つの半導体素子２毎に切断する。この時、切断線Ｘ−Ｘは、連接して形成されたリード３の中央部分に沿っており、この切断線Ｘ−Ｘに沿って切断することで、個々の半導体装置に切り離す。このように、基板２０上へのリード３の形成を接近させて効率的に行え、１つの基板２０からの取り数を増やすことができ、量産化・コスト低減が可能となる。また、リード３における表面層１２は、切断線Ｘ−Ｘ上を避けた位置に形成されているので、表面層１２をリード部１３全面に形成した場合に比べて切断が容易になるとともに、マイグレーションの発生を防ぐことができる。   Next, as shown in FIG. 7 (d), the resin sealing body 7 is diced along the cutting line XX and cut into each semiconductor element 2. At this time, the cutting line XX is along the central portion of the lead 3 formed in a connected manner, and the semiconductor device is cut into individual semiconductor devices by cutting along the cutting line XX. As described above, the formation of the leads 3 on the substrate 20 can be performed efficiently by approaching, and the number of pieces taken from one substrate 20 can be increased, thereby enabling mass production and cost reduction. Further, since the surface layer 12 in the lead 3 is formed at a position avoiding the cutting line XX, the cutting is easier than in the case where the surface layer 12 is formed on the entire surface of the lead portion 13 and migration is performed. Can be prevented.

ここで、連接形成されたリード３の中央部分を切断する場合において、表面層１２をリード部１３上面全面に形成すると、表面層１２も樹脂封止体７の側面から露出されてしまうため、樹脂封止体７側面において隣接するリード３間にてマイグレーションが起こりやすく、しかも、表面層１２を銀とした時に顕著に現れていた。そこで、本実施形態の半導体装置のように、リード３における表面層１２を樹脂封止体７の側面から露出されないようリード部１３上に形成することで、マイグレーションによる不良を可及的に防ぐことができる。   Here, in the case where the central portion of the lead 3 formed in a connected manner is cut, if the surface layer 12 is formed on the entire upper surface of the lead portion 13, the surface layer 12 is also exposed from the side surface of the resin sealing body 7. Migration was likely to occur between the adjacent leads 3 on the side surface of the sealing body 7 and remarkably appeared when the surface layer 12 was made of silver. Therefore, as in the semiconductor device of this embodiment, the surface layer 12 of the lead 3 is formed on the lead portion 13 so as not to be exposed from the side surface of the resin encapsulant 7, thereby preventing defects due to migration as much as possible. Can do.

なお、本実施形態においては、左右方向にてリード３を連接形成し、その中央部分を切断しているが、前後方向にてリード３を連接形成し、その中央部分を切断しても良い。もちろん、図８に示すように、前後左右方向にてリード３を連接形成（各半導体装置における隅部において）し、その中央部分を切断しても良い。この場合、樹脂封止体７から露出するリード３は、裏面と側面だけでなく、正面、背面からも露出させることができる。   In the present embodiment, the lead 3 is connected and formed in the left-right direction and the center portion thereof is cut. However, the lead 3 may be connected and formed in the front-rear direction and the center portion may be cut. Of course, as shown in FIG. 8, the leads 3 may be connected in the front-rear and left-right directions (at the corners of each semiconductor device), and the center portion thereof may be cut. In this case, the lead 3 exposed from the resin sealing body 7 can be exposed not only from the back surface and the side surface but also from the front surface and the back surface.

また、各実施形態においては、表面層１２（第３金属層３３）を形成するためのレジストパターン層３６を直描装置による直接描画によって形成しているが、裏面層１１（第１金属層３１）、ダイパッド部１４・リード部１３（第２金属層３２）を形成するためのレジストパターン層２５についても係る方法にて形成しても良い。また、各実施形態においては、樹脂封止体７を切断線Ｘ−Ｘに沿って切断するためにアライメントマーク（切断マーク）を基板２０の外周、あるいは最外に配置されるリード３の外周に設けることが好ましく、図８に示すように、連接形成されたリード３のうちの最外に位置するリード３の一部に凹み９を設ければ、この凹み９がアライメントマーク（切断マーク）の役割となり、アライメントマーク（切断マーク）が備わったリード３とすることができる。   Moreover, in each embodiment, although the resist pattern layer 36 for forming the surface layer 12 (third metal layer 33) is formed by direct drawing with a direct drawing device, the back surface layer 11 (first metal layer 31). The resist pattern layer 25 for forming the die pad portion 14 and the lead portion 13 (second metal layer 32) may also be formed by such a method. Moreover, in each embodiment, in order to cut | disconnect the resin sealing body 7 along the cutting | disconnection line XX, an alignment mark (cutting mark) is put on the outer periphery of the board | substrate 20, or the outer periphery of the lead | read | reed 3 arrange | positioned outermost. As shown in FIG. 8, if a recess 9 is provided in a part of the lead 3 positioned at the outermost position among the connected leads 3, the recess 9 serves as an alignment mark (cutting mark). Thus, the lead 3 having an alignment mark (cutting mark) can be obtained.

１ 半導体装置
２ 半導体素子
３ リード
４ ダイパッド
５ 電極
６ ワイヤ
７ 樹脂封止体
１１ 裏面層
１２ 表面層
１３ リード部
１４ ダイパッド部
２０ 基板
２５ レジストパターン層
３１ 第１金属層
３２ 第２金属層
３３ 第３金属層
３６ レジストパターン層 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor element 3 Lead 4 Die pad 5 Electrode 6 Wire 7 Resin sealing body 11 Back surface layer 12 Surface layer 13 Lead part 14 Die pad part 20 Substrate 25 Resist pattern layer 31 1st metal layer 32 2nd metal layer 33 3rd Metal layer 36 Resist pattern layer

Claims (7)

半導体素子（２）と、前記半導体素子（２）と電気的に接続されるリード（３）とが樹脂封止体（７）により封止されている半導体装置の製造方法であって、
基板（２０）の一面側に前記リード（３）の形成箇所を除く部分に対応するレジスト体（２５ａ）を有するレジストパターン層（２５）を形成する工程と、
前記レジストパターン層（２５）から露出する前記基板（２０）の表面にリード部（１３）を形成した後、前記レジストパターン層（２５）及び前記リード部（１３）上に表面層（１２）の形成箇所を除く部分に対応するレジスト体（３６ａ）を有するレジストパターン層（３６）を形成し、前記レジストパターン層（３６）から露出する前記リード部（１３）の表面の一部分に前記表面層（１２）を積層形成して前記リード（３）を形成する工程と、
前記基板（２０）より前記レジストパターン層（２５）及び前記レジストパターン層（３６）を除去する工程と、
前記半導体素子（２）と前記リード（３）の前記表面層（１２）とを電気的に接続する工程と、
前記半導体素子（２）と前記リード（３）とを封止樹脂（３８）でモールドして樹脂封止体（７）を形成する工程と、
前記基板（２０）を除去する工程とを有することを特徴とする半導体装置の製造方法。 A semiconductor device manufacturing method in which a semiconductor element (2) and a lead (3) electrically connected to the semiconductor element (2) are sealed with a resin sealing body (7),
Forming a resist pattern layer (25) having a resist body (25a) corresponding to a portion excluding a portion where the lead (3) is formed on one surface side of the substrate (20);
After forming a lead portion (13) on the surface of the substrate (20) exposed from the resist pattern layer (25), the surface layer (12) is formed on the resist pattern layer (25) and the lead portion (13). A resist pattern layer (36) having a resist body (36a) corresponding to a portion excluding the formation portion is formed, and the surface layer (36) is formed on a part of the surface of the lead portion (13) exposed from the resist pattern layer (36). 12) forming the leads (3) by laminating;
Removing the resist pattern layer (25) and the resist pattern layer (36) from the substrate (20);
Electrically connecting the semiconductor element (2) and the surface layer (12) of the lead (3);
Molding the semiconductor element (2) and the lead (3) with a sealing resin (38) to form a resin sealing body (7);
And a step of removing the substrate (20). 前記レジストパターン層（２５）から露出する前記基板（２０）の表面に前記リード部（１３）を形成する前に、裏面層（１１）を形成することを特徴とする請求項１に記載の半導体装置の製造方法。   The semiconductor according to claim 1, wherein a back layer (11) is formed before forming the lead portion (13) on the surface of the substrate (20) exposed from the resist pattern layer (25). Device manufacturing method. 前記レジストパターン層（２５）から露出する前記基板（２０）の表面に前記リード部（１３）を形成した後、前記レジストパターン層（２５）及び前記リード部（１３）上に直描装置（３５）を用いてレジストパターン層（３６）を形成し、前記レジストパターン層（３６）から露出する前記リード部（１３）の表面に前記表面層（１２）を形成することを特徴とする請求項１または２に記載の半導体装置の製造方法。   After forming the lead part (13) on the surface of the substrate (20) exposed from the resist pattern layer (25), a direct drawing device (35) is formed on the resist pattern layer (25) and the lead part (13). The resist pattern layer (36) is formed by using (1), and the surface layer (12) is formed on the surface of the lead portion (13) exposed from the resist pattern layer (36). Or the manufacturing method of the semiconductor device of 2. 前記樹脂封止体（７）には前記半導体素子（２）及び前記リード（３）を複数封止し、前記基板（２０）を除去した後、前記樹脂封止体（７）を切断線（Ｘ）に沿って個々の半導体装置に切断してあって、隣接する半導体装置の前記リード（３）を連接形成し、前記切断線（Ｘ）が連接形成した前記リード（３）の中央部分に沿っていることを特徴とする請求項１ないし３のいずれかに記載の半導体装置の製造方法。   A plurality of the semiconductor elements (2) and the leads (3) are sealed in the resin sealing body (7), and after removing the substrate (20), the resin sealing body (7) is cut along a cutting line ( X) is cut into individual semiconductor devices, and the leads (3) of adjacent semiconductor devices are connected and formed at the central portion of the leads (3) where the cutting lines (X) are connected and formed. The method of manufacturing a semiconductor device according to claim 1, wherein 前記リード（３）の前記表面層（１２）が前記切断線（Ｘ）上を避けた位置に形成することを特徴とする請求項１ないし４のいずれかに記載の半導体装置の製造方法。   5. The method of manufacturing a semiconductor device according to claim 1, wherein the surface layer (12) of the lead (3) is formed at a position avoiding the cutting line (X). 前記請求項１ないし５のいずれに記載の半導体装置の製造方法によって得られる半導体装置であって、隅部に位置する前記リード（３）が前記樹脂封止体（７）の正面、背面、側面、及び裏面から露出していることを特徴とする半導体装置。   6. A semiconductor device obtained by the method for manufacturing a semiconductor device according to claim 1, wherein the leads (3) located at corners are front, back and side surfaces of the resin sealing body (7). And a semiconductor device exposed from the back surface. 前記リード（３）の前記表面層（１２）が前記樹脂封止体（７）から露出されないように前記樹脂封止体（７）の内部に位置することを特徴とする請求項６に記載の半導体装置。   The said surface layer (12) of the said lead (3) is located inside the said resin sealing body (7) so that it may not be exposed from the said resin sealing body (7). Semiconductor device.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104465418A (en) * 2014-12-24 2015-03-25 南通富士通微电子股份有限公司 Fan-out wafer-level encapsulating method
JP2016136573A (en) * 2015-01-23 2016-07-28 新日本無線株式会社 Manufacturing method for lead built-in circuit package

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09266267A (en) * 1996-03-28 1997-10-07 Hitachi Chem Co Ltd Transfer wiring supporting member and method of manufacturing semiconductor package using the same
JP2000268722A (en) * 1999-03-18 2000-09-29 Fujitsu Ltd Forming method and device for repeated pattern
JP2001326316A (en) * 2000-05-12 2001-11-22 Dainippon Printing Co Ltd Frame for resin-sealed semiconductor device
JP2002009196A (en) * 2000-06-20 2002-01-11 Kyushu Hitachi Maxell Ltd Manufacturing method of semiconductor device
JP2002289739A (en) * 2001-03-23 2002-10-04 Dainippon Printing Co Ltd Resin sealed type semiconductor device, and circuit member for semiconductor device and its manufacturing method
JP2004165329A (en) * 2002-11-12 2004-06-10 Sony Corp Defective mask and its manufacturing method, defect inspecting method of mask, and manufacturing method of semiconductor device
JP2004214265A (en) * 2002-12-27 2004-07-29 Kyushu Hitachi Maxell Ltd Semiconductor device and its manufacturing method
WO2009060745A1 (en) * 2007-11-06 2009-05-14 Nikon Corporation Control device, exposure method, and exposure device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09266267A (en) * 1996-03-28 1997-10-07 Hitachi Chem Co Ltd Transfer wiring supporting member and method of manufacturing semiconductor package using the same
JP2000268722A (en) * 1999-03-18 2000-09-29 Fujitsu Ltd Forming method and device for repeated pattern
JP2001326316A (en) * 2000-05-12 2001-11-22 Dainippon Printing Co Ltd Frame for resin-sealed semiconductor device
JP2002009196A (en) * 2000-06-20 2002-01-11 Kyushu Hitachi Maxell Ltd Manufacturing method of semiconductor device
JP2002289739A (en) * 2001-03-23 2002-10-04 Dainippon Printing Co Ltd Resin sealed type semiconductor device, and circuit member for semiconductor device and its manufacturing method
JP2004165329A (en) * 2002-11-12 2004-06-10 Sony Corp Defective mask and its manufacturing method, defect inspecting method of mask, and manufacturing method of semiconductor device
JP2004214265A (en) * 2002-12-27 2004-07-29 Kyushu Hitachi Maxell Ltd Semiconductor device and its manufacturing method
WO2009060745A1 (en) * 2007-11-06 2009-05-14 Nikon Corporation Control device, exposure method, and exposure device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104465418A (en) * 2014-12-24 2015-03-25 南通富士通微电子股份有限公司 Fan-out wafer-level encapsulating method
JP2016136573A (en) * 2015-01-23 2016-07-28 新日本無線株式会社 Manufacturing method for lead built-in circuit package

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