JP2017005261A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Semiconductor device and semiconductor device manufacturing method Download PDF

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JP2017005261A
JP2017005261A JP2016162142A JP2016162142A JP2017005261A JP 2017005261 A JP2017005261 A JP 2017005261A JP 2016162142 A JP2016162142 A JP 2016162142A JP 2016162142 A JP2016162142 A JP 2016162142A JP 2017005261 A JP2017005261 A JP 2017005261A
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electrode
layer
semiconductor device
semiconductor element
island
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中川　宏史
Hiroshi Nakagawa
宏史 中川
良弘 小林
Yoshihiro Kobayashi
良弘 小林
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Maxell Ltd
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Hitachi Maxell Ltd
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method of the same, which achieve improvement in reliability of electrode continuity in a compact and thin type semiconductor device in consideration of mass productivity.SOLUTION: In a semiconductor device which has an island part 2a for mounting a semiconductor element S and one and more electrode parts 2b, and in which the semiconductor element S and the electrode part 2b are resin encapsulated after being electrically connected with rear faces of the island part 2a and the electrode part 2b being exposed on the same plane with a bottom face of a resin layer 4, each of the island part 2a and the electrode parts 2b is formed by electrocasting at least in a two-layer structure with a metal layer film 11 for mounting on the rear face side and a lead layer 12 integrally laminated on a top face of the metal layer film so that it is unnecessary to form plating for mounting on the exposed surface of the electrode parts separately in a post-process thereby to achieve electrode continuity at the time of mounting and improvement in reliability.SELECTED DRAWING: Figure 1

Description

本発明は半導体装置およびその製造方法に関し、小型・薄型化を図れ、かつ信頼性の高い樹脂封止型の半導体装置に関する。   The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a resin-encapsulated semiconductor device that can be reduced in size and thickness and has high reliability.

従来、この種樹脂封止型の半導体装置として、母型基板上に半導体素子Ｓ搭載用の金属層と外部導出用の電極層から成る電鋳製のリード材を形成し、リード材上に半導体素子Ｓを搭載の後結線処理を行い、母型基板上で樹脂封止した後母型基板のみを除去し個々に切断して構成することは公知である（特許文献１参照）。特許文献１に係る半導体装置は、上記リード材を構成する半導体素子Ｓが搭載される金属層と外部導出用の電極層の各裏面が樹脂封止体から露出して構成され、ガラスエポキシ基板やセラミック基板等の基板を使用することなく、半導体装置の高さを低くし装置全体を小型化することができるとともに、放熱性にも優れるという利点がある。   Conventionally, as this type of resin-encapsulated semiconductor device, an electroformed lead material composed of a metal layer for mounting a semiconductor element S and an electrode layer for external derivation is formed on a base substrate, and a semiconductor is formed on the lead material. It is known that after the element S is mounted, a connection process is performed, and after sealing the resin on the mother board, only the mother board is removed and individually cut (see Patent Document 1). The semiconductor device according to Patent Document 1 is configured such that the back surface of the metal layer on which the semiconductor element S constituting the lead material is mounted and the electrode layer for external derivation are exposed from the resin sealing body, Without using a substrate such as a ceramic substrate, there is an advantage that the height of the semiconductor device can be reduced, the entire device can be reduced in size, and heat dissipation is excellent.

特開２００２−９１９６号公報JP 2002-9196 A

特許文献１に係る半導体装置においては、当該半導体装置を実装するにあたって、電極導通の信頼性向上のために、あらかじめ外部導出用の電極層等に導電性に優れた金や銀等の金属薄膜１１を形成しておくことが好ましいが、その場合樹脂封止後に切断された個々の半導体装置をバレルメッキ等の方法で、樹脂封止体裏面から露出した金属層および電極層に金やスズ，ハンダ，パラジウムの薄膜を形成する方法が採られている。   In the semiconductor device according to Patent Document 1, in order to improve the reliability of electrode conduction when mounting the semiconductor device, a metal thin film 11 such as gold or silver having excellent conductivity in an electrode layer for external derivation or the like in advance. In this case, it is preferable to form gold, tin, solder on the metal layer and the electrode layer exposed from the back surface of the resin sealing body by a method such as barrel plating. A method of forming a palladium thin film has been adopted.

しかしながらこの場合、半導体装置の製造工程と半導体装置完成後のメッキ工程とは全くの別工程となるために、このことが量産性を阻害する要因となるとともに、バレルメッキ時におけるメッキ装置内での揺動、回転によって、半導体装置内部の半導体素子Ｓと電極層間の結線個所に外れや断線等の電気的不良を生ずる虞もある。   However, in this case, since the manufacturing process of the semiconductor device and the plating process after completion of the semiconductor device are completely separate processes, this becomes a factor that hinders mass productivity, and in the plating apparatus during barrel plating. Oscillation and rotation may cause an electrical failure such as disconnection or disconnection at a connection point between the semiconductor element S and the electrode layer in the semiconductor device.

この発明の目的は、半導体装置の小型、薄型形状の形態は維持したまま実装時の外部電極部２ｂ分の導通性を向上させることにある。また、この発明の目的は、上記半導体装置を量産性に優れかつ安価に生産できる製造方法を提供することにある。   An object of the present invention is to improve the electrical conductivity of the external electrode portion 2b during mounting while maintaining the small and thin shape of the semiconductor device. Another object of the present invention is to provide a manufacturing method capable of producing the semiconductor device with excellent mass productivity and at low cost.

この発明は、半導体素子Ｓが搭載されるアイランド部２ａと、該アイランド部２ａの周りに所定の間隔をおいて配置される１以上の電極部２ｂとを有し、上記アイランド部２ａ上に搭載した半導体素子Ｓと上記電極部２ｂとの間を電気的に接続した後樹脂封止して、アイランド部２ａと電極部２ｂのそれぞれ裏面が樹脂層４の底面と同一平面で露出して構成される半導体装置において、上記アイランド部２ａおよび電極部２ｂはそれぞれ電鋳により、裏面側の実装用金属薄膜１１とこの上面に一体に積層されるリード層１２の少なくとも二層構造からあらかじめ形成されていることを特徴とする（請求項１）。   The present invention has an island portion 2a on which a semiconductor element S is mounted and one or more electrode portions 2b arranged at a predetermined interval around the island portion 2a, and is mounted on the island portion 2a. The semiconductor element S and the electrode part 2b are electrically connected and then resin-sealed, and the back surfaces of the island part 2a and the electrode part 2b are exposed in the same plane as the bottom surface of the resin layer 4. In this semiconductor device, each of the island portion 2a and the electrode portion 2b is formed in advance by electroforming from at least a two-layer structure of a mounting metal thin film 11 on the back surface side and a lead layer 12 laminated integrally on the upper surface. (Claim 1).

この発明は、少なくとも電極部２ｂのリード層１２上面にボンディング用金属膜１３を形成したことを特徴とする（請求項２）   The present invention is characterized in that a metal film 13 for bonding is formed on at least the upper surface of the lead layer 12 of the electrode portion 2b (claim 2).

この発明は、導電性基板１の一面側に、半導体素子Ｓ搭載用のアイランド部２ａおよび半導体素子Ｓの電極Ｌと接続される電極部２ｂを形成するための所定パターンから成るレジストパターン層６を形成する工程と、上記基板１の露出面に、実装用金属薄膜１１をメッキ成長させるとともに該金属薄膜１１上に電鋳工程によりリード層１２を積層して成長させ一体化して、金属薄膜１１とこの上面に一体に積層されるリード層１２の少なくとも二層構造から成るアイランド部２ａおよび電極部２ｂを独立して形成する工程と、基板１よりレジストパターン層６を除去する工程と、上記アイランド部２ａに半導体素子Ｓを搭載した後、半導体素子Ｓと電極部２ｂとを電気的に接続する工程と、上記基板１を除去して、アイランド部２ａおよび電極部２ｂの金属薄膜１１の各裏面が、樹脂層４の底面と同一平面で露出した状態で形成される工程とを有する半導体装置の製造方法にある（請求項３）。   In the present invention, a resist pattern layer 6 having a predetermined pattern for forming an island portion 2a for mounting a semiconductor element S and an electrode portion 2b connected to an electrode L of the semiconductor element S is provided on one surface side of a conductive substrate 1. A metal thin film for mounting 11 is grown on the exposed surface of the substrate 1 by plating, and a lead layer 12 is laminated and grown on the metal thin film 11 by an electroforming process. A step of independently forming the island portion 2a and the electrode portion 2b having at least a two-layer structure of the lead layer 12 integrally laminated on the upper surface, a step of removing the resist pattern layer 6 from the substrate 1, and the island portion After the semiconductor element S is mounted on 2a, the step of electrically connecting the semiconductor element S and the electrode part 2b, the substrate 1 is removed, and the island part 2a and the electrode part 2b are electrically connected. Each rear surface of the part 2b of the metal thin film 11 is in a method of manufacturing a semiconductor device having a step formed in a state of being exposed at the bottom surface flush with the resin layer 4 (claim 3).

この発明は、少なくとも電極部２ｂのリード層１２上面に、メッキ工程によってボンディング用金属膜１３を一体に成長形成し、半導体素子Ｓと電気的に接続させるようにしたことを特徴とする（請求項４）   The present invention is characterized in that a bonding metal film 13 is integrally grown and formed on at least the upper surface of the lead layer 12 of the electrode portion 2b by a plating process so as to be electrically connected to the semiconductor element S. 4)

この発明では、半導体素子Ｓが搭載されるアイランド部２ａと、該アイランド部２ａの周りに所定の間隔をおいて配置される１以上の電極部２ｂとを有し、上記アイランド部２ａ上に搭載した半導体素子Ｓと上記電極部２ｂとの間を電気的に接続した後樹脂封止して、アイランド部２ａと電極部２ｂのそれぞれ裏面が樹脂層４の底面と同一平面で露出して構成される小型、薄型の半導体装置において、アイランド部２ａと電極部２ｂを電鋳で形成する際に、少なくとも電極部２ｂを構成するリード層１２の裏面側に、実装用の導電性に優れた金属薄膜１１をあらかじめ形成しておき、金属薄膜１１とリード層１２の二層構造とすることで、後工程で別途実装用のメッキを電極部２ｂ露出面に形成する必要が無く、実装時の電極導通性、信頼性に優れた小型、薄型の半導体装置を構成できる。（請求項１）   In the present invention, an island portion 2a on which a semiconductor element S is mounted and one or more electrode portions 2b arranged at a predetermined interval around the island portion 2a are mounted on the island portion 2a. The semiconductor element S and the electrode part 2b are electrically connected and then resin-sealed, and the back surfaces of the island part 2a and the electrode part 2b are exposed in the same plane as the bottom surface of the resin layer 4. In a small and thin semiconductor device, when the island portion 2a and the electrode portion 2b are formed by electroforming, a metal thin film having excellent conductivity for mounting on at least the back surface side of the lead layer 12 constituting the electrode portion 2b 11 is formed in advance and has a two-layer structure of the metal thin film 11 and the lead layer 12, so that it is not necessary to separately form a plating for mounting on the exposed surface of the electrode portion 2b in a later process, and the electrode conduction at the time of mounting Reliability Excellent small, can be constructed thin semiconductor device. (Claim 1)

少なくとも電極部２ｂのリード層１２上面にボンディング用金属膜１３を形成し、電極層を三層構造にしておけば、アイランド部２ａ上に搭載された半導体素子Ｓの電極Ｌと電極層２ｂとをワイヤボンディング等の方法で結線する際に、作業性、信頼性を向上させることができる（請求項２）   If the bonding metal film 13 is formed at least on the upper surface of the lead layer 12 of the electrode portion 2b and the electrode layer has a three-layer structure, the electrode L and the electrode layer 2b of the semiconductor element S mounted on the island portion 2a are connected to each other. Workability and reliability can be improved when connecting by a method such as wire bonding (Claim 2).

また、この発明では、導電性基板１の一面側に、半導体素子Ｓ搭載用のアイランド部２ａおよび半導体素子Ｓの電極と接続される電極部２ｂを形成するための所定パターンから成るレジストパターン層６を形成する工程と、上記基板１の露出面に、実装用金属薄膜１１をメッキ成長させるとともに該金属薄膜１１上に電鋳工程によりリード層１２を積層して成長させ一体化して、金属薄膜１１とこの上面に一体に積層されるリード層１２の少なくとも二層構造から成るアイランド部２ａおよび電極部２ｂを独立して形成する工程と、基板１よりレジストパターン層６を除去する工程と、上記アイランド部２ａに半導体素子Ｓを搭載した後、半導体素子Ｓと電極部２ｂとを電気的に接続する工程と、上記基板１を除去して、アイランド部２ａおよび電極部２ｂの金属薄膜１１の各裏面が、樹脂層４の底面と同一平面で露出した状態で形成される工程とを有する半導体装置の製造方法にあるので、基板１上でアイランド部２ａや電極部２ｂ等の電鋳製部品を電鋳工程で形成する際に、レジストパターン形成後に、実装用の接触面となる金属薄膜１１の形成とその後積層されるリード層１２との形成を、連続した工程の中で行うことができ、量産性に優れ、安価な生産を行うことが可能となる（請求項３）。   Further, in the present invention, the resist pattern layer 6 having a predetermined pattern for forming the island part 2a for mounting the semiconductor element S and the electrode part 2b connected to the electrode of the semiconductor element S on one surface side of the conductive substrate 1 is provided. Forming a metal thin film 11 for mounting on the exposed surface of the substrate 1 and laminating and integrating a lead layer 12 on the metal thin film 11 by an electroforming process. And a step of independently forming the island portion 2a and the electrode portion 2b having at least a two-layer structure of the lead layer 12 integrally laminated on the upper surface, a step of removing the resist pattern layer 6 from the substrate 1, and the island After the semiconductor element S is mounted on the part 2a, the step of electrically connecting the semiconductor element S and the electrode part 2b, the substrate 1 is removed, and the island part 2a And the step of forming the back surface of the metal thin film 11 of the electrode portion 2b in a state of being exposed in the same plane as the bottom surface of the resin layer 4, the island portion 2a and the When forming an electroformed part such as the electrode portion 2b in the electroforming process, after the resist pattern is formed, the formation of the metal thin film 11 that becomes a contact surface for mounting and the formation of the lead layer 12 that is subsequently laminated are continuously performed. It is possible to carry out in the process, which is excellent in mass productivity and can be produced at low cost (Claim 3).

少なくとも電極部２ｂのリード層１２上面に、ボンディング用金属膜１３をメッキ工程によって一体に成長形成させているので、電極結線時の信頼性を向上させるためのボンディング用金属膜１３を効率良く形成することができる（請求項４）。   Since the bonding metal film 13 is integrally grown and formed at least on the upper surface of the lead layer 12 of the electrode portion 2b by the plating process, the bonding metal film 13 for improving the reliability at the time of electrode connection is efficiently formed. (Claim 4).

（ａ）は、本発明の半導体装置の第１実施例を示す断面図，（ｂ）はその裏面図である。(A) is sectional drawing which shows 1st Example of the semiconductor device of this invention, (b) is the back view. （ａ）乃至（ｆ）は、本発明の第１実施例に示す半導体装置の製造方法を説明する断面図である。(A) thru | or (f) is sectional drawing explaining the manufacturing method of the semiconductor device shown in 1st Example of this invention. （ａ）乃至（ｅ）は、図２（ｆ）に続く半導体装置の製造方法を説明する断面図である。(A) thru | or (e) is sectional drawing explaining the manufacturing method of the semiconductor device following FIG.2 (f). 本発明の半導体装置の他の実施例を示す断面図である。It is sectional drawing which shows the other Example of the semiconductor device of this invention.

（第１実施例）図１乃至図３に本発明に係る半導体装置の構成および製造方法の第１実施例を示す。図１は、本発明に係るリードレス表面実装型の半導体装置を示しており、同図（ａ）は断面図、同図（ｂ）は底面図である。同図において、Ｓは半導体素子Ｓであって、アイランド部２ａ上に接着されて搭載されている。Ｌは半導体素子Ｓ上に形成された電極であり、上記アイランド部２ａと独立して並設された対応する電極部２ｂ２ｂと金等の導電性のワイヤ３により結線され、電気的に接続されている。上記半導体素子Ｓの搭載部分は熱硬化性エポキシ樹脂等の樹脂層４にて封止されており、上記アイランド部２ａと電極部２ｂの各裏面が樹脂層４と同一平面で露出した樹脂封止体が構成されている。   (First Embodiment) FIGS. 1 to 3 show a first embodiment of the structure and manufacturing method of a semiconductor device according to the present invention. 1A and 1B show a leadless surface mounting type semiconductor device according to the present invention, in which FIG. 1A is a sectional view and FIG. 1B is a bottom view. In the figure, S is a semiconductor element S, which is mounted on the island portion 2a by bonding. L is an electrode formed on the semiconductor element S, and is connected to the corresponding electrode part 2b2b arranged in parallel independently of the island part 2a by a conductive wire 3 such as gold, and is electrically connected. Yes. The mounting portion of the semiconductor element S is sealed with a resin layer 4 such as a thermosetting epoxy resin, and the back surfaces of the island portion 2a and the electrode portion 2b are exposed in the same plane as the resin layer 4. The body is composed.

ここで、図１（ａ）において、上記アイランド部２ａおよび電極部２ｂは、上端部周縁をそれぞれ庇状に張り出し形成して構成されており、樹脂封止体としての樹脂層４に対する喰い付き効果によって、アイランド部２ａ，電極部２ｂと樹脂層４との結着力が向上し、樹脂剥れやズレを効果的に防止できる構成となっている。また、アイランド部２ａおよび電極部２ｂは、それぞれ裏面側が金，スズ，ハンダ，パラジウム等の導電性に優れた実装用金属薄膜１１が０．０５〜１μｍ程度の厚さで形成され、その上面にニッケル等の電鋳金属から成るリード層１２が一体に積層された二層構造からあらかじめ形成されており、さらには、本実施例の場合、リード層１２の上面に、金，銀等から成るワイヤ３との結線力向上のためのボンディング用金属膜１３が０．３〜０．４μｍ厚程度形成されている。このボンディング用金属膜１３については必須の構成ではない。   Here, in FIG. 1 (a), the island part 2a and the electrode part 2b are formed by extending the peripheral edge of the upper end part in a bowl shape, and the biting effect on the resin layer 4 as the resin sealing body is formed. Thus, the binding force between the island portion 2a, the electrode portion 2b, and the resin layer 4 is improved, and the resin can be effectively prevented from peeling or shifting. In addition, the island part 2a and the electrode part 2b are each formed on the upper surface with a metal thin film 11 for mounting having excellent conductivity, such as gold, tin, solder, palladium, etc., having a thickness of about 0.05 to 1 μm on the back side. The lead layer 12 made of electroformed metal such as nickel is formed in advance from a two-layer structure in which the lead layer 12 is integrally laminated. Furthermore, in this embodiment, a wire made of gold, silver or the like is formed on the upper surface of the lead layer 12. The bonding metal film 13 for improving the connection force with the film 3 is formed to a thickness of about 0.3 to 0.4 μm. The bonding metal film 13 is not an essential configuration.

図２及び図３は上記半導体装置の製造方法を工程ごとに示しており、図２（ａ）はステンレスやアルミ，銅等の導電性の金属板、例えば本実施例の場合ＳＵＳ４３０により形成された基板１の両面に約５０μｍ厚のアルカリタイプの感光性フィルムレジストを熱圧着等の方法でラミネートする等して、感光性レジスト層５，５を密着させる工程であり、次いで図２（ｂ）のごとく基板１の一面側の感光性レジスト層５上に所定パターンのフィルムＦを配した状態で紫外線照射による両面露光を行った後現像処理を行い図２（ｃ）に示すような、基板１の一面側に所定のパターンニングを施したレジストパターン層６とのその裏面に硬化したレジスト層５を得る。   2 and 3 show the manufacturing method of the semiconductor device for each process, and FIG. 2A is formed of a conductive metal plate such as stainless steel, aluminum, or copper, for example, SUS430 in this embodiment. In this step, the photosensitive resist layers 5 and 5 are adhered to each other by laminating an alkali type photosensitive film resist having a thickness of about 50 μm on both surfaces of the substrate 1 by a method such as thermocompression bonding. As shown in FIG. 2 (c), after performing double-sided exposure by ultraviolet irradiation with the film F having a predetermined pattern placed on the photosensitive resist layer 5 on one side of the substrate 1, the development process is performed. A resist layer 5 having a predetermined patterning on one side and a cured resist layer 5 on the back side are obtained.

次いで、基板１の一面側のレジストパターン層６で覆われていない露出面に対し、必要に応じて化学エッチングによる表面酸化被膜除去や薬品による周知の化学処理等の表面活性化処理を行った後、図２（ｄ）に示すごとく基板１のレジストパターン層６６により規定された露出面に０．０５〜１μｍ厚で金を成長させて、実装用金属薄膜１１を形成する。本実施例の場合、微細パターン部の金メッキ処理において、金メッキの成長不良や付着不良の発生を事前に防止する目的で、上記化学エッチング等の化学処理を行い、基板１上の不活性膜を除去する工程を付加しているが、基板１の材質、メッキする金属の選択によっては、この工程は省略可能である。   Next, after the surface activation treatment such as removal of the surface oxide film by chemical etching or well-known chemical treatment with chemicals is performed on the exposed surface not covered with the resist pattern layer 6 on the one surface side of the substrate 1 as necessary. As shown in FIG. 2D, gold is grown on the exposed surface defined by the resist pattern layer 66 of the substrate 1 to a thickness of 0.05 to 1 μm to form the mounting metal thin film 11. In the case of this embodiment, in the gold plating process of the fine pattern portion, the chemical treatment such as the above chemical etching is performed to remove the inactive film on the substrate 1 for the purpose of preventing the occurrence of defective gold plating growth or adhesion failure in advance. However, depending on the selection of the material of the substrate 1 and the metal to be plated, this step can be omitted.

次いで、図２（ｅ）のごとく、ニッケルや銅，ニッケル−コバルト等の合金等から選択される電鋳金属、本実施例の場合はニッケルを上記金属薄膜１１上面に、一体に積層して電着することでリード層１２を形成し、上記金属薄膜１１とリード層１２の二層構造から成る、半導体搭載用のアイランド部２ａと、該アイランド部２ａに対して１以上の独立した電極部２ｂを、各々対として複数組を並列形成する。なお、本実施例においては、本工程で電着形成されるリード層１２をレジストパターン層６の厚みを越えて（例えば６０〜８０μｍ厚で）形成することで、アイランド部２ａおよび電極部２ｂの上端部周縁に庇状の張り出しを形成するようにしている。   Next, as shown in FIG. 2 (e), an electroformed metal selected from nickel, copper, an alloy such as nickel-cobalt, etc., in the case of this embodiment, nickel is laminated on the upper surface of the metal thin film 11 in an integrated manner. A lead layer 12 is formed by attaching, and a semiconductor mounting island portion 2a having a two-layer structure of the metal thin film 11 and the lead layer 12, and one or more independent electrode portions 2b with respect to the island portion 2a. Are formed in parallel in pairs. In this embodiment, the lead layer 12 formed by electrodeposition in this step is formed beyond the thickness of the resist pattern layer 6 (for example, 60 to 80 μm thick), so that the island portion 2a and the electrode portion 2b are formed. A hook-like overhang is formed on the periphery of the upper end.

次いで、必要に応じて各アイランド部２ａおよび電極部２ｂの表面に後述のワイヤボンディング時の結着力向上用の金メッキ等を０．３〜０．４μｍ厚で行い、ボンディング用金属膜１３を形成して、基板１の両面よりレジストパターン層６及びレジスト層５を除去することで、図２（ｆ）の状態となる。なお、レジストの除去法としてはアルカリ溶液による膨潤除去の方法等が考えられる。また、ボンディング用金属膜１３は金の他、銀，スズ等でも良い。   Next, as necessary, the surface of each island portion 2a and electrode portion 2b is subjected to gold plating for improving the binding force at the time of wire bonding, which will be described later, with a thickness of 0.3 to 0.4 μm to form a bonding metal film 13. Then, by removing the resist pattern layer 6 and the resist layer 5 from both surfaces of the substrate 1, the state shown in FIG. In addition, as a method for removing the resist, a method for removing swelling with an alkaline solution, or the like can be considered. The bonding metal film 13 may be gold, silver, tin, or the like.

次いで、図３（ａ）に示すごとく、半導体素子Ｓを公知の手法によりアイランド部２ａ上に接着して搭載するとともに、上記半導体素子Ｓ上の電極Ｌにこれと対応する電極層２ｂとを、図３（ｂ）のごとく、金線等の導電性のワイヤ３を用いて超音波ボンディング装置等により結線する。この時、電極層２ｂの上面に上記のごとくボンディング用金属膜１３としての金メッキを形成しておけば、結線力が一層向上し、結線ミスを低減できる。   Next, as shown in FIG. 3A, the semiconductor element S is mounted on the island portion 2a by a known method, and the electrode layer 2b corresponding to the electrode L on the semiconductor element S is mounted. As shown in FIG. 3B, the wire is connected by an ultrasonic bonding apparatus or the like using a conductive wire 3 such as a gold wire. At this time, if the gold plating as the bonding metal film 13 is formed on the upper surface of the electrode layer 2b as described above, the connection force is further improved, and connection errors can be reduced.

次いで、基板１上の半導体素子Ｓ搭載部分を、図３（ｃ）のごとく熱硬化性エポキシ樹脂等の樹脂層４でモールドし、基板１上に樹脂封止体を形成する。具体的には基板１の一面側をモールド金型（上型）に装着するとともに、モールド金型内にエポキシ樹脂をキャビティにより圧入するもので、基板１上に並列して形成した、複数組の半導体素子Ｓ搭載部が樹脂層４により連続して封止された状態となる。この場合基板１自体が樹脂モールド時における下型の機能を果たす。なお、モールド時に複数の基板１を並列に配置して、エポキシ樹脂をライナを通して各基板１と上金型との間に圧入するようにすれば、効率良く多数の樹脂封止を行うことが可能である。   Next, the semiconductor element S mounting portion on the substrate 1 is molded with a resin layer 4 such as a thermosetting epoxy resin as shown in FIG. 3C to form a resin sealing body on the substrate 1. Specifically, one surface side of the substrate 1 is attached to a mold die (upper die), and epoxy resin is press-fitted into the mold die by a cavity, and a plurality of sets formed in parallel on the substrate 1 The semiconductor element S mounting portion is continuously sealed by the resin layer 4. In this case, the substrate 1 itself functions as a lower mold during resin molding. If a plurality of substrates 1 are arranged in parallel at the time of molding and an epoxy resin is press-fitted between each substrate 1 and the upper mold through a liner, a large number of resins can be sealed efficiently. It is.

ここで、上記のごとくアイランド部２ａおよび電極部２ｂの上端部を、庇状に張り出し形成しておけば、樹脂層４による封止状態において、樹脂層４はくい込み状に位置した状態で硬化しているため、この喰い付き効果により、後工程の樹脂封止体からの基板１の剥離作業時に基板１を引き剥がし除去する際、アイランド部２ａおよび電極部２ｂは樹脂層４側に確実に残留し、基板１とともにくっついて引き離されることはなく、ズレや欠落等が効果的に防止でき、製造工程時の歩留まりが向上するとともに、さらに、完成した半導体装置自体の信頼性も向上する。   Here, if the upper end portions of the island portion 2a and the electrode portion 2b are formed so as to protrude in a bowl shape as described above, the resin layer 4 is cured in a state of being bitten in a sealed state by the resin layer 4. Therefore, due to this biting effect, when the substrate 1 is peeled and removed during the peeling operation of the substrate 1 from the resin sealing body in the subsequent process, the island portion 2a and the electrode portion 2b are reliably left on the resin layer 4 side. However, they are not separated from each other with the substrate 1, so that misalignment or omission can be effectively prevented, the yield during the manufacturing process is improved, and the reliability of the completed semiconductor device itself is also improved.

次いで、図３（ｄ）のごとく、樹脂封止体から基板１を除去することにより、樹脂封止体の底面には複数組のアイランド部２ａと電極部２ｂの各裏面が露出するとともに、アイランド部２ａ，電極部２ｂの各裏面と樹脂層４の底面は略同一平面となっている。すなわち、アイランド部２ａおよび電極部２ｂを搭載する実装用金属薄膜１１が樹脂層４の底面と略同一平面で露出する状態となっている。上記基板１を除去する方法としては、樹脂封止体から基板１を引き剥がす等強制的に剥離除去する方法の他、例えば基板１等を構成する材質に応じては、樹脂封止体側への影響のない溶剤等により基板１を溶解して除去する方法も含まれるものである。   Next, as shown in FIG. 3D, by removing the substrate 1 from the resin sealing body, the back surfaces of the plurality of sets of island portions 2a and electrode portions 2b are exposed on the bottom surface of the resin sealing body. The back surfaces of the portion 2a and the electrode portion 2b and the bottom surface of the resin layer 4 are substantially in the same plane. That is, the mounting metal thin film 11 on which the island portion 2 a and the electrode portion 2 b are mounted is in a state of being exposed in substantially the same plane as the bottom surface of the resin layer 4. As a method for removing the substrate 1, in addition to a method for forcibly peeling and removing the substrate 1 from the resin sealing body, for example, depending on the material constituting the substrate 1, A method of dissolving and removing the substrate 1 with an unaffected solvent or the like is also included.

次いで、図３（ｅ）のごとく樹脂封止体を切断線Ｘ−Ｘに沿って１つの半導体素子Ｓの対毎に切断して切り離すダイシングの工程を経て、個々の樹脂封止体すなわち半導体装置が完成するものである。   Next, as shown in FIG. 3E, each resin sealing body, that is, a semiconductor device, is subjected to a dicing process in which the resin sealing body is cut and separated into pairs of one semiconductor element S along the cutting line XX. Will be completed.

このように製造した半導体装置およびその製造方法によれば、ダイシングによる切り離し工程が終了した時点で、各半導体装置の裏面から露出する全ての電極層２ｂには導電性に優れた金等の実装用金属薄膜１１が形成されているため、その後のバレルメッキ等の工程に移ることなく、すぐにこの状態で搬送することができる。また、金属薄膜１１とリード層１２とは、連続した電鋳工程の中で積層して一体化形成するため、量産性にも優れている。   According to the semiconductor device manufactured as described above and the manufacturing method thereof, all electrode layers 2b exposed from the back surface of each semiconductor device are mounted on gold or the like having excellent conductivity when the separation process by dicing is completed. Since the metal thin film 11 is formed, the metal thin film 11 can be immediately transported in this state without moving to subsequent steps such as barrel plating. Moreover, since the metal thin film 11 and the lead layer 12 are laminated and integrated in a continuous electroforming process, they are excellent in mass productivity.

次に図４は他の実施例における半導体装置の断面図を示しており、第１実施例における半導体素子Ｓ搭載用アイランド部２ａおよび電極部２ｂの各上端部周縁の庇状の張り出しを形成しない形状とした。この場合、製造工程中、電鋳による各リード層１２形成時に、レジストパターン層６の厚みの範囲内で電鋳を行うようにすれば良い。また、本実施例に示すように、リード層１２上面にはボンディング用金属膜１３を必ずしも形成する必要は無い。   Next, FIG. 4 shows a cross-sectional view of a semiconductor device according to another embodiment, in which no ridge-like protrusions are formed at the periphery of each upper end portion of the semiconductor element S mounting island portion 2a and the electrode portion 2b in the first embodiment. Shaped. In this case, electroforming may be performed within the range of the thickness of the resist pattern layer 6 when the lead layers 12 are formed by electroforming during the manufacturing process. Further, as shown in the present embodiment, the bonding metal film 13 is not necessarily formed on the upper surface of the lead layer 12.

１ 導電性基板
２ａ アイランド部
２ｂ 電極部
４ 樹脂層
６ レジストパターン層
１１ 実装用金属薄膜
１２ リード層
１３ ボンディング用金属膜
Ｓ 半導体素子 DESCRIPTION OF SYMBOLS 1 Conductive substrate 2a Island part 2b Electrode part 4 Resin layer 6 Resist pattern layer 11 Metal thin film for mounting 12 Lead layer 13 Metal film for bonding S Semiconductor element

Claims (4)

半導体素子Ｓが搭載されるアイランド部２ａと、該アイランド部２ａの周りに所定の間隔をおいて配置される１以上の電極部２ｂとを有し、上記アイランド部２ａ上に搭載した半導体素子Ｓと上記電極部２ｂとの間を電気的に接続した後樹脂封止して、アイランド部２ａと電極部２ｂのそれぞれ裏面が樹脂層４の底面と同一平面で露出して構成される半導体装置において、
上記アイランド部２ａおよび電極部２ｂはそれぞれ電鋳により、裏面側の実装用金属薄膜１１とこの上面に一体に積層されるリード層１２の少なくとも二層構造からあらかじめ形成されていることを特徴とする半導体装置。 A semiconductor element S having an island part 2a on which the semiconductor element S is mounted and one or more electrode parts 2b arranged around the island part 2a at a predetermined interval, and mounted on the island part 2a. And the electrode part 2b are electrically connected and then resin-sealed, and in each of the semiconductor devices, the back surfaces of the island part 2a and the electrode part 2b are exposed in the same plane as the bottom surface of the resin layer 4. ,
Each of the island part 2a and the electrode part 2b is formed in advance by electroforming from at least a two-layer structure of a mounting metal thin film 11 on the back surface side and a lead layer 12 laminated integrally on the upper surface. Semiconductor device. 少なくとも電極部２ｂのリード層１２上面にボンディング用金属膜１３を形成したことを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein a bonding metal film is formed on at least the upper surface of the lead layer of the electrode portion. 導電性基板１の一面側に、半導体素子Ｓ搭載用のアイランド部２ａおよび半導体素子Ｓの電極Ｌと接続される電極部２ｂを形成するための所定パターンから成るレジストパターン層６を形成する工程と、
上記基板１の露出面に、実装用金属薄膜１１をメッキ成長させるとともに該金属薄膜１１上に電鋳工程によりリード層１２を積層して成長させ一体化して、金属薄膜１１とこの上面に一体に積層されるリード層１２の少なくとも二層構造から成るアイランド部２ａおよび電極部２ｂを独立して形成する工程と、
基板１よりレジストパターン層６を除去する工程と、
上記アイランド部２ａに半導体素子Ｓを搭載した後、半導体素子Ｓと電極部２ｂとを電気的に接続する工程と、
上記基板１を除去して、アイランド部２ａおよび電極部２ｂの金属薄膜１１の各裏面が、樹脂層４の底面と同一平面で露出した状態で形成される工程
とを有する半導体装置の製造方法。 Forming a resist pattern layer 6 having a predetermined pattern on one surface side of the conductive substrate 1 for forming the island portion 2a for mounting the semiconductor element S and the electrode portion 2b connected to the electrode L of the semiconductor element S; ,
A metal thin film for mounting 11 is grown on the exposed surface of the substrate 1 and a lead layer 12 is laminated and grown on the metal thin film 11 by an electroforming process so as to be integrated with the metal thin film 11 and the upper surface. Independently forming the island portion 2a and the electrode portion 2b having at least a two-layer structure of the lead layer 12 to be laminated;
Removing the resist pattern layer 6 from the substrate 1;
A step of electrically connecting the semiconductor element S and the electrode part 2b after mounting the semiconductor element S on the island part 2a;
A method of manufacturing a semiconductor device, comprising the step of removing the substrate 1 and forming each back surface of the metal thin film 11 of the island portion 2a and the electrode portion 2b in the same plane as the bottom surface of the resin layer 4. 少なくとも電極部２ｂのリード層１２上面に、メッキ工程によってボンディング用金属膜１３を一体に成長形成し、半導体素子Ｓと電気的に接続させるようにしたことを特徴とする請求項３に記載の半導体装置の製造方法。   4. The semiconductor according to claim 3, wherein a bonding metal film 13 is integrally grown and formed on at least the upper surface of the lead layer 12 of the electrode portion 2b by a plating process so as to be electrically connected to the semiconductor element S. Device manufacturing method.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60234380A (en) * 1984-05-07 1985-11-21 Nippon Mining Co Ltd Substrate for solar cell
JPS6142796B2 (en) * 1983-02-09 1986-09-24 Furukawa Electric Co Ltd
JPS61243193A (en) * 1985-04-18 1986-10-29 Nisshin Steel Co Ltd Method for plating pure gold on stainless steel
JP2002016181A (en) * 2000-04-25 2002-01-18 Torex Semiconductor Ltd Semiconductor device, manufacturing method thereof, and electrodeposition frame
JP2002289739A (en) * 2001-03-23 2002-10-04 Dainippon Printing Co Ltd Resin sealed type semiconductor device, and circuit member for semiconductor device and its manufacturing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6142796B2 (en) * 1983-02-09 1986-09-24 Furukawa Electric Co Ltd
JPS60234380A (en) * 1984-05-07 1985-11-21 Nippon Mining Co Ltd Substrate for solar cell
JPS61243193A (en) * 1985-04-18 1986-10-29 Nisshin Steel Co Ltd Method for plating pure gold on stainless steel
JP2002016181A (en) * 2000-04-25 2002-01-18 Torex Semiconductor Ltd Semiconductor device, manufacturing method thereof, and electrodeposition frame
JP2002289739A (en) * 2001-03-23 2002-10-04 Dainippon Printing Co Ltd Resin sealed type semiconductor device, and circuit member for semiconductor device and its manufacturing method

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