JP7132298B2 - Substrate for semiconductor device, method for manufacturing semiconductor device - Google Patents

Substrate for semiconductor device, method for manufacturing semiconductor device Download PDF

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JP7132298B2
JP7132298B2 JP2020156856A JP2020156856A JP7132298B2 JP 7132298 B2 JP7132298 B2 JP 7132298B2 JP 2020156856 A JP2020156856 A JP 2020156856A JP 2020156856 A JP2020156856 A JP 2020156856A JP 7132298 B2 JP7132298 B2 JP 7132298B2
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base material
semiconductor device
matrix
substrate
metal
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JP2020205451A (en
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佑也 五郎丸
達也 古賀
真幸 林田
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Maxell Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

本発明は、母型上にダイパッドおよび/またはリードを備える半導体装置用基板、該半導体装置用基板を用いた半導体装置の製造方法に関する。 The present invention relates to a semiconductor device substrate having a die pad and/or leads on a mother die, and a semiconductor device manufacturing method using the semiconductor device substrate.

ダイパッドやリードとなる金属部が形成された半導体装置用基板を準備し、該半導体装置用基板上に半導体素子を搭載して配線等の処理後、半導体素子や配線のある金属部の表面側を封止樹脂で封止し、金属部が底部に一部露出した構成とされる半導体装置は、その高さを低くして省スペース化が図れ、小型の半導体装置の分野で利用が進んでいる。こうした半導体装置は、主に、母型上にダイパッドやリードとなる金属部をめっき(電鋳)により半導体装置の所望個数分まとめて形成し、半導体素子が搭載され配線等の処理を経た金属部の表面側を封止樹脂で封止した後、母型のみを除去し、一体にまとまった状態の多数の半導体装置を個別に切り分ける、といった製造過程を経て製造されており、このような半導体装置の製造方法が特許文献1に開示されている。 A substrate for a semiconductor device is prepared on which a metal portion to be used as a die pad and leads is formed, a semiconductor element is mounted on the substrate for a semiconductor device, and after processing such as wiring, the surface side of the metal portion having the semiconductor element and the wiring is removed. A semiconductor device that is sealed with a sealing resin and has a structure in which the metal part is partially exposed at the bottom can be reduced in height to save space, and is being used in the field of small semiconductor devices. . Such semiconductor devices are mainly formed by plating (electroforming) a desired number of metal portions, which will become die pads and leads, on a matrix, and forming the desired number of semiconductor devices. After sealing the surface side of the semiconductor device with a sealing resin, only the matrix is removed, and a large number of integrated semiconductor devices are individually cut into pieces. is disclosed in Patent Document 1.

特開2004-214265号公報JP 2004-214265 A

近年、半導体装置の更なる小型化が要求されており、この要求に対応するためには、ダイパッドやリードとなる金属部の微小化が必要となる。しかしながら、ダイパッドやリードとなる金属部を微小化すれば、金属部と封止樹脂との接触面積が小さくなることによって密着力が弱まり、母型除去時に、金属部のズレやヌケが発生するおそれがある。 In recent years, there has been a demand for further miniaturization of semiconductor devices, and in order to meet this demand, it is necessary to miniaturize metal portions that serve as die pads and leads. However, miniaturizing the metal parts that become the die pads and leads reduces the contact area between the metal parts and the encapsulation resin, weakening the adhesion force, and there is a risk that the metal parts will be misaligned or missing when the matrix is removed. There is

本発明の目的は、上記課題を解消するためになされたものであり、金属部のズレやヌケの発生を防止できる半導体装置用基板、並びにこの半導体装置用基板を用いる半導体装置の製造方法を提供することにある。 SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems, and to provide a substrate for a semiconductor device capable of preventing the occurrence of misalignment and voids in metal portions, and a method for manufacturing a semiconductor device using this substrate for a semiconductor device. to do.

本発明は、装置底面に露出するリード3またはダイパッド4となる金属部が母型20上に形成された半導体装置用基板であって、母型20は最表層となる第1基材20aを含む複数の基材が積層形成されたものであり、金属部が形成されている側の第1基材20a表面の密着性より各基材間の密着性が弱い構成であることを特徴とする。これは、金属部が形成されている側の第1基材20a表面に比べて各基材間の密着性を弱く設定することで実現できる。また、母型20は第1基材20aと第2基材20bとが積層形成されており、第2基材20b上に第1基材20aがめっき形成されていることを特徴とする。また、第2基材20bがステンレスからなり、第1基材20aがニッケルからなることを特徴とする。 The present invention is a substrate for a semiconductor device in which a metal part that becomes the lead 3 or the die pad 4 exposed on the bottom surface of the device is formed on a mother mold 20, the mother mold 20 including a first base material 20a serving as the outermost layer. A plurality of substrates are laminated, and the adhesiveness between the substrates is weaker than the adhesiveness of the surface of the first substrate 20a on which the metal part is formed. This can be achieved by setting the adhesion between the base materials weaker than the surface of the first base material 20a on which the metal portion is formed. Further, the mother die 20 is characterized in that a first base material 20a and a second base material 20b are laminated, and the first base material 20a is plated on the second base material 20b. Also, the second base material 20b is made of stainless steel, and the first base material 20a is made of nickel.

また本発明は、装置底面に露出するリード3またはダイパッド4となる金属部が母型20上に形成された半導体装置用基板の製造方法であって、最表層となる第1基材20aを含む複数の基材を積層して母型20を形成する工程と、母型20の第1基材20a表面に、金属部を形成するためのレジストパターン層25を形成する工程と、レジストパターン層25から露出する第1基材20a表面に、金属部を形成する工程と、レジストパターン
層25を除去する工程とを有することを特徴とする。また、母型20はステンレスからなる第2基材20b上に、ニッケルめっきにより第1基材20aを積層形成したことを特徴とする。
The present invention also relates to a method of manufacturing a substrate for a semiconductor device in which a metal part that becomes the lead 3 or the die pad 4 exposed on the bottom surface of the device is formed on the mother mold 20, and includes the first base material 20a that becomes the outermost layer. forming a matrix 20 by laminating a plurality of base materials; forming a resist pattern layer 25 for forming a metal part on the surface of the first base material 20a of the matrix 20; and a step of removing the resist pattern layer 25 on the surface of the first base material 20a exposed from the substrate. Further, the matrix 20 is characterized in that the first base material 20a is laminated on the second base material 20b made of stainless steel by nickel plating.

また本発明は、半導体素子2と、該半導体素子2と接続されるリード3または半導体素子2が載置されるダイパッド4となる金属部とが樹脂により封止され、底面に金属部が露出する半導体装置の製造方法であって、最表層となる第1基材20aを含む複数の基材を積層して母型20を形成する工程と、母型20の第1基材20a表面に、金属部を形成するためのレジストパターン層25を形成する工程と、レジストパターン層25から露出する第1基材20a表面に、金属部を形成する工程と、レジストパターン層25を除去する工程と、金属部上に、半導体素子2を搭載するとともに、半導体素子2と金属部とを電気的に接続する工程と、半導体素子2及び金属部を樹脂で封止して樹脂封止体7を形成する工程と、樹脂封止体7から母型20を除去する工程を有し、母型20を除去する工程においては、金属部が形成されている第1基材20aを除く基材を除去した後に、第1基材20aを除去することを特徴とする。また、母型20はステンレスからなる第2基材20b上に、ニッケルめっきにより第1基材20aを積層形成したものであり、第2基材20bは剥離除去することを特徴とする。 Further, according to the present invention, the semiconductor element 2 and the lead 3 connected to the semiconductor element 2 or the metal part that becomes the die pad 4 on which the semiconductor element 2 is mounted are sealed with a resin, and the metal part is exposed on the bottom surface. A method for manufacturing a semiconductor device, comprising a step of forming a matrix 20 by laminating a plurality of substrates including a first substrate 20a serving as an outermost layer; a step of forming a resist pattern layer 25 for forming a portion; a step of forming a metal portion on the surface of the first base material 20a exposed from the resist pattern layer 25; a step of removing the resist pattern layer 25; A step of mounting the semiconductor element 2 on the part and electrically connecting the semiconductor element 2 and the metal part, and a process of sealing the semiconductor element 2 and the metal part with resin to form a resin sealing body 7 and a step of removing the matrix 20 from the resin sealing body 7, and in the step of removing the matrix 20, after removing the base material excluding the first base material 20a on which the metal part is formed, It is characterized by removing the first base material 20a. Further, the matrix 20 is formed by laminating the first base material 20a by nickel plating on the second base material 20b made of stainless steel, and the second base material 20b is peeled off.

本発明によれば、最表層となる第1基材を含む複数の基材が積層形成された母型上に、リードまたはダイパッドとなる金属部を形成した半導体装置用基板を用いることにより、生産性、信頼性に優れた半導体装置を提供することができる。 According to the present invention, by using a semiconductor device substrate in which a metal part serving as a lead or a die pad is formed on a master mold in which a plurality of base materials including a first base material serving as the outermost layer are laminated, a production process can be performed. Thus, a semiconductor device with excellent performance and reliability can be provided.

本発明の第1実施形態に係る半導体装置用基板の断面図である。1 is a cross-sectional view of a semiconductor device substrate according to a first embodiment of the present invention; FIG. 本発明の第1実施形態に係る半導体装置の断面図及び斜視図である。1A and 1B are a sectional view and a perspective view of a semiconductor device according to a first embodiment of the present invention; FIG. 本発明の第1実施形態に係る半導体装置用基板の製造方法を説明するための図である。FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor device substrate according to the first embodiment of the present invention; 本発明の第1実施形態に係る半導体装置用基板の製造方法を説明するための図である。FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor device substrate according to the first embodiment of the present invention; 本発明の第1実施形態に係る半導体装置の製造方法を説明するための図である。It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第1実施形態の他実施例に係る半導体装置用基板の断面図である。FIG. 4 is a cross-sectional view of a semiconductor device substrate according to another example of the first embodiment of the present invention;

(第1実施形態) 図1乃至図5に本発明の第1実施形態に係る半導体装置用基板及び半導体装置を示す。図1は、本実施形態に係る半導体装置用基板の断面図である。図2(a)は、本実施形態に係る半導体装置の断面図であり、図2(b)は、本実施形態に係る半導体装置の斜視部である。 (First Embodiment) FIGS. 1 to 5 show a semiconductor device substrate and a semiconductor device according to a first embodiment of the present invention. FIG. 1 is a cross-sectional view of a semiconductor device substrate according to this embodiment. 2A is a cross-sectional view of the semiconductor device according to this embodiment, and FIG. 2B is a perspective view of the semiconductor device according to this embodiment.

半導体装置用基板10は、母型20上にリード3やダイパッド4となる金属部が形成されたものである。そして、半導体装置1は、この半導体装置用基板10を用いて製造されるリードレス表面実装型であり、半導体素子2と、この半導体素子2が載置されるダイパッド4と、半導体素子2を囲むように配されたリード3と、半導体素子2の上面に形成された電極5とリード3とを電気的に接続するワイヤ6とを有し、これら半導体素子2、リード3、ダイパッド4およびワイヤ6はエポキシ樹脂などの樹脂により封止され、全体としてブロック形状に形成された樹脂封止体7が構成され、底面側には、ダイパッド4とリード3とが露出している。本実施形態では、図1及び図2に示すように、1つの半導体素子2と、6つ(複数個)のリード3と、1つのダイパッド4とを有し、樹脂により封止されている。なお、ダイパッド4はない構成であっても良く、その場合は、半導体素子2とリード3とがフリップチップボンディングなどにて接続される。 A substrate 10 for a semiconductor device is obtained by forming a metal portion that will become the lead 3 and the die pad 4 on a mother mold 20 . The semiconductor device 1 is a leadless surface mount type manufactured using this semiconductor device substrate 10, and includes a semiconductor element 2, a die pad 4 on which the semiconductor element 2 is mounted, and a semiconductor element 2 surrounding the semiconductor element 2. and wires 6 for electrically connecting the leads 3 to the electrodes 5 formed on the upper surface of the semiconductor element 2. These semiconductor element 2, leads 3, die pad 4 and wires 6 is sealed with a resin such as epoxy resin to form a block-shaped resin sealing body 7 as a whole, and the die pad 4 and the leads 3 are exposed on the bottom side. In this embodiment, as shown in FIGS. 1 and 2, one semiconductor element 2, six (plural) leads 3, and one die pad 4 are provided and sealed with resin. A configuration without the die pad 4 may be used, in which case the semiconductor element 2 and the leads 3 are connected by flip-chip bonding or the like.

母型20は、最表層となる第1基材20aを含む複数の基材が積層して構成され、図1に示すように、第2基材20b上に第1基材20aを積層してなるものである。この第1基材20aおよび第2基材20bは、ステンレス、アルミニウム、ニッケル、銅などの金属で形成されており、第1基材20aと第2基材20bとは、同一金属で構成されても良いし、異なる金属で構成されても良い。第1基材20aとしては、この表面に形成される第1金属層12が拡散しがたい基材を用いることが好ましい。ここで、後述する半導体装置の製造方法における母型除去工程、特に、母型20を剥離除去する場合において、リード3やダイパッド4のズレやヌケを防止できる母型20の構成について説明すると、第1基材20aは第2基材20bより薄く形成すると良い。具体的には、第1基材20aの厚さは10~30μm、第2基材20bの厚さは100~500μmが好ましい。また、第1基材20aは第2基材20bより柔らかい材質で形成すると良い。例えば、第2基材20bがステンレスからなり第1基材20aがニッケルからなるもの、第2基材20bがニッケルからなり第1基材20aが銅からなるものなどが挙げられる。また、第2基材20b表面に剥離処理を施した上で第1基材20aを形成すると良い。この剥離処理としては、酸化膜や有機膜などの形成が挙げられる。また、第1基材20aと第2基材20bとをレジストや接着剤などの樹脂を介して接合すると良い。この場合、突弧面あるいは凹弧面どうしが対向する状態で接合することで、第1基材20aおよび第2基材20bの二次元ないしは三次元曲面状の反りが相殺され、母型20を平坦状に形成することができるので、この母型20上に形成されるリード3やダイパッド4の平坦度を向上でき、半導体装置の信頼性を向上できる。なお、第1基材20aと第2基材20bとをレジストや接着剤などの樹脂を介して接合した場合の母型20の除去方法は、引き剥がしによる剥離除去や処理液を用いた溶解除去にて行うが、第1基材20aと第2基材20bとをレジストを介して接合した場合は、第1基材20aから第2基材20bを剥離除去し難いので、第1基材20aおよび/または第2基材20bの表面にレジストを形成した後に半露光を行うと良い。このように、母型20として上述したような構成が挙げられるが、第1基材20aと第2基材20bに求められる機能としては、リード3やダイパッド4となる金属部が形成される第1基材20aは、高強度や柔軟性を備えたものが良く、第1基材20aが積層形成される第2基材20bは、可撓性やコシを備えたものが良い。 The matrix 20 is configured by laminating a plurality of base materials including a first base material 20a serving as the outermost layer, and as shown in FIG. It will be. The first base material 20a and the second base material 20b are made of a metal such as stainless steel, aluminum, nickel, or copper, and the first base material 20a and the second base material 20b are made of the same metal. , or may be composed of different metals. As the first base material 20a, it is preferable to use a base material on which the first metal layer 12 formed on the surface is difficult to diffuse. Here, the configuration of the matrix 20 that can prevent the lead 3 and the die pad 4 from being dislocated or missing in the matrix removing process in the manufacturing method of the semiconductor device to be described later, particularly in the case of removing the matrix 20 by peeling, will be described. The first base material 20a is preferably formed thinner than the second base material 20b. Specifically, the thickness of the first base material 20a is preferably 10 to 30 μm, and the thickness of the second base material 20b is preferably 100 to 500 μm. Also, the first base material 20a is preferably made of a softer material than the second base material 20b. For example, the second base material 20b may be made of stainless steel and the first base material 20a may be made of nickel, or the second base material 20b may be made of nickel and the first base material 20a may be made of copper. Moreover, it is preferable to form the first base material 20a after applying a peeling treatment to the surface of the second base material 20b. Formation of an oxide film, an organic film, or the like can be cited as the peeling treatment. Moreover, it is preferable to bond the first base material 20a and the second base material 20b via a resin such as a resist or an adhesive. In this case, the two-dimensional or three-dimensional curved warp of the first base material 20a and the second base material 20b is offset by joining the convex arc surfaces or the concave arc surfaces facing each other, and the matrix 20 is formed. Since they can be formed flat, the flatness of the leads 3 and die pads 4 formed on the matrix 20 can be improved, and the reliability of the semiconductor device can be improved. When the first base material 20a and the second base material 20b are bonded via a resin such as a resist or an adhesive, the method for removing the matrix 20 may be removal by peeling off or removal by dissolution using a treatment liquid. However, when the first base material 20a and the second base material 20b are bonded via a resist, it is difficult to separate and remove the second base material 20b from the first base material 20a. And/or semi-exposure may be performed after forming a resist on the surface of the second base material 20b. As described above, the matrix 20 may have the above-described configuration, but the functions required of the first base material 20a and the second base material 20b are the metal parts forming the leads 3 and the die pad 4. The first base material 20a preferably has high strength and flexibility, and the second base material 20b, on which the first base material 20a is laminated, preferably has flexibility and stiffness.

リード3とダイパッド4は、単層あるいは複数の層が積層して構成され、本実施形態では、第1金属層12、第2金属層14、第3金属層層16を下方側から順に積層してなるものである。第1金属層12は、金・銀・パラジウム・スズ・ハンダなど導電性やはんだぬれに優れた金属からなり、0.01~1μm程度の厚さで形成されている。第2金属層14は、ニッケル・銅・これら各金属の合金などからなり、20~100μm程度の厚さで形成されている。第3金属層16は、金・銀・パラジウム・白金などの金属からなり、0.01~1μm程度の厚さで形成されている。なお、ダイパッド4においては、第3金属層16を形成しなくても良い。 The lead 3 and the die pad 4 are constructed by laminating a single layer or a plurality of layers. It is a thing. The first metal layer 12 is made of a metal such as gold, silver, palladium, tin, solder, or the like, which is excellent in conductivity and solder wettability, and is formed with a thickness of about 0.01 to 1 μm. The second metal layer 14 is made of nickel, copper, an alloy of these metals, or the like, and is formed with a thickness of about 20 to 100 μm. The third metal layer 16 is made of metal such as gold, silver, palladium, and platinum, and is formed with a thickness of about 0.01 to 1 μm. Note that the third metal layer 16 may not be formed on the die pad 4 .

図3は、上記半導体装置用基板の製造方法を工程ごとに示している。まず、図3(a)に示すごとく、ステンレスからなる第2基材20b上にニッケルめっきにより第1基材20aを積層形成した母型20上に、アルカリタイプの感光性レジストを熱圧着などの方法でラミネートしてレジスト層21を形成し、母型20の一面側のレジスト層21上に所定パターン22を有するパターンフィルム23(ガラスマスク)を配した状態で紫外線の照射による露光を行った後、現像処理を行うことで、図3(b)に示すように、母型20の一面側にレジスト体25aを有するレジストパターン層25を得る。なお、レジストパターン層25は、パターンフィルム23(ガラスマスク)を用いずに、直接描画にて形成するようにしても良い。 FIG. 3 shows each step of the method for manufacturing the semiconductor device substrate. First, as shown in FIG. 3(a), an alkali type photosensitive resist is applied by thermocompression bonding or the like on a master mold 20 in which a first base material 20a is laminated on a second base material 20b made of stainless steel by nickel plating. After forming a resist layer 21 by laminating by a method, and exposing a pattern film 23 (glass mask) having a predetermined pattern 22 on the resist layer 21 on one surface side of the master mold 20, exposure is performed by irradiating ultraviolet rays. 3(b), a resist pattern layer 25 having a resist body 25a on one side of the mother die 20 is obtained. The resist pattern layer 25 may be formed by direct drawing without using the pattern film 23 (glass mask).

次いで、図3(c)に示すごとく、母型20の一面側の第1基材20aにめっきを施すことにより、リード3及びダイパッド4を形成する。 Next, as shown in FIG. 3(c), the lead 3 and the die pad 4 are formed by plating the first substrate 20a on one side of the mother die 20. Then, as shown in FIG.

このダイパッド4及びリード3の形成工程について具体的に説明すると、まず、図4(a)に示すごとく、母型20の第1基材20aのレジストパターン層25で覆われていない露出面に対し、めっき前処理(酸浸漬、陰極電解、化学エッチング、ストライクめっきなど)や剥離処理を行った後、係る露出面に0.05~1μm厚で金をめっき成長させて、第1金属層12を形成する。本実施形態のように、母型20(第1基材20a)上に金の薄層(第1金属層12)をめっき成長させる場合、金めっきの成長不良や付着不良の発生を事前に防止する目的で、上記めっき前処理を適宜行い、母型20(第1基材20a)上の不活性膜を除去しているが、母型20(第1基材20a)やめっき金属(第1金属層12)の材質や厚さによって、上記めっき前処理を適宜選択して行ったり、省略したりする。剥離処理も同様である。なお、母型20の露出面にめっき前処理として化学エッチングを行った場合、その露出面は粗面となるとともに、化学エッチングされた分だけ凹み形状となる。 Specifically, the process of forming the die pad 4 and the leads 3 will be described. First, as shown in FIG. , After performing plating pretreatment (acid immersion, cathodic electrolysis, chemical etching, strike plating, etc.) and stripping treatment, gold is plated to a thickness of 0.05 to 1 μm on the exposed surface to form the first metal layer 12. Form. When a thin layer of gold (first metal layer 12) is plated on the matrix 20 (first base material 20a) as in the present embodiment, the occurrence of poor growth and poor adhesion of gold plating can be prevented in advance. In order to achieve this, the pretreatment for plating is appropriately performed to remove the inert film on the matrix 20 (first base material 20a). Depending on the material and thickness of the metal layer 12), the above pre-plating treatment is appropriately selected or omitted. The peeling process is also the same. When the exposed surface of the matrix 20 is subjected to chemical etching as pre-plating treatment, the exposed surface becomes a rough surface and has a concave shape corresponding to the amount of the chemical etching.

次いで、図4(b)に示すごとく、上記第1金属層12の表面に20~80μm厚でニッケルをめっき(電鋳)して、第2金属層14を積層形成する。なお、本工程において、第2金属層14をレジストパターン層25の厚みを越えてめっき(電鋳)形成することで、ダイパッド4及びリード3の上端部周縁に張出部を形成することができる。 Next, as shown in FIG. 4B, the surface of the first metal layer 12 is plated (electroformed) with nickel to a thickness of 20 to 80 μm to form a second metal layer 14 as a laminate. In this step, by plating (electroforming) the second metal layer 14 so as to exceed the thickness of the resist pattern layer 25, it is possible to form overhangs on the periphery of the upper ends of the die pad 4 and the leads 3. .

次いで、図4(c)に示すごとく、後述のワイヤボンディング時の結着力を向上させるために、第2金属層14の表面に1.0~2.5μm厚で銀をめっき成長させて、第3金属層16を積層形成する。その後、レジストパターン層25を除去することで、図4(d)や図1に示すごとく、母型20上にダイパッド4及びリード3が形成された半導体装置用基板が得られる。なお、本実施形態のように、第2金属層14をニッケルやニッケル合金とし、この第2金属層14上にめっき成長させる第3金属層16を銀とした場合、ニッケルと銀は相性が悪いため、銀めっきの成長不良や付着不良が生じるおそれがあるので、第2金属層14上に金やパラジウムなどをめっき形成する、もしくは第2金属層14上に金、銀、銅などによるストライクめっきを施したうえで、第3金属層16をめっき成長させることで、係る不良の発生を防止することができる。また、第3金属層16は、第2金属層14の表面全面ではなく、ワイヤボンディングされる箇所に部分的に形成されたものでも良い。 Next, as shown in FIG. 4(c), silver is plated to a thickness of 1.0 to 2.5 μm on the surface of the second metal layer 14 in order to improve binding strength during wire bonding, which will be described later. 3. A metal layer 16 is laminated. Thereafter, by removing the resist pattern layer 25, a semiconductor device substrate having the die pad 4 and the leads 3 formed on the matrix 20 is obtained as shown in FIG. 4(d) and FIG. Note that when the second metal layer 14 is made of nickel or a nickel alloy and the third metal layer 16 grown by plating on the second metal layer 14 is made of silver as in the present embodiment, nickel and silver are not compatible with each other. Therefore, the second metal layer 14 is plated with gold, palladium, or the like, or the second metal layer 14 is strike-plated with gold, silver, copper, or the like. Then, the third metal layer 16 is grown by plating, thereby preventing the occurrence of such defects. Also, the third metal layer 16 may be formed not on the entire surface of the second metal layer 14 but on a portion thereof to be wire-bonded.

続いて、半導体装置の製造方法を説明する。図5は、上述の半導体装置用基板を用いた半導体装置の製造方法を工程ごとに示している。まず、図5(a)に示すごとく、半導体素子2をダイボンディングによりダイパッド4上に接着して搭載するとともに、図5(b)に示すごとく、金や銅などの導電性のワイヤ6を用いて超音波ボンディング装置等により上記半導体素子2上の電極5とこれに対応するリード3とを結線する。係る結線においては、電極5の部分はボールボンディング、リード3部分はウェッジボンディングが好ましい。このように、リード3においては、ワイヤ6の結線箇所に第3金属層16が形成されており、この第3金属層16としてリード3とワイヤ6との結着性に優れた金属を採用することにより、結線力が一層向上し、結線ミスを低減できる。 Next, a method for manufacturing a semiconductor device will be described. FIG. 5 shows each step of a method of manufacturing a semiconductor device using the substrate for a semiconductor device described above. First, as shown in FIG. 5A, a semiconductor element 2 is mounted on a die pad 4 by die bonding, and as shown in FIG. Then, the electrodes 5 on the semiconductor element 2 and the corresponding leads 3 are connected by an ultrasonic bonding device or the like. In such connection, ball bonding is preferably used for the electrode 5 portion, and wedge bonding is preferably used for the lead 3 portion. In this way, the lead 3 has the third metal layer 16 formed at the connection point of the wire 6, and a metal having excellent binding properties between the lead 3 and the wire 6 is used as the third metal layer 16. As a result, the connection force is further improved, and connection errors can be reduced.

次いで、母型20上の半導体素子2搭載部分を、図5(c)に示すごとく、熱硬化性エポキシ樹脂などの樹脂38でモールドし、母型20上に樹脂封止体7を形成する。具体的には、母型20の一面側をモールド金型(上型)に装着するとともに、モールド金型内に封止樹脂38をキャビティにより圧入するもので、母型20上に並列して形成した、複数組の半導体素子2搭載部分が封止樹脂38により連続して封止された状態の樹脂封止体7が形成される。この場合、母型20自体が樹脂モールド時における下型の機能を果たす。なお、モールド時に複数の母型20を並列に配置して、ライナを通して封止樹脂38を各
母型20と上金型との間に圧入するようにすれば、効率良く多数の樹脂封止を行うことが可能である。
Next, as shown in FIG. 5(c), the portion of the mold 20 on which the semiconductor element 2 is mounted is molded with a resin 38 such as a thermosetting epoxy resin to form the resin sealing body 7 on the mold 20. As shown in FIG. Specifically, one surface side of the mother die 20 is attached to a mold (upper mold), and a sealing resin 38 is press-fitted into the mold through a cavity. Thus, a resin sealing body 7 is formed in which a plurality of sets of semiconductor element 2 mounting portions are continuously sealed with the sealing resin 38 . In this case, the mother die 20 itself functions as a lower die during resin molding. If a plurality of mother dies 20 are arranged in parallel during molding and the sealing resin 38 is press-fitted between each mother die 20 and the upper mold through a liner, a large number of resin sealing can be efficiently performed. It is possible to do

次いで、図5(d)に示すごとく、樹脂封止体7から母型20を除去する。上記母型20を除去する方法としては、樹脂封止体7から母型20を引き剥がすことにより剥離除去する。詳しくは、まず、母型20を構成する第1基材20aから第2基材20bを剥離除去したのち、樹脂封止体7から第1基材20aを剥離除去する。この時、第2基材20b表面に剥離処理を施した上で第1基材20aを積層形成することで、第2基材20bの剥離除去が容易となる。この他の母型20の除去方法としては、第1基材20aを溶解可能な材質で形成することで、第1基材20aから第2基材20bを除去したのち、樹脂封止体7に対して影響のない処理液などを用いて第1基材20aを溶解(エッチング)することにより溶解除去できる。このように、樹脂封止体7から母型20を除去することにより、樹脂封止体7の底面には、複数組のリード3とダイパッド4の各裏面が露出するとともに、ダイパッド4とリード3の各裏面と樹脂封止体7の底面は略同一平面となっている。すなわち、ダイパッド4とリード3における第1金属層12が樹脂封止体7の底面と略同一平面で露出する状態となっている。 Next, as shown in FIG. 5(d), the matrix 20 is removed from the resin sealing body 7. Next, as shown in FIG. As a method for removing the matrix 20, the matrix 20 is peeled off from the resin sealing body 7 to be removed. Specifically, first, the second base material 20b is peeled off from the first base material 20a constituting the matrix 20, and then the first base material 20a is peeled off from the resin sealing body . At this time, the surface of the second base material 20b is subjected to peeling treatment, and then the first base material 20a is layered, thereby facilitating the peeling and removal of the second base material 20b. As another method for removing the matrix 20, the first base material 20a is made of a dissolvable material, and after removing the second base material 20b from the first base material 20a, the resin sealing body 7 is removed. It can be dissolved and removed by dissolving (etching) the first base material 20a using a treatment liquid or the like that does not affect the first base material 20a. By removing the matrix 20 from the resin sealing body 7 in this way, the back surfaces of the plurality of sets of the leads 3 and the die pads 4 are exposed on the bottom surface of the resin sealing body 7 , and the die pads 4 and the leads 3 are exposed on the bottom surface of the resin sealing body 7 . and the bottom surface of the resin sealing body 7 are substantially flush with each other. That is, the first metal layer 12 of the die pad 4 and the leads 3 is exposed substantially flush with the bottom surface of the resin sealing body 7 .

次いで、図5(e)に示すごとく、樹脂封止体を切断線X-Xに沿って1つの半導体素子2毎に切断して切り離すダイシング工程を経て、個々の樹脂封止体7、すなわち、半導体装置1が完成する。 Next, as shown in FIG. 5(e), through a dicing step of cutting the resin sealing body along the cutting line XX for each semiconductor element 2, the individual resin sealing bodies 7, that is, The semiconductor device 1 is completed.

このような半導体装置の製造方法によれば、金属部形成側の第1基材20a表面に比べて第1基材20aと第2基材20bとの間の密着性を弱くした母型20を用意し、この母型20の除去工程において、第2基材20bを除去したのちに第1基材20aを除去するように、第1基材20aと第2基材20bとの除去を段階的に行うことにより、単層母型に比べ、母型除去時におけるリード3やダイパッド4の変形・ズレ・ヌケを可及的に防ぐことができる。また、第1基材20aをめっきにより形成すれば、第1基材20aを薄く形成することができるだけでなく、めっき時における光沢剤の添加量や電流密度を調整することで、第1基材20aの表面粗さを容易に設定することができるため、母型20(第1基材20a)の平面度を高めることができ、ひいては母型20(第1基材20a)上に形成するリード3やダイパッド4の平面度を高めることができるので、半導体装置の信頼性を向上できる。また、母型20の第2基材20bだけを除去した状態(第1基材20a上に樹脂封止体7が形成された状態)で搬送や保管をすれば、第2基材20bがない分だけ、搬送や保管が容易になるとともに、第1基材20aがリード3やダイパッド4の裏面の酸化や塵埃付着を防止する保護層としての役割を果たすことができる。なお、母型20を剥離除去するにあたり、リード3やダイパッド4となる金属部、封止樹脂38、第1基材20a、第2基材20bにおける各層間の密着性の強さとしては、「金属部(第1金属層12)と第1基材20aとの間>第1基材20aと第2基材20bとの間、封止樹脂38と第1基材20aとの間>第1基材20aと第2基材20bとの間、金属部と封止樹脂38との間>金属部(第1金属層12)と第1基材20aとの間」の条件を満たすのが望ましい。係る条件は、第1基材20aおよび第2基材20bの表面へのめっき前処理や剥離処理を適宜選択して行うことで設定できる。 According to such a method of manufacturing a semiconductor device, the master mold 20 is formed in which the adhesion between the first base material 20a and the second base material 20b is weaker than that of the surface of the first base material 20a on the metal part forming side. In the step of removing the master mold 20, the first base material 20a and the second base material 20b are removed step by step so that the first base material 20a is removed after the second base material 20b is removed. By doing so, it is possible to prevent the leads 3 and the die pad 4 from being deformed, displaced, and missing as much as possible when the matrix is removed, as compared with the case of the single-layer matrix. In addition, if the first base material 20a is formed by plating, not only can the first base material 20a be formed thin, but also by adjusting the amount of the brightener added and the current density during plating, the first base material can be thinned. Since the surface roughness of the matrix 20a can be easily set, the flatness of the matrix 20 (first base material 20a) can be improved, and the leads formed on the matrix 20 (first base material 20a) can be improved. Since the flatness of 3 and die pad 4 can be improved, the reliability of the semiconductor device can be improved. Further, if the mold 20 is transported or stored in a state in which only the second base material 20b is removed (a state in which the resin sealing body 7 is formed on the first base material 20a), there is no second base material 20b. Accordingly, transportation and storage are facilitated, and the first base material 20a can serve as a protective layer for preventing oxidation and adhesion of dust to the back surfaces of the leads 3 and the die pad 4. FIG. In peeling and removing the master mold 20, the strength of adhesion between the layers of the metal portion that becomes the lead 3 and the die pad 4, the sealing resin 38, the first base material 20a, and the second base material 20b is as follows: Between the metal portion (first metal layer 12) and the first base material 20a>Between the first base material 20a and the second base material 20b, Between the sealing resin 38 and the first base material 20a>First Between the base material 20a and the second base material 20b, between the metal part and the sealing resin 38>between the metal part (first metal layer 12) and the first base material 20a". . Such conditions can be set by appropriately selecting pre-plating treatment and peeling treatment on the surfaces of the first base material 20a and the second base material 20b.

また、リード3及びダイパッド4を構成する第1金属層12、第2金属層14、第3金属層16を連続しためっき・電鋳工程の中で積層形成するので、量産性に優れ、さらに、各半導体装置の裏面からは、導電性やはんだぬれ性に優れた金属からなる第1金属層12が露出されるため、その後のバレルめっきや無電解めっきを行うことなく、実装基板への実装工程に移ることができる点でも、量産性に優れる。 Moreover, since the first metal layer 12, the second metal layer 14, and the third metal layer 16, which constitute the lead 3 and the die pad 4, are laminated in a continuous plating/electroforming process, the mass productivity is excellent. Since the first metal layer 12 made of a metal with excellent conductivity and solder wettability is exposed from the back surface of each semiconductor device, the mounting process on the mounting board can be performed without subsequent barrel plating or electroless plating. It is also excellent in mass productivity in terms of being able to move to.

本実施形態において、図4に示すリード3やダイパッド4となる金属部(第2金属層14)を形成する際に、レジストパターン層25の厚みを越えてめっき(電鋳)形成することで、図6に示すように、ダイパッド4及びリード3の上端部周縁に張出部を形成することができる。このように、ダイパッド4やリード3の上端部に張出部を有することにより、封止樹脂38による封止状態において、封止樹脂38はくい込み状に位置した状態で硬化するため、この喰い付き効果(アンカー効果)により、後工程の樹脂封止体7から母型20を引き剥がし除去するときに、ダイパッド4やリード3は樹脂封止体7側に確実に残留し、母型20とともにくっついて引き離されることはなく、ズレや欠落などを防止できる。さらに、上記のように、母型20を積層構造とすることで、母型20除去時のダイパッド4やリード3のズレや欠落などをより効果的に防止でき、製造時の歩留まりが向上でき、係る製造方法によって完成される半導体装置自体の信頼性も向上する。 In this embodiment, when forming the metal portion (second metal layer 14) that becomes the lead 3 and the die pad 4 shown in FIG. As shown in FIG. 6, the die pad 4 and the leads 3 can be formed with overhangs on their upper edges. Since the die pad 4 and the upper ends of the leads 3 have protrusions in this manner, the encapsulation resin 38 hardens in a state of being bitten in when the encapsulation resin 38 is sealed. Due to the effect (anchor effect), when the mother die 20 is peeled off and removed from the resin encapsulant 7 in the post-process, the die pad 4 and the leads 3 reliably remain on the resin encapsulant 7 side and stick together with the mother die 20. Therefore, it is possible to prevent misalignment and missing. Further, as described above, by forming the matrix 20 to have a laminated structure, it is possible to more effectively prevent the die pad 4 and the leads 3 from being displaced or missing when the matrix 20 is removed, thereby improving the manufacturing yield. The reliability of the semiconductor device itself completed by such a manufacturing method is also improved.

1 半導体装置
2 半導体素子
3 リード
4 ダイパッド
5 電極
6 ワイヤ
7 樹脂封止体
10 半導体装置用基板
12 第1金属層
14 第2金属層
16 第3金属層
20 母型
20a 第1基材
20b 第2基材
25 レジストパターン層
REFERENCE SIGNS LIST 1 semiconductor device 2 semiconductor element 3 lead 4 die pad 5 electrode 6 wire 7 resin sealing body 10 substrate for semiconductor device 12 first metal layer 14 second metal layer 16 third metal layer 20 matrix 20a first base material 20b second second Base material 25 resist pattern layer

Claims (6)

母型(20)上に、リード(3)および/またはダイパッド(4)となる金属部が形成された半導体装置用基板であって、
前記母型(20)は、前記金属部が形成される第1基材(20a)と第2基材(20b)とを含み、
前記第1基材(20a)は、前記第2基材(20b)上にめっきにより形成されており、
前記母型(20)は、前記第1基材(20a)と前記第2基材(20b)との間で分離可能であり、
前記第1基材(20a)は、前記第2基材(20b)より薄く形成されているとともに、前記第2基材(20b)より柔らかい材質で形成されていることを特徴とする半導体装置用基板。
A substrate for a semiconductor device in which a metal part that becomes a lead (3) and/or a die pad (4) is formed on a matrix (20),
The master mold (20) includes a first base material (20a) and a second base material (20b) on which the metal part is formed,
The first base material (20a) is formed by plating on the second base material (20b),
The matrix (20) is separable between the first substrate (20a) and the second substrate (20b),
A semiconductor device, wherein the first base material (20a) is thinner than the second base material (20b) and is made of a softer material than the second base material (20b). substrate.
前記第2基材(20b)の表面には剥離処理がされており、剥離処理された前記第2基材(20b)上に前記第1基材(20a)が形成されていることを特徴とする請求項1に記載の半導体装置用基板。 The surface of the second base material (20b) is subjected to release treatment, and the first base material (20a) is formed on the second base material (20b) subjected to the release treatment. 2. The semiconductor device substrate according to claim 1. 前記第1基材(20a)の厚さは10~30μmであり、前記第2基材(20b)の厚さは100~500μmであることを特徴とする請求項1または2に記載の半導体装置用基板。 3. The semiconductor device according to claim 1, wherein the thickness of the first base material (20a) is 10-30 μm, and the thickness of the second base material (20b) is 100-500 μm. substrate. 前記金属部と前記第1基材(20a)との間の密着性の強さは、前記第1基材(20a)と前記第2基材(20b)との間の密着性の強さより強いことを特徴とする請求項1ないし3のいずれかに記載の半導体装置用基板。 The strength of adhesion between the metal portion and the first base material (20a) is stronger than the strength of adhesion between the first base material (20a) and the second base material (20b). 4. The semiconductor device substrate according to claim 1, wherein: 請求項1ないし4のいずれかに記載の半導体装置用基板を用い、半導体素子(2)と、前記金属部とが樹脂により封止され、底面に前記金属部が露出する半導体装置の製造方法であって、
前記母型(20)の前記第1基材(20a)表面に、レジストパターン層(25)を形成する工程と、
前記レジストパターン層(25)から露出する前記第1基材(20a)表面に、前記金属部を形成する工程と、
前記レジストパターン層(25)を除去する工程と、
前記金属部上に、前記半導体素子(2)を搭載し、前記半導体素子(2)と前記金属部とを電気的に接続する工程と、
前記半導体素子(2)及び前記金属部を封止樹脂(38)でモールドして樹脂封止体(7)を形成する工程と、
前記樹脂封止体(7)から前記母型(20)を除去する工程とを有し、
前記母型(20)を除去する工程において、前記第1基材(20a)から前記第2基材(20b)を剥離除去したのち、前記樹脂封止体(7)から前記第1基材(20a)を剥離除去することを特徴とする半導体装置の製造方法。
A method for manufacturing a semiconductor device using the semiconductor device substrate according to any one of claims 1 to 4, wherein the semiconductor element (2) and the metal portion are sealed with a resin, and the metal portion is exposed on the bottom surface. There is
forming a resist pattern layer (25) on the surface of the first substrate (20a) of the master mold (20);
forming the metal part on the surface of the first base material (20a) exposed from the resist pattern layer (25);
removing the resist pattern layer (25);
a step of mounting the semiconductor element (2) on the metal part and electrically connecting the semiconductor element (2) and the metal part;
a step of molding the semiconductor element (2) and the metal part with a sealing resin (38) to form a resin sealing body (7);
removing the matrix (20) from the resin sealing body (7);
In the step of removing the matrix (20), after peeling and removing the second base material (20b) from the first base material (20a), the first base material ( 20a) is removed by peeling.
前記金属部と前記第1基材(20a)との間の密着性の強さは前記第1基材(20a)と前記第2基材(20b)との間の密着性の強さより強く、前記封止樹脂(38)と前記第1基材(20a)との間の密着性の強さは前記第1基材(20a)と前記第2基材(20b)との間の密着性の強さより強く、前記金属部と前記封止樹脂(38)との間の密着性の強さは前記金属部と前記第1基材(20a)との間の密着性の強さより強いことを特徴とする請求項5に記載の半導体装置の製造方法。
The strength of adhesion between the metal portion and the first base material (20a) is stronger than the strength of adhesion between the first base material (20a) and the second base material (20b), The strength of the adhesion between the sealing resin (38) and the first base material (20a) is determined by the strength of the adhesion between the first base material (20a) and the second base material (20b). strength, and the strength of adhesion between the metal portion and the sealing resin (38) is stronger than the strength of adhesion between the metal portion and the first base material (20a). 6. The method of manufacturing a semiconductor device according to claim 5, wherein
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JP2915888B1 (en) 1998-01-28 1999-07-05 日本特殊陶業株式会社 Wiring board and manufacturing method thereof
JP2006295114A (en) 2005-03-17 2006-10-26 Hitachi Cable Ltd Substrate for electronic device, its manufacturing method, electronic device and its manufacturing method
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JP2915888B1 (en) 1998-01-28 1999-07-05 日本特殊陶業株式会社 Wiring board and manufacturing method thereof
JP2006295114A (en) 2005-03-17 2006-10-26 Hitachi Cable Ltd Substrate for electronic device, its manufacturing method, electronic device and its manufacturing method
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