CN105655300A - Packaging substrate, manufacturing method thereof, and semiconductor device - Google Patents
Packaging substrate, manufacturing method thereof, and semiconductor device Download PDFInfo
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- CN105655300A CN105655300A CN201510512781.7A CN201510512781A CN105655300A CN 105655300 A CN105655300 A CN 105655300A CN 201510512781 A CN201510512781 A CN 201510512781A CN 105655300 A CN105655300 A CN 105655300A
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- molding
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- conductor pattern
- base plate
- electric conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
Abstract
The invention provides a packaging substrate, a manufacturing method thereof, and a semiconductor device. In a packaging substrate of a moulding object embedded with and holding a conductor pattern, falling of the conductor pattern from the moulding object or a position offset of the conductor pattern is eliminated, so that operation during conveying and installation of a semiconductor component is simply carried out. The conductor pattern (1) comprises a lower conducting layer (6) and an upper conducting layer (7). Any one of outer shapes of the lower conducting layer (6) and the upper conducting layer (7) is larger than the other from a top view. A block layer (11) preventing the conductor pattern (1) from falling off the moulding object (2) is arranged at any square part of upper and lower surfaces of the moulding object (2) . The block layer (1) is configured to cover a part, protruding from the moulding object (2), of the lower conducting layer (6) or the upper conducting layer (7). Thus, the block layer (11) blocks the conductor pattern (1) and prevents the conductor pattern (1) from falling off the moulding object (2). The packaging substrate can be simply operated.
Description
Technical field
The present invention relates to electric conductor pattern bury underground and be held in the base plate for packaging of molding and manufacture method thereof, withAnd semiconductor device. Electric conductor pattern exposes from the upper and lower surface of molding. And semiconductor device is in envelopeOn dress substrate, semiconductor element is installed and is sealed by seal.
Background technology
With the light-duty object that turns to of base plate for packaging, in patent documentation 1, disclose a kind of electric conductor pattern and buried underground alsoBe held in the base plate for packaging of molding, this is known. In the electrode package body of this patent documentation 1, toolThe electrode layer that is integrally formed at this conductive pattern layer for conductive pattern layer with layered laminate is (below, by oneThe conductive pattern layer and the electrode layer that form are called pattern electrode layer. ). Pattern electrode layer is sealed in tabular treeIn fat (molding), show out conductive pattern layer of this tabular resin, and show out at anotherElectrode layer. In the manufacture of electrode package body, first on the metal substrate being formed by stainless steel, form and leadThe resist layer of electrical pattern layer correspondence, utilizes electroforming afterwards and forms conductive pattern layer. Then, above-mentioned anti-In erosion agent layer and conductive pattern layer, form the resist layer corresponding with electrode layer, utilize afterwards electroforming and layerThe folded electrode layer that forms. Again next, remove two resist layers, apply in the mode that pattern electrode layer is buried undergroundResin also makes it curing, thereby is sealed in tabular resin. Finally, cut the surface of tabular resin,And peel off and remove metal substrate from pattern electrode layer and tabular resin, being manufactured on thus upper and lower surface and dividingDo not expose and have the electrode package of conductive pattern layer and electrode layer body.
If as the electrode package body of patent documentation 1, the metal substrate using while replacing electroforming, and utilizeTabular resin keeps pattern electrode layer, can make the weight lightness of electrode package body entirety, thus energyCost when enough manufacturer delivery electrodes packaging bodies reducing to semiconductor device. And, aspect manufacturer,In the time manufacturing semiconductor device with electrode package body, can economize the trouble that removes metal substrate, therebyAlso can contribute to the minimizing of the manufacturing cost of semiconductor device.
Prior art document
Patent documentation 1: TOHKEMY 2005-244033 communique (the 0014th section, Fig. 1)
In the electrode package of patent documentation 1, owing to keeping pattern electrode layer with thinner tabular resin,So for example in the time carrying, when the installation of semiconductor element, easily produce deflection, torsion etc. in electrode packageDistortion. And, if produce distortion in electrode package, have the limit between pattern electrode layer and tabular resinThe worry that generation of interfaces is peeled off. And, have pattern electrode layer inclined to one side from tabular resin wear or generation positionThe worry of moving. By cautiously processing in the mode that does not produce deflection, torsion in electrode package, canPrevent coming off of pattern electrode layer etc., but like this, operation when conveying, when the installation of semiconductor elementBecome loaded down with trivial details.
Summary of the invention
The object of the present invention is to provide following base plate for packaging and manufacture method thereof and semiconductor device:Electric conductor pattern is buried underground and is held in the base plate for packaging of molding, eliminates electric conductor pattern de-from moldingFall or produce the bad of position skew, thereby can carry simply time, the peace of semiconductor elementOperation when dress.
Molding 2 is buried and be held in to the present invention exposes electric conductor pattern 1 state with its upper and lower surface undergroundBase plate for packaging as object. It is characterized in that, electric conductor pattern 1 is by lower conductiving layer 6 and stacked being formed onUpper conductive layer 7 on lower conductiving layer 6 forms. Lower conductiving layer 6 while overlooking and the profile shape of upper conductive layer 7It is larger than the opposing party that shape is formed as any one party. And, the upper surface of molding 2 or lower surface arbitrarilyOne side, is formed with the bulk layers 11 that stops electric conductor pattern 1 to come off from molding 2.
Bulk layers 11 be formed as the electric conductor pattern 1 to exposing from molding 2 lower conductiving layer 6 orA part for conductive layer 7 covers.
The outer shape of lower conductiving layer 6 is formed as larger than the outer shape of upper conductive layer 7, at molding 2Lower surface form bulk layers 11.
The outer shape of upper conductive layer 7 is formed as larger than the outer shape of lower conductiving layer 6, at molding 2Upper surface form bulk layers 11.
Electric conductor pattern 1 forms by electroforming, is used to form the lower anti-of lower conductiving layer 6 and upper conductive layer 7Erosion body 18 and upper body against corrosion 21 double as the molding 2 of burying underground and keeping electric conductor pattern 1.
Bulk layers 11 is formed by the solder mask 26 of light-cured type.
And the present invention is a kind of manufacture method of base plate for packaging, buries underground and keep leading by down at molding 2The electric conductor pattern 1 that electricity layer 6 and the stacked upper conductive layer 7 being formed on lower conductiving layer 6 form, makes to leadElectricity body pattern 1 exposes in the upper and lower surface of molding 2, in the upper surface of molding 2 or appointing of lower surfaceThe side that anticipates, is formed with the bulk layers 11 that stops electric conductor pattern 1 to come off from molding 2. It is characterized in that,Comprise: an electroforming process, in this operation, anti-under the surface of flat electroforming master mold 15 formsErosion body 18, and form lower conductiving layer 6 on the surface of the electroforming master mold 15 not covered by lower body 18 against corrosion; TwoInferior electroforming process, in this operation, at the table of lower conductiving layer 6 or lower conductiving layer 6 and lower body 18 against corrosionFace forms body 21 against corrosion, and not by the body 21 against corrosion lower conductiving layer 6 or the lower conductiving layer 6 that coverWith conductive layer 7 in the stacked formation in surface of lower body 18 against corrosion; And bulk layers formation operation, in this operationIn, any one party shape in burying underground and keeping the upper surface of molding 2 of electric conductor pattern 1 or lower surfaceBecome bulk layers 11. Form in operation in bulk layers, the upper surface of molding 2 or lower surface arbitrarilyThe solder mask 26 of one square one-tenth light-cured type, and by photoetching process with to conduction exposing from molding 2The mode that a part for the exposed division of layer 6 or upper conductive layer 7 covers forms bulk layers 11.
After secondary electroforming process, carry out molding process, form and bury underground and keep the molded of electric conductor pattern 1Body 2. In molding process, by once and the body lower against corrosion forming in secondary electroforming process and on anti-Erosion body 18,21 is removed, and remove lower body against corrosion and on space after body 18,21 against corrosion, fill softThe moulded resin 22 of having changed, makes it to be solidified to form molding 2 afterwards.
In the situation of overlooking, the outer shape of lower conductiving layer 6 is formed as larger than the outer shape of upper conductive layer 7,And form bulk layers 11 at the lower surface of molding 2. Form between operation in molding process and bulk layers,Comprise that the master mold of peeling off and remove electroforming master mold 15 from electric conductor pattern 1 and molding 2 removes operation.
In the situation of overlooking, the outer shape of upper conductive layer 7 is formed as larger than the outer shape of lower conductiving layer 6,And form bulk layers 11 at the upper surface of molding 2. After being included in bulk layers formation operation, from conductionBody pattern 1 and molding 2 are peeled off and are removed the master mold of electroforming master mold 15 and remove operation.
Be retained in once and the body lower against corrosion forming in secondary electroforming process and upper body against corrosion 18,21,And two bodies 18,21 against corrosion double as the molding 2 of burying underground and keeping electric conductor pattern 1.
And the present invention is a kind of semiconductor dress that semiconductor element S is installed at above-mentioned base plate for packagingPut. Electric conductor pattern 1 possesses outer electrode 4, the electrode 31 that semiconductor element S is possessed and outsideAfter 4 electrical connections of portion's electrode, utilize seal 30 sealing semiconductor element S.
The effect of invention is as follows.
In base plate for packaging of the present invention, electric conductor pattern 1 is led by lower conductiving layer 6 and stacked being formed on downUpper conductive layer 7 on electricity layer 6 forms, the lower conductiving layer 6 while overlooking and the outer shape shape of upper conductive layer 7Become any one party larger than the opposing party. And, in any one party of upper surface or the lower surface of molding 2,Be formed with the bulk layers 11 that stops electric conductor pattern 1 to come off from molding 2. Like this, if at molding 2The upper surface of molding 2 or any one party of lower surface form bulk layers 11, even when carryTime, semiconductor element installation time base plate for packaging produce in the situation of the distortion such as deflection, torsion, also can profitStop electric conductor pattern 1 to come off from molding 2 by bulk layers 11. Therefore, can obtain eliminating conductionBody pattern 1 comes off or produces position skew and can carry simply time, partly lead from molding 2The base plate for packaging of the operation when installation of body member. And, and bulk layers 11 is set correspondingly, improve phaseFor the resistance of the distortion such as deflection, torsion, thereby can suppress base plate for packaging distortion.
If bulk layers 11 be formed as the electric conductor pattern 1 to exposing from molding 2 lower conductiving layer 6 orA part for upper conductive layer 7 covers, by the lower conductiving layer 6 of bulk layers 11 covered parts orThe upper conductive layer 7 of person is stopped by bulk layers 11, and can limit electric conductor pattern 1 to being formed with bulk layers 11One side side shifting.
If the outer shape of lower conductiving layer 6 is formed as larger than the outer shape of upper conductive layer 7, and at molding2 lower surface forms bulk layers 11, limits electric conductor pattern 1 by bulk layers 11 and reveals to lower conductiving layer 6Side shifting below going out, and can stop electric conductor pattern 1 to come off from molding 2.
If the outer shape of upper conductive layer 7 is formed as larger than the outer shape of lower conductiving layer 6, and at molding2 upper surface forms bulk layers 11, by bulk layers 11 limit electric conductor pattern 1 upwards conductive layer 7 revealThe upper face side going out moves, and can stop electric conductor pattern 1 to come off from molding 2.
If be used to form body lower against corrosion and the upper body against corrosion 18,21 of lower conductiving layer 6 and upper conductive layer 7Double as molding 2, can be by two bodies 18,21 against corrosion as the mould of burying and keep electric conductor pattern 1 undergroundBody 2 processed. Therefore, can not needed to make in addition electric conductor pattern 1 bury and be held in molding 2 underground andPossess the base plate for packaging of bulk layers 11, thereby can reduce the manufacturing cost of base plate for packaging.
If bulk layers 11 is formed by the solder mask 26 of light-cured type, can easily form by photoetching processThe bulk layers 11 of desirable pattern, thus the base plate for packaging that possesses bulk layers 11 can further be reducedManufacturing cost. And, due to compared with general photoresist taking phenolic resins as base polymer, resistanceThe structural strength of layer 26 is high, thus can suppress the breakage of the bulk layers such as crack, breach 11, and canEffectively stop electric conductor pattern 1 come off or produce position skew from molding 2.
In manufacture method of the present invention, comprise electroforming process, secondary electroforming process and bulk layers one timeForm operation, and form base plate for packaging. And, form in operation, at the upper table of molding 2 in bulk layersAny one party of face or lower surface forms solder mask 26, and by photoetching process with to exposing from molding 2Lower conductiving layer 6 or the mode that covers of the part of the exposed division of upper conductive layer 7 form bulk layers11. Like this, can utilize with once and the identical equipment of secondary electroforming process expose, develop, dryEach processing such as dry, and owing to can easily forming the bulk layers 11 of desirable pattern, so canReduce the manufacturing cost of the base plate for packaging that possesses bulk layers 11.
In molding process after secondary electroforming process, by once and form in secondary electroforming processLower body against corrosion and upper body against corrosion 18,21 are removed, and remove lower body against corrosion 18 and on body 21 against corrosionAfter space, fill the moulded resin 22 having softened, make it to be afterwards solidified to form and bury underground and keep leadingThe molding 2 of electricity body pattern 1. Like this, possess desirable mechanical strength, material behavior by utilizationMoulded resin 22 forms molding 2, can utilize the molding 2 of the use that is suitable for base plate for packaging mostBury underground and keep electric conductor pattern 1. Therefore, need in stable on heating situation, by example at base plate for packagingAs used polybutylene terephthalate (PBT) or polyethylene etc. at moulded resin 22, can obtain heat resistanceExcellent base plate for packaging. And, by moulded resin 22 is made as with to being installed on partly leading of base plate for packagingThe resin material of the same or homologous ray of seal 30 that body member S seals, can make molding 2And the stationary state between seal 30 is firm, and can make both roughly phases of coefficient of thermal expansion of 2,30With, thereby can prevent that the generation of boundary face between molding 2 and seal 30 from peeling off.
In the situation of overlooking, the outer shape of lower conductiving layer 6 is formed as larger than the outer shape of upper conductive layer 7,And be formed with bulk layers 11 at the lower surface of molding 2. And, form work in molding process and bulk layersBetween order, comprise that the master mold of peeling off and remove electroforming master mold 15 from electric conductor pattern 1 and molding 2 removesOperation. Like this, because electric conductor pattern 1 and molding 2 are formed on electroforming master mold 15, so energyThe lower surface that exposes face and molding 2 that enough makes to remove the lower conductiving layer 6 after electroforming master mold 15 becomes flatA sliding face. Therefore, do not need to carry out milled processed etc. as the pre-treatment of carrying out bulk layers formation operation,Thereby can reduce the manufacturing cost of base plate for packaging.
In the situation of overlooking, the outer shape of upper conductive layer 7 is formed as larger than the outer shape of lower conductiving layer 6,And be formed with bulk layers 11 at the upper surface of molding 2. And, after being included in bulk layers formation operation,Peel off and remove the master mold of electroforming master mold 15 from electric conductor pattern 1 and molding 2 and remove operation. Like this,Due to via bulk layers peel off and remove electroforming master mold 15 in forming the final operation after operation, soIn the manufacture process of base plate for packaging, can under the state being supported reliably by electroforming master mold 15, manufacture and leadElectricity body pattern 1 and molding 2, thus can be under stable state manufacturing and encapsulation substrate.
Be retained in once and the body 18 lower against corrosion forming in secondary electroforming process and upper body against corrosion 21, andTwo bodies 18,21 against corrosion double as the molding 2 of burying underground and keeping electric conductor pattern 1. Like this, do not need separatelyOuter formation molding 2, and can omit the operation that forms molding 2, thus correspondingly can further subtractThe manufacturing cost of few base plate for packaging.
Be provided with in the semiconductor device of semiconductor element S at above-mentioned base plate for packaging, by electric conductor patternAfter electrode 31 electrical connections that 1 outer electrode possessing 4 and semiconductor element S possess, utilize closeEnvelope body 30 has sealed semiconductor element S. Like this, between outer electrode 4 and electrode 31 be connected operation,And while utilizing the sealing operation that seal 30 carries out, if base plate for packaging has produced the change of deflection, torsionShape, electric conductor pattern 1 also can not come off or produce position skew from molding 2, thereby can be simpleThe operation of base plate for packaging when ground carries out above-mentioned operation. And, can reduce the manufacture of semiconductor device timeDefective products formation rate, and the productivity ratio of raising semiconductor device.
Brief description of the drawings
Fig. 1 is the vertical profile side view of the base plate for packaging of the first embodiment of the present invention.
Fig. 2 is the partial top view of the base plate for packaging of the first embodiment.
Fig. 3 represents saying of an electroforming process in the manufacture method of base plate for packaging of the first embodimentBright figure.
Fig. 4 represents saying of secondary electroforming process in the manufacture method of base plate for packaging of the first embodimentBright figure.
Fig. 5 is molding process and the master mold representing in the manufacture method of base plate for packaging of the first embodimentRemove the key diagram of operation.
Fig. 6 represents that the bulk layers in the manufacturing process of base plate for packaging of the first embodiment forms operationKey diagram.
Fig. 7 is the vertical profile side view of the semiconductor device of the first embodiment.
Fig. 8 is the stereogram of the semiconductor device of the first embodiment.
Fig. 9 is the key diagram that represents the manufacture method of the semiconductor device of the first embodiment.
Figure 10 is the partial top view of the manufacture method of the semiconductor device for the first embodiment is described.
Figure 11 is the vertical profile side view of the base plate for packaging of the second embodiment of the present invention.
Figure 12 be represent master mold in the manufacture method of base plate for packaging of the second embodiment remove operation andBulk layers forms the key diagram of operation.
Figure 13 is the vertical profile side view of the base plate for packaging of the 3rd embodiment of the present invention.
Figure 14 represents saying of an electroforming process in the manufacture method of base plate for packaging of the 3rd embodimentBright figure.
Figure 15 represents saying of secondary electroforming process in the manufacture method of base plate for packaging of the 3rd embodimentBright figure.
Figure 16 is molding process, the bulk layers representing in the manufacture method of base plate for packaging of the 3rd embodimentForm operation and master mold and remove the key diagram of operation.
Figure 17 is the vertical profile side view of the base plate for packaging of the 4th embodiment of the present invention.
Figure 18 be represent bulk layers in the manufacture method of base plate for packaging of the 4th embodiment form operation withAnd master mold is removed the key diagram of operation.
In figure:
1-electric conductor pattern, 2-molding, 4-outer electrode, 6-lower conductiving layer (the first electroformed layer),7-upper conductive layer (the second electroformed layer), 11-bulk layers, 15-electroforming master mold, 18-lower body against corrosion (theOne body against corrosion), 21-upper body against corrosion (the second body against corrosion), 22-moulded resin, 26-solder mask, 30-seal, 31-electrode, S-semiconductor element, W-metal wire.
Detailed description of the invention
(the first embodiment)
In Fig. 1 to Figure 10, represent base plate for packaging of the present invention and manufacture method thereof and semiconductor deviceThe first embodiment. As shown in Figure 1 and Figure 2, the electric conductor pattern 1 of base plate for packaging is buried underground and is held inMolding 2, electric conductor pattern 1 forms by electrocasting, and the upper and lower surface of molding 2 is exposed. LeadThe mounting mat 3 that 1 utilization of electricity body pattern loads for semiconductor element S and the both sides that are disposed at mounting mat 3Six outer electrodes 4 and forming as one group of unit cell pattern at molding 2, dispose multiple rectangularlyUnit cell pattern.
Electric conductor pattern 1 has shape on the electroforming master mold 15 of electric conductivity at stainless steel or aluminium etc. during by electroformingThe first electroformed layer (lower conductiving layer) 6 becoming and the second electroformed layer of stacked formation on the first electroformed layer 6(upper conductive layer) 7 forms, and the outer shape of the first electroformed layer 6 is formed as than the profile of the second electroformed layer 7Shape is large. The second electroformed layer 7 is by basic unit 8 and realize scolding tin or the close-burning raising of metal wire WSuperficial layer 9 form. The basic unit 8 of the first electroformed layer 6 and the second electroformed layer 7 can be by nickel, nickel-cobaltAlloy or copper form. And the superficial layer 9 of the second electroformed layer 7 can be formed by noble metal, Neng GouyouThe formation such as gold or gold-palldium alloy. The second electroformed layer 7 formed mounting mat 3 and outer electrode 4,The installed surface side of semiconductor element S.
Boundary face between electric conductor pattern 1 and the molding 2 of burying and be held in molding 2 underground producesIn situation about peeling off, electric conductor pattern 1 stops because the first electroformed layer 6 is molded body 2, and can be towards secondThe upper face side (top of seeing towards Fig. 1) that electroformed layer 7 exposes is mobile. But, owing to not limiting conductionBody pattern 1 expose towards the first electroformed layer 6 below the mechanism of movement of side (see towards Fig. 1 lower to),So there is electric conductor pattern 1 come off or produce the worry of position skew from molding 2. Like this, forStop electric conductor pattern 1 to come off or produces position from molding 2 and be offset, and in the following table of molding 2Face has formed bulk layers 11.
The part that bulk layers 11 is formed as the first electroformed layer 6 to having exposed from molding 2 covers.Particularly, have the window 12 that the first electroformed layer 6 is exposed at bulk layers 11 openings, window 12 is formed as ratioForm the little circle of outer shape of the first electroformed layer 6 of mounting mat 3 and outer electrode 4. Thus, conductionBody pattern 1 stops by the circumference of the window 12 of bulk layers 11 because of the outer edge of the first electroformed layer 6, and towards fromThe movement that molding 2 separates the direction of (coming off) is restricted. Bulk layers 11 is used the resistance of light-cured typeLayer 26 and forming with photoetching process. On the surface of first electroformed layer 6 relative with window 12, be formed with realizationThe superficial layer 13 of the close-burning raising of scolding tin or metal wire W. Superficial layer 13 can be by noble metal shapeBecome, can be formed by gold or gold-palldium alloy etc.
In Fig. 3 to Fig. 6, represent the manufacture method of the base plate for packaging of present embodiment. Base plate for packaging is via Fig. 3(a) the secondary electroforming shown in an electroforming process shown in～Fig. 3 (d), Fig. 4 (a)～Fig. 4 (d)Master mold shown in molding process shown in operation, Fig. 5 (a)～Fig. 5 (b), Fig. 5 (c) is removed operationAnd the bulk layers shown in Fig. 6 (a)～Fig. 6 (c) forms operation and forms. The manufacture of base plate for packaging is usedThe electroforming master mold 15 with the flat stainless steel of electric conductivity carries out.
In an electroforming process, as shown in Fig. 3 (a), form first at the upper surface of electroforming master mold 15Photoresist layer 16, afterwards at the upper surface of this first photoresist layer 16, loads and is close to and haveThe first patterned films 17 of the loophole corresponding with the first electroformed layer 6. Next, shine with ultraviolet light modulationPenetrate ultraviolet and expose, and each processing of developing, being dried, dissolve and remove unexposed portion,As shown in Fig. 3 (b), on electroforming master mold 15, form thus corresponding with the first electroformed layer 6 first against corrosionBody (lower body against corrosion) 18. In addition, the first photoresist layer 16 uses with the height of regulation and contrasts land productivityWith hot pressing by one or more pieces alkali develop, negative aobvious photonasty dry film lamination against corrosion and photoresist after formingAgent layer. For example, can use the general resist using phenolic resins as base polymer.
Next, as shown in Fig. 3 (c), by utilizing electrocasting to make the electrodeposition of nickel as electroforming metalOn the electroforming master mold 15 except the first body 18 against corrosion, form the first electroformed layer 6. Forming firstAfter electroformed layer 6, by the surface of the first body 18 against corrosion and the first electroformed layer 6 is ground, byThis makes the surface of the first body 18 against corrosion and the first electroformed layer 6 become a face as shown in Fig. 3 (d).
In secondary electroforming process, as shown in Fig. 4 (a), at the first electroformed layer 6 and the first body against corrosion18 upper surface forms the second photoresist layer 19, afterwards at the upper table of this second photoresist layer 19Face, loads and is close to second patterned films 20 with the loophole corresponding with the second electroformed layer 7, wherein,The outer shape of the second electroformed layer 7 is less than the outer shape of the first electroformed layer 6. Next, use ultravioletLight irradiation ultraviolet exposes, and each processing of developing, being dried, and dissolves the unexposed portion of removingPoint, as shown in Fig. 4 (b), on the first electroformed layer 6 and the first body 18 against corrosion, form and second thusSecond body against corrosion (upper body against corrosion) 21 of electroformed layer 7 correspondences. In addition, the second photoresist layer 19 withThe first photoresist layer 16 is identical, uses with the height of regulation and contrasts and utilize hot pressing by one or more piecesAlkali develops, negative aobvious photonasty dry film lamination against corrosion and photoresist layer after forming. For example, can makeWith the general resist using phenolic resins as base polymer.
Next, as shown in Fig. 4 (c), by utilizing electrocasting to make the electrodeposition of nickel as electroforming metalOn the first electroformed layer 6 except the second body 21 against corrosion, come the basic unit of stacked formation the second electroformed layer 78. Afterwards, by the surface of the second body 21 against corrosion and basic unit 8 is ground, come as Fig. 4 (d)Shown in make the surface of the second body 21 against corrosion and the second electroformed layer 7 become a face. In addition, in basic unit8 gauge, than in the little situation of the gauge of the second body 21 against corrosion, also can save grinding step.Carry out after grinding step, by making golden electro-deposition in basic unit 8, carried out stacked formation the second electroformed layer 7Superficial layer 9 (with reference to Fig. 1).
In molding process, as shown in Fig. 5 (a), by once and form in secondary electroforming processThe first body 18 against corrosion and the second body against corrosion 21 dissolve to be removed, and fills out removing both spaces after 18,21Fill the moulded resin 22 being formed by the thermoplastic epoxy resin having softened, make it afterwards curing, thereby asShown in Fig. 5 (b), form molding 2. In the time filling moulded resin 22, with opposed with electroforming master mold 15Mode configure metal die and will remove space after two bodies 18,21 against corrosion as cavity, guide afterwards1, electricity body pattern is filled moulded resin 22 and makes it curing, but not shown to this. Metal die withThe contact-making surface that moulded resin 22 contacts is pasted with teflon sheets. Thus, in the time pulling down metal die, energyEnough prevent from adhering to moulded resin 22 at metal die. And, can make the upper surface and second of molding 2The upper surface of electroformed layer 7 is formed as a face, in addition, can prevent that moulded resin 22 is at the second electroformed layer7 upper surface solidifies. If the upper surface that is attached to the second electroformed layer 7 at moulded resin 22,The surface of grinding after solidifying and remove molding 2 and the second electroformed layer 7.
Remove in operation at master mold, forcibly from electric conductor pattern 1 (the first electroformed layer 6) and moldedElectroforming master mold 15 is peeled off and removed to body 2 (moulded resin 22). Thus, obtained shown in Fig. 5 (c)The base plate for packaging of molding 2 is buried and be held in to electric conductor pattern 1 underground.
Form in operation in bulk layers, as shown in Fig. 6 (a), will remove the envelope obtaining in operation at master moldDress substrate reverses up and down, forms solder mask 26 at the upper surface of the first electroformed layer 6 and molding 2, andAnd load and be close to the 3rd patterned films 27, the three patterned films 27 at the upper surface of this solder mask 26There is the loophole more corresponding than the window 12 of the little circle of the outer shape of the first electroformed layer 6 with outer shape. ConnectGet off, expose with ultraviolet light irradiation ultraviolet, and each processing of developing, being dried,Unexposed portion is removed in dissolving, thus as shown in Fig. 6 (b) at the first electroformed layer 6 and molding 2Upper formation bulk layers 11, forms fenestrate 12 in this bulk layers 11. In addition, solder mask 26 has used and has passed throughContrast the dry film that utilizes hot pressing one or more pieces alkali to be developed, born aobvious photonasty welding resistance with the height of regulationLamination and solder mask after forming. Finally, at the face that exposes of first electroformed layer 6 relative with window 12, logicalCross electroless plating and be formed with the superficial layer 13 being formed by gold, afterwards it is reversed up and down, thereby obtained possessingThe base plate for packaging of the bulk layers 11 shown in Fig. 6 (c).
In Fig. 7 and Fig. 8, be illustrated in base plate for packaging and be provided with the semiconductor device of semiconductor element S. AsShown in Fig. 7, semiconductor device is by utilizing the seal 30 that is made up of epoxy resin in base plate for packaging instituteThe semiconductor element S installing in the unit cell pattern of the electric conductor pattern 1 having is sealed to form. To partly leadBody member S is installed on the base plate for packaging surface of the opposing face side of bulk layers 11, and it is adhesively fixed onOn mounting mat 3, by will being formed at the electrode 31 of upper surface of semiconductor element S and outer with metal wire WPortion's electrode 4 is electrically connected, and is installed on base plate for packaging. Seal 30 seals shape to these semiconductor elementsS and metal wire W etc. seal, and semiconductor device entirety is formed as quadrangle bulk, from bottom surfaceThe relative window 12 of side exposes the surperficial superficial layer 13 (with reference to Fig. 8) that is formed at the first electroformed layer 6.
In Fig. 9 and Figure 10, represent the manufacture method of the semiconductor device of present embodiment. As Fig. 9 (a)Shown in, be installed on mounting mat 3 bonding semiconductor element S, as shown in Fig. 9 (b), use afterwardsThe metal wire W being formed by gold and utilize lead wire connecting apparatus by the electrode on semiconductor element S 31 and and itsBetween corresponding outer electrode 4, link. Now, owing to having improved metal wire W's with superficial layer 9Caking property, so the defective products formation rate can reduce manufacturing process time. In addition electrode 31 and outside electricity,Connection between the utmost point 4 is not limited to use the wire-bonded of metal wire W, can be by having used scolding tinDeng flip-chip bonded be electrically connected.
Next, as shown in Fig. 9 (c), use the semiconductor on the hermetically sealed substrate of thermoplastic epoxyThe mounting portion of element S, thus seal 30 on base plate for packaging, formed. Particularly, will encapsulate basePlate, as master mold, is installed molded metal die (patrix) and formation cavity at the upper face side of base plate for packaging, andTo being pressed into the thermoplastic epoxy resin having softened in cavity, and make it curing. Thus, obtained multiple halfConductor element S, by the aggregate of the semiconductor device under the hermetically sealed form of seal 30, wherein, partly leadsBody member S is provided with and is formed as rectangular unit cell pattern at base plate for packaging. Finally, by along as Fig. 9 (c),Cut-out line in Figure 10 shown in chain-dotted line cuts, thereby has obtained the semiconductor device shown in Fig. 7.
As described above, in the base plate for packaging of present embodiment, due to bulk layers 11 is formed as to fromThe outer edge of the first electroformed layer 6 that molding 2 exposes covers, so can utilize the periphery of window 12The bulk layers 11 of portion stops the first electroformed layer 6 and the movement of restriction electric conductor pattern 1.
Larger than the outer shape of the second electroformed layer 7 due to the outer shape of the first electroformed layer 6 is formed as, andBe formed with bulk layers 11 at the lower surface of molding 2, so not by the electric conductor of molding 2 moving-limitingsPattern 1 expose to the first electroformed layer 6 below the movement of side can be limited by bulk layers 11. Therefore, energyEnough utilize bulk layers 11 to stop electric conductor pattern 1 to come off from molding 2. And, passing through electrocasting shapeWhile becoming the second electroformed layer 7, owing to only making electroformed layer increase on the first electroformed layer 6 of electrode that becomes cathode sideLong, so there is the second electroforming of the outer shape larger than the outer shape of the first electroformed layer 6 with formationThe situation of layer 7 is compared, and can reduce the consumption of the metal electrode of the anode-side while forming the second electroformed layer 7,And can shorten the electroforming time, correspondingly can reduce the manufacturing cost of base plate for packaging.
And, in the manufacture method of the base plate for packaging of present embodiment, the mould after secondary electroforming processIn operation processed, remove once and the first body 18 against corrosion forming in secondary electroforming process and second anti-Erosion body 21, and in the space of having removed two bodies 18,21 against corrosion, fills the moulded resin 22 having softened, itAfter make it curing, thereby formed the molding 2 of burying underground and keeping electric conductor pattern 1. According to this manufacturerMethod, the moulded resin 22 that possesses desirable mechanical strength, material behavior by utilization forms molding2, can utilize the molding 2 of the use that is suitable for base plate for packaging most to bury underground and keep electric conductor pattern1. Therefore, need in stable on heating situation at base plate for packaging, poly-right by for example using at moulded resin 22Benzene dicarboxylic acid butanediol ester or polyethylene etc., can obtain the base plate for packaging of excellent heat resistance. And, logicalCross moulded resin 22 is made as to the seal sealing with the semiconductor element S to being installed on base plate for packagingThe resin material of 30 same or same systems, can make the fixing shape between molding 2 and seal 30State is firm, and owing to can making both coefficient of thermal expansions of 2,30 roughly the same, so can prevent at mouldBoundary face between body 2 processed and seal 30 produces and peels off.
And, make the outer shape formation of the first electroformed layer 6 larger than the outer shape of the second electroformed layer 7,Molding process and bulk layers form between operation, comprise from electric conductor pattern 1 and molding 2 and peel off and removeGo the master mold of electroforming master mold 15 to remove operation. According to this manufacture method, due to electric conductor pattern 1 and mouldBody 2 processed is formed on electroforming master mold 15, so can make to remove electroforming master mold 15 the first electroformed layer afterwards6 the lower surface that exposes face and molding 2 becomes a level and smooth face. Therefore, as carrying out bulk layersForm the pre-treatment of operation, do not need to carry out milled processed etc., thereby can reduce manufacturing of base plate for packagingThis.
(the second embodiment)
In Figure 11 and Figure 12, represent the second embodiment of base plate for packaging of the present invention. In present embodimentIn, omit molding process this point in the manufacture process of base plate for packaging different from the first embodiment. AlsoIn other words, as shown in figure 11, first anti-by what be used to form the first electroformed layer 6 and the second electroformed layer 7Erosion body 18 and the second body 21 against corrosion are as the molding 2 of burying and keep electric conductor pattern 1 underground. And,The upper surface of electroforming master mold 15, as shown in Figure 12 (a), removes in operation in order to realize master mold described laterThe facilitation of peeling off, be laminated with in advance nickel dam 15a and the copper layer 15b of film-form. Other and first implementMode is identical, thereby identical parts are marked to identical symbol, also the description thereof will be omitted.
The base plate for packaging of present embodiment via the master mold shown in Figure 12 (b) remove operation and Figure 12 (c)～Bulk layers shown in Figure 12 (e) forms operation and is formed at the secondary electricity shown in Fig. 4 (a)～Fig. 4 (d)Base plate for packaging (with reference to Figure 12 (a)) in manufacture process after foundry work order finishes. Remove in operation at master mold,Forcibly peel off remove electroforming master mold 15 and be pre-formed nickel dam 15a on electroforming master mold 15 itAfter, to copper layer, 15b removes (etching). Thus, obtained being resisted by the first body 18 against corrosion and secondThe encapsulation of the electric conductor pattern 1 shown in Figure 12 (b) is buried and maintained to the molding 2 that erosion body 21 forms undergroundSubstrate. Like this, finally by removing copper layer 15b, can make master mold remove the electroforming master mold 15 in operationPeel off and become easily, and can suppress the breakage of two bodies 18,21 against corrosion.
Form in operation in bulk layers, as shown in Figure 12 (c), will remove the envelope obtaining in operation at master moldDress substrate reverses up and down, forms solder mask 26 at the upper surface of the first electroformed layer 6 and the first body 18 against corrosion,And load and be close to the 3rd patterned films 27, the three patterned films 27 at the upper surface of this solder mask 26There is the loophole more corresponding than the window 12 of the little circle of the outer shape of the first electroformed layer 6 with outer shape. ConnectGet off, expose with ultraviolet light irradiation ultraviolet, and each processing of developing, being dried,Unexposed portion is removed in dissolving, against corrosion at the first electroformed layer 6 and first as shown in Figure 12 (d) thusOn body 18, form bulk layers 11, form fenestrate 12 in this bulk layers 11. Finally, relative with window 12The surface of the first electroformed layer 6, forms the superficial layer 13 being made up of gold by electroless plating, and it is anti-up and downTurn, obtained thus possessing the base plate for packaging of the bulk layers 11 shown in Figure 12 (e). In present embodimentBase plate for packaging that the semiconductor device of semiconductor element S is installed is identical with the first embodiment, therefore omitIts explanation.
As described above, in the base plate for packaging of present embodiment, due to the first body 18 against corrosion and secondBody 21 against corrosion doubles as molding 2, so can be by two bodies against corrosion 18,21 as burying underground and keeping electric conductorThe molding 2 of pattern 1. Therefore, can not needed to make in addition electric conductor pattern 1 bury underground and be held inMolding 2 and possess the base plate for packaging of bulk layers 11. And, in the system of the base plate for packaging of present embodimentIn making method, be retained in once and secondary electroforming process in the first body 18 against corrosion of forming and second anti-Erosion body 21, and two bodies 18,21 against corrosion double as the molding 2 of burying underground and keeping electric conductor pattern 1, therebyCan omit the operation that forms molding 2, correspondingly can reduce the manufacturing cost of base plate for packaging.
In the second above-mentioned embodiment, the first photoresist layer 16 and the second photoresist layer,19 have used negative aobvious photonasty dry film against corrosion, but bear the dry film of aobvious photonasty welding resistance, energy by useEnough structural strengths that improves the molding 2 being formed by the first body 18 against corrosion and the second body 21 against corrosion, therebyCan effectively prevent molding 2 breakages.
In the present embodiment, due to the basic unit via grinding the second body 21 against corrosion and the second electroformed layer 7Stacked formation superficial layer 9 after 8 surperficial operation, so as shown in figure 11, superficial layer 9 is with from molding2 the outstanding state of upper surface forms. In addition, the gauge of basic unit 8 is being formed as more against corrosion than secondThe gauge of body 21 is little and saved in the situation of grinding step, and the upper surface of superficial layer 9 can be takedBecome a face with the upper surface of molding 2 or be positioned at than the upper surface of molding 2 form of side on the lower.
(the 3rd embodiment)
In Figure 13 to Figure 16, represent the 3rd embodiment of base plate for packaging of the present invention. In the present embodiment,The magnitude relationship of the outer shape of the first electroformed layer 6 and the second electroformed layer 7 contrary form aspect andAccompany and becoming outer shape and be formed as the upper surface of the molding 2 of the second larger electroformed layer 7 sides in thisThe aspect that is formed with bulk layers 11 is different from the first embodiment. Form the second electroforming of electric conductor pattern 1The outer shape of layer 7 is formed as larger than the outer shape of the first electroformed layer 6, and the first electroformed layer 6 is by basic unit 8Form with superficial layer 9. On the surface of second electroformed layer 7 relative with the window 12 that is opened on bulk layers 11,Be formed with superficial layer 13. In the present embodiment, the first electroformed layer 6 of electric conductor pattern 1 forms installationThe installed surface side of the semiconductor element S of pad 3 and outer electrode 4. Other is identical with the first embodiment,Thereby identical parts are marked to identical symbol and the description thereof will be omitted.
In Figure 14 to Figure 16, represent the manufacture method of the base plate for packaging of present embodiment. Base plate for packaging is via figureSecondary shown in an electroforming process shown in 14 (a)～Figure 14 (d), Figure 15 (a)～Figure 15 (d)Molding process shown in electroforming process, Figure 16 (a), Figure 16 (b), Figure 16 (c), Figure 16 (d) instituteThe bulk layers of showing forms the master mold shown in operation and Figure 16 (e) and removes operation and form. Once electricIn foundry work order, as shown in Figure 14 (a), form the first photoresist at the upper surface of electroforming master mold 15Layer 16, loads and is close to the first patterned films 17 at the upper surface of this first photoresist layer 16 afterwards,This first patterned films 17 has the loophole corresponding with the first electroformed layer 6. Next, use ultravioletLight irradiation ultraviolet and exposing, and develop, dry each processing, dissolve the unexposed portion of removingPoint, formation corresponding with the first electroformed layer 6 the on electroforming master mold 15 as Figure 14 (b) as shown in thusOne body 18 against corrosion.
Next,, as shown in Figure 14 (c), make the electroforming mother of golden electro-deposition beyond the first body 18 against corrosionOn mould 15, and the superficial layer 9 of formation the first electroformed layer 6, and by utilizing electrocasting to make as electroformingThe electrodeposition of nickel of metal is on superficial layer 9, and stacked formation basic unit 8, thereby form the first electroformed layer 6 (ginsengAccording to Figure 13). After forming the first electroformed layer 6, by grinding the first body 18 against corrosion and the first electroformingThe surface of layer 6 (basic units 8) makes the first body 18 against corrosion and the first electroforming as shown in Figure 14 (d)The surface of layer 6 becomes a face.
In secondary electroforming process, as shown in Figure 15 (a), at the first electroformed layer 6 and the first body against corrosion18 upper surface forms the second photoresist layer 19, afterwards at the upper table of this second photoresist layer 19Face loads and is close to the second patterned films 20, and this second patterned films 20 has with outer shape than the first electricityThe loophole of the second electroformed layer 7 correspondences that the outer shape of cast layer 6 is large. Next, shine with ultraviolet light modulationPenetrate ultraviolet and expose, and each processing of developing, being dried, dissolve and remove unexposed portion,As shown in Figure 15 (b), on the first body 18 against corrosion, form corresponding with the second electroformed layer 7 second thusBody 21 against corrosion.
Next, as shown in Figure 15 (c), by utilizing electrocasting to make the electrodeposition of nickel as electroforming metalOn the first electroformed layer 6 and the first body 18 against corrosion beyond the second body 21 against corrosion, carry out stacked formation secondElectroformed layer 7. After forming the second electroformed layer 7, by grinding the second body 21 against corrosion and the second electroformingThe surface of layer 7, the next table that makes the second body 21 against corrosion and the second electroformed layer 7 as shown in Figure 15 (d)Face becomes a face.
In molding process, as shown in Figure 16 (a), by once and form in secondary electroforming processThe first body 18 against corrosion and the second body against corrosion 21 dissolve to be removed, and fills out removing both spaces after 18,21Fill the moulded resin 22 being formed by the thermoplastic epoxy resin having softened, make it afterwards curing, thereby asShown in Figure 16 (b), form molding 2.
Form in operation, as shown in Figure 16 (c), at the second electroformed layer 7 and molding 2 in bulk layersUpper surface form solder mask 26, load and to be close to the 3rd pattern thin at the upper surface of this solder mask 26 afterwardsFilm 27, the three patterned films 27 have with outer shape than the little circle of the outer shape of the second electroformed layer 7The loophole of window 12 correspondences. Next, expose with ultraviolet light irradiation ultraviolet, andDevelop, dry each processing, dissolve and remove unexposed portion, thus as shown in Figure 16 (d)On the second electroformed layer 7 and molding 2, form bulk layers 11, form fenestrate 12 in this bulk layers 11. ItAfter, on the surface of second electroformed layer 7 relative with window 12, form the surface being formed by gold by electroless platingLayer 13.
Remove in operation at master mold, by from electric conductor pattern 1 (the second electroformed layer 7) and molding 2(moulded resin 22) peeled off forcibly and removed electroforming master mold 15, thus (e) institute that obtains possessing Figure 16The base plate for packaging of the bulk layers 11 of showing.
In the manufacture of the semiconductor device of present embodiment, make the reversion up and down of base plate for packaging, make the first electroformingAbove layer 6 is positioned at, afterwards semiconductor element S is arranged on mounting mat 3, and uses the gold being formed by goldBelong to line W and utilize lead wire connecting apparatus by electrode 31 and and its corresponding outer electrode 4 between link. SeparatelyOutward, with the mounting portion of the semiconductor element 2 on the hermetically sealed substrate of thermoplastic epoxy, thereby in envelopeOn dress substrate, form seal 30.
As described above, in the base plate for packaging of present embodiment, due to bulk layers 11 is formed as to fromThe outer edge of the second electroformed layer 7 that molding 2 exposes covers, so can utilize the periphery of window 12The bulk layers 11 of portion stops the second electroformed layer 7 and the movement of restriction electric conductor pattern 1.
Larger than the outer shape of the first electroformed layer 6 due to the outer shape of the second electroformed layer 7 is formed as, andBe formed with bulk layers 11 at the upper surface of molding 2, so not by the electric conductor of molding 2 moving-limitingsThe movement of the upper face side that pattern 1 exposes to the second electroformed layer 7 can be limited by bulk layers 11, thereby canStop electric conductor pattern 1 to come off from molding 2 by bulk layers 11.
And, in the manufacture method of the base plate for packaging of present embodiment, be included in bulk layers form operation itAfter, peel off and remove the master mold of electroforming master mold 15 from electric conductor pattern 1 and molding 2 and remove operation.According to this manufacture method, due to via bulk layers peel off and remove electricity in forming the final operation after operationCasting master mold 15, so in the manufacture process of base plate for packaging, can supported reliably by electroforming master mold 15State under manufacture electric conductor pattern 1 and molding 2, thereby can be with stable state manufacturing and encapsulation basePlate.
(the 4th embodiment)
In Figure 17 and Figure 18, represent the 4th embodiment of base plate for packaging of the present invention. In present embodimentIn, different from the 3rd embodiment aspect the molding process in the manufacture process of having omitted base plate for packaging.That is to say, as shown in figure 18, will be used to form first of the first electroformed layer 6 and the second electroformed layer 7Body 18 against corrosion and the second body 21 against corrosion are as the molding 2 of burying and keep electric conductor pattern 1 underground. And,In the manufacture of manufacturing and encapsulation substrate, with the second embodiment identical, use and have a film-form upper surface is stackedThe electroforming master mold 15 of nickel dam 15a and copper layer 15b. Other is identical with the 3rd embodiment, thereby to identicalParts mark identical symbol the description thereof will be omitted.
The base plate for packaging of present embodiment finishes at the secondary electroforming process shown in Figure 15 (a)～Figure 15 (d)Afterwards, form shown in operation and Figure 18 (c) via the bulk layers shown in Figure 18 (a), Figure 18 (b)Master mold is removed operation and is formed. Form in operation, as shown in Figure 18 (a), in the second electroforming in bulk layersThe upper surface of layer 7 and the second body 21 against corrosion forms solder mask 26, afterwards at the upper table of this solder mask 26Face loads and is close to the 3rd patterned films 27, the three patterned films 27 to be had with outer shape than the second electricityThe loophole of window 12 correspondences of the little circle of outer shape of cast layer 7. Next, use ultraviolet light irradiationUltraviolet and exposing, and develop, dry each processing, dissolve and remove unexposed portion, byThis forms bulk layers 11 as shown in Figure 18 (b) on the second electroformed layer 7 and the second body 21 against corrosion,Form fenestrate 12 in this bulk layers 11. Afterwards, on the surface of second electroformed layer 7 relative with window 12,Form the superficial layer 13 being formed by gold by electroless plating.
Remove in operation at master mold, forcibly peeling off and removing electroforming master mold 15 and be pre-formed in electroformingAfter nickel dam 15a on master mold 15, to copper layer, 15b removes (etching), has obtained thus possessing figureThe base plate for packaging of the bulk layers 11 shown in 18 (c).
In the above-described embodiment, the first photoresist layer 16 and the second photoresist layer 19Use negative aobvious photonasty dry film against corrosion, but identical with the second embodiment before, negative aobvious by usingThe dry film of photonasty welding resistance, can improve the mould being formed by the first body 18 against corrosion and the second body 21 against corrosionThe structural strength of body 2 processed, thus can effectively prevent molding 2 breakages.
Semiconductor device and the 3rd enforcement of semiconductor element S are installed at the base plate for packaging of present embodimentMode is identical, thereby the description thereof will be omitted.
As mentioned above, in the base plate for packaging of above-mentioned each embodiment, the formation electric conductor pattern while overlookingIn the first electroformed layer 6 of 1 and the outer shape of the second electroformed layer 7 one square become larger than the opposing party, at mouldAny outer surface of body 2 processed, is formed with the bulk layers that stops electric conductor pattern 1 to come off from molding 211, thereby even when carry time, semiconductor element installation time base plate for packaging produced deflection, torsion etc.In the situation of distortion, can stop electric conductor pattern 1 to come off from molding 2 by bulk layers 11. Therefore,Can obtain following base plate for packaging: eliminate electric conductor pattern 1 and come off or to produce position inclined to one side from molding 2Move, and operation can carry simply time, when the installation of semiconductor element. And, and piece is setShape layer 11 correspondingly, improves the resistance with respect to the distortion such as deflection, torsion, thereby can suppress encapsulationSubstrate distortion.
Because the solder mask 26 by light-cured type forms bulk layers 11, so can be by photoetching process easilyForm the bulk layers 11 of desirable pattern, thereby can further reduce the encapsulation base that possesses bulk layers 11The manufacturing cost of plate. And, due to general photoresist phase using phenolic resins as base polymerRatio, the structural strength of solder mask 26 is high, thus can suppress the breakage of the bulk layers such as crack, breach 11,And can effectively stop electric conductor pattern 1 come off or produce position skew from molding 2.
And, in the manufacture method of the base plate for packaging of above-mentioned each embodiment, comprise electroforming process,Secondary electroforming process and bulk layers form operation, and form the base plate for packaging that possesses bulk layers 11. And,Form in operation in bulk layers, form solder mask 26 at any outer surface of molding 2, and pass through lightQuarter, method formed the bulk layers 11 of predetermined pattern. According to this manufacture method, can utilize with once and secondaryEach processing such as the equipment that electroforming process is identical exposes, develops, is dried, and can easily form ruleDetermine the bulk layers 11 of pattern, thereby can reduce the manufacturing cost of the base plate for packaging that possesses bulk layers 11.
And, the semiconductor device of semiconductor element S is installed at the base plate for packaging of above-mentioned each embodimentIn, connecting with metal wire W outer electrode 4 and the semiconductor element S institute that electric conductor pattern 1 possessesAfter the electrode 31 possessing, semiconductor element S and metal wire W are sealed by seal 30. According toThis semiconductor device, the outer electrode 4 that utilizes metal wire W to carry out and electrode 31 be connected operation, withAnd while utilizing the sealing operation that seal 30 carries out, if base plate for packaging has produced the distortion of deflection, torsion,Electric conductor pattern 1 also can not come off or produce position skew from molding 2, thereby can enter simplyThe operation of base plate for packaging when the above-mentioned operation of row. And, bad can reduce the manufacture of semiconductor device timeProduct formation rate, and can improve the productivity ratio of semiconductor device.
Above-mentioned first and the 3rd in embodiment, with second and the 4th embodiment identical, canBe formed with the nickel dam 15a of film-form and the electroforming master mold 15 of copper layer 15b carrys out manufacturing and encapsulation substrate with stacked.The fissility of the electroforming master mold 15 now, can improve master mold and remove operation time. And, second andIn the 4th embodiment, with first and the 3rd embodiment identical, can use do not possess nickel dam 15a withAnd the electroforming master mold 15 of copper layer 15b carrys out manufacturing and encapsulation substrate.
In above-mentioned each embodiment, electric conductor pattern 1 forms by electroforming, but can be by etchingAnd form. The outer shape of the first electroformed layer 6 and the second electroformed layer 7 is respectively as a flat layerAnd form, but the outer shape of the electroformed layer of a side of less formation can be also four frame shapes, circle frame shape," コ " shape, partial circle ring-type or be divided into multiple, in a word, if not from a side of larger formationOuter shape is outstanding, can adopt shape arbitrarily. Electric conductor pattern 1 also can possess mounting mat 3And beyond outer electrode 4, also possess sheet lead-in wire (tablead), terminal pin etc. Form the first electroformingLayer 6 and the metal material of the second electroformed layer 7, form moulded resin 22 and seal 30 resin material,The basis that forms the first photoresist layer 16 and the second photoresist layer 19 and solder mask 26 is poly-The resin material of compound etc. is not limited to the material of enumerating in above-mentioned embodiment. And molding 2 also canTo use welding resistance, and the material that can have a dielectricity by pottery etc. except resin material forms. Window12 opening shape is not limited to the shape of enumerating in above-mentioned embodiment, can stop electric conductor pattern 1Come off. Semiconductor element S also can be arranged on the one side that is formed with bulk layers 11 of base plate for packagingSide.
Claims (12)
1. a base plate for packaging, is configured to the state that electric conductor pattern (1) exposes with its upper and lower surface and buries undergroundAnd be held in molding (2), above-mentioned base plate for packaging is characterised in that,
Electric conductor pattern (1) by lower conductiving layer (6) and stacked be formed on lower conductiving layer (6) on leadElectricity layer (7) forms,
Lower conductiving layer (6) while overlooking and the outer shape of upper conductive layer (7) are formed as any one party than anotherOne side is large,
In the upper surface of molding (2) or any one party of lower surface, be formed with and stop electric conductor pattern(1) bulk layers (11) coming off from molding (2).
2. base plate for packaging according to claim 1, is characterized in that,
Bulk layers (11) is formed as the lower conductiving layer of the electric conductor pattern (1) to exposing from molding (2)(6) or a part for upper conductive layer (7) cover.
3. base plate for packaging according to claim 1 and 2, is characterized in that,
The outer shape of lower conductiving layer (6) is formed as larger than the outer shape of upper conductive layer (7),
Be formed with bulk layers (11) at the lower surface of molding (2).
4. base plate for packaging according to claim 1 and 2, is characterized in that,
The outer shape of upper conductive layer (7) is formed as larger than the outer shape of lower conductiving layer (6),
Be formed with bulk layers (11) at the upper surface of molding (2).
5. according to the base plate for packaging described in claim 1～4 any one, it is characterized in that,
Electric conductor pattern (1) forms by electroforming, is used to form lower conductiving layer (6) and upper conductive layer (7)Body lower against corrosion (18) and upper body against corrosion (21) double as the mould of burying underground and keeping electric conductor pattern (1)Body processed (2).
6. according to the base plate for packaging described in claim 1～5 any one, it is characterized in that,
Bulk layers (11) is formed by the solder mask (26) of light-cured type.
7. a manufacture method for base plate for packaging,
Bury underground and keep by lower conductiving layer (6) and the stacked lower conductiving layer (6) that is formed at molding (2)On upper conductive layer (7) form electric conductor pattern (1), make electric conductor pattern (1) in molding (2)Upper and lower surface expose,
In the upper surface of molding (2) or any one party of lower surface, be formed with and stop electric conductor pattern(1) bulk layers (11) coming off from molding (2), the feature of the manufacture method of above-mentioned base plate for packaging existsIn, comprising:
An electroforming process, in this operation, forms lower anti-on the surface of flat electroforming master mold (15)Erosion body (18), and lead under the surface of the electroforming master mold (15) not covered by lower body against corrosion (18) formsElectricity layer (6);
Secondary electroforming process, in this operation, resists with lower at lower conductiving layer (6) or lower conductiving layer (6)Erosion body (18) surface form body against corrosion (21), and not by body against corrosion (21) cover under leadConductive layer (7) in the stacked formation in surface of electricity layer (6) or lower conductiving layer (6) and lower body against corrosion (18);And
Bulk layers forms operation, in this operation, at the molding of burying and keep electric conductor pattern (1) underground(2) upper surface or any one party of lower surface, form bulk layers (11),
Form in operation in bulk layers, any one party shape of upper surface or the lower surface of molding (2)Become the solder mask (26) of light-cured type, and by photoetching process with to the lower conductiving layer exposing from molding (2)(6) or the mode that covers of a part for the exposed division of upper conductive layer (7) form bulk layers (11).
8. the manufacture method of base plate for packaging according to claim 7, is characterized in that,
After secondary electroforming process, carry out molding process, form and bury underground and keep electric conductor pattern (1)Molding (2),
In molding process, by once and the body lower against corrosion forming in secondary electroforming process and on against corrosionBody (18,21) is removed, and remove lower body against corrosion and on space after body against corrosion (18,21), fill outFill the moulded resin (22) having softened, make it to be afterwards solidified to form molding (2).
9. the manufacture method of base plate for packaging according to claim 8, is characterized in that,
In the situation of overlooking, the outer shape of lower conductiving layer (6) is formed as than the profile of upper conductive layer (7)Shape is large, and is formed with bulk layers (11) at the lower surface of molding (2),
Form between operation in molding process and bulk layers, comprise from electric conductor pattern (1) and molding(2) master mold of peeling off and remove electroforming master mold (15) is removed operation.
10. according to the manufacture method of the base plate for packaging described in claim 7 or 8, it is characterized in that,
In the situation of overlooking, the outer shape of upper conductive layer (7) is formed as than the profile of lower conductiving layer (6)Shape is large, and is formed with bulk layers (11) at the upper surface of molding (2),
After being included in bulk layers formation operation, peel off also from electric conductor pattern (1) and molding (2)Remove the master mold of electroforming master mold (15) and remove operation.
The manufacture method of 11. base plate for packaging according to claim 7, is characterized in that,
Be retained in once and the body lower against corrosion forming in secondary electroforming process and upper body against corrosion (18,21),And two bodies against corrosion (18,21) double as the molding (2) of burying underground and keep electric conductor pattern (1).
12. 1 kinds of semiconductor devices, are provided with half at the base plate for packaging described in claim 1～6 any oneConductor element (S), above-mentioned semiconductor device is characterised in that,
Electric conductor pattern (1) possesses outer electrode (4), at the electrode that semiconductor element (S) is possessed(31) and after outer electrode (4) electrical connection, utilize seal (30) sealing semiconductor element (S).
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014-242397 | 2014-11-28 | ||
| JP2014242397A JP6552811B2 (en) | 2014-11-28 | 2014-11-28 | Package substrate, method of manufacturing the same, and semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105655300A true CN105655300A (en) | 2016-06-08 |
| CN105655300B CN105655300B (en) | 2019-12-27 |
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| CN (1) | CN105655300B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105655300B (en) * | 2014-11-28 | 2019-12-27 | 麦克赛尔控股株式会社 | Package substrate, method for manufacturing the same, and semiconductor device |
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| JP2001044589A (en) * | 1999-07-30 | 2001-02-16 | Nitto Denko Corp | Circuit board |
| JP2005244033A (en) * | 2004-02-27 | 2005-09-08 | Torex Semiconductor Ltd | Electrode package and semiconductor device |
| TW200608851A (en) * | 2004-08-25 | 2006-03-01 | Shinko Electric Ind Co | Substrate, semiconductor device, substrate fabricating method, and semiconductor device fabricating method |
| US20070268675A1 (en) * | 2006-05-22 | 2007-11-22 | Hitachi Cable Ltd. | Electronic device substrate, electronic device and methods for fabricating the same |
| JP2012195430A (en) * | 2011-03-16 | 2012-10-11 | Sanken Electric Co Ltd | Light emitting diode and method for manufacturing the same |
| JP5174494B2 (en) * | 2008-03-10 | 2013-04-03 | 日東電工株式会社 | Wiring circuit board and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7851856B2 (en) * | 2008-12-29 | 2010-12-14 | Alpha & Omega Semiconductor, Ltd | True CSP power MOSFET based on bottom-source LDMOS |
| JP6552811B2 (en) * | 2014-11-28 | 2019-07-31 | マクセルホールディングス株式会社 | Package substrate, method of manufacturing the same, and semiconductor device |
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2014
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001044589A (en) * | 1999-07-30 | 2001-02-16 | Nitto Denko Corp | Circuit board |
| JP2005244033A (en) * | 2004-02-27 | 2005-09-08 | Torex Semiconductor Ltd | Electrode package and semiconductor device |
| TW200608851A (en) * | 2004-08-25 | 2006-03-01 | Shinko Electric Ind Co | Substrate, semiconductor device, substrate fabricating method, and semiconductor device fabricating method |
| US20070268675A1 (en) * | 2006-05-22 | 2007-11-22 | Hitachi Cable Ltd. | Electronic device substrate, electronic device and methods for fabricating the same |
| JP5174494B2 (en) * | 2008-03-10 | 2013-04-03 | 日東電工株式会社 | Wiring circuit board and manufacturing method thereof |
| JP2012195430A (en) * | 2011-03-16 | 2012-10-11 | Sanken Electric Co Ltd | Light emitting diode and method for manufacturing the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105655300B (en) * | 2014-11-28 | 2019-12-27 | 麦克赛尔控股株式会社 | Package substrate, method for manufacturing the same, and semiconductor device |
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| Publication number | Publication date |
|---|---|
| CN105655300B (en) | 2019-12-27 |
| TW201620084A (en) | 2016-06-01 |
| JP6552811B2 (en) | 2019-07-31 |
| JP2016103608A (en) | 2016-06-02 |
| TWI684250B (en) | 2020-02-01 |
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