CN103996663A

CN103996663A - Semiconductor modules and methods of formation thereof

Info

Publication number: CN103996663A
Application number: CN201410053705.XA
Authority: CN
Inventors: R·奥特雷姆巴; J·赫格劳尔
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 2013-02-18
Filing date: 2014-02-17
Publication date: 2014-08-20
Also published as: DE102014102006A1; US8916474B2; DE102014102006B4; DE102014019962B4; US20140232015A1

Abstract

In accordance with an embodiment of the present invention, a semiconductor module includes a first semiconductor package having a first semiconductor die, which is disposed in a first encapsulant. An opening is disposed in the first encapsulant. A second semiconductor package including a second semiconductor die is disposed in a second encapsulant. The second semiconductor package is disposed at least partially within the opening in the first encapsulant.

Description

Semiconductor module and forming method thereof

Technical field

The present invention relates in general to semiconductor device, and more specifically relates to semiconductor module and forming method thereof.

Background technology

Semiconductor device is used in many electronic application and other application.Semiconductor device comprises integrated circuit or discrete device, and this discrete device is permitted the film of eurypalynous material by deposition on semiconductor wafer and the film of this material of patterning is formed on semiconductor wafer to form integrated circuit.

Semiconductor device is encapsulated in the main body of pottery or plastics conventionally to protect it to avoid physical damage and corrosion.Encapsulation is gone back Supporting connectivity and is electrically contacted to device is needed.It is available being permitted type and desired use that eurypalynous encapsulation depends on packed nude film.Typical encapsulation (for example size, the pin-count of encapsulation) can be observed for example open standard from joint electron device engineering council (JEDEC).Encapsulation also can be called as semiconductor device assembling or only be called as assembling.

Encapsulation can be technique with high costs, and this is the complexity of simultaneously protecting these electrical connections and chip below due to multiple electrical connections are connected to external pads.

Device through encapsulation is installed on printed circuit board (PCB) or other equivalent unit for being connected with other parts.In many application, the limited space on printed circuit board (PCB) or for example, in final equipment (handheld device).Therefore encapsulate in some designs by mutually stacking.But in the time that parts must be packaged in the confined space, vertical stacking may be inadequate.Alternatively, in single package, the nude film of vertical stacking is more expensive due to more complicated packaging technology, and must design in advance and therefore cannot provide flexibility for client.

Summary of the invention

According to embodiments of the invention, a kind of semiconductor module comprises: the first semiconductor packages, comprises the first semiconductor die being arranged in the first encapsulation agent; Opening in the first encapsulation agent; And second semiconductor packages, comprise the second semiconductor die being arranged in the second encapsulation agent.Within the second semiconductor packages is arranged on the opening in the first encapsulation agent at least in part.

According to embodiments of the invention, a kind of semiconductor packages comprises the first semiconductor die being arranged in the first encapsulation agent, the opening in the first encapsulation agent, and is arranged at least in part the second semiconductor die within the opening in the first encapsulation agent.

According to embodiments of the invention, a kind of method that forms semiconductor module comprises: semiconductor packages is provided, and this semiconductor packages comprises the semiconductor die being arranged in the first encapsulation agent; And in the first encapsulation agent of semiconductor packages, form opening to expose multiple contacting metals of semiconductor die.Then on multiple contacting metals, form contact pad.Within opening, place semiconductor device and semiconductor device is attached to contact pad.

According to embodiments of the invention, the method that forms semiconductor module comprises: a semiconductor packages is provided, and this semiconductor packages comprises: multiple lead-in wires, supportted and be arranged on the first semiconductor die in the first encapsulation agent, a region be coupled to the clamp of the lead-in wire in multiple lead-in wires of semiconductor packages by nude film advance expenditure.In the first encapsulation agent of semiconductor packages, form the part of opening with the top surface of exposure clamp.Within semiconductor device is placed on to opening.Semiconductor device is attached to the part of the exposure of the top surface of clamp.

Brief description of the drawings

For the more complete understanding to the present invention and advantage thereof, referring now to following description together with accompanying drawing, in the accompanying drawings:

Fig. 1 comprises Figure 1A-1B, and Fig. 1 illustrates semiconductor module according to an embodiment of the invention, wherein Figure 1A illustrated section figure and Figure 1B illustrates top view;

Fig. 2 comprises Fig. 2 A-2B, and Fig. 2 illustrates semiconductor module according to an embodiment of the invention, wherein Fig. 2 A illustrated section figure and Fig. 2 B diagram top view;

Fig. 3 comprises Fig. 3 A-3C, and Fig. 3 illustrates semiconductor module according to an embodiment of the invention, wherein Fig. 3 A and Fig. 3 B illustrated section figure and Fig. 3 C diagram top view;

Fig. 4 illustrates the alternative of the sectional view of semiconductor module;

Fig. 5 diagram is overflowed the sectional view of the semiconductor module of layer according to having of alternative of the present invention;

Fig. 6 illustrates according to the semiconductor module with outstanding semiconductor device of alternative of the present invention;

Fig. 7 illustrates according to the semiconductor module of alternative of the present invention, and this semiconductor module has by Direct Bonding and there is no additional protective layer to the semiconductor device of base portion semiconductor packages;

Fig. 8 diagram is attached to the nude film of lead frame according to an embodiment of the invention during the making of base portion semiconductor module;

Fig. 9 comprises Fig. 9 A-9C, and Fig. 9 diagram is the semiconductor packages during making attached interconnection after according to an embodiment of the invention, wherein Fig. 9 A and Fig. 9 B illustrate dissimilar clamp and Fig. 9 C diagram as the bonding line interconnecting;

Figure 10 diagram is the semiconductor packages during forming making after protecting encapsulant layer nude film around according to an embodiment of the invention;

Figure 11 diagram forms the semiconductor packages during making after opening according to an embodiment of the invention in encapsulant layer.

Figure 12 diagram forms the semiconductor packages during making after pad according to an embodiment of the invention in the opening exposing;

Figure 13 diagram is placed the semiconductor packages during making after semiconductor device according to an embodiment of the invention on opening;

Figure 14 diagram semiconductor packages during making according to an embodiment of the invention, it has the second encapsulant material that is arranged on the first encapsulant material and fills the opening that accommodates semiconductor device;

Figure 15 diagram according to alternative of the present invention on the first encapsulant material, form opening after making during semiconductor module.

Figure 16 diagram is placed the semiconductor module during making after semiconductor device according to alternative of the present invention on opening;

Figure 17 diagram forms the semiconductor module during making after another encapsulation agent according to alternative of the present invention on semiconductor device.

Except as otherwise noted, corresponding label and symbol generally represents corresponding part in different accompanying drawings.Draw accompanying drawing with the related fields of illustrated embodiment clearly and may not draw in proportion.

Embodiment

Discuss in detail below making and the use of each embodiment.But should be understood that the invention provides many applicable inventive concepts that can embody in specific environment widely.The specific embodiment of discussing only illustrates to be made and uses ad hoc fashion of the present invention and do not limit the scope of the invention.

To utilize Fig. 1 to describe structural embodiment of the present invention.By utilizing Fig. 2-5, other alternative construction embodiment is described.By utilizing Fig. 8-14, the method for assembled semiconductor module is described.By utilizing Figure 15-17, the alternative of assembled semiconductor module is described.

Fig. 1 comprises Figure 1A-1B, and Fig. 1 illustrates semiconductor module according to an embodiment of the invention, wherein Figure 1A illustrated section figure and Figure 1B illustrates top view.

In each embodiment, semiconductor module comprises base portion semiconductor packages 200 and the semiconductor device on semiconductor packages 200 150.Although single semiconductor device 150 has been shown in each embodiment, embodiments of the invention comprise the more than one semiconductor device being stacked on semiconductor packages 200.In addition in certain embodiments, can be on semiconductor device 150 stacking one or more semiconductor devices.

With reference to Figure 1A, semiconductor packages comprises at least one nude film 50 being embedded in the first encapsulant material 80.Nude film 50 is arranged on lead frame 10, and lead frame 10 has multiple lead-in wires 60 and encapsulates for contact semiconductor.It can be any suitable material that nude film 50 is fixed to lead frame 10 that nude film 50 utilizes the first adhesive layer to be attached to lead frame 10, the first adhesive layers 30.The first bond layer 30 can be the conductibility bonding agent that permission contacts with the back side of nude film 50.For example, the back side of nude film 50 can comprise the contact pad for the nude film 50 that is coupled.Nude film 50 also can have the one or more contact pads on front.Nude film contact pad can comprise conductive of material, and can comprise gold, tin, copper, aluminium, silver, nickel, platinum and combination thereof.In other embodiments, semiconductor packages can comprise the encapsulation of any type, such as wafer-level package, wafer-level package comprises wafer level process encapsulation or embedded wafer level process encapsulation, BGA Package, thin outline packages, transistor outline package and other.In one embodiment, semiconductor packages is thin short outline packages (thin short outline package).

In each embodiment, nude film 50 can be coupled to multiple lead-in wires 60 by various types of interconnection.For example in one embodiment, the first clamp 20A and the second clamp 20B can be arranged on nude film 50 first contact areas and the second contact area, and are embedded in the first encapsulant material 80.In alternative, nude film 50 can utilize the interconnection (such as bonding line, pin, band and other suitable connected mode) of other type to be coupled.

The first and second clamp 20A and 20B can utilize the second adhesive phase 40 to be attached in nude film 50, and the second adhesive phase 40 can comprise conducting shell.In one or more embodiments, the first adhesive layer 30 and the second adhesive layer 40 can comprise the polymer such as cyaniding ester or epoxy resin, and can comprise silver-colored particle.In one embodiment, the first adhesive layer 30 and the second adhesive layer 40 can comprise composite material, and composite material is included in the conductive particles in polymeric matrix.In alternative, the first adhesive layer 30 and the second adhesive layer 40 can comprise conductibility nano pulp.Alternatively, in another embodiment, the first adhesive layer 30 and the second adhesive layer 40 can comprise the scolder such as lead-tin material.In each embodiment, can use any applicable conductibility binder material that comprises metal or metal alloy (such as aluminium, titanium, gold, silver, copper, palladium, platinum, nickel, chromium or nickel vanadium) to form the first adhesive layer 30 and the second adhesive layer 40.

As shown in Figure 1A, opening 100 is arranged in the first encapsulating material 80 above nude film 50.In one embodiment, opening 100 can expose one or more contact pads of nude film 50.Alternatively, opening 100 can be exposed to the metal level on nude film 50.In one embodiment, opening 100 exposes a part of the first and second clamp 20A and 20B.

Semiconductor device 150 is arranged on the first and second clamp 20A and 20B in opening 100.In each embodiment, semiconductor device 150 can be fully arranged in opening 100.Alternatively, in certain embodiments, semiconductor device 150 can protrude through outside opening 100.

In each embodiment, semiconductor device 150 can be single die package or can comprise multiple nude films.In alternative, semiconductor device 150 can comprise semiconductor die before encapsulation.In certain embodiments, semiconductor device 150 can comprise the wafer-level package of for example utilizing wafer level process to produce.In other embodiments, semiconductor device 150 can comprise the encapsulation of other type, such as BGA Package, thin short outline packages, transistor outline package and other.

In certain embodiments, semiconductor device 150 can comprise the passive device such as inductor, resistor and/or capacitor.In one embodiment, semiconductor device 150 comprises it being for example the discrete passive component of discrete inductor, discrete resistor or discrete capacitor.

As shown in Figure 1A, semiconductor device 150 can comprise that component pad 140 is for contacting semiconductor device 150 and be coupled with the first and second clamp 20A below with 20B.In one embodiment, component pad 140 can directly be coupled to the first and second clamp 20A and 20B.In alternative, it is for example that solder material, conductibility slurry and other adhesive layer are attached to the first and second clamp 20A and 20B that component pad 140 can be utilized.

In one or more embodiments, the second encapsulating material 180 can be arranged on semiconductor device 150.Partially or fully filling opening 100 of the second encapsulating material 180.In one embodiment, the first encapsulating material 80 and the second encapsulating material 180 can comprise identical material.But in certain embodiments, the first encapsulating material 80 can be different from the second encapsulating material 180.Particularly, the second encapsulating material 180 may form (deposition and curing) in the temperature lower than the first encapsulating material 80.In addition, the second encapsulating material 180 may need to flow in the cavity between semiconductor device 150 and the sidewall of opening 100.Therefore, the second encapsulating material 180 can be designed as than the first encapsulating material 80 and flows better.

As shown in Figure 1A, the first encapsulating material 80(or base portion semiconductor packages 200) there is the first thickness D1, this thickness D1 is the thickness of base portion semiconductor packages.Semiconductor device 150 has the second thickness D2, and this thickness D2 is less than the first thickness D1.But, comprising that the assembled package of base portion semiconductor packages and semiconductor device 150 has the 3rd thickness D3, this thickness D3 is less than the first thickness D1 and the second thickness D2 sum.

Figure 1B illustrates the cross-sectional top view of semiconductor packages.As shown in Figure 1B, the first and second clamp 20A and 20B extend to multiple lead-in wires 60 on nude film 50.Semiconductor device 150 is set up on the first and second clamp 20A and 20B in opening 100.

Therefore,, in each embodiment, semiconductor device uses the lead-in wire of base portion semiconductor packages to contact with external component.

Fig. 2 comprises Fig. 2 A-2B, and Fig. 2 illustrates semiconductor module according to an embodiment of the invention, wherein Fig. 2 A illustrated section figure and Fig. 2 B diagram top view.

In multiple embodiment, semiconductor device 150 can be placed on the optional position on semiconductor packages.For example, in an embodiment shown in Fig. 2, semiconductor device 150 is placed a side of semiconductor packages on multiple clamps.

Fig. 3 comprises Fig. 3 A-3C, and Fig. 3 illustrates semiconductor module according to an embodiment of the invention, wherein Fig. 3 A and Fig. 3 B illustrated section figure and Fig. 3 C diagram top view.

In alternative, semiconductor device 150 can directly be placed on the contact pad of nude film 50.As shown in Figure 3A, base portion semiconductor packages 200 can be included in the nude film 50 on the first first type surface with multiple contact areas.The second first type surface of nude film 50 can utilize the adhesive layer 30 as described at embodiment to be before coupled to the nude film pad (die paddle) 10 of lead frame.

In each embodiment, nude film 50 can be coupled to multiple lead-in wires 60.In one embodiment, semiconductor device 150 can be coupled to the lead-in wire 130 that heavily distributes, and the lead-in wire 130 that heavily distributes in certain embodiments can be coupled to nude film 50.Alternatively, one or more heavy distribution lead-in wires 130 can be isolated with nude film 50 electricity.For example, the contact pad of semiconductor device 150 can be coupled to the lead-in wire in multiple lead-in wires 60 and not be coupled to nude film 50.

In one embodiment, semiconductor device 150 can protrude through outside the first encapsulating material 80.In other embodiments, within semiconductor device 150 can be fully arranged on base portion semiconductor packages 200.

In one or more embodiments, can on base portion semiconductor 200 or the first encapsulating material 80, cover the second encapsulating material 180.The second encapsulating material 180 can partially or fully be filled the opening 100 in the first encapsulating material 80.

Fig. 3 C illustrates the top view of semiconductor module according to an embodiment of the invention.As shown in Figure 3 C, nude film 50 can utilize various types of interconnection to be coupled to multiple lead-in wires 60.For example, Fig. 3 C illustrates that the first clamp 20A and the second clamp 20B are coupled to the difference lead-in wire in multiple lead-in wires 60.In addition, semiconductor device 150 be coupled to first heavily distribute lead-in wire 130A and second heavily distributes go between 130B.The lead-in wire that heavily distributes can have different shapes in each embodiment.For example in one embodiment, illustrate L shaped heavily distribution lead-in wire as the second lead-in wire 130B that heavily distributes.As further illustrated in Fig. 3 C, first heavily distribute lead-in wire 130A be coupled to the first contact pad 140A, and second heavily distribute lead-in wire 130B be coupled to the second contact pad 140B.The first and second contact pad 140A and 140B can be parts for semiconductor device 150.

In each embodiment, the one or more pads on nude film 50 can utilize bonding line 75 to be coupled to multiple lead-in wires 60.In one embodiment, nude film 50 can be power nude film, and it is configured to operate with for example high voltage more than 20V.In one embodiment, the gate regions of power nude film can utilize bonding line 75 and be coupled, and the source area of power nude film can utilize clamp type interconnect and be coupled.Embodiments of the invention are included in the combination of the embodiment describing in Fig. 2 and Fig. 3.For example in one embodiment, first component can be stacked on the contacting metal of base portion semiconductor packages as shown in Figure 3, and second component can be stacked on clamp as shown in Figure 2.

Fig. 4 illustrates the alternative of the sectional view of semiconductor module.

With reference to Fig. 4, within semiconductor device 150 is fully arranged on the opening 100 of the first encapsulating material 80.As shown in the figure, the second thickness D2 can be less than the height of opening 100.In such embodiments, the first thickness D1 of base portion semiconductor packages 200 and the 3rd thickness D3 of semiconductor module are roughly the same.

Fig. 5 diagram is overflowed the semiconductor module of layer (overflow layer) according to having of alternative of the present invention.

In one or more embodiments, the second encapsulating material 180 can have the portion of overflowing of the top main surfaces that covers the first encapsulating material 80.Overflow layer leafing (delamination) that can contribute to prevent the second encapsulating material 180 around the turning of opening 100.

Fig. 6 illustrates according to semiconductor module alternative of the present invention, that have outstanding semiconductor device.

In one or more embodiments, semiconductor device 150 can be bonded to the clamp of base portion semiconductor packages 200.In certain embodiments, the height of opening 100 can be less than the height (the second depth D 2) of semiconductor device.In such embodiments, semiconductor device 150 can highlight.In addition as shown in the figure, in certain embodiments, may be without additional encapsulating material or protective material.In one embodiment, semiconductor device 150 can, by Direct Bonding, further not processed after this.This can be useful for minimization cost, and can carry out at low cost facility place.

Fig. 7 illustrates according to the semiconductor module of alternative of the present invention, and this semiconductor module has by Direct Bonding and there is no additional protective layer to the semiconductor device of base portion semiconductor packages 200.

In another embodiment, semiconductor device 150 is bonded to bonding welding pad or the contact pad of base portion semiconductor packages 200.As in the embodiment of Fig. 6, on base portion semiconductor packages 200, there is no additional protective layer.Thereby remain with gap between the sidewall of opening 100 and semiconductor device 150.In the embodiment shown, semiconductor device 150 is fully arranged in opening 100.Equally, because it needs minimum treatment step, so this embodiment can carry out in low cost facility.

Fig. 8 to 14 illustrates each stage of the making of semiconductor module according to an embodiment of the invention.

In each embodiment, base portion semiconductor packages 200 can be the encapsulation of any type.In one embodiment, base portion semiconductor packages 200 is lead-frame packages.Fig. 8 to 10 diagram is according to the making of the lead-frame packages of an embodiment.If but base portion semiconductor packages is different, those skilled in the art can correspondingly revise the making of base portion semiconductor packages.

For example can utilize conventional treatment to carry out scribing to form multiple nude films 50 to wafer.Can such as body silicon substrate or silicon-on-insulator (SOI) substrate silicon-like substrate on form nude film 50.Alternatively, nude film 50 can be at the upper device forming of silicon-carbon-silicon carbide (SiC).Embodiments of the invention can also be included in the device forming on composite semiconductor substrate, and can be included in the device on heteroepitaxy substrate.In one embodiment, nude film 50 is the devices that above form at gallium nitride (GaN) at least in part, and this gallium nitride (GaN) can be the gallium nitride (GaN) on sapphire or silicon substrate.

In each embodiment, nude film 50 can comprise power chip, and this power chip for example can draw (being for example greater than 30 amperes) large electric current.In each embodiment, nude film 50 can comprise discrete vertical device, such as two-terminal power device or three terminal power devices.The example of nude film 50 comprises PIN or Schottky diode, MISFET, JFET, BJT, IGBT or thyristor.

In each embodiment, nude film 50 can be to be configured to the vertical semiconductor device to about 1000V operation at about 20V.In one embodiment, nude film 50 can be configured at about 20V to about 100V operation.In another embodiment, nude film 50 can be configured at about 100V to about 500V operation.In another embodiment, nude film 50 can be configured at about 500V to about 1000V operation.In one embodiment, nude film 50 can be NPN transistor.In another embodiment, nude film 50 can be PNP transistor.In another embodiment, nude film 50 can be n raceway groove MISFET.In an embodiment again, nude film 50 can be p raceway groove MISFET.In one or more embodiments, nude film 50 can comprise multiple devices, such as vertically MISFET and diode or alternatively for being isolated two MISFET devices that distinguish.

In each embodiment, the thickness from the extremely relative basal surface of top surface of nude film 50 can be less than 50 μ m.In one or more embodiments, the thickness to basal surface from top surface of nude film 50 can be less than 20 μ m.In certain embodiments, in order to improve heat radiation, in one or more embodiments, the thickness to basal surface from top surface of nude film 50 can be less than 10 μ m.

With reference to Fig. 8, on lead frame 10, place nude film 50.Can utilize the first adhesive layer 30 that nude film 50 is attached to lead frame 10, the first adhesive layer 30 can insulate in one embodiment.In certain embodiments, the first adhesive layer 30 can be conductive, for example, can comprise nanometer conductibility slurry.In alternative, the first adhesive layer 30 is can welding material.

In one embodiment, the first adhesive layer 30 comprises the polymer such as cyaniding ester or epoxide resin material, and can comprise silver-colored particle.In one embodiment, the first adhesive layer 30 can be applied as the conductive particles in polymeric matrix, to form composite material after solidifying.In alternative, can apply the conductibility nano pulp such as silver nanoparticle slurry.Alternatively, in another embodiment, the first adhesive layer 30 comprises the scolder such as lead-tin material.In each embodiment, can use any applicable conductibility binder material that comprises metal or metal alloy (such as aluminium, titanium, gold, silver, copper, palladium, platinum, nickel, chromium or nickel vanadium) to form die attached layer 280.

Can under nude film 50, grant the first adhesive layer 30 by controlled amounts.First adhesive layer 30 with polymer can be cured at approximately 125 DEG C to approximately 200 DEG C, and the first adhesive layer 30 based on scolder can be cured at 250 DEG C to approximately 350 DEG C.Utilize the first adhesive layer 30 nude film 50 to be attached to the nude film pad of lead frame 10.

Fig. 9 comprises Fig. 9 A-9C, and Fig. 9 diagram is the semiconductor packages during making after attached interconnection according to an embodiment of the invention.Fig. 9 A and Fig. 9 B illustrate dissimilar clamp and the bonding line of Fig. 9 C diagram conduct interconnection.

With reference to Fig. 9 A, at an embodiment, multiple clamps (for example the first clamp 20A) are attached to the pad on nude film 50.For example can while attached other clamp (not shown) in another sectional plane.Can on nude film 50, form the second adhesive layer 40, and can utilize the second adhesive layer 40 that the first fixture 20A is attached to nude film 50.Utilize the second adhesive layer 40 that nude film 50 is attached to the first clamp 20A.With reference to Fig. 9 A, can utilize another part of the second adhesive layer 40 that the other end of the first clamp 20A is attached to the lead-in wire in multiple lead-in wires 60.In each embodiment, can form the second adhesive layer 40 according to the mode similar to the first adhesive layer 30.

In one or more embodiments, the second adhesive layer 40 can be the adhesive layer of conduction.In other embodiments, the second adhesive layer 40 can be slicken solder or nanometer die attached thing.In one embodiment, the second adhesive layer 40 comprises the polymer such as cyaniding ester or epoxide resin material, and can comprise silver-colored particle.In one embodiment, the second adhesive layer 40 can be applied as the conductive particles in polymeric matrix, to form composite material after solidifying.In alternative, can apply the conductibility nano pulp such as silver nanoparticle slurry.Alternatively, in another embodiment, the second adhesive layer 40 comprises the scolder such as lead-tin material.In each embodiment, can use any applicable conductibility binder material that comprises metal or metal alloy (such as aluminium, titanium, gold, silver, copper, palladium, platinum, nickel, chromium or nickel vanadium) to form the second adhesive layer 40.Can solidify second adhesive layer 40 with polymer at approximately 125 DEG C to approximately 200 DEG C, and can be at 250 DEG C to approximately 350 DEG C the second adhesive layers 40 that solidify based on scolder.

In one or more embodiments, utilize wiring bonding technology (Fig. 9 A) to use bonding line 75 that other contact pad on nude film 50 is coupled to lead frame 10.Can utilize soldered ball bonding line 75 to be soldered to lead-in wire 60 and the contact pad of lead frame 10.In one or more embodiments, can minimize the time that forms wiring bonding with high speed wiring bonding apparatus.In certain embodiments, during wiring bonding technology, can carry out orientation to nude film 50 with image identification system.

The alternative of Fig. 9 B diagram interconnection, compacting in this interconnection, molded or bending clamp are to form and the contacting of nude film 50.Fig. 9 C diagram is utilized another alternative of wiring bonding.Some line bonding in line bonding can be thicker in to support higher electric current.For example, going to the source connection bonding 75S of the source electrode contact pad of nude film 50 can be thicker than the grid connection bonding 75G that goes to gate contact pad.

Figure 10 diagram is the semiconductor module during forming making after protecting encapsulant layer nude film around according to an embodiment of the invention.

With reference to Figure 10, deposit the first encapsulating material 80 comprising on multiple clamps, nude film 50 and the lead frame 10 of the first clamp 20A.In each embodiment, on whole the first clamp 20A, nude film 50 and lead frame 10, cover the first encapsulating material 80.Thereby nude film 50 is embedded in the first encapsulating material 80.In one embodiment, utilize compression molded technique to apply the first encapsulating material 80.In compression molded, the first encapsulating material 80 can be placed in molding cavity, then close molding cavity to compress the first encapsulating material 80.In the time of molded single pattern, can utilize compression molded.In alternative, for example, in batch processing, utilize transmission molding process to apply the first encapsulating material 80, and can after curing process, form independent encapsulation by singualtion.

In other embodiments, can utilize injection molding, granulation is molded, powder is molded or molded first encapsulating material 80 that applies of liquid.Alternatively, can utilize the typography such as masterplate or silk screen printing to apply the first encapsulating material 80.

In each embodiment, the first encapsulating material 80 comprises dielectric material, and can comprise mold compound in one embodiment.In other embodiments, the first encapsulating material 80 can comprise polymer, biopolymer, fiber impregnation polymer (for example carbon fiber in resin or glass fibre), be filled with polymer and other organic material of particle.In one or more embodiments, the first encapsulating material 80 comprises the sealant that not utilizes mold compound and the material such as epoxy resin and/or silicones to form.In each embodiment, the first encapsulating material 80 can be made up of any suitable rigid plastics, thermoplastics or thermosets or laminated sheet.The material of the first encapsulating material 80 can comprise packing material in certain embodiments.In one embodiment, the first encapsulating material 80 can comprise epoxide resin material and packing material, and this packing material comprises other electric insulation mineral filler or the granule of organic filler material of glass or picture aluminium oxide and so on.

The first encapsulating material 80 can be solidified, through heat-treated with sclerosis, thereby form the sealing of protection nude film 50, the first and second adhesive layers 30 and 40, the first clamp 20A and lead frame 10.Therefore form base portion semiconductor packages 200 according to embodiments of the invention.

Follow with reference to Figure 11, can be at the interior formation opening 100 of base portion semiconductor packages 200.Opening 100 is intended to open contact area on nude film 50.For example, opening 100 can be opened the metal that heavily distributes on nude film 50.Alternatively, opening 100 can be opened the region of the first clamp 20A.Can utilize in one embodiment etch process to form opening 100.In another embodiment, can utilize laser technology (for example localized heating technique) to form opening 100.In each embodiment, can utilize chemistry, machinery, plasma and/or heating process to form opening 100.

Figure 12 diagram forms the semiconductor packages during making after pad according to an embodiment of the invention in the opening exposing.

Then as shown in figure 12, in one or more embodiments, can carry out electroplating technology (galvanic process) to be formed on the larger contact area on nude film 50.In one embodiment, the contact pad of nude film 50 can be exposed to electroplating technology.The electroplating technology copper layer of can growing on the pad of the exposure of nude film 50, forms thus and electroplates pad 55.

For example in one embodiment, nude film 50 can comprise heavy distributing line and/or below bump metal, and this below bump metal can comprise multilayer.For example, stackingly can comprise conductive pads, Seed Layer and the thin conducting shell forming in the above.In each embodiment, opening 100 can expose these heavy distributing lines and/or below bump metal pad.

In each embodiment, can on these heavy distributing lines, form by electroplating technology additional contact pad (electroplating pad 55).In each embodiment, can deposit the plated metal such as copper.Although can use in certain embodiments other applicable conductor.In a further embodiment, additional contact pad can be configured to form and be bonded to the good bonding of the semiconductor device 150 of base portion semiconductor packages 200.In each embodiment, electroplate pad 55 and can comprise multilayer, for example comprise in one embodiment Cu/Ni, Cu/Ni/Pd/Au, Cu/NiMoP/Pd/Au or Cu/Sn.In the time combining with the contact material of semiconductor device 150, can select the material of electroplating pad 55 for example, to form scolder (eutectic solder).

Figure 13 diagram is placed the semiconductor module during making after semiconductor device according to an embodiment of the invention on opening.

Then with reference to Figure 13, on the opening 100 in base portion semiconductor packages 200, locate semiconductor device 150.Semiconductor device 150 can be attached to and electroplate pad 55.In each embodiment, can utilize nanometer conductibility slurry, solder material to carry out the attached of semiconductor device 150.In another embodiment, the component pad on semiconductor device 150 140 is bonded to and electroplates pad 55.

In one or more embodiments, can utilize electroplating technology to carry out the cutting lead-in wire that heavily distributes.As an example, can widen the lead-in wire that heavily distributes to form contact pad.In another example, can be in certain embodiments at the new heavily distribution lead-in wire of the interior formation of opening 100.

In certain embodiments, can stop further processing.But in alternative, within semiconductor device 150 can being sealed in to the second encapsulating material 180.

Figure 14 diagram semiconductor packages during making according to an embodiment of the invention, it has the second encapsulant material that is arranged on the first encapsulant material and fills the opening that accommodates semiconductor device.

Can on the first type surface of base portion semiconductor packages 200, apply the second encapsulating material 180.The second encapsulating material 180 can be filled the gap entering between semiconductor device 150 and the sidewall of opening 100.In a further embodiment, the second encapsulating material 180 can be liquid, and it flows with any space between filling semiconductor parts 150 and nude film 50 below semiconductor device 150.

In each embodiment, on the whole surface of the first encapsulating material 80, apply the second encapsulating material 180, and the second encapsulating material 180 is cured.In one embodiment, the second encapsulating material 180 can be put into molding cavity, then close molding cavity to compress the second encapsulating material 180.After curing process, can obtain final structure.

Figure 15 to 17 diagram is according to the semiconductor module during each stage of making of alternative of the present invention.

In the embodiment shown in fig. 15, opening 100 exposes a part of clamp (such as the first clamp 20A).Electroplating technology can form additional contact pad or solder layer (be illustrated as and electroplate pad 55) on the part of the exposure of the first clamp 20A.For example, can on the first clamp 20A, deposit in one or more embodiments the multiple-level stack of Cu/Ni, Cu/Ni/Pd/Au, Cu/NiMoP/Pd/Au or Cu/Sn.

Figure 16 diagram is placed the semiconductor module during making after semiconductor device according to alternative of the present invention on opening.On opening 100, place semiconductor device 150, and be for example bonded to and electroplate pad 55(Figure 16 by application of pressure and/or heating).

Figure 17 diagram forms the semiconductor module after another encapsulation agent according to alternative of the present invention on semiconductor device.

As shown in figure 17, in certain embodiments, can utilize the second encapsulating material 180 to carry out sealing semiconductor parts 150 alternatively.Alternatively, in certain embodiments, can avoid further processing to minimize production cost.

Although described the present invention with reference to illustrative embodiment, this description is not intended to understand on limited significance.After with reference to description, the various amendments of illustrative embodiment of the present invention and other embodiment and combination will will be apparent to those skilled in the art.As example, the embodiment describing in Fig. 1-17 can combine mutually in alternative.What therefore wish is that claims contain any such amendment or embodiment.

Although described the present invention and advantage thereof in detail, should be appreciated that and can make various changes, replacement and change and not depart from the spirit and scope of the present invention as defined by the appended claims at this.What for example, the person skilled in the art will easily understand is to make a change and still within the scope of the invention many features described herein, function, technique and material.

The specific embodiment of technique, machine, manufacture, material composition, device, method and step that in addition, the application's scope is not intended to be limited to describe in specification.Those skilled in the art by be easy to public consciousness according to the present invention to can utilize according to the present invention current existing or need after exploitation technique, machine, manufacture, material composition, device, method and step, it is carried out substantially the same function with corresponding embodiment or reaches substantially the same result.Therefore, claims are intended to comprise this type of technique, machine, manufacture, material composition, device, method and step within the scope of it.

Claims

1. a semiconductor module, comprising:

The first semiconductor packages, comprises the first semiconductor die being arranged in the first encapsulation agent;

Opening in described the first encapsulation agent; And

The second semiconductor packages, comprises the second semiconductor die being arranged in the second encapsulation agent, within wherein said the second semiconductor packages is arranged on the described opening in described the first encapsulation agent at least in part.

2. semiconductor module according to claim 1, also comprises:

Be arranged on the 3rd encapsulation agent on described the second semiconductor packages.

3. semiconductor module according to claim 1, wherein said the first semiconductor die and described the second semiconductor die comprise discrete power semiconductor.

4. semiconductor module according to claim 1, wherein said the first semiconductor packages comprises the clamp that the contact pad on described the first semiconductor die is coupled to lead-in wire, and wherein said the second semiconductor packages comprises the contact pad of a part that is coupled to described clamp.

5. semiconductor module according to claim 1, wherein said the first semiconductor die comprises contact pad, wherein said the second semiconductor packages comprises the contact pad of the described contact pad that is coupled to described the first semiconductor die.

6. semiconductor module according to claim 1, also comprise the heavy distribution layer that is arranged on described the first semiconductor die, be arranged on the contact pad on described heavy distribution layer, described the second semiconductor packages comprises the component pad that is coupled to described contact pad.

7. semiconductor module according to claim 1, wherein said the second semiconductor packages comprises inductor, resistor and/or capacitor.

8. semiconductor module according to claim 1, wherein said the second semiconductor packages comprises discrete passive component.

9. a semiconductor module, comprising:

Semiconductor packages, comprises the first semiconductor die being arranged in the first encapsulation agent;

Opening in described the first encapsulation agent; And

The second semiconductor die, within being arranged at least in part the described opening in described the first encapsulation agent.

10. semiconductor module according to claim 9, wherein said the second semiconductor die comprises inductor, resistor and/or capacitor.

11. semiconductor modules according to claim 9, wherein said the second semiconductor die comprises discrete passive component.

12. semiconductor modules according to claim 9, also comprise:

Be arranged on the second encapsulation agent on described the second semiconductor die and described semiconductor packages.

13. semiconductor modules according to claim 12, wherein said the first semiconductor die and described the second semiconductor die comprise discrete power semiconductor.

14. semiconductor modules according to claim 12, wherein said the second semiconductor die is projected into outside described opening.

15. semiconductor modules according to claim 12, within wherein said the second semiconductor die is completely set in described opening.

16. semiconductor modules according to claim 12, wherein said semiconductor packages comprises the clamp that the contact pad on described the first semiconductor die is coupled to lead-in wire, wherein said the second semiconductor die comprises the contact pad of a part that is coupled to described clamp, and wherein said the second semiconductor die is arranged on described clamp.

17. semiconductor modules according to claim 12, wherein said the first semiconductor die comprises the first contact pad, wherein said the second semiconductor die comprises the second contact pad of described the first contact pad that is attached to described the first semiconductor die.

18. 1 kinds form the method for semiconductor module, and described method comprises:

Semiconductor packages is provided, and described semiconductor packages comprises the semiconductor die being arranged in the first encapsulation agent;

In described first encapsulation agent of described semiconductor packages, form opening to expose multiple contacting metals of described semiconductor die;

On described multiple contacting metals, form contact pad;

Within described opening, place semiconductor device; And

Described semiconductor device is attached to described contact pad.

19. methods according to claim 18, are also included in and on described semiconductor device, form the second encapsulation agent.

20. methods according to claim 18 wherein form contact pad and comprise execution electrochemical deposition process on described multiple contacting metals.

21. methods according to claim 18, are wherein attached to described semiconductor device described contact pad and comprise and carry out semiconductor device described in electric coupling by bonding technology.

22. methods according to claim 18, are also included in described semiconductor device are attached to and apply the second encapsulation agent after described contact pad.

23. methods according to claim 18, wherein said semiconductor die comprises power semiconductor die.

24. methods according to claim 18, wherein said semiconductor device comprises the semiconductor die being encapsulated within encapsulation agent.

25. methods according to claim 18, wherein said semiconductor device is included in the semiconductor die after wafer singualtion.

26. 1 kinds form the method for semiconductor module, and described method comprises:

Semiconductor packages is provided, and described semiconductor packages comprises:

Multiple lead-in wires;

The first semiconductor die, it supports and is arranged in the first encapsulation agent by nude film advance expenditure,

Clamp, it is coupled to a region in the lead-in wire in described multiple lead-in wires of described semiconductor packages;

In described first encapsulation agent of described semiconductor packages, form opening to expose the part of top surface for described clamp;

Within described opening, place semiconductor device; And

Described semiconductor device is attached to the described part of the exposure of the described top surface of described clamp.

27. methods according to claim 26, are also included in and on described semiconductor device, form the second encapsulation agent.

28. methods according to claim 26, the described part that is also included in the described top surface that exposes described clamp deposits contact pad by carrying out electrochemical deposition process afterwards.

29. methods according to claim 26, are also included in attached described semiconductor device and apply the second encapsulation agent afterwards.

30. methods according to claim 26, wherein said semiconductor device comprises the semiconductor die being encapsulated in encapsulation agent.

31. methods according to claim 26, wherein said semiconductor device is included in the semiconductor die after wafer singualtion.