CN205319149U - Semiconductor package - Google Patents
Semiconductor package Download PDFInfo
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- CN205319149U CN205319149U CN201521108674.XU CN201521108674U CN205319149U CN 205319149 U CN205319149 U CN 205319149U CN 201521108674 U CN201521108674 U CN 201521108674U CN 205319149 U CN205319149 U CN 205319149U
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- fin
- die
- semiconductor package
- package body
- semiconductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The utility model relates to a semiconductor package. The one or more embodiment relates to the semiconductor package including integral fin. In an embodiment, this semiconductor package is including the semiconductor nude film that is coupled to the first surface of nude film pad. The fin is coupled to the second surface of this nude film pad. The encapsulating material surrounds this nude film and this nude film pad and on this fin partly and the location. The the bottom part of this fin can keep exposing from this encapsulating material. In addition, a part of one side extension that can follow this encapsulating material of this fin. According to the utility model discloses a scheme can provide a performance modified semiconductor package.
Description
Technical field
This disclosure relates to semiconductor package body.
Background technology
Semiconductor package body is subject to sizable heat during operation. Power device package body feelingsCondition is especially true, and these packaging bodies comprise the power device with high electric current and/or voltage level operationPart, thereby the heat of generation significant quantity.
In order to help to remove heat from packaging body body, outside power device package body is coupled to conventionallyPortion's radiator. But external heat sink is limited in the amount of the heat that can remove. AlsoBe exactly that radiator only can remove the heat that it receives from packaging body. Therefore, expect packaging bodyInterior improvement is to be fully passed to radiator by the heat being produced by packaging body.
Usually describe, power device package body generally includes the die pad that is mounted to lead frameSemiconductor die. Dielectric substance (as encapsulating material) covers semiconductor die and nude film welderingDish. But conventionally, the lower surface of die pad keeps exposing. Die pad be receive byThe Heat Conduction Material of the heat that nude film produces. The lower surface of die pad can be coupled to radiatorHeat transmission is left to packaging body.
Recently, the thickness of die pad increases, and part is in order to improve the heat power of packaging bodyLearn. Namely, in order to improve the heat transmission from packaging body to radiator. But this significantly increasesAdd the cost of packaging body. Therefore, further improve and expect.
Summary of the invention
One or more embodiment relate to a kind of semiconductor package body that comprises integral fin. ?In an embodiment, provide a kind of semiconductor package body, it is characterized in that, comprising: nude film welderingDish, described die pad has first surface and separates the of the first thickness with described first surfaceTwo surfaces; A plurality of leads, described a plurality of leads has identical with described the first thickness second thickDegree; The first jointing material, described the first jointing material has the first melt temperature; Second is bondingMaterial, described the second jointing material has the second melt temperature, the institute of described the second jointing materialState the second melt temperature higher than described first melt temperature of described the first jointing material; Partly leadBody nude film, described semiconductor die is coupled to described die pad by described the first jointing materialDescribed first surface, described semiconductor die is electrically coupled to described a plurality of leads; Fin,Described fin is coupled to described second of described die pad by described the second jointing materialSurface; And encapsulating material, described encapsulating material is in described semiconductor die, the weldering of described nude filmOn dish and the part of surrounding described fin and described a plurality of leads.
In one embodiment, described fin is from the side surface of described encapsulating material to extensionStretch.
In one embodiment, the outer surface of described packaging body by the surface of described encapsulating material andThe surface of described fin forms.
In one embodiment, the described surface of described encapsulating material and described fin described inSurface co-planar.
In one embodiment, this semiconductor package body further comprises described semiconductor dieBe electrically coupled to the conductor wire of described a plurality of leads.
In one embodiment, described fin is metal material or pottery.
In one embodiment, described the second jointing material is conductive adhesion material.
Another embodiment provides a kind of semiconductor package body, it is characterized in that, comprising: nude film welderingDish, described die pad has first surface and second surface; A plurality of leads; Semiconductor die,Described semiconductor die is coupled to the described first surface of described die pad and is electrically coupled to instituteState a plurality of leads; Fin, described fin is coupled to described nude film weldering by electroconductive binderThe described second surface of dish; And encapsulating material, it is naked that described encapsulating material covers described semiconductorAt least a portion of one or more side surfaces of sheet, described die pad and described fin.
In one embodiment, described encapsulating material covers the side of the Part I of described finSurface, wherein, the side surface of the Part II of described fin keeps revealing from described encapsulating materialGo out.
In one embodiment, described semiconductor die is coupled to described nude film by jointing materialThe described first surface of pad, described jointing material is different from described conductive adhesion material.
In one embodiment, described jointing material has lower than described conductive adhesion materialMelt temperature.
According to scheme of the present utility model, can provide a kind of semiconductor packages of improvement in performanceBody.
Brief description of the drawings
In the accompanying drawings, the similar element of identical reference numbers identify. May not draw in proportionThe size of the element in accompanying drawing and relative position.
Figure 1A to Fig. 1 D has shown according to the various of the semiconductor package body of an embodiment and has lookedFigure.
Fig. 2 A is the top view of leadframe strip.
Fig. 2 B to Fig. 2 E has shown the semiconductor packages that is used to form according to the embodiment of this disclosureThe horizontal stroke in each stage of the assembly technology of body (as the semiconductor package body of Figure 1A to Fig. 1 D)Sectional view.
Detailed description of the invention
Should be understood that, although described for illustration purposes the concrete reality of this disclosure at thisExecute example, but can in the case of not departing from the spirit and scope of this disclosure, make various amendments.
In the following description, stated some detail to provide disclosed themeThe complete understanding of different aspect. But disclosed theme can not have these detailsSituation under implement. In some instances, not yet to being included in the enforcement of this disclosed themeWell-known semiconductor machining structure and the method (as semiconductor power device) of example are carried out in detailCarefully describe to avoid the otherwise description of fuzzy disclosure.
Figure 1A is according to the top view of the semiconductor package body 10 of this disclosure embodiment.Figure 1B and Fig. 1 C are respectively upward view and the side views of the semiconductor package body 10 of Figure 1A,And Fig. 1 D is the cross-sectional view of the semiconductor package body 10 of Figure 1A.
Semiconductor package body 10 comprises having the first outer surface 14, relative with the first outer surfaceThe packaging body body 12 of the second outer surface 16 and outer surface. As shown in Fig. 1 D the best,Packaging body 10 has lead frame, and this lead frame comprises die pad 18 and a plurality of leads 20. ToolBody ground, lead-in wire 20 comprises and is arranged in the Part I 20a of packaging body body 12 and from packaging bodyThe Part II 20b that the side surface of body 12 extends.
The Part II 20b of lead-in wire 20 forms electrode, and these electrodes are for for example passing through weldingBe electrically coupled to the lip-deep electric contact of printed circuit board (PCB) (PCB) (not shown), as abilityWell-known in territory. For example, packaging body 10 can be for for example passing through through hole technology (THT)Being mounted to printed circuit board (PCB) (PCB) makes lead-in wire 20 formation of packaging body 10 be inserted into PCBThrough hole in the power device package body of electrode. Alternately, can be by electrode welding extremelyPCB, as known in the art.
Die pad 18 has first surface 30 and second surface 32 and first surface 30 HesDistance between second surface 32 forms the first thickness therebetween. Lead-in wire 20 has with nude film and weldsCoil 18 identical thickness. Namely, form a plurality of leads 20 and die pad 18 from itLead frame at least has single thickness for lead-in wire and die pad. In one embodiment,The thickness of lead-in wire 20 and die pad 18 is 0.3 millimeter. Lead frame is made up also of conductive materialAnd can be metal material, as copper or copper alloy.
By the first jointing material 38, semiconductor die 36 is coupled to of die pad 18One surface 30. Semiconductor die 36 comprises semi-conducting material (such as silicon) and integrated anyElectronic building brick. Electronic building brick can be power device, as power diode or power MOSFET.The first jointing material 38 can be to be configured to for semiconductor die 36 being fixed on to nude film welderingDish any material of 18, as scolder, viscose glue, film, sticky cream, adhesive tape, epoxy resin, itCombination or any suitable material. The first jointing material 38 can be conductive material and/orHeat Conduction Material. In one embodiment, the first jointing material 38 is scolders of low melting glass,As started the scolder of melting at the temperature lower than 185 DEG C, and in one embodiment littleIn or equal to start melting at the temperature of 183 DEG C.
By conductor wire 41, semiconductor die 36 is electrically coupled to at least one in lead-in wire 20Lead-in wire, as shown in Figure 1 D. Particularly, the first end of conductor wire 41 is coupled to nude film36 bonding welding pad and the second end are coupled to the Part I 20a of lead-in wire 20. Conductor wire41 can be that semiconductor die 36 is electrically coupled to lead-in wire any conductive material of 20 and passableMetal material, as aluminium, gold, copper and alloy thereof. Although in the cross-sectional view of Fig. 1 D notIllustrate, the lead-in wire (as central tap) in lead-in wire 20 can be coupled to die pad 18Or integrated with it, this lead-in wire forms the drain electrode of power MOSFET in one embodiment,And outside lead can form source electrode and the gate electrode of power MOSFET.
Although at three lead-in wires 20 shown in Figure 1A, semiconductor package body 10 can comprise appointsThe lead-in wire of what quantity, as two or more lead-in wires, as known in the art.
Although not shown, surperficial at least a portion of lead-in wire 20 can be plated with one or manyIndividual conductive layer. These one or more conductive layers are nanometer layer or microbedding, and can be any leadingElectric material is made. In one embodiment, one or more conductive layers are multiple stacking metalsLayer, as Ni/Pd/Ag, Ni/Pd/Au-Ag alloy or Ni/Pd/Au/Ag. These are one or moreConductive layer can protect lead frame material to avoid corrosion, and can help bonding conductive features,As conductor wire 41 being bonded to lead-in wire 20.
Packaging body 10 further comprises fin 40, and this fin is by the second jointing material 42 couplingsBe connected to the second surface 32 of die pad 18. Preferably, the second jointing material 42 heat conduction andAlso can conduct electricity. The second jointing material 42 can be to be listed as with reference to the first jointing material 38 in the aboveAny in the jointing material going out. The second jointing material 42 can have than the first bonding materialThe melt temperature that material 38 is higher. For example, the second jointing material 42 can be more than or equal toAt the temperature of 185 DEG C, start melting, and be more than or equal to 190 DEG C in one embodimentTemperature under start melting. Alternately, the second jointing material 42 can be bonding with firstThe jointing material that material 38 is identical.
Fin 40 is any Heat Conduction Materials. For example, fin 40 can be metal material,As copper and aluminium and alloy, pottery or any other Heat Conduction Material. Fin 40 receives partly leadsThe heat that body nude film 36 produces during operation. Namely, fin receives and welds by nude filmDish 18 and the first jointing material 38 and the second jointing material 42 receive from semiconductor die 36Heat.
Fin 40 has below die pad 18 and by packaging body body 12 partlyThe Part I 40a covering and the Part II 40b that extends beyond packaging body body 12. SpecificallyGround, fin 40 is coupled to die pad 18 at the first surface of Part I 40a. Heat radiationThe second surface of sheet 40 forms a part for the second outer surface 16 of packaging body body 12.
The size of fin 40 is to allow to remove suitably the heat being produced by semiconductor die 36In any size of some heats. In one embodiment, the Part I of fin 4040a can cover the whole second surface 32 of die pad 18. In this respect, fin 40There is the maximized surface coordinating with die pad 18 long-pending, for removing by die pad 18 from halfThe heat that conductor nude film 36 receives. In this respect, the Part I 40a of fin 40 canIt is identical with die pad 18 size or larger than die pad 18. Of fin 40Two part 40b can be larger than the Part I 40a of fin 40.
Fin 40 can also provide the support together with die pad 18 to semiconductor die 36.Namely, lead frame material is thinner and be not enough to support semiconductor in assembling between processing period thereinIn some embodiment of nude film 36, fin 40 can provide entering semiconductor die 36One step supports. Usually, the thickness of fin 40 (, first surface and second surface itBetween distance) be the outside that is suitable for heat to be sent to from semiconductor die 36 packaging body 10Any thickness. In certain embodiments, fin 40 has the thickness of approximately 2 to 4.5 millimeters.
Packaging body body 12 is partly welded by encirclement semiconductor die 36, conductor wire 41, nude filmThe encapsulating material 46 of the part of dish 18 and lead-in wire 20 and fin 40 forms. Particularly,Semiconductor die 36, conductor wire and die pad 18 are completely enclosed in encapsulating material 46.The Part I 20a of lead-in wire 20 is arranged in encapsulating material 46, and Part II 20b is from sealingThe side surface (side surface of its formation packaging body body 12) of material 46 extends. Encapsulating materialOn the first surface of the 46 Part I 40a at fin 40 and along of fin 40A part 40a side surface and locate. But, the second surface of Part I 40a keep fromEncapsulating material 46 exposes. Similarly, the Part II 40b of fin 40 keeps from sealing materialMaterial 46 exposes.
Encapsulating material 46 is dielectric substances, protects the electric component of semiconductor die 36 and leadsElectric wire 41 is not damaged, as burn into physical damage, moisture damage or to electrical equipment and materialThe other reasons of the damage of material. In one embodiment, encapsulating material 46 is polymer, asEpoxy resin mould.
As mentioned above, the first surface of the Part I of fin 40 is covered by encapsulating material 46,And second surface keeps exposing from encapsulating material 46. Namely, whole second of fin 40Expose from encapsulating material 46 on surface. The second surface of fin 40 can be at packaging body body 12The surface co-planar of the second outer surface 16 and encapsulating material 46.
The radiator that fin 40 can be configured to for being coupled to packaging body outside (does not showGo out). Namely, radiator can be coupled to the second surface of fin. At some embodimentIn, the Part II 40b of fin 40 can comprise for receiving securing member with by fin40 are coupled to the opening (not shown) of radiator. Alternately, fin 40 can be by clipOr jointing material is fixed to radiator. Radiator also contributes to remove heat from packaging body 10.
By thering is single gauge leadframe package body or having for lead-in wire and die padThe lead frame (as described above) of single thickness, has reduced the assembling that is used to form lead frameTechnique. In addition, also reduced the cost being associated with the lead frame that is formed for forming packaging body.In addition, by having single gauge lead frame, can reducing, to be mounted to the semiconductor of lead frame nakedThe cracking of sheet. Particularly, due to the different thermal expansion between semiconductor die and die padCoefficient (CTE) has caused thinner nude film (if thickness is 100 microns or less nude film)Cracking. By the thin nude film weldering with the fin that is coupled to it is provided in packaging body itselfDish allows some deflections, thereby reduces contingent in packaging body in packaging body itselfStress. Namely, because the thickness of die pad reduces, die pad ratio is at thicker nude filmMore can deflection in the situation of pad. In addition, fin can serve as for naked during deflectionThe supporting construction of sheet pad. In this respect, can be than encapsulating in prior art in this packaging bodyIn body, provide and adapt to better cause due to different CTE between nude film and die padAny expansion and contraction.
In addition, there is the packaging body that is integrated in the fin in packaging body body by formation, obtainObtained various benefits. As mentioned above, fin provides naked to semiconductor during assembly technologyThe support of sheet. In addition, the size of fin (as thickness) can be confirmed as adapting to packaging bodyNeeds, as being assemblied in the type of the semiconductor die in packaging body, or to for encapsulationThe needs of the heat request of the application of body. Finally, in packaging body body, there is fin for consumptionPerson provides the individual unit of simplifying.
Fig. 2 A is used to form multiple independent packaging bodies (as the packaging body of Figure 1A to Fig. 1 D10) the part top view of leadframe strip 50. Although only two independent envelopes of lead frameDress body divides and is illustrated that (each independent packaging body part has die pad 18 and with nakedThree lead-in wires 20 that sheet pad 18 is associated), but it should be understood that leadframe strip50 can comprise any amount of independent of lead frame with the form of single band or matrixPackaging body part. Lead-in wire 20 is coupled in together by pitman, and these pitmans will be separatelyThe assembling of packaging body after in singualtion step, remove.
Fig. 2 B to Fig. 2 E has shown and has been used to form Fig. 1's according to this disclosure embodimentThe cross-sectional view of the different phase of the assembly technology of packaging body 10. As shown in Figure 2 B, lead-in wireThe thickness of moulding band 50 is that this is also referred to as single gauge lead frame uniformly. Namely,Die pad 18 and the lead-in wire 20 of leadframe strip 50 have identical thickness.
As shown in Fig. 2 C, fin 40 is coupled to the second surface 32 of die pad 18.Particularly, the second jointing material 42 be applied to the second surface 32 of die pad 18 and fall apartAt least one in the Part I 40a of backing 40. By the Part I 40a of fin 40Be placed on the second surface 32 of die pad 18, they are by the second jointing material 42 couplingsBe connected together. In certain embodiments, can in fin 40 and die pad 18 extremelyFew one applies heat and/or pressure, to assist coupling of fin 40 and die pad 18. AsThe above, fin 40 can provide in (as during die attached) during following processTo the further support of die pad 18, this will be described below.
As shown in Fig. 2 D, semiconductor die 36 is (as naked in the semiconductor of integrated power deviceSheet) be coupled to the first surface 30 of die pad 18. Particularly, by the first jointing material42 are applied in the rear side of semiconductor die 36 and the first surface 30 of die pad 18At least one. Semiconductor die 36 is placed on die pad 18. Can be naked to semiconductorAt least one in sheet 36 and die pad 18 applies heat and/or pressure, to assist semiconductor nakedSheet 36 couples with die pad 18.
Semiconductor die 36 is electrically coupled to the Part I 20a of lead-in wire 20. Namely, leadThe first end of electric wire 41 is coupled to the bonding welding pad of semiconductor die 36, and conductor wire 41The second end be coupled to lead-in wire 20 Part I 20a. Although not shown, can partly leadBetween body nude film 36 and lead-in wire 20, couple the conductor wire of one or more.
As shown in Fig. 2 E, surround the of semiconductor die 36, conductor wire 41, lead-in wire 20A part for part 40a, die pad 18 and fin 40 forms encapsulating material 46. ExampleAs, can form encapsulating material 46 with molding process. Namely, can be by lead-in wire mouldingBe with 50 to be positioned in mould and by encapsulating material 46 and to be injected in mould. Encapsulating material 46As time goes on can harden, this also can comprise curing schedule. As mentioned above, sealMaterial 46 can be polymer, as epoxy resin mould.
Then by leadframe strip 50 singualtion, to form independent packaging body 10, thus shapeBecome multiple independent packaging bodies. Singualtion can occur by various cutting methods, comprises saw, punchingHole and laser cutting. As understood well in the art, during singualtion technique, removeThe pitman of leadframe strip, thus it is electrically isolated from one to go between.
The various embodiments described above can be combined to provide further embodiment. In this manualMentioned and/or in application materials table listed all United States Patent (USP)s, U.S. Patent applicationPublication, U.S. Patent application, foreign patent, foreign patent application and non-patent publications are allBe combined in by reference this in full with it. If necessary, can carry out the each side of embodimentAmendment, to utilize the concept of each patent, application and publication that further embodiment is provided.
In view of above detailed description, can make these and other variations to embodiment. In a word,In following claims, the term using should not be interpreted as claim publishing houseBe limited to disclosed in the specification and claims specific embodiment, but should be explainedBe comprise all possible embodiment, together with these claims equivalent whole obtaining of having the rightIndividual scope. Therefore, claims are not subject to the restriction of this disclosure.
Claims (11)
1. a semiconductor package body, is characterized in that, comprising:
Die pad, described die pad has first surface and separates with described first surfaceThe second surface of one thickness;
A plurality of leads, described a plurality of leads has second thickness identical with described the first thickness;
The first jointing material, described the first jointing material has the first melt temperature;
The second jointing material, described the second jointing material has the second melt temperature, and described secondDescribed second melt temperature of jointing material is than described first melting of described the first jointing materialTemperature is higher;
Semiconductor die, described in described semiconductor die is coupled to by described the first jointing materialThe described first surface of die pad, described semiconductor die is electrically coupled to described a plurality of leads;
Fin, described fin is coupled to described die pad by described the second jointing materialDescribed second surface; And
Encapsulating material, described encapsulating material is on described semiconductor die, described die padAnd surround the part of described fin and described a plurality of leads.
2. semiconductor package body as claimed in claim 1, is characterized in that, described heat radiationSheet stretches out from the side surface of described encapsulating material.
3. semiconductor package body as claimed in claim 1, is characterized in that, described encapsulationThe outer surface of body is formed by the surface of described encapsulating material and the surface of described fin.
4. semiconductor package body as claimed in claim 3, is characterized in that, described in sealThe described surface of material and the described surface co-planar of described fin.
5. semiconductor package body as claimed in claim 1, is characterized in that, further bagDraw together the conductor wire that described semiconductor die is electrically coupled to described a plurality of leads.
6. semiconductor package body as claimed in claim 1, is characterized in that, described heat radiationSheet is metal material or pottery.
7. semiconductor package body as claimed in claim 1, is characterized in that, described secondJointing material is conductive adhesion material.
8. a semiconductor package body, is characterized in that, comprising:
Die pad, described die pad has first surface and second surface;
A plurality of leads;
Semiconductor die, described semiconductor die is coupled to described first table of described die padFace and be electrically coupled to described a plurality of leads;
Fin, described fin by electroconductive binder be coupled to described die pad described inSecond surface; And
Encapsulating material, described encapsulating material cover described semiconductor die, described die pad andAt least a portion of one or more side surfaces of described fin.
9. semiconductor package body as claimed in claim 8, is characterized in that, described in sealMaterial covers the side surface of the Part I of described fin, wherein, and second of described finThe side surface of part keeps exposing from described encapsulating material.
10. semiconductor package body as claimed in claim 8, is characterized in that, describedly partly leadsBody nude film is coupled to the described first surface of described die pad by jointing material, described bondingMaterial is different from described conductive adhesion material.
11. semiconductor package body as claimed in claim 10, is characterized in that, described stickyCondensation material has than the lower melt temperature of described conductive adhesion material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521108674.XU CN205319149U (en) | 2015-12-28 | 2015-12-28 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521108674.XU CN205319149U (en) | 2015-12-28 | 2015-12-28 | Semiconductor package |
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| Publication Number | Publication Date |
|---|---|
| CN205319149U true CN205319149U (en) | 2016-06-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201521108674.XU Active CN205319149U (en) | 2015-12-28 | 2015-12-28 | Semiconductor package |
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| CN (1) | CN205319149U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106920781A (en) * | 2015-12-28 | 2017-07-04 | 意法半导体有限公司 | Semiconductor package body and the method for forming semiconductor package body |
| CN107785357A (en) * | 2016-08-26 | 2018-03-09 | 意法半导体研发(深圳)有限公司 | Anti- viscose glue for optical sensor package body overflows cap |
-
2015
- 2015-12-28 CN CN201521108674.XU patent/CN205319149U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106920781A (en) * | 2015-12-28 | 2017-07-04 | 意法半导体有限公司 | Semiconductor package body and the method for forming semiconductor package body |
| CN107785357A (en) * | 2016-08-26 | 2018-03-09 | 意法半导体研发(深圳)有限公司 | Anti- viscose glue for optical sensor package body overflows cap |
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