CN103311222B - Semiconductor package part and forming method thereof - Google Patents

Semiconductor package part and forming method thereof Download PDF

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Publication number
CN103311222B
CN103311222B CN201310073377.5A CN201310073377A CN103311222B CN 103311222 B CN103311222 B CN 103311222B CN 201310073377 A CN201310073377 A CN 201310073377A CN 103311222 B CN103311222 B CN 103311222B
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China
Prior art keywords
wafer
film layer
conductive material
contact
packaging part
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CN201310073377.5A
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CN103311222A (en
Inventor
霍斯特·托伊斯
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Infineon Technologies AG
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Infineon Technologies AG
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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The invention discloses a kind of semiconductor package part and forming method thereof.In one embodiment, the forming method of a kind of semiconductor package part includes being applied on carrier the film layer with pass through openings, and the back side of semiconductor chip attaches to described film layer.On the front of semiconductor chip, there is contact.Described method includes utilizing the first public deposition and patterning step to form conductive material in the opening.The contact of semiconductor chip described in described conductive material contacts.The wafer reconfigured is formed by utilizing the second public deposition and patterning step semiconductor chip, film layer and conductive material to be encapsulated in encapsulant.Carry out separating to form multiple packaging part by this wafer reconfigured.

Description

Semiconductor package part and forming method thereof
Technical field
This patent disclosure relates generally to semiconductor devices, more particularly, to semiconductor package part and forming method thereof.
Background technology
Semiconductor devices is applied at multiple electronics and other applications.Semiconductor devices includes integrated circuit or divides Vertical device, described integrated circuit or discrete device by by polytype thin-film material deposition at semiconductor crystal wafer (wafer) Go up and thin-film material be patterned to form integrated circuit and formed on a semiconductor wafer.
Semiconductor devices is normally encapsulated in ceramic body or plastic body is interior against physical damage and corrosion.Encapsulation is also supported Require to be connected to the electrical contact of device.Type according to packed wafer (die, nude film) and desired use, can obtain multiple Different types of encapsulation.Typical encapsulation (such as, the size of packaging, number of pins) can meet combined electronics assembly engineering committee member The open standard of meeting (JEDEC).Encapsulation is referred to as semiconductor apparatus assembly or is called for short assembly.
Due to by externally connected for multiple electrical connection arrangements liner and protect these electrical connection arrangements and lower floor simultaneously The complexity of chip, encapsulation is probably a kind of technique consuming great amount of cost.
Summary of the invention
The illustrative embodiment generally utilizing the present invention solves or avoids these or other problems, and the most generally realizes Technical advantage.
In one embodiment, the forming method of a kind of semiconductor package part includes executing the film layer with pass through openings It is added on carrier, and the back side of semiconductor chip is attached to described film layer.On the front of semiconductor chip, there is contact.Institute The method of stating includes utilizing the first public deposition and patterning step to form conductive material in the opening.Described conductive material contacts The contact of described semiconductor chip.By utilize the second public deposition and patterning step by semiconductor chip, film layer and Conductive material is encapsulated in encapsulant and forms the wafer reconfigured.Carry out separating to be formed many by this wafer reconfigured Individual packaging part.
The feature describing embodiments of the invention outlined above, in order to can be best understood from below the present invention is detailed Describe.The additional feature and advantage of the embodiment of the present invention are described below, and these additional feature and advantage constitute the present invention Claimed subject matter.It will be understood by those skilled in the art that disclosed design and specific embodiment can be easy to be used as Revise or design the basis of other structures or technique, to realize the identical purpose of the present invention.One of ordinary skill in the art would recognize that, These equivalent constructions are without departing substantially from the spirit and scope of the present invention illustrated in claims.
Accompanying drawing explanation
In order to be more fully appreciated with the present invention and advantage thereof, with reference now to following description with reference to the accompanying drawings, in the accompanying drawings:
Fig. 1 shows the cross-sectional view of the semiconductor devices using embodiments of the invention to be formed；
Fig. 2 A and Fig. 2 B show according to embodiments of the present invention during manufacture film layer is being formed on carrier it After semiconductor package part, wherein Fig. 2 A shows cross-sectional view, and Fig. 2 B shows top view；
Fig. 3 A and Fig. 3 B show according to embodiments of the present invention during manufacture wafer is being attached on film layer it After semiconductor package part, wherein Fig. 3 A shows cross-sectional view, and Fig. 3 B shows top view；
Fig. 4 A and Fig. 4 B show according to embodiments of the present invention during manufacture after forming via and/or wire Semiconductor package part, wherein Fig. 4 A shows cross-sectional view, and Fig. 4 B shows top view；
Fig. 5 shows the horizontal stroke of semiconductor package part after encapsulated wafer during manufacture according to embodiments of the present invention Sectional view；
Fig. 6 A and Fig. 6 B show according to embodiments of the present invention (cutting, singulating) reconfigure separating Semiconductor package part after wafer, wherein Fig. 6 A shows cross-sectional view, and Fig. 6 B shows bottom view；
Fig. 7 A and Fig. 7 B shows and during manufacture film layer is being formed at load according to alternative embodiment of the present invention Semiconductor package part after on body, wherein Fig. 7 A shows cross-sectional view, and Fig. 7 B shows the top view of amplification；
Fig. 8 A and Fig. 8 B shows and during manufacture wafer is being attached to film according to alternative embodiment of the present invention Semiconductor package part after on layer, wherein Fig. 8 A shows cross-sectional view, and Fig. 8 B shows top view；
Fig. 9 A and Fig. 9 B shows and is forming via and/or wire during manufacture according to alternative embodiment of the present invention Semiconductor package part afterwards, wherein Fig. 9 A shows cross-sectional view, and Fig. 9 B shows top view；
Figure 10 A and Figure 10 B show according to alternative embodiment of the present invention during manufacture after encapsulated wafer Semiconductor package part, wherein Figure 10 A shows cross-sectional view, and Figure 10 B shows top view；
After Figure 11 A and Figure 11 C shows according to the wafer newly configured at separating heavy of alternative embodiment of the present invention Semiconductor package part, wherein Figure 11 A shows that cross-sectional view, Figure 11 B show bottom view, and Figure 11 C shows top view；
Figure 12-16 shows the alternative embodiment forming the semiconductor package part including multiple chip during manufacture；
Figure 17 A-17C shows the semiconductor devices using embodiments of the invention to be formed；And
Figure 18 A-18D shows and uses that embodiments of the invention are formed and install semiconductor packages on circuit boards Part.
Except as otherwise noted, the respective digital in different figures and symbol generally refer to corresponding component.Graphing is with clear The related fields of embodiment are shown, but are not necessarily intended to scale relative to.
Detailed description of the invention
The following will discuss making and the use of each embodiment.However, it should be understood that the invention provides can be respectively The multiple applicable inventive concept implemented under the specific environment of formula various kinds.The specific embodiment discussed only illustrates to make and use The concrete mode of the present invention, and do not limit the scope of the invention.
In different embodiments, present invention teach that use low cost process forms semiconductor package part, thus greatly reduce The cost of encapsulation semiconductor devices.As will be described in detail, in different embodiments, multiple Process step combinations are become single work Skill step is to reduce manufacturing cost.Relatively for other conventional arts, it is less that single step processes the time spent, and complexity is more Low, and decrease waste.
By utilizing Fig. 1, the Constructional embodiments of semiconductor package part is described.Figure 17 A-17C and 18A-will be utilized Other Constructional embodiments of 18D is described.Fig. 1-6B will be utilized manufacture semiconductor packages according to embodiments of the present invention The method of part is described.By utilizing Fig. 7 A-11C and Figure 12-16, the other embodiments manufacturing semiconductor package part is retouched State.
Fig. 1 shows the cross-sectional view of the semiconductor devices using embodiments of the invention to be formed.
With reference to Fig. 1, this semiconductor package part includes embedding the multiple wafers 50 in encapsulating material 80.Multiple wafers 50 are arranged On film layer 20, this film layer has the opening being filled with conductive material 65, thus forms via (through via) 75, It forms the engagement pad for semiconductor package part.Conductive material 65 is also formed with wire 70, and described wire is by multiple wafers 50 On contact 60 couple with via 75.
Fig. 2 A and Fig. 2 B shows semiconductor package part after being formed on carrier by film layer during manufacture, its Middle Fig. 2 A shows cross-sectional view, and Fig. 2 B shows top view.
With reference to Fig. 2 A, utilize carrier 10 to form this semiconductor package part, carrier provides in process machinery support with Stability.In different embodiments, carrier 10 can be by rigid material (such as, the such as metal of nickel, steel or stainless steel, layer Pressing plate, film or material stack etc.) plate made.Carrier 10 can have at least one flat surfaces, and semiconductor chip is permissible It is placed on this at least one flat surfaces.In one or more embodiments, carrier 10 can also is that circle or square, but It is that this carrier 10 can also be any applicable shape in different embodiments.In different embodiments, carrier 10 can have Any suitable size.In certain embodiments, carrier 10 can include adhesive tape (such as, be laminated on carrier 10 is two-sided Adhesive tape).Carrier 10 can include framework, and in one embodiment, this framework is to have glue paper tinsel (adhesive foil, viscosity Paper tinsel) loop configuration (annular).In one or more embodiments, this glue paper tinsel can support along outer cause framework.
Film layer 20 is formed over the carrier 10.Film layer 20 is formed as having pattern so that opening 30 is formed at film layer In 20.In different embodiments, typography, molding process or laminating technology is used to form film layer 20.One or more In embodiment, film layer 20 and opening 30 are formed over the carrier 10 with single step, and without carrying out the patterning added.Single Step is the technique on whole carrier 10, deposition and patterning being merged into a step.Because process the whole of carrier 10 simultaneously Individual surface, so the some of carrier 10 is not sequentially exposed, such as, as at step-scan photoetching (step and scan Lithography) conducted in instrument.The example of this technique includes printing, moulds or be laminated.
In one embodiment, utilize typography to form film layer 20, such as, utilize stencil print process, be followed by Technology for Heating Processing.In other embodiments, it is possible to use include the other kinds of printing of serigraphy.
Molding process is waited to form film layer 20 it is alternatively possible to utilize compression molded.In one embodiment, can make Molding process is assisted with film.In film auxiliary molding process, before carrier 10 is loaded in molding cavity, plastic foil quilt Suck downwards in the inner surface of mould.The surface of molding cavity includes the figure for opening 30 in film layer 20.Then Molding material is liquefied, and is forced in the molding cavity of closing and is kept under heat and pressure, until all liquefaction Molding material solidification, is consequently formed the film layer 20 of patterning.Film layer 20(such as, paper tinsel) seal the region between mould And it is positioned at some region on layer that is on carrier 10 or that apply in advance.This ensures that these regions do not mould flash (mold Flash) (vestige of molding material), and if it is required, these regions can be used as electrical contact after a while.Alternatively, may be used There is the film layer 20 of opening 30 to use such as other molding techniques such as injection molding, powder molding, liquid mold to be formed. In different embodiments, after applying film layer 20, the curing process added can be performed.
In different embodiments, film layer 20 includes plastic material.In one such embodiment, film layer 20 includes gathering Paraxylene, photoresist, acid imide, epoxy resin, thermosetting plastics.In alternative embodiments, film layer 20 includes Machine silicon, silicon nitride or ceramic-like material (such as silicon carbon compound).In one embodiment, film layer 20 includes pre-impregnated fiber Material, this material is fibrofelt (such as glass or carbon fiber) and the composition of resin (such as thermoset plastic material).
In different embodiments, the thickness of film layer 20 is of about 10 μm to about 50 μm, is in alternative embodiments About 2 μm are to about 10 μm.
Fig. 3 A and Fig. 3 B shows semiconductor package part after being attached on film layer by wafer during manufacture, its Middle Fig. 3 A shows cross-sectional view, and Fig. 3 B shows top view.
With reference to Fig. 3 A and 3B, multiple wafers 50 or semiconductor chip are attached on film layer 20.In different embodiments, Multiple wafers 50 can utilize adhesive to be attached.Multiple wafers 50 can include contact 60 as depicted.In different embodiments In, this adhesive can include glue or other adhesive type materials.Attachment layer is relatively thin to carry out typography subsequently, such as Less than about 100 μm, and it is that 1 μm is to about 50 μm in another embodiment.
In different embodiments, multiple wafers 50 can include any kind of wafer.In different embodiments, Duo Gejing Sheet 50 includes low-power chip, such as, use the chip of low current (such as, less than 10 amperes).Such as, high-current consumption (example As, more than 30 amperes) power chip need the heavy gauge wire of low conductivity, thereby increases and it is possible to be not suitable for described in the embodiment of the present invention This encapsulation.
In different embodiments, multiple wafers 50 can include logic chip, storage chip, analog chip, mixed signal Chip.Embodiments of the invention also include the multiple chips on film layer 20.For example, it is possible to two or more chips are placed in Between opening 30.
Fig. 4 A and Fig. 4 B shows during manufacture forming the semiconductor package part after via and/or wire, wherein Fig. 4 A shows cross-sectional view, and Fig. 4 B shows top view.
Conductive material 65 is applied over the carrier 10.Advantageously, with single step, conductive material 65 is applied to whole load On body 10.For example, it is possible to apply conductive material 65 in the case of not using the complex steps such as patterning, photoetching.On the contrary, permissible Utilize printing, mould or be laminated conductive material 65 is applied directly on whole carrier 10.
In different embodiments, conductive material 65 can be applied as liquid, paste or solder.An embodiment In, conductive material 65 can be applied as the conductive particle in polymeric matrix to form composite after solidification. In alternative embodiments, the electrical-conductive nanometer cream of such as silver nanoparticle cream can be applied.In different embodiments, including such as aluminium, Any suitably electrically conductive material 65 of the metal or metal alloy of titanium, gold, silver, copper, palladium, platinum, nickel, chromium or nickel vanadium may be used to shape Become conductive material 65.
Advantageously, conductive paste couples the contact 60 on multiple wafer 50, thus forms wire 70 and via 75.Advantageously, Wire 70 and via 75 can be formed in a single step.Further, with the wire bonding technique being sequentially formed wire Difference, multiple wire 70(such as, multiple wires of the multiple wafers in connection package) can concurrently form.
In different embodiments, typography (such as utilize stencil print process, be followed by Technology for Heating Processing) is utilized to execute Add conductive material 65.In other embodiments, it is possible to use include the other kinds of printing of serigraphy.Alternatively, may be used To utilize compression molded molding process such as grade to apply conductive material 65.In one embodiment, it is possible to use film auxiliary molding is come Form conductive material 65.Alternatively, such as injection molding, powder molding, other molding techniques of liquid mold may be used for Apply conductive material 65.In different embodiments, after applying conductive material 65, Technology for Heating Processing can be performed with hardening also Curing conductive material 65.Therefore, the bottom side of the packaging part of formation includes surface and the surface of film layer 20 of conductive material 65.
Fig. 5 shows the cross-sectional view of semiconductor package part after encapsulated wafer during manufacture.
Encapsulating material 80 is applied on multiple wafer 50 and conductive material 65.In different embodiments, printing, mould are used Encapsulating material 80 is applied on whole carrier 10 by system or laminating technology.As it has been described above, in one or more embodiments, permissible Mould printing, film auxiliary molding is used to carry out depositing encapsulation material 80.Encapsulating material 80 covers multiple wafer 50.
In different embodiments, encapsulating material 80 includes dielectric material, and can include moldingization in one embodiment Compound.In other embodiments, (such as, encapsulating material 80 can include polymer, biopolymer, fiber impregnation polymer Carbon in resin or glass fibre), particle-filled polymer and other organic materials.In one or more embodiments, encapsulation Material 80 includes sealant and the material of such as epoxy resin and/or organosilicon not being to utilize mold compound to be formed.? In different embodiments, encapsulating material 80 can be by any suitable thermosetting plastics, thermoplastic or thermosetting material or stacking System becomes.In certain embodiments, the material of encapsulating material 80 can include packing material.In one embodiment, encapsulation material Material 80 can include epoxy material and have packing material or the mineral-filled material of other electric insulations of less glass particle Material (such as aluminum oxide or organic filler material).
Encapsulating material 80 can be cured, such as, carry out being heat-treated with solidification, thus forms the multiple wafer of protection 50 with many The sealing of individual wire 70.
Fig. 6 A and Fig. 6 B shows and the wafer separate reconfigured is become the semiconductor package part after independent packaging part, its Middle Fig. 6 A shows cross-sectional view, and Fig. 6 B shows bottom view.
Encapsulating material 80 after hardening is separated with carrier 10, thus forms the wafer 100 reconfigured.Embedding with traditional Enter wafer scale technique different, form, at the end of processing, the wafer reconfigured.The wafer 100 reconfigured is separated, Thus form single packaging part.The bottom of the via 75 being arranged in film layer 20 is formed with semiconductor package as shown in Figure 6B The external contact pin (contact pin) of piece installing.Packaging part can utilize these contact feets to install, such as, such as Figure 17 A- Shown in 17C and Figure 18 A-18D.Utilize embodiments of the invention, it is not necessary to additional lead mount structure etc. contacts packaging part.One In a little embodiments, before separation, the basal surface of the wafer 100 reconfigured can carry out the plating added, such as with For welding subsequently.
Fig. 7 A-11B shows the alternative embodiment of the present invention forming packaging part on packaging part.
The technique of this embodiment is similar to the technique of the preceding embodiment in Fig. 7 A-9B.In Figure 10 A and 10B, with previously Embodiment is different, forms thin encapsulation oxidant layer, thus eliminates and formed and in package on package can process any follow-up thinning Needs.
Fig. 7 A and Fig. 7 B shows semiconductor package part after being formed on carrier by film layer during manufacture, its Middle Fig. 7 A shows cross-sectional view, and Fig. 7 B shows the top view of amplification.As in the previous embodiment, will with single step Film layer 20 is formed on whole carrier 10.
Fig. 8 A and Fig. 8 B shows semiconductor package part after being attached on film layer by wafer during manufacture, its Middle Fig. 8 A shows cross-sectional view, and Fig. 8 B shows top view.As in the previous embodiment, the thinnest adhesive linkage is utilized Multiple wafers 50 with contact 60 are attached on film layer 20.
Fig. 9 A and Fig. 9 B shows during manufacture forming the semiconductor package part after via and/or wire, wherein Fig. 9 A shows cross-sectional view, and Fig. 9 B shows top view.As in the previous embodiment, with single step by via 75 And/or wire 70 is formed on whole carrier 10.
Figure 10 A and Figure 10 B shows semiconductor packages after by wafer package on whole carrier during manufacture Part, wherein Figure 10 A shows cross-sectional view, and Figure 10 B shows top view.
Unlike preceding embodiment, the layer of thin encapsulating material 80 is formed on multiple wafer 50.Real in difference Executing in example, the thickness of encapsulating material 80 is of about 100 μm to about 500 μm, and is of about 100 μm in one embodiment extremely About 300 μm.(wafer wherein reconfigured must be supported subsequent treatment and therefore must be thicker with embedding wafer-level process ) different, there is no any restriction here, reason is that great majority process the most completes in this stage.Therefore, implement in difference In example, in the case of not damaging mechanical stability, the layer of thin encapsulating material 80 can be formed.
In different embodiments, utilize printing, mould or encapsulating material 80 is applied to whole carrier 10 by the technique such as lamination On.Encapsulating material 80 covers multiple wafer 50 but exposes wire 70.
In different embodiments, as in the previous embodiment, encapsulating material 80 includes dielectric material, and an embodiment In can include mold compound.In other embodiments, encapsulating material 80 can include polymer, biopolymer, fiber Impregnated polymer (such as, the carbon in resin or glass fibre), particle-filled polymer and other organic materials.At one or In multiple embodiments, sealant that encapsulating material 80 includes not being to utilize mold compound to be formed and such as epoxy resin and/ Or the material of organosilicon.In different embodiments, encapsulating material 80 can be by any suitable thermosetting plastics (duroplastic, rigid plastics), thermoplastic or thermosetting material or duplexer are made.In certain embodiments, encapsulation The material of material 80 can include packing material.In one embodiment, encapsulating material 80 can include epoxy material and tool There are packing material or other electric insulation mineral fillers (the such as aluminum oxide or organic filling material of less glass particle Material).
As in the previous embodiment, with cure package material 80, thus the wafer 100 reconfigured can be formed.
Figure 11 A and Figure 11 B shows the semiconductor package part after separation, and wherein Figure 11 A shows cross-sectional view, figure 11B shows bottom view, and Figure 11 C shows top view.
As it has been described above, the wafer 100 reconfigured formed in previously step (Figure 10 A and 10B) is separated, with Form single packaging part.
Figure 12-16 shows the alternative embodiment forming the semiconductor package part including multiple chip during manufacture.
This embodiment can include to preceding embodiment described in the similar step of step.It addition, in this embodiment, Multiple chips are interconnected.Further, one or more in chip all can contact with the relative back side from front.
With reference to Figure 12, film-grade interconnection 15 is formed on whole carrier 10.In different embodiments, will with single step Multiple film-grade interconnections 15 are formed on the whole surface of carrier 10.For example, it is possible to relate to deposition, photoetching, figure not using Film-grade interconnection 15 is applied in the case of the step that is complicated and that waste material of case.In different embodiments, film-grade Interconnection 15 can utilize printing, mould or the technique such as lamination directly applies.
In one or more embodiments, film-grade interconnection 15 can be applied as liquid, paste or solder.? In one embodiment, film-grade interconnection 15 can be applied as the conductive particle in polymeric matrix.In replaceable enforcement In example, the electrical-conductive nanometer cream of such as silver nanoparticle cream can be applied.In different embodiments, including such as aluminium, titanium, gold, silver, copper, Any suitable material of the metal or metal alloy of palladium, platinum, nickel, chromium or nickel vanadium may be used to form film-grade interconnection 15.
Figure 13 shows semiconductor package part after being formed on carrier by film layer during manufacture.Thin being formed After film level interconnection 15, with single step, film layer 20 is formed on the whole surface of carrier 10.Film-grade interconnection 15 It is formed on identical vertical height (the most close) with film layer 20, and in different embodiments, film-grade interconnection Similar with the thickness of film layer.
Figure 14 shows semiconductor package part after being attached on film layer 20 by wafer during manufacture.As previously Described in embodiment, utilize thin adhesive linkage that multiple wafers 50 with contact 60 are attached to film layer 20.As shown in figure 14, many It is one or more that a wafer in individual wafer 50 can contact in film-grade interconnection 15.Such as, in fig. 14, in wafer One couple from the back side, and another wafer does not couples from the back side.This be possibly due in wafer is vertical wafer (vertical wafer, vertical die), this vertical wafer such as includes the vertical device of the most discrete vertical transistor.Replaceable Ground, this wafer can include vertical circuit, such as by front is coupled to the via at the back side.
Figure 15 shows during manufacture forming the semiconductor package part after via and/or wire.Via 75 and/or Wire 70 is formed as in the previous embodiment.It addition, be formed with wafer scale interconnection 85 near multiple wafers.Wafer scale is mutual Portion of company 85 can be coupled to the film-grade interconnection 15 coupled with wafer.Advantageously, via 75, wire 70 and wafer scale interconnection 85 concurrently form in a single step, such as, it is not necessary to carry out the patterning added.In different embodiments, it is possible to use printing, The techniques such as molding or lamination apply conductive material, thus form via 75 as above, wire 70 and wafer scale interconnection 85.
Figure 16 shows semiconductor package part after encapsulated wafer during manufacture.Utilize printing, mould or be laminated Encapsulation is performed in a single step, as in the previous embodiment etc. technique.The wafer reconfigured formed can be entered Row separates, as mentioned above.
Figure 17 A-17C shows the semiconductor package part using the embodiment of the present invention to be formed.
As shown in Figure 17 A, the packaging part formed in Figure 11 A-11C can be laminated to each other, thus forms package on package.? In shown packaging part, multiple wafers 50 only have contact area (such as contact 60) on side.Replacing shown in Figure 17 B Change in embodiment, it is possible to use the packaging part of Figure 16 forms package on package, in the packaging part of Figure 16, at least in wafer The individual both sides at wafer all have contact area.In different embodiments, it is possible to use embodiments of the invention stacking inhomogeneity The packaging part of type.Figure 17 C shows the situation that different types of packaging part is laminated to each other.Further, embodiments of the invention The plural packaging part of stacking.
Figure 18 A-18D shows and uses that embodiments of the invention are formed and install semiconductor packages on circuit boards Part.
In one embodiment, the semiconductor package part using embodiments of the invention to be formed may be mounted at printed circuit On plate 110.In one embodiment, semiconductor package part can face down on the first type surface being arranged on printed circuit board (PCB) 110.Example As, additional soldered ball 120 can be formed at below via 75 to couple with printed circuit board (PCB) 110.In different embodiments, may be used To use other kinds of mounting means.It is possible to further additional structure is attached to semiconductor package part.Such as, figure 18D shows the radiator 150 being arranged on semiconductor package part.Radiator 150 can utilize thin adhesive portion 130 to carry out coupling Connecing, this thin adhesive portion can with heat conduction, thus allow to conduct heat away from multiple wafers 50.Embodiments of the invention include Figure 17 A- The combination of 17C and Figure 18 A-18D.
Embodiments of the invention include flexible package, and this flexible package reduces packaging cost because technique is simple.By This packaging part formed can include multiple chip, include multiple parts that package on package configures.Advantageously, metal level is permissible Being formed on front and the opposite face of semiconductor chip, metal level can serve as electrical contact or makes heat conduct away from wafer.
Further, advantageously, the embodiments of the invention using Fig. 2 A-6B, Fig. 7 A-11B and Figure 12-16 to describe utilize Conventional patterning process greatly reduces processing cost and complexity.On the contrary, the technique of similar wafer is utilized to form all features, The technique of this similar wafer (concurrently, different from the sequential processes engaged that such as goes between) simultaneously is in same unit processing module Form feature, avoid deposition the most against corrosion, photoetching, anti-etching etc. order wafer scale technique simultaneously.On the contrary, at each unit In processing module, form these features with single step.
Although with reference to illustrative embodiment, invention has been described, but this description is not intended to enter in limiting sense Row is explained.Will be apparent from for a person skilled in the art be, after with reference to this description, can be to illustrative embodiment Carry out various amendment and combination, and carry out other embodiments of the present invention.Such as, the embodiment described in Fig. 6 A and 6B is permissible With Figure 11 A-11C, 16, embodiment described in 17A-17C and/or 18A-18D combines.Similarly, Fig. 2 A-6B, figure Technique described in 7A-11B and/or Figure 12-16 can be combined.Therefore, the purpose of claims is to contain to appoint What such amendment or embodiment.
Although the present invention and advantage thereof being described in detail, it should be appreciated that without departing substantially from such as claims In the case of the spirit and scope of the present invention limited, various change can be carried out, substitute and change.Such as, art technology Personnel will readily appreciate that, various features described herein, function, technique and material can be changed, and simultaneously falls in this In the range of invention.
Additionally, scope of the present application is not limited to the technique described in this specification, machine, manufacture, composition, hand Section, method and the specific embodiment of step.As those of ordinary skill in the art will from the disclosure easily Recognize, can used according to the invention that presently, there are or later developed, perform big to corresponding embodiment described herein Cause identical function or obtain the technique of roughly the same result, machine, manufacture, composition, means, method or step.Accordingly Ground, in the range of claims are intended to be included in such as technique, machine, manufacture, composition, means, method or step etc..

Claims (27)

1. a semiconductor package part, including:
First wafer, is arranged on film layer；
Encapsulant material, surrounds described first wafer and is arranged on described film layer；And
First interconnection, has the first end and the second relative end, described first end in contact be positioned on described first wafer One contact, and described second end forms the first external contact pin of described semiconductor package part, described first external contact pin It is arranged in described film layer,
Wherein, described film layer has the opening being filled with conductive material, thus forms via, and the bottom of described via forms the Two external contact pin, and described conductive material forms the second interconnection, and described second interconnection has the first end and the second end, First end in contact of described second interconnection is positioned at the second contact on described first wafer, and the of described second interconnection Two ends are coupled to described via,
Wherein, described packaging part farther includes:
Second wafer, is arranged on described film layer and embeds in described encapsulant, and
Described second interconnection also has the 3rd end, and described 3rd end couples the contact being positioned on described second wafer.
Packaging part the most according to claim 1, wherein, described first and second external contact pin and the table of described film layer Face shares a common surface.
Packaging part the most according to claim 1, wherein, described first interconnection includes conductive material, described conductive material Including the resin being filled with conductive particle.
Packaging part the most according to claim 1, wherein, described first interconnection is included in polymeric matrix has conduction The composite of particle.
Packaging part the most according to claim 1, wherein, described first interconnection includes hardening metal cream.
Packaging part the most according to claim 1, wherein, described first interconnection includes solidifying silver nanoparticle cream.
7. the method forming semiconductor package part, described method includes:
Utilizing the first public deposition and patterning step, be applied on carrier by film layer, described film layer has pass through openings；
The back side of semiconductor chip is attached to described film layer, the front of described semiconductor chip has contact；
Utilize the second public deposition and patterning step, conductive material is formed in described pass through openings, described conductive material Contact described contact；
The wafer reconfigured is formed by semiconductor chip, film layer and conductive material being encapsulated in encapsulant；With And
The described wafer reconfigured is separated, to form multiple packaging part, wherein
Fill described conductive material in described pass through openings thus the surface of conductive material in described pass through openings is described heavy Forming external contact pin on the bottom side of newly configured wafer, described conductive material is by the described contact of described semiconductor chip and institute State pass through openings to couple.
Method the most according to claim 7, farther includes to remove described carrier.
Method the most according to claim 7, wherein, described first public deposition and patterning step include printing, molding, Or lamination.
Method the most according to claim 7, wherein, described second public deposition and patterning step include printing, mould System or lamination.
11. methods according to claim 7, wherein, described first and second public depositions and patterning step include print Brush.
12. methods according to claim 11, wherein, described printing includes serigraphy.
13. methods according to claim 7, wherein, described first and second public depositions and patterning step include mould System.
14. methods according to claim 13, wherein, described molding includes that film assists molding process.
15. methods according to claim 7, wherein, encapsulating after described semiconductor chip, be positioned at described in reconfigure Wafer top side on conductive material surface formed engagement pad.
16. methods according to claim 7, wherein, the step forming the wafer reconfigured includes existing with single step Engagement pad is formed on the top side of the described wafer reconfigured.
17. methods according to claim 16, farther include the first packaging part stacking in the plurality of packaging part On the second packaging part in the plurality of packaging part.
18. methods according to claim 16, farther include the first packaging part stacking in the plurality of packaging part Below the second packaging part being different from described first packaging part, described first and second packaging parts are by described engagement pad coupling Connect.
19. methods according to claim 7, wherein, the step forming conductive material includes applying conductive paste, described conduction Cream includes the resin with metallic particles.
20. 1 kinds of methods forming semiconductor package part, described method includes:
Utilize the first public deposition and patterning step, will be patterned into conductive layer and be applied on carrier；
Utilize the second public deposition and patterning step, film layer is applied on the carrier and laterally adjacent described patterning
Conductive layer, described film layer has pass through openings；
The back side of semiconductor chip is attached to described film layer, the front of described semiconductor chip has front contact；
Utilize the 3rd public deposition and patterning step, conductive material is formed in described pass through openings, described conductive material Contact described front contact and the conductive layer of described patterning of described semiconductor chip；
Utilize the 4th public deposition and patterning step, by semiconductor chip, film layer and conductive material are encapsulated in envelope Dress agent forms the wafer reconfigured；And
The described wafer reconfigured is separated.
21. methods according to claim 20, wherein, the back side of described semiconductor chip have rear contact, described after The conductive layer of patterning described in contact.
22. methods according to claim 20, wherein, described first public deposition and patterning step include printing, mould System or lamination.
23. methods according to claim 20, wherein, described first public deposition and patterning step include screen printing Brush.
24. methods according to claim 20, wherein, described first public deposition and patterning step include that film assists Molding.
25. methods according to claim 20, wherein, described second public deposition and patterning step include screen printing Brush.
26. methods according to claim 20, wherein, described second public deposition and patterning step include that film assists Molding.
27. methods according to claim 20, wherein, described third and fourth public deposition and patterning step include print Brush, molding or lamination.
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