TWI682514B - 用於超(跳)貫孔整合之金屬互連及其製造方法 - Google Patents
用於超(跳)貫孔整合之金屬互連及其製造方法 Download PDFInfo
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Abstract
本揭露係關於半導體結構,且更尤指用於超(跳)貫孔整合之金屬互連結構及製造方法。該結構包括:具有一或多個佈線結構之第一佈線層;包括互連件與佈線結構之第二佈線層;以及於第二佈線層上面定位有一或多個貫孔互連件與佈線結構之至少一個上佈線層。一或多個貫孔互連件與佈線結構部分地包括第一金屬材料、及第一金屬材料上方具有導電材料之其餘部分。跳貫孔通過第二佈線層,並延展至第一佈線層之一或多個佈線結構。跳貫孔部分地包括金屬材料,且該跳貫孔之其餘部分包括位在第一金屬材料上方之導電材料。
Description
本揭露係關於半導體結構,且更尤指用於超(跳)貫孔整合之金屬互連結構及製造方法。
貫孔(via)乃是一種介於實體電子電路中諸佈線結構(例如:諸佈線層)之間的電連接,其貫穿一或多個相鄰層件之平面。舉例而言,在積體電路設計中,貫孔是絕緣氧化物層中的小型開口,在不同佈線層之間提供導電性連接。將最下層金屬連接至擴散或多晶之貫孔一般稱為「接觸(contact)」。
在貫孔技術中,超貫孔(super via)亦稱為跳貫孔(skip via),可穿過許多絕緣體層來形成,例如:可將絕緣體層內之一或多個佈線結構旁通,用以與下佈線結構連接。這使得下佈線結構(例如於M0層)之電阻特性提升,電容降到最小,並在晶片製造過程中提供面積效率。
不過,使用跳貫孔會有許多挑戰要面對。舉例而言,在製造過程中,跳貫孔將會需要著落於下層階(例如:M0階)中之佈線結構上,而正規貫孔將會需要著落於上層階(例如:M1或上面層階)中之佈線結構上。此外,在跳貫孔程序中,習知的銅鍍覆程序乃用於將貫孔填充。不過,銅鍍覆程序生長自所有方向,包括貫孔之側壁及底端,從而產生因側壁生長造成夾止(pinch-off)而建立之延展空洞(void),且因高深寬比(aspect ratio)貫孔上物理氣相沉積(physical vapor deposition;PVD)晶種涵蓋範圍不足而產生底端空洞。空洞亦可導因於超低k(ultra-low k;ULK)電漿誘發型損壞(plasma-induced-damage;PID)或覆蓋體對層間介電選擇性所形成之底部截槽(undercut)外形。此外,襯墊/晶種亦不足以包覆高深寬比貫孔之全長,空洞亦因而形成。這些空洞負面地影響跳貫孔之電阻率,進而使裝置效能下降。
在本揭露之一態樣中,一種結構包含:具有一或多個佈線結構之第一佈線層;包含互連結構及佈線結構之第二佈線層;於該第二佈線層上面定位有一或多個貫孔互連件與佈線結構之至少一個上佈線層,該至少一個上佈線層之該一或多個貫孔互連件與佈線結構部分地包含第一金屬材料,該第一金屬材料具有在其上方包含導電材料之其餘部分;以及通過該第二佈線層並延展至該第一佈線層之該一或多個佈線結構的跳貫孔,該跳貫孔部分地包含該金屬材料,該金屬材料具有在其上方包含該導電材料之其餘部分。
在本揭露之一態樣中,一種方法包含:形成 貫孔以使上佈線層之一或多個佈線結構曝露;形成通過該上佈線層並使下佈線層之一或多個佈線結構曝露之跳貫孔;選擇性生長位在該貫孔中並部分地位在該跳貫孔內之金屬材料;以及用導電材料將該跳貫孔之其餘部分填充。
在本揭露之一態樣中,一種方法包含:形成在下佈線層中具有一或多個佈線結構之佈線層;形成在上佈線層中具有一或多個佈線結構之佈線層,定位於該下佈線層上面;形成貫孔以使該上佈線層之該一或多個佈線結構曝露;形成通過該上佈線層並使該下佈線層中之該一或多個佈線結構曝露之跳貫孔;選擇性生長在該上佈線層與該下佈線層之該一或多個佈線結構之曝露部分上之金屬材料;以及用導電材料將該上佈線層上面另一佈線層之該跳貫孔與溝槽之其餘部分填充。
10‧‧‧結構
12‧‧‧絕緣體材料
14‧‧‧佈線結構、下佈線結構或下佈線層
16‧‧‧覆蓋層
18‧‧‧上絕緣體層或絕緣體材料
20‧‧‧佈線結構或上佈線結構
22‧‧‧互連結構或貫孔互連結構
24‧‧‧覆蓋層
26‧‧‧絕緣體層
28‧‧‧遮罩材料
30‧‧‧光阻
32a‧‧‧貫孔開口、貫孔或跳貫孔
32b‧‧‧貫孔開口、貫孔或互連貫孔
36‧‧‧溝槽
38‧‧‧鈷
40‧‧‧導電材料
42‧‧‧覆蓋層
本揭露乃是藉由本揭露例示性具體實施例的非限制性實施例,參照註記的複數個圖式,在以下詳細說明中作說明。
第1圖根據本揭露之態樣,除其它特徵以外,還展示數種佈線結構與跳貫孔結構、及各別製造程序。
第2圖根據本揭露之態樣,除其它特徵以外,還展示填充有鈷材料之跳貫孔結構、及各別製造程序。
第3圖根據本揭露之態樣,除其它特徵以外,還展示跳貫孔結構與正規貫孔結構中之敷金屬、及各別製造程序。
本揭露係關於半導體結構,且更尤指用於超(跳)貫孔整合之金屬互連結構及製造方法。更具體地說,本揭露說明選擇性無電式鈷(Co)或鎳(Ni)(或其合金)程序,其在跳貫孔結構中由下而上生長例如鈷或鎳之材料。因此,藉由使用選擇性無電式(electroless)生長程序,鈷或鎳將不會在跳貫孔之側壁上形成,進而確保填充無空洞不受跳貫孔之外形與深寬比影響。按照這種方式,有助益的是,可防止因側壁生長造成夾止所致的延展空洞、及因高深寬比貫孔上物理氣相沉積(PVD)晶種涵蓋範圍不足所造成之底端空洞,其進而使跳貫孔之電阻率下降,並因此提升裝置效能。此外,有助益的是,就習知BEOL或MOL敷金屬(metallization)可能無法延展之7nm及更先進裝置,本文中所述之金屬互連結構對後段(backend-of-the line;BEOL)及中段(middle-of-the-line;MOL)互連結構會有影響。
本揭露之金屬互連結構可使用若干不同工具以若干方式來製造。不過,一般來說,該等方法及工具係用於形成微米及奈米級尺寸的結構。用於製造本揭露之金屬互連結構的方法(即技術)已由積體電路(IC)技術所採用。舉例而言,此等結構乃建置於晶圓上,並在晶圓之頂部藉由光微影製程所圖案化之材料膜中實現。特別的是,製造該等金屬互連結構使用了三個基本建構塊:(i)在基材上沉積材料薄膜,(ii)藉由光微影成像術在膜上塗敷圖案化遮罩,以及(iii)選擇性地對遮罩進行膜之蝕刻。
第1圖根據本揭露之態樣展示一種結構及各別製造程序。在具體實施例中,第1圖所示之結構10舉例來說,可以是BEOL或MOL結構。特別的是,結構10在晶粒(die)中包括複數個佈線階,例如:M0、M1等。舉例而言,結構10包括設於絕緣體材料12中之佈線結構14。如所屬技術領域中具有通常知識者應該理解的是,佈線結構14乃是就BEOL在M0層階處、或就中段(MOL)在CA/CB層階處代表性表示之下佈線結構;但佈線結構14可設於本結構之任何下層階處。
在具體實施例中,絕緣體材料12乃是氧化物為基礎之材料(SiO2),例如層間介電材料,其可藉由習知的沉積方法來沉積,例如藉由化學氣相沉積(chemical vapor deposition;CVD)。絕緣體材料12亦可以是超低k介電材料、摻碳絕緣體材料、或附有孔隙率之其它絕緣體材料。
佈線結構14可藉由所屬技術領域中具有通常知識者已知的習知微影、蝕刻及沉積方法來形成。舉例而言,使絕緣體材料12上方形成之光阻曝露至能量(光)以形成圖案(開口)。用到選擇性化學作用之蝕刻程序,例如反應性離子蝕刻(reactive ion etching;RIE),將用於貫穿光阻之開口在絕緣體材料12中形成一或多個溝槽。光阻可接著藉由習知的氧氣灰化程序或其它已知的條化劑(stripant)來移除。光阻移除過後,可在一或多個溝槽中藉由任何習知的沉積程序來沉積導電材料,例如:藉由化學氣相沉積(CVD)程序。佈線結構14可由舉例如銅、鎢、鈷、鎳、鋁、釕等任何導電材料所組成。佈線結構14亦可內襯(lined)有Ti、Ta、TiN、TaN、釕、鈷等。絕緣體材料12之表面上的任何殘餘材料14可藉由習知的化學機械研磨(chemical mechanical polishing;CMP)程序來移除。
CMP程序過後,在佈線結構14及絕緣體材料12上形成覆蓋層16。在具體實施例中,覆蓋層16可以是擴散阻障層,例如:銅擴散阻障層,其防止銅或其它敷金屬擴散至上絕緣體層18,並防止氧擴散至佈線結構14。佈線結構20及貫孔互連結構22乃是在上絕緣體層18中形成。在具體實施例中,佈線結構20及互連結構22可在佈線結構14之該者上面之任何佈線層中形成。因此,佈線結構20乃是M1、M2等層階處表示之上佈線結構,而互連結構22乃是V0、V1等層階處表示之上貫孔互連結構。佈線結構20及互連結構22可使用習知的微影、蝕刻及沉積程序來形成,與關於形成下佈線結構14所述者類似。佈線結構20及貫孔互連結構22可由舉例如銅、鈷、鎳、鎢、鋁、釕等任何導電材料所組成,內襯有Ti、Ta、TiN、TaN、釕、鈷等。
用以將任何殘餘材料從絕緣體材料18之表面移除之CMP程序過後,在佈線結構20及絕緣體材料18上形成覆蓋層24。在具體實施例中,覆蓋層24可以是擴散阻障層,例如銅擴散阻障層,如上所述,絕緣體材料18可以是如上所述之任何絕緣體材料。遮罩材料28乃是在絕緣體材料之表面上形成,介於M1層階上所選擇佈線結構 20之邊緣與M0層階上之佈線結構14之間。遮罩材料28可以是TiN,乃是藉由習知的沉積與蝕刻程序(例如,RIE)來沉積且圖案化。光阻30乃是在遮罩材料28及絕緣體材料18上形成,其乃曝露至能量(光)以分別形成與M0、M1層階處一或多個佈線結構14、22對準之圖案(開口)。
用到選擇性化學作用之蝕刻程序(例如:RIE)將用於貫穿光阻之開口在絕緣體材料18及覆蓋層24中形成一或多個貫穿開口32a、32b。蝕刻程序可定時終止於一深度,上佈線結構20之表面乃藉由貫孔32b曝露於此深度。按照這種方式,貫孔32b將會位於著落在M1層階上之佈線結構20之表面上並使其曝露之深度,而貫孔32a將會著落在並曝露下佈線(例如:M0層階)層14(通過上佈線層,例如M1層階)之表面。可進行溝槽RIE以形成溝槽36,例如上層階(例如層階M2)上佈線結構用之溝槽,然後藉由習知的條化劑將光阻30移除,並藉由濕式程序將遮罩材料28移除。在具體實施例中,貫孔32a、32b及溝槽36可藉由單鑲嵌或雙鑲嵌程序來形成。跳貫孔32a與溝槽36之組合在深度方面可為約30nm至約150nm,且在寬度方面可為約12nm至約50nm,例如高深寬比;但其它深寬比在本文中也列入考量範圍內。
如第2圖所示,跳貫孔32a乃是用鈷(Co)38來部分填充;而互連貫孔32b可在相同程序期間用鈷(Co)38來完全填充。在具體實施例中,貫孔32b亦可用鈷(Co)38來部分填充,端視沉積程序之定時條件而定。此外,舉例 來說,貫孔32b上面之溝槽36乃用鈷(Co)38來部分填充;亦即,鈷(Co)38將不會過量填充溝槽,反而僅部分地填充M1層階上之佈線結構20上面之溝槽36。所屬技術領域中具有通常知識者應了解的是,貫孔32a中所形成之互連結構將會是跳貫孔結構,電性並直接地連接至M0層階上之佈線結構14,舉例來說,將M1或上面層階中之任何連接旁通。貫孔32a中之鈷(Co)38可以是正規雙鑲嵌互連結構,對下層階上之佈線結構14提供電性與直接連接。另一方面,貫孔32b中之鈷(Co)38將會是正規單鑲嵌溝槽互連結構,對下層階上之佈線結構20提供電性與直接連接。在具體實施例中,舉一實施例來說,鈷可用鎳來取代。在進一步具體實施例中,生長材料可以是鎳或鈷之合金。
在具體實施例中,鈷(Co)38乃藉由選擇性無電式生長程序在M0、M1層階上形成,在貫孔32a、32b中自底端起向上形成。更具體地說,在具體實施例中,鈷(Co)38將會在下佈線層之一或多個佈線結構14及上佈線層上之佈線結構20的已曝露金屬表面上選擇性生長,而且不在貫孔32a、32b之絕緣體側壁上生長,例如:鈷(Co)38將不會在形成貫孔之側壁的絕緣體材料上生長。按照這種方式,鈷(Co)38生長程序將會由下往上在跳貫孔32a之下部分中進行完全填充,防止貫孔32a內發生任何空洞形成。換句話說,選擇性生長程序將會確保跳貫孔32a之填充無空洞,不管其外形與深寬比、晶種涵蓋範圍、佈線結構14、20任一者上之超低k(ULK)電漿誘發型損壞(PID)、 或覆蓋體對層間介電選擇性。這樣無空洞形成互連結構進而將使跳貫孔32a之電阻率下降。所屬技術領域中具有通常知識者亦應了解的是,鈷(Co)之無電式生長程序與介電材料相容,因此無需用到阻障層。
如第3圖所示,將貫孔32a及溝槽36之其餘部分(就上佈線結構而言)用導電材料40填充以形成雙鑲嵌結構,例如:互連結構及上佈線結構。在具體實施例中,金屬材料可以是銅、鈷、鎳、鋁、鎢、其合金等,這裡僅列舉數種列入考量範圍內之材料。導電材料40可藉由習知的沉積方法來沉積,例如:無電式、電鍍、CVD及/或物理氣相沉積(PVD)及/或原子層沉積(ALD),後面跟著習知的平坦化程序(例如:CMP),用以將絕緣體層26上之任何殘餘材料移除。接著可在絕緣體層26及導電材料40上方形成覆蓋層42,後面跟著習知的BEOL程序,用於上層階建置直到焊料連接結構為止。
本方法如以上所述,係用於製造積體電路晶片。產生之積體電路晶片可由製造商以空白晶圓形式(也就是說,作為具有多個未封裝晶片的單一晶圓)、當作裸晶粒、或以封裝形式來配送。在後例中,晶片乃嵌裝於單晶片封裝(例如:塑膠載體,有導線黏貼至主機板或其它更高層次載體)中、或多晶片封裝(例如:具有表面互連或埋置型互連任一者或兩者的陶瓷載體)中。在任一例子中,該晶片接著與其它晶片、離散電路元件、及/或其它信號處理裝置整合成下列之部分或任一者:(a)諸如主機板之中間產 品,或(b)最終產品。最終產品可以是包括積體電路晶片之任何產品,範圍涵蓋玩具及其它低階應用至具有顯示器、鍵盤或其它輸入裝置、及中央處理器的進階電腦產品。
本揭露之各項具體實施例的描述已為了說明目的而介紹,但用意不在於窮舉或受限於所揭示的具體實施例。許多修改及變例對於所屬技術領域中具有通常知識者將會顯而易知,但不會脫離所述具體實施例的範疇及精神。本文中使用的術語是為了最佳闡釋具體實施例之原理、對市場出現之技術所作的實務應用或技術改良、或讓所屬技術領域中具有通常知識者能夠理解本文中所揭示之具體實施例而選擇。
12‧‧‧絕緣體材料
14‧‧‧佈線結構、下佈線結構或下佈線層
16‧‧‧覆蓋層
18‧‧‧上絕緣體層或絕緣體材料
20‧‧‧佈線結構或上佈線結構
22‧‧‧互連結構或貫孔互連結構
24‧‧‧覆蓋層
26‧‧‧絕緣體層
32a‧‧‧貫孔開口、貫孔或跳貫孔
32b‧‧‧貫孔開口、貫孔或互連貫孔
38‧‧‧鈷
40‧‧‧導電材料
42‧‧‧覆蓋層
Claims (20)
- 一種半導體結構,其包含:具有一或多個佈線結構之第一佈線層;包含互連結構及佈線結構之第二佈線層;於該第二佈線層上面定位有一或多個貫孔互連件與佈線結構之至少一個上佈線層,該至少一個上佈線層之該一或多個貫孔互連件與佈線結構部分地包含第一金屬材料,該第一金屬材料具有在該第一金屬材料上方包含導電材料之其餘部分;以及通過該第二佈線層並延展至該第一佈線層之該一或多個佈線結構的跳貫孔,該跳貫孔部分地包含該第一金屬材料,該第一金屬材料具有在該第一金屬材料上方包含該導電材料之該跳貫孔的其餘部分,其中,該第一金屬材料是在該至少一個上佈線層之一或多個貫孔開口與佈線溝槽中及該跳貫孔內選擇性生長。
- 如申請專利範圍第1項所述之半導體結構,其中,該第一金屬材料與該第一佈線層之該一或多個佈線結構接觸。
- 如申請專利範圍第2項所述之半導體結構,其中,該第一金屬材料是鈷。
- 如申請專利範圍第1項所述之半導體結構,其中,該導電材料是鈷、鎳或其合金。
- 如申請專利範圍第4項所述之半導體結構,其中,該 鈷或鎳或其合金將該至少一個上佈線層之該一或多個貫孔開口完全填充。
- 如申請專利範圍第5項所述之半導體結構,其中,該跳貫孔沒有空洞。
- 如申請專利範圍第5項所述之半導體結構,其中,該鈷或鎳或其合金將填充有該鈷之該一或多個貫孔開口上面之佈線溝槽部分地填充。
- 如申請專利範圍第7項所述之半導體結構,其中,該導電材料將形成該至少一個上佈線層之該佈線結構的該佈線溝槽之其餘部分填充。
- 一種製造半導體結構之方法,其包含:形成貫孔以使上佈線層之一或多個佈線結構曝露;形成通過該上佈線層並使下佈線層之一或多個佈線結構曝露之跳貫孔;選擇性生長位在該貫孔中並部分地位在該跳貫孔內之金屬材料,其中,選擇性生長金屬材料之步驟包含選擇性生長該跳貫孔中之該金屬材料及合金以將該跳貫孔部分地填充;以及用導電材料將該跳貫孔之其餘部分填充。
- 如申請專利範圍第9項所述之方法,其中,該金屬材料是鈷、鎳或其合金。
- 如申請專利範圍第10項所述之方法,其中,選擇性生長鈷、鎳或其合金之步驟是無電式生長程序。
- 如申請專利範圍第11項所述之方法,其中,該無電式生長程序於該跳貫孔內向上起自底端,並起始自該下佈線層之該一或多個佈線結構之曝露部分。
- 如申請專利範圍第11項所述之方法,其中,該無電式生長程序未在該跳貫孔之絕緣體側壁上生長。
- 如申請專利範圍第13項所述之方法,其中,該無電式生長程序防止該跳貫孔中發生空洞形成。
- 如申請專利範圍第11項所述之方法,其中,該導電材料是鈷、鎳或其合金。
- 如申請專利範圍第11項所述之方法,其中,該鈷、鎳或其合金之生長將該貫孔上面之佈線溝槽部分地填充,且該方法更包含用該導電材料將該佈線溝槽之其餘部分填充以形成上佈線層。
- 一種製造半導體結構之方法,其包含:形成在下佈線層中具有一或多個佈線結構之佈線層;形成在上佈線層中具有一或多個佈線結構之佈線層,定位於該下佈線層上面;形成貫孔以使該上佈線層之該一或多個佈線結構曝露;形成通過該上佈線層並使該下佈線層中之該一或多個佈線結構曝露之跳貫孔;選擇性生長在該上佈線層與該下佈線層之該一或多個佈線結構之曝露部分上之金屬材料,其中,選擇 性生長金屬材料之步驟包含該金屬材料之無電式選擇性生長程序,用以將該跳貫孔部分地填充;以及用導電材料將該上佈線層上面另一佈線層之該跳貫孔與溝槽之其餘部分填充。
- 如申請專利範圍第17項所述之方法,其中,該金屬材料是鈷或鎳。
- 如申請專利範圍第17項所述之方法,其中,該無電式選擇性生長程序於該跳貫孔內向上起自底端,並起始自該下佈線層之該一或多個佈線結構之曝露部分。
- 如申請專利範圍第17項所述之方法,其中,該金屬材料之該無電式選擇性生長程序將該貫孔上面之佈線溝槽部分地填充,且該方法更包含用該導電材料將該佈線溝槽之其餘部分填充以形成上佈線層。
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US20180269150A1 (en) | 2018-09-20 |
CN108461477B (zh) | 2021-07-30 |
US10026687B1 (en) | 2018-07-17 |
TW201838129A (zh) | 2018-10-16 |
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