TWI681472B - 傳輸微小元件的方法 - Google Patents

傳輸微小元件的方法 Download PDF

Info

Publication number
TWI681472B
TWI681472B TW106111839A TW106111839A TWI681472B TW I681472 B TWI681472 B TW I681472B TW 106111839 A TW106111839 A TW 106111839A TW 106111839 A TW106111839 A TW 106111839A TW I681472 B TWI681472 B TW I681472B
Authority
TW
Taiwan
Prior art keywords
elements
micro
carrier substrate
substrate
buffer layer
Prior art date
Application number
TW106111839A
Other languages
English (en)
Other versions
TW201838046A (zh
Inventor
李允立
林子暘
賴育弘
陳培欣
Original Assignee
英屬開曼群島商錼創科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 英屬開曼群島商錼創科技股份有限公司 filed Critical 英屬開曼群島商錼創科技股份有限公司
Priority to TW106111839A priority Critical patent/TWI681472B/zh
Priority to US15/612,839 priority patent/US10431569B2/en
Priority to US16/045,748 priority patent/US10632727B2/en
Publication of TW201838046A publication Critical patent/TW201838046A/zh
Application granted granted Critical
Publication of TWI681472B publication Critical patent/TWI681472B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/27002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/27003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the layer preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29005—Structure
    • H01L2224/29006—Layer connector larger than the underlying bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
    • H01L2224/2908—Plural core members being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29118—Zinc [Zn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/301—Disposition
    • H01L2224/3018—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/30181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/305—Material
    • H01L2224/30505—Layer connectors having different materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32013—Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83053—Bonding environment
    • H01L2224/83095—Temperature settings
    • H01L2224/83096—Transient conditions
    • H01L2224/83097—Heating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Led Device Packages (AREA)

Abstract

一種傳輸微小元件的方法。提供一載體基板。載體基板上設置有一緩衝層以及多個微小元件。緩衝層位於載體基板與微小元件之間。微小元件彼此分離且透過緩衝層而定位於載體基板上。令一接收基板與載體基板上的微小元件相接觸。至少改變載體基板與接收基板其中一個的溫度，而使至少部分微小元件從載體基板釋放並傳輸至接收基板上。至少部分微小元件的數量介於1000個至2000000之間。

Description

傳輸微小元件的方法
本發明是有關於一種傳輸的方法，且特別是有關於一種可巨量傳輸微小元件的方法。
現今可透過靜電力或磁力等超距力的方式，將載體基板上的發光二極體轉板至接收基板上。然而，透過上述方式所傳輸的發光二極體的數量因受限靜電頭或磁力頭大小，因此無法有效提升傳輸的效率，進而無法滿足巨量傳輸的需求。此外，上述方式必須先透過靜電頭或磁力頭接觸載體基板上的發光二極體以靜電或磁力的方式拾取後，再轉移且定位於接收基板上；之後，透過解除靜電力或磁力等超距力的方式將發光二極體釋放至接收基板上。上述如此步驟繁複的傳輸發光二極體的步驟，使得發光二極體於轉板的程序中效率難以提升。
本發明提供一種傳輸微小元件的方法，其可達到巨量傳輸微小元件的目的，且可具有傳輸效率高的優勢。
本發明的傳輸微小元件的方法，其包括以下步驟。提供一載體基板，載體基板上設置有一緩衝層以及多個微小元件，緩衝層位於載體基板與微小元件之間，微小元件彼此分離且透過緩衝層而定位於載體基板上；令一接收基板與載體基板上的微小元件相接觸；以及至少改變載體基板與接收基板其中一個的溫度，而使至少部分微小元件從載體基板釋放並傳輸至接收基板上，其中至少部分微小元件的數量介於1000個至2000000個之間。
在本發明的一實施例中，上述的緩衝層覆蓋載體基板的一下表面，而微小元件暴露出部分緩衝層。
在本發明的一實施例中，上述的緩衝層包括多個對應微小元件的緩衝部，緩衝部彼此分離且暴露出部分載體基板。
在本發明的一實施例中，上述的令接收基板與載體基板上的微小元件相接觸的步驟包括：於微小元件與接收基板之間提供一接合層，微小元件透過接合層與接收基板相接觸。
在本發明的一實施例中，上述的接合層形成於微小元件上或接收基板上，以整面覆蓋微小元件的多個下表面或接收基板的一上表面。
在本發明的一實施例中，上述的接合層包括多個對應微小元件的接合部。
在本發明的一實施例中，上述的接合部形成於微小元件上、接收基板上或微小元件與接收基板上。
在本發明的一實施例中，上述的至少改變載體基板與接收基板其中一個的溫度的步驟包括：升高載體基板的溫度，以降低至少部分微小元件與載體基板之間的接合力，而使微小元件傳輸至接收基板。
在本發明的一實施例中，上述的升高載體基板的溫度至攝氏溫度50度至200度之間。
在本發明的一實施例中，上述的至少改變載體基板與接收基板其中一個的溫度，其中載體基板的溫度與接收基板的溫度不同。
在本發明的一實施例中，上述的接合層的材質與緩衝層的材質相同，接合層的熔點溫度為Tmr，載體基板的溫度為Tc，接收基板的溫度為Tr，且Tr＜Tmr＜Tc。
在本發明的一實施例中，上述的該接合層的材質與該緩衝層的材質不同，接合層的熔點溫度為Tmr，緩衝層的熔點溫度為Tmc，載體基板的溫度為Tc，接收基板的溫度為Tr，且Tc＞Tmc，且Tr＜Tmr。
在本發明的一實施例中，上述的每一微小元件的最大寬度介於3微米至100微米之間。
在本發明的一實施例中，上述的每一微小元件為一無機發光二極體。
在本發明的一實施例中，上述的載體基板由一無機材料所構成，而緩衝層由一有機材料所構成，且載體基板的硬度大於緩衝層的硬度。
在本發明的一實施例中，上述的緩衝層的楊氏模量(Young’s modulus)小於10 GPa，而載體基板的楊氏模量大於20 GPa。
在本發明的一實施例中，上述的微小元件的硬度大於緩衝層的硬度。
在本發明的一實施例中，上述的緩衝層的楊氏模量小於10 GPa，而微小元件的楊氏模量大於20 GPa。
在本發明的一實施例中，上述的載體基板的表面粗糙度小於2.5微米。
基於上述，本發明的傳輸微小元件的方法是令接收基板與載體基板上的微小元件相接觸之後，透過至少改變載體基板與接收基板其中一個的溫度，而使數量介於1000個至2000000個之間的微小元件同時性地從載體基板釋放並傳輸至接收基板上。相較於習知透過靜電力或磁力等超距力的方式來進行發光二極體的轉板程序而言，本發明的傳輸微小元件的方法可達成巨量傳輸微小元件的目的，且可具有傳輸效率高的優勢。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A至圖1C繪示為本發明的一實施例的一種傳輸微小元件的方法的剖面示意圖。請先參考圖1A，依照本實施例的傳輸微小元件的方法，首先，提供一載體基板100。載體基板100上設置有一緩衝層110a以及多個微小元件120，其中緩衝層110a位於載體基板100與微小元件120之間，而微小元件120彼此分離且透過緩衝層110a而定位於載體基板100上。
詳細來說，本實施例的載體基板100的表面粗糙度例如是小於2.5微米，較佳地，介於0.01微米至2 微米，且載體基板100的材質是一無機材料，例如是藍寶石基板或玻璃基板，但並不以此為限。控制載體基板100的表面粗糙度小於2.5微米，可使得微小元件120的水平高度均一，傳輸微小元件120的製程穩定度較高。如圖1A所示，緩衝層110a整面覆蓋載體基板100的一下表面102，其中緩衝層110a可視為一緩衝結構，其材質為一有機材料，例如為一具有黏性的高分子聚合物，以熱固化或ＵＶ固化而成，如環氧樹脂、聚醯亞胺、聚酯、聚氨酯、苯並環丁烯、聚乙烯、聚丙烯、聚丙烯酸酯及上述材料之組合。也就是說，緩衝層110a可同時具有黏著以及緩衝的功能。再者，緩衝層110a可為一層或多層結構，舉例來說，緩衝層110a可為二種高分子材料的雙層結構，或是由二種高分子交替堆疊而成多層結構，但不以此為限。此外，本實施例的緩衝層110a的材質亦可為熔點低於攝氏溫度200度的金屬或是合金，例如銦、銦鉍合金、錫鉍合金、鉛錫合金、鋅錫合金等，但不以此為限。載體基板100的硬度大於緩衝層110a的硬度，而微小元件120的硬度大於緩衝層110a的硬度，其中緩衝層110a的楊氏模量小於10 GPa，而載體基板110a的楊氏模量大於20 GPa，且微小元件120的楊氏模量大於20 GPa。
如圖1A所示，本實施例的微小元件120透過緩衝層110a而以陣列排列的方式定位於載體基板100上，其中微小元件120暴露出部分緩衝層110a，意即相鄰兩微小元件120之間會暴露出部分緩衝層110a。此處，微小元件120例如是無機發光二極體，如水平式發光二極體或垂直式發光二極體，較佳地，每一微小元件120的最大寬度例如是介於3微米至100微米之間。也就是說，本實施例的微小元件120具體化為微型發光二極體。
接著，請再參考圖1A，提供一接收基板130，其中接收基板130具體化為薄膜電晶體（Thin Film Transistor, TFT）基板。在其他的實施例中，接收基板130可以是玻璃基板、陶瓷基板、半導體（Semiconductor）基板、次黏著基台（Submount）、互補式金屬氧化物半導體（Complementary Metal-Oxide-Semiconductor, CMOS）電路基板、矽基液晶（Liquid Crystal on Silicon, LCOS）基板或其他具有驅動單元的基板。
須說明的是，為了提高載體基板100與接收基板130的結構強度，本實施例的載體基板100可配置於一第一支撐板S1上，而接收基板130可配置於一第二支撐板S2上，其中第一支撐板S1可為一具有加熱功能的支撐板或一沒有加熱功能的支撐板，而第二支撐板S2可為一具有加熱功能的支撐板或一沒有加熱功能的支撐板。
接著，請同時參考圖1A與圖1B，令接收基板130與載體基板100上的微小元件120相接觸。在本實施例中，令接收基板130與載體基板100上的微小元件120相接觸的步驟包括：於微小元件120與接收基板130之間提供一接合層140a，其中微小元件120透過接合層140a與接收基板130相接觸。此處，接合層140a具體化包括多個對應微小元件120的接合部142a，而接合部142a是形成於接收基板130上，但並不以此為限。換言之，微小元件120是夾置於設置在載體基板100上的緩衝層110a與形成在接合基板130上的接合層140a之間。此處，接合層140a的材質可與緩衝層110a的材質相同，藉著不同溫度的載體基板100與接收基板130，使得緩衝層110a與接合層140a為不同的相態。舉例來說，當緩衝層110a為液態，而接合層140a為固態時，意即緩衝層110a與接合層140a呈現不同的相態，此時微小元件120轉移的時候不會產生滑動或位移的現狀，因而使微小元件120從載體基板100釋放並可準確地傳輸至接收基板130上的對應位置。此外，本實施例的接合層140a的材質也可與緩衝層110a的材質不同，接合層140a的材質並不受限，金屬或高分子聚合物均可為接合層140a的材質，可用以接合微小元件120與接收基板130，並搭配緩衝層110a的材料熔點選擇適合的材料皆可作為接合層110a的材料。
由於緩衝層110a的硬度小於載體基板100的硬度以及微小元件120的硬度，因此當接收基板130與載體基板100上的微小元件120相接觸時，硬度較大的載體基板100與微小元件120不會受到損壞，可確保傳輸後的微小元件120良率。再者，緩衝層110a的楊氏模量數小於載體基板100的楊氏模量數以及微小元件120的楊氏模量數，意即緩衝層110a可具有較大的彈性，因此，當接收基板130與載體基板100上的微小元件120相接觸時所產生的應力可由緩衝層110a所吸收，可使微小元件120準確的傳輸到預定的位置，降低因微小元件120位移而產生的良率問題。較佳地，緩衝層110a的楊氏模量介於0.01GPa至10 GPa，而微小元件120與載體基板100的楊氏模量介於20 GPa至300 GPa。
須說明的是，此處所繪示的接合層140a的接合部142a為一示意結構，其必須搭配微小元件120的結構型態來設計。舉例來說，當微小元件120具體化為一水平式發光二極體時，接合部142a須搭配微小元件120的兩個電極而形成彼此分離的兩個部分；而，當微小元件120具體化為一垂直式發光二極體時，接合部142a須搭配微小元件120的一個電極，而如圖1A至圖1C中所繪示的型態。此外，本實施例的接合層140a的接合部142a的個數實質上與微小元件120的個數相同，因此本實施例的微小元件120可全部傳輸到形成在接收基板130上的接合層140a的接合部142a上。特別是，本實施例中傳輸到接收基板的微小元件120的數量，較佳地，介於1000個至1000002000000個之間。
最後，請參考圖1C，至少改變載體基板100與接收基板130其中一個的溫度，而使至少部分微小元件120從載體基板100釋放並傳輸至接收基板130上。詳細來說，至少改變載體基板100與接收基板130其中一個的溫度的步驟包括：首先，升高載體基板100的溫度，以降低至少部分微小元件120與載體基板100之間的接合力。此處，可透過第一支撐板S1來加熱載體基板100，以升高載體基板100的溫度或是透過第二支撐板S2來加熱，藉由熱傳導機制來加熱載體基板100。當載體基板100的溫度上升時，緩衝層110a因其材料特性的關係，會產生融（熔）態，而因此降低微小元件120與載體基板100之間的接合力，藉此微小元件120便從載體基板100釋放並傳輸至接收基板130上。
除上述步驟外，可進一步包含一微小元件120與接收基板130接合的步驟，詳述如下，升高接收基板130的溫度，以液化接合層140a。此處，可透過第二支撐板S2來加熱接收基板130，以升高接收基板130的溫度。當接收基板130的溫度上升時，接合層140a因其材料特性的關係會液化。最後，須對接收基板130進行一退火處理，使接合層140a由液態相轉變為固態，以加強微小元件120與接收基板130之間接合力。
此外，也可以改為使用具有黏性的材料作為接合層140a，選擇黏性足夠的材料，使得微小元件120與接合層140a之間的黏著力大於微小元件120與載體基板100之間的接合力，因此將微小元件120透過接合層140a而接合到接收基板130上。
進一步來說，至少改變載體基板100與接收基板130其中一個的溫度後，載體基板100的溫度與接收基板130的溫度不同。較佳地，升高載體基板100的溫度至攝氏溫度 50度至200度之間，而升高接收基板130的溫度至攝氏溫度 80度至280度之間。更具體來說，若接合層140a的材質與緩衝層110a的材質相同，緩衝層110a的熔點溫度為Tmr，載體基板100的溫度為Tc，接收基板130的溫度為Tr，且Tr＜Tmr＜Tc。也就是說，在接合層140a與緩衝層110a採相同材質的情況下，緩衝層110a的熔點溫度Tmc必須介於接收基板130的溫度Tr與載體基板100的溫度Tc之間。如此一來，載體基板100上的微小元件120才可透過載體基板100與接收基板130之間的溫度差而轉移至接收基板130上。
另一方面，若接合層140a的材質與緩衝層110a的材質不同，接合層140a的熔點溫度為Tmr，緩衝層110a的熔點溫度為Tmc，載體基板100的溫度為Tc，接收基板130的溫度為Tr，且Tc＞Tmc，且Tr＜Tmr。也就是說，在接合層140a與緩衝層110a採不同材質的情況下，載體基板100的溫度Tc要大於緩衝層110a的熔點溫度Tmc，以有效使緩衝層110a因其材料特性的關係產生融（熔）態，因而降低微小元件120與載體基板100之間的接合力；而接收基板130的溫度Tr要小於接合層140a的熔點溫度Tmr，而使微小元件120轉移至接收基板130。
簡言之，本實施例的傳輸微小元件的方法是令接收基板130與載體基板100上數量介於1000個至2000000個之間的微小元件120相接觸之後，透過載體基板100與接收基板130之間的溫度差，而使的微小元件120從載體基板100釋放並傳輸至接收基板130上，而完成傳輸微小元件的動作。相較於習知透過靜電力或磁力等超距力的方式來進行發光二極體的轉板程序而言，本實施例的傳輸微小元件的方法可一次傳輸1000個至2000000個微小元件，可達成巨量傳輸微小元件120的目的，且可具有傳輸效率高的優勢。
在此必須說明的是，下述實施例沿用前述實施例的元件標號與部分內容，其中採用相同的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，下述實施例不再重複贅述。
圖2A至圖2C繪示為本發明的另一實施例的一種傳輸微小元件的方法的剖面示意圖。請同時參考圖2A與圖1A，本實施例的傳輸微小元件與圖1A的傳輸微小元件相似，兩者的差異在於：於提供載體基板100的步驟中，本實施例的緩衝層110b包括多個對應微小元件120的緩衝部112，其中緩衝部112彼此分離且暴露出部分載體基板100。此處，緩衝部112的個數實質上與微小元件120的個數相同，而接合層140a的接合部142a的個數實質上與微小元件120的個數相同。特別是，緩衝部112於載體基板100上的正投影面積完全重疊且小於對應的微小元件120於載體基板100上的正投影面積，其目的在於當微小元件120轉板時緩衝部112能提供更好的緩衝效果。
接著，同圖1B的步驟，請參考圖2B，令接收基板130與載體基板100上的微小元件120相接觸。此處，載體基板100上的微小元件120分別與接收基板130上的接合層140a的接合部142a相接觸。之後，同圖1C的步驟，請參考圖2C，改變載體基板100與接收基板130的溫度，透過載體基板100與接收基板130之間的溫度差，而使微小元件120全部從載體基板100釋放到接收基板130上。
圖3A至圖3C繪示為本發明的另一實施例的一種傳輸微小元件的方法的剖面示意圖。請同時參考圖3A與圖3B以及圖2A與圖2B，本實施例的傳輸微小元件與圖2A與圖2B的傳輸微小元件相似，兩者的差異在於：於接收基板130與載體基板100上的微小元件120相接觸的步驟中，本實施例的接合層140c的接合部142c是形成於部分微小元件120上。也就是說，接合層140c的接合部142c是選擇性地形成在微小元件120上。因此，當接收基板130與載體基板100上的微小元件120相接觸時，僅只有部分的微小元件120可透過接合層140c的接合部142c接合於接收基板130上。
之後，同圖2C的步驟，請參考圖3C，改變載體基板100與接收基板130的溫度，透過載體基板100與接收基板130之間的溫度差，而使部分微小元件120從載體基板100釋放到接收基板130上。此時，如圖3C所示，尚有一部分的微小元件120是仍定位在載體基板100上，並未被傳輸到接收基板130上。換言之，本實施例的傳輸微小元件的方法可以是局部地或有選擇性地將載體基板100上的微小元件120傳輸至接收基板130上。
圖4A至圖4C繪示為本發明的另一實施例的一種傳輸微小元件的方法的剖面示意圖。請同時參考圖4A與圖4B以及圖2A與圖2B，本實施例的傳輸微小元件與圖2A與圖 2B的傳輸微小元件相似，兩者的差異在於：於接收基板130與載體基板100上的微小元件120相接觸的步驟中，本實施例的接合層140d的接合部142d形成於接收基板130上，且接合部142d僅對應部分微小元件130。也就是說，接合層140d的接合部142d是選擇性地形成在接收基板130上。因此，當接收基板130與載體基板100上的微小元件120相接觸時，僅只有部分的微小元件120可透過接合層140d的接合部142d接合於接收基板130上。
之後，同圖2C的步驟，請參考圖4C，改變載體基板100與接收基板130的溫度，透過載體基板100與接收基板130之間的溫度差，而使部分微小元件120從載體基板100釋放到接收基板130上。此時，如圖4C所示，尚有一部分的微小元件120是仍定位在載體基板100上，並未被傳輸到接收基板130上。換言之，本實施例的傳輸微小元件的方法可以是局部地或有選擇性地將載體基板100上的微小元件120傳輸至接收基板130上。
圖5A至圖5C繪示為本發明的另一實施例的一種傳輸微小元件的方法的剖面示意圖。請同時參考圖5A與圖5B以及圖2A與圖2B，本實施例的傳輸微小元件與圖2A與圖2B的傳輸微小元件相似，兩者的差異在於：於接收基板130與載體基板100上的微小元件120相接觸的步驟中，本實施例的接合層140e形成於接收基板130上，且是以整面覆蓋接收基板130的一上表面132。也就是說，接合層140e為一無圖案化的結構層，因此當接收基板130與載體基板100上的微小元件120相接觸時，微小元件120可全部透過接合層140c接合於接收基板130上。
之後，同圖2C的步驟，請參考圖5C，改變載體基板100與接收基板130的溫度，透過載體基板100與接收基板130之間的溫度差，而使全部的微小元件120從載體基板100釋放到接收基板130上。簡言之，本實施例的傳輸微小元件的方法可以是全部地將載體基板100上的微小元件120傳輸至接收基板130上。
綜上所述，本發明的傳輸微小元件的方法是令接收基板與載體基板上數量介於1000個至2000000個之間的微小元件相接觸之後，透過至少改變載體基板與接收基板其中一個的溫度，而使至少部分微小元件從載體基板釋放並傳輸至接收基板上，而完成傳輸微小元件的動作。相較於習知透過靜電力或磁力等超距力的方式來進行發光二極體的轉板程序而言，本發明的傳輸微小元件的方法可達成巨量傳輸微小元件的目的，且可具有傳輸率高的優勢。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100‧‧‧載體基板102‧‧‧下表面110a、110b‧‧‧緩衝層112‧‧‧緩衝部120‧‧‧微小元件130‧‧‧接收基板132‧‧‧上表面140a、140c、140d、140e‧‧‧接合層142a、142c、142d‧‧‧接合部S1‧‧‧第一支撐板S2‧‧‧第二支撐板
圖1A至圖1C繪示為本發明的一實施例的一種傳輸微小元件的方法的剖面示意圖。 圖2A至圖2C繪示為本發明的另一實施例的一種傳輸微小元件的方法的剖面示意圖。 圖3A至圖3C繪示為本發明的另一實施例的一種傳輸微小元件的方法的剖面示意圖。 圖4A至圖4C繪示為本發明的另一實施例的一種傳輸微小元件的方法的剖面示意圖。 圖5A至圖5C繪示為本發明的另一實施例的一種傳輸微小元件的方法的剖面示意圖。
100‧‧‧載體基板
102‧‧‧下表面
110a‧‧‧緩衝層
120‧‧‧微小元件
130‧‧‧接收基板
140a‧‧‧接合層
142a‧‧‧接合部
S1‧‧‧第一支撐板
S2‧‧‧第二支撐板

Claims (20)

  1. 一種傳輸微小元件的方法，包括：提供一載體基板，該載體基板上設置有一緩衝層以及多個微小元件，該緩衝層位於該載體基板與該些微小元件之間，該些微小元件彼此分離且透過該緩衝層而定位於該載體基板上；提供一接合層於該載體基板上的該些微小元件與一接收基板之間，該些微小元件透過該接合層與該接收基板相接觸，其中該接合層形成於該些微小元件上或該接收基板上，以整面覆蓋該些微小元件的多個下表面或該接收基板的一上表面；以及至少改變該載體基板與該接收基板其中一個的溫度，而使至少部分該些微小元件從該載體基板釋放並傳輸至該接收基板上，其中至少部分該些微小元件的數量介於1000個至2000000個之間。
  2. 如申請專利範圍第1項所述的傳輸微小元件的方法，其中該緩衝層覆蓋該載體基板的一下表面，而該些微小元件暴露出部分該緩衝層。
  3. 如申請專利範圍第1項所述的傳輸微小元件的方法，其中該緩衝層包括多個對應該些微小元件的緩衝部，該些緩衝部彼此分離且暴露出部分該載體基板。
  4. 如申請專利範圍第1項所述的傳輸微小元件的方法，其中至少改變該載體基板與該接收基板其中一個的溫度的步驟包括： 升高該載體基板的溫度，以降低至少部分該些微小元件與該載體基板之間的接合力，而使該些微小元件傳輸至該接收基板。
  5. 如申請專利範圍第4項所述的傳輸微小元件的方法，其中升高該載體基板的溫度至攝氏溫度50度至200度之間。
  6. 如申請專利範圍第1項所述的傳輸微小元件的方法，其中至少改變該載體基板與該接收基板其中一個的溫度後，該載體基板的溫度與該接收基板的溫度不同。
  7. 如申請專利範圍第6項所述的傳輸微小元件的方法，其中該接合層的材質與該緩衝層的材質相同，該接合層的熔點溫度為Tmr，該載體基板的溫度為Tc，該接收基板的溫度為Tr，且Tr<Tmr<Tc。
  8. 如申請專利範圍第6項所述的傳輸微小元件的方法，其中該接合層的材質與該緩衝層的材質不同，該接合層的熔點溫度為Tmr，該緩衝層的熔點溫度為Tmc，該載體基板的溫度為Tc，該接收基板的溫度為Tr，且Tc>Tmc，且Tr<Tmr。
  9. 如申請專利範圍第1項所述的傳輸微小元件的方法，其中各該微小元件的最大寬度介於3微米至100微米之間。
  10. 如申請專利範圍第1項所述的傳輸微小元件的方法，其中各該微小元件為一無機發光二極體。
  11. 如申請專利範圍第1項所述的傳輸微小元件的方法，其中該載體基板由一無機材料所構成，該緩衝層由一有機材料所構成，且該載體基板的硬度大於該緩衝層的硬度。
  12. 如申請專利範圍第11項所述的傳輸微小元件的方法，其中該緩衝層的楊氏模量小於10GPa，而該載體基板的楊氏模量大於20GPa。
  13. 如申請專利範圍第11項所述的傳輸微小元件的方法，其中該些微小元件的硬度大於該緩衝層的硬度。
  14. 如申請專利範圍第13項所述的傳輸微小元件的方法，其中且該緩衝層的楊氏模量小於10GPa，而該些微小元件的楊氏模量大於20GPa。
  15. 如申請專利範圍第1項所述的傳輸微小元件的方法，其中該載體基板的表面粗糙度小於2.5微米。
  16. 如申請專利範圍第1項所述的傳輸微小元件的方法，其中於至少改變該載體基板與該接收基板其中一個的溫度時，藉由不同溫度的該載體基板與該接收基板，使該緩衝層與該接合層呈現不同的相態。
  17. 如申請專利範圍第1項所述的傳輸微小元件的方法，更包括：提供一第一支撐板，該載體基板配置於該第一支撐板上，其中該第一支撐板為一具有加熱功能的支撐板或一沒有加熱功能的支撐板。
  18. 如申請專利範圍第17項所述的傳輸微小元件的方法，更包括： 提供一第二支撐板，該接收基板配置於該第二支撐板上，其中該第二支撐板為一具有加熱功能的支撐板或一沒有加熱功能的支撐板。
  19. 一種傳輸微小元件的方法，包括：提供一載體基板，該載體基板上設置有一緩衝層以及多個微小元件，該緩衝層位於該載體基板與該些微小元件之間，該些微小元件彼此分離且透過該緩衝層而定位於該載體基板上；提供一接合層於該載體基板上的該些微小元件與一接收基板之間，該些微小元件透過該接合層與該接收基板相接觸，其中該接合層包括多個對應該些微小元件的接合部；以及至少改變該載體基板與該接收基板其中一個的溫度，而使至少部分該些微小元件從該載體基板釋放並傳輸至該接收基板上，其中至少部分該些微小元件的數量介於1000個至2000000個之間。
  20. 如申請專利範圍第19項所述的傳輸微小元件的方法，其中該些接合部形成於該些微小元件上、該接收基板上或該些微小元件與該接收基板上。
TW106111839A 2017-04-10 2017-04-10 傳輸微小元件的方法 TWI681472B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW106111839A TWI681472B (zh) 2017-04-10 2017-04-10 傳輸微小元件的方法
US15/612,839 US10431569B2 (en) 2017-04-10 2017-06-02 Method of transferring micro devices
US16/045,748 US10632727B2 (en) 2017-04-10 2018-07-26 Method of transferring micro devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW106111839A TWI681472B (zh) 2017-04-10 2017-04-10 傳輸微小元件的方法

Publications (2)

Publication Number Publication Date
TW201838046A TW201838046A (zh) 2018-10-16
TWI681472B true TWI681472B (zh) 2020-01-01

Family

ID=63710426

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106111839A TWI681472B (zh) 2017-04-10 2017-04-10 傳輸微小元件的方法

Country Status (2)

Country Link
US (1) US10431569B2 (zh)
TW (1) TWI681472B (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI616116B (zh) * 2016-12-02 2018-02-21 錼創科技股份有限公司 顯示器及其修補方法
US11257704B2 (en) * 2018-04-15 2022-02-22 Hon Hai Precision Industry Co., Ltd. Device for transferring and integrating micro-devices and method of transfer
CN111199908A (zh) * 2018-11-20 2020-05-26 昆山工研院新型平板显示技术中心有限公司 微发光器件的转移方法及转移设备
US10910239B1 (en) * 2019-07-10 2021-02-02 Mikro Mesa Technology Co., Ltd. Method of transferring micro devices and device transfer system
TWI705038B (zh) * 2019-10-31 2020-09-21 隆達電子股份有限公司 取料裝置及其取料方法
US11302561B2 (en) * 2019-11-12 2022-04-12 Palo Alto Research Center Incorporated Transfer elements that selectably hold and release objects based on changes in stiffness
US11348905B2 (en) 2020-03-02 2022-05-31 Palo Alto Research Center Incorporated Method and system for assembly of micro-LEDs onto a substrate
CN115226413A (zh) * 2021-02-20 2022-10-21 厦门三安光电有限公司 一种微发光元件、微发光阵列、转移方法及其显示器
TWI814434B (zh) * 2022-04-01 2023-09-01 友達光電股份有限公司 發光二極體陣列基板

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201023243A (en) * 2008-11-04 2010-06-16 Canon Kk Transfer method of functional region, LED array, LED printer head, and LED printer

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9773750B2 (en) * 2012-02-09 2017-09-26 Apple Inc. Method of transferring and bonding an array of micro devices
US8835940B2 (en) * 2012-09-24 2014-09-16 LuxVue Technology Corporation Micro device stabilization post
US9054235B2 (en) * 2013-01-22 2015-06-09 Micron Technology, Inc. Solid-state transducer devices with optically-transmissive carrier substrates and related systems, methods, and devices
US20160144608A1 (en) * 2014-11-23 2016-05-26 Mikro Mesa Technology Co., Ltd. Method for transferring device
US20170215280A1 (en) 2016-01-21 2017-07-27 Vuereal Inc. Selective transfer of micro devices
WO2018096455A1 (en) 2016-11-25 2018-05-31 Vuereal Inc. Integration of micro-devices into system substrate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201023243A (en) * 2008-11-04 2010-06-16 Canon Kk Transfer method of functional region, LED array, LED printer head, and LED printer

Also Published As

Publication number Publication date
US20180294387A1 (en) 2018-10-11
TW201838046A (zh) 2018-10-16
US10431569B2 (en) 2019-10-01

Similar Documents

Publication Publication Date Title
TWI681472B (zh) 傳輸微小元件的方法
TWI685946B (zh) 載板結構及微型元件結構
CN108695412B (zh) 传输微小元件的方法
TWI706554B (zh) 畫素陣列基板及其製造方法
US10632727B2 (en) Method of transferring micro devices
TWI745515B (zh) 電子裝置與其製造方法
US11177154B2 (en) Carrier structure and micro device structure
US20160111605A1 (en) Method for transferring light-emitting elements onto a package substrate
CN107768415B (zh) 柔性显示器件、显示装置以及制造方法
TWM602725U (zh) 薄膜覆晶封裝結構與顯示裝置
TW202008043A (zh) 陣列基板及其製造方法，及應用此陣列基板的顯示裝置及其製造方法
TWI677975B (zh) 載板結構及微型元件結構
TWI693449B (zh) 電子裝置與其製造方法
JP2006509252A (ja) 薄膜トランジスタ基板、これの製造方法、これを有する液晶表示装置及びこれの製造方法
US10825787B2 (en) Electronic element and electronic device comprising the same
TWI751848B (zh) 電子元件的接合方法
JP5932919B2 (ja) フレキシブル表示装置の製造方法
TWI818827B (zh) 可撓性顯示裝置及其製造方法
TW202207382A (zh) 薄膜覆晶封裝結構與顯示裝置
KR101392577B1 (ko) 유기전계발광소자 분리방법, 이를 이용한 플렉서블 유기전계발광소자 제조방법, 및 이에 의하여 제조된 플렉서블 유기전계발광소자
WO2024195449A1 (ja) 接続構造体の製造方法及びガイドフィルム
TWI760806B (zh) 薄膜覆晶封裝結構與顯示裝置
US11056375B2 (en) Micro LED carrier board
KR20190009454A (ko) 편광판, 이를 포함하는 표시 장치 및 이의 제조방법
TW202117884A (zh) 轉印模具