TWI675447B - 轉換結構及高頻封裝 - Google Patents
轉換結構及高頻封裝 Download PDFInfo
- Publication number
- TWI675447B TWI675447B TW107113381A TW107113381A TWI675447B TW I675447 B TWI675447 B TW I675447B TW 107113381 A TW107113381 A TW 107113381A TW 107113381 A TW107113381 A TW 107113381A TW I675447 B TWI675447 B TW I675447B
- Authority
- TW
- Taiwan
- Prior art keywords
- ground
- wire
- ground pin
- signal
- pin wire
- Prior art date
Links
- 230000007704 transition Effects 0.000 title 1
- 238000006243 chemical reaction Methods 0.000 claims abstract description 25
- 230000005540 biological transmission Effects 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 6
- 239000000919 ceramic Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 230000007423 decrease Effects 0.000 claims description 2
- 230000003467 diminishing effect Effects 0.000 claims 1
- 239000004020 conductor Substances 0.000 abstract description 25
- 239000013256 coordination polymer Substances 0.000 description 7
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 5
- 238000003780 insertion Methods 0.000 description 3
- 230000037431 insertion Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P5/00—Coupling devices of the waveguide type
- H01P5/02—Coupling devices of the waveguide type with invariable factor of coupling
- H01P5/022—Transitions between lines of the same kind and shape, but with different dimensions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6611—Wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1903—Structure including wave guides
- H01L2924/19032—Structure including wave guides being a microstrip line type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1903—Structure including wave guides
- H01L2924/19033—Structure including wave guides being a coplanar line type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1903—Structure including wave guides
- H01L2924/19038—Structure including wave guides being a hybrid line type
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Waveguide Connection Structure (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
一種轉換結構,設置於一高頻封裝,該轉換結構包括一第一接地引腳導線及一第二接地引腳導線;以及一訊號引腳導線,設置於該第一接地引腳導線與該第二接地引腳導線之間,其中該第一接地引腳導線及該第二接地引腳導線具有一外部邊緣以及一內部邊緣,該訊號引腳導線耦接於形成於一傳輸線載體之一金屬線以及該高頻封裝中一晶片之一訊號端;其中,於該外部邊緣上形成於該第一接地引腳導線與該第二接地引腳導線之間之一外部間隙寬於該內部邊緣上形成於該第一接地引腳導線及該第二接地引腳導線之間之一內部間隙。
Description
本發明係指一種轉換結構及高頻封裝,尤指一種可達到較佳高頻效能的轉換結構及高頻封裝。
未來行動通訊系統及衛星通訊系統需操作於高頻。然而,傳統封裝結構並未針對高頻操作進行設計,於高頻處會導致相當損失,而使封裝結構的效能降低。
習知技術已提出將封裝結構中的導線架(lead frame)設計為傳輸線的概念。習知技術中,導線架的接地引腳導線與訊號引腳導線可設計為共平面波導(coplanar waveguide,CPW)或接地-訊號-接地(ground-signal-ground,GSG)結構。然而,封裝結構以外的訊號路徑(signal path)通常是以微帶線來實現,而於封裝結構的外部邊緣上,射頻訊號被迫被立刻轉成共平面波導結構,而使射頻效能變差。
因此,習知技術實有改善之必要。
因此,本發明之主要目的即在於提供一種可達到較佳高頻效能的轉換結構及高頻封裝,以改善習知技術的缺點。
本發明實施例揭露一種轉換結構,設置於一高頻封裝,該轉換結構包括一第一接地引腳導線及一第二接地引腳導線;以及一訊號引腳導線,設置於該第一接地引腳導線與該第二接地引腳導線之間,其中該第一接地引腳導線及該第二接地引腳導線具有一外部邊緣以及一內部邊緣,該訊號引腳導線耦接於形成於一傳輸線載體之一金屬線以及該高頻封裝中一晶片之一訊號端;其中,於該外部邊緣上形成於該第一接地引腳導線與該第二接地引腳導線之間之一外部間隙寬於於該內部邊緣上形成於該第一接地引腳導線及該第二接地引腳導線之間之一內部間隙。
本發明實施例另揭露一種高頻封裝,設置於一傳輸線載體,該高頻封裝包括一晶片座;一晶片,設置於該晶片座;以及一轉換結構,包括一第一接地引腳導線及一第二接地引腳導線;以及一訊號引腳導線,設置於該第一接地引腳導線與該第二接地引腳導線之間,其中該第一接地引腳導線及該第二接地引腳導線具有一外部邊緣以及一內部邊緣,該訊號引腳導線耦接於形成於一傳輸線載體的一金屬線以及該高頻封裝中該晶片的一訊號端;其中,於該外部邊緣上形成於該第一接地引腳導線與該第二接地引腳導線之間之一外部間隙寬於於該內部邊緣上形成於該第一接地引腳導線及該第二接地引腳導線之間之一內部間隙。
10、40‧‧‧高頻封裝
100、400‧‧‧轉換結構
102‧‧‧晶片
104‧‧‧晶片座
106g、106s‧‧‧接合線
20‧‧‧金屬線
22‧‧‧印刷電路板
A-A’‧‧‧線
CP、CP4‧‧‧中央部
D1、D2‧‧‧方向
E_ex、E_in‧‧‧邊緣
G1、G2、G14、G24‧‧‧接地引腳導線
GP_ex、GP_in‧‧‧間隙
GT‧‧‧接地端
PT‧‧‧突出部
SL、SL4‧‧‧訊號引腳導線
ST‧‧‧訊號端
W_ex、W_in‧‧‧寬度
第1圖為本發明實施例一高頻封裝的俯視示意圖。
第2圖為第1圖高頻封裝的剖面示意圖。
第3圖為微帶線(microstrip line)以及共平面波導的磁力線示意圖。
第4圖為本發明實施例一高頻封裝的俯視示意圖。
第5圖為本發明實施例高頻封裝的插入損失(Insertion Loss)的頻率響應。
第1圖為本發明實施例一高頻封裝10,第2圖為高頻封裝10沿第1圖中一A-A’線的的剖面示意圖。高頻封裝10設置於一傳輸線載體22,傳輸線載體22上形成有一金屬線20。傳輸線載體22可為一印刷電路板(printed circuit board,PCB)、一陶瓷基板、一半導體基板或一層壓印刷電路板(Laminate PCB),而不在此限,另外,金屬線20用來傳遞一射頻訊號。高頻封裝10包括一轉換結構100、一晶片(Die)102以及一晶片座(Die Paddle)104。轉換結構100設置於高頻封裝10的一面(如正面(topside)或背面(backside)),晶片102設置於高頻封裝10中的晶片座104。為了方面說明,第1圖僅繪示高頻封裝10的一部分,另外,以下將以傳輸線載體22為印刷電路板為例進行說明。
轉換結構100形成為一傳輸線,其包括一訊號引腳導線SL以及接地引腳導線G1、G2,接地引腳導線G1、G2透過接地接合線106g電性連接於晶片102的接地端GT。接地引腳導線G1、G2具有一外部邊緣E_ex以及一內部邊緣E_in。外部邊緣E_ex可為環繞高頻封裝10的外部表面,而內部邊緣E_in位於高頻封裝10內,即內部邊緣E_in相較於外部邊緣E_ex較靠近晶片102。另一方面,訊號引腳導線SL設置於接地引腳導線G1與接地引腳導線G2之間,訊號引腳導線SL電性連接於形成於印刷電路板22的金屬線20,以傳遞高頻封裝10的射頻訊號,另外,
訊號引腳導線SL透過一訊號接合線106s電性連接於晶片102的一訊號端ST。需注意的是,晶片座104可連接於接地引腳導線G1及接地引腳導線G2,以達到較佳的射頻效能。另外,連接於接地引腳導線G1、G2的接地接合線106g與連接於訊號引腳導線SL的訊號接合線106s形成一接地-訊號-接地(ground-signal-ground,GSG)結構,其連接於晶片102以達到較佳的射頻效能。
於外部邊緣E_ex上,接地引腳導線G1與接地引腳導線G2之間形成有一外部間隙(Gap)GP_ex,外部間隙GP_ex具有一寬度W_ex;於內部邊緣E_in上,接地引腳導線G1與接地引腳導線G2之間形成有一內部間隙GP_in,內部間隙GP_in具有一寬度W_in。需注意的是,外部間隙GP_ex寬於內部間隙GP_in,即寬度W_ex寬於/大於寬度W_in。另一方面,接地引腳導線G1與G2之間的間隙從外部邊緣E_ex往內部邊緣E_in可逐漸變窄。
另外,訊號引腳導線SL包括一中央部CP以及突出部PT。突出部PT自中央部CP朝向一第一方向D1突出以形成一電容,其中第一方向D1平行於外部邊緣E_ex或內部邊緣E_in。關於晶片102突出部PT的細節請參考申請人於台灣專利第105101822號專利申請案所揭露的內容,於此不再贅述。中央部CP可呈現一帶狀(strip shape),中央部CP的長邊垂直於第一方向D1而平行於一第二方向D2,其中第二方向D2代表從外部邊緣E_ex往內部邊緣E_in的方向,而第二方向D2垂直於第一方向D1。需注意的是,中央部CP與接地引腳導線G1/G2之間於第一方向D1的距離從外部邊緣E_ex到內部邊緣E_in呈現遞減趨勢,也就是說,中央部CP與接地引腳導線G1/G2之間於第一方向D1的距離由外部邊緣E_ex而內部邊緣E_in遞減。
需注意的是,轉換結構100(其為傳輸線)用來將一微帶線(microstrip line)結構逐漸轉換成具有接地-訊號-接地結構的一共平面波導(coplanar waveguide,CPW)。詳細來說,訊號引腳導線SL的一向外(朝向外部)末端可形成微帶線結構;而訊號引腳導線SL的一向內(朝向內部)末端與接地引腳導線G1、G2可一同形成共平面波導結構或接地-訊號-接地結構。詳細來說,請參考第3圖,第3圖繪示微帶線結構及共平面波導(接地-訊號-接地)結構的磁力線。於第3圖左側的子圖中,Strip可代表訊號引腳導線SL的向外末端;而於第3圖右側的子圖中,Strip可代表訊號引腳導線SL的向內末端,Ground可代表接地引腳導線G1、G2。請再參考第1圖,於訊號引腳導線SL的向外末端,因接地引腳導線G1、G2遠離訊號引腳導線SL,磁力線會掉至印刷電路板20下方的接地版(未繪示於第1圖),其類似於第3圖左方的子圖,因此,訊號引腳導線SL的向外末端形成微帶線結構。從向外末端(外部邊緣E_ex)至向內末端(內部邊緣E_in),接地引腳導線G1與G2之間的間距逐漸變/縮窄。於訊號引腳導線SL的向內末端,接地引腳導線G1、G2足夠靠近訊號引腳導線SL,此時磁力線被抬升起來而導向與訊號引腳導線SL共平面的接地引腳導線G1、G2,其類似於第3圖右方的子圖,因此,訊號引腳導線SL的向內末端與接地引腳導線G1、G2一同形成共平面波導結構或接地-訊號-接地結構。更進一步地,因形成於印刷電路板22的金屬線20大致為微帶線結構,設置於封裝10內的轉換結構100逐漸將磁力線從微帶線型式轉換成為共平面波導(接地-訊號-接地)型式,因此,轉換結構100逐漸將微帶線結構轉換成為共平面波導(接地-訊號-接地)結構。
另外,請再參考第2圖,為了降低因接合線與高頻封裝10模封塑料接觸而產生的電感效應,接合線的長度需要盡可能地縮短。為了達成此目的,可形成晶片座104(如透過蝕刻的方式)使得晶片102的頂面(top surface)與引腳導
線(如訊號引腳導線SL或接地引腳導線G1/G2))的頂面對齊或共平面。於一實施例中,晶片座104可形成有一凹槽而晶片102可設置於該凹槽,使得晶片102的頂面可與訊號引腳導線SL的頂面或接地引腳導線G1/G2的頂面共平面。關於晶片102的頂面與引腳導線共平面的特性,請參考申請人於台灣專利第105102435號專利申請案所揭露的內容,於此不再贅述。
需注意的是,前述實施例用以說明本發明之概念,本領域具通常知識者當可據以做不同的修飾,而不限於此。舉例來說,接地引腳導線及訊號引腳導線的形狀並未有所限。請參考第4圖,第4圖為本發明實施例一高頻封裝40的俯視示意圖。高頻封裝40與高頻封裝10類似,故相同元件沿用相同符號。與高頻封裝10不同的是,高頻封裝40中一轉換結構400之一訊號引腳導線SL4接地引腳導線G14、G24的形狀與高頻封裝40中轉換結構400的接地引腳導線G1、G2的形狀不同,只要外部間隙GP_ex寬於內部間隙GP_in,即符合本發明的要求而屬於本發明的範疇。
更進一步地,請參考第5圖,第5圖繪示本發明實施例高頻封裝的插入損失(Insertion Loss)的頻率響應。如第5圖所示,本發明高頻封裝的特性頻率(插入損失為1dB的頻率)推至41GHz,其高於申請人於台灣專利第105102435號及第105101822號專利申請案所揭露封裝的特性頻率31GHz。因此,相較於習知技術,本發明高頻封裝可達到更佳的射頻效能。
綜上所述,本發明利用轉換結構(其具有外部邊緣寬於內部邊緣的接地引腳導線),將微帶線結構轉換成為共平面波導(接地-訊號-接地)結構,以達到更佳的射頻效能。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
Claims (13)
- 一種轉換結構,設置於一高頻封裝,該轉換結構包括:一第一接地引腳導線及一第二接地引腳導線;以及一訊號引腳導線,設置於該第一接地引腳導線與該第二接地引腳導線之間,其中該第一接地引腳導線及該第二接地引腳導線具有一外部邊緣以及一內部邊緣,該訊號引腳導線耦接於形成於一傳輸線載體之一金屬線以及該高頻封裝中一晶片之一訊號端;其中,該外部邊緣上該第一接地引腳導線與該第二接地引腳導線之間之一外部間隙寬於該內部邊緣上該第一接地引腳導線及該第二接地引腳導線之間之一內部間隙;其中,該第一接地引腳導線與該第二接地引腳導線之間的一間距從該外部邊緣往該內部邊緣逐漸變縮窄。
- 如請求項1所述的轉換結構,其中該訊號引腳導線的一向外末端形成一微帶線結構,而該訊號引腳導線的一向內末端與該第一接地引腳導線及該第二接地引腳導線於該內部邊緣一同形成共平面波導結構。
- 如請求項1所述的轉換結構,其中該訊號引腳導線包括一突出部,該突出部自該訊號引腳導線的一中央部朝向一第一方向突出,該第一方向平行於該內部邊緣或該外部邊緣。
- 如請求項1所述的轉換結構,其中該訊號引腳導線包括一中央部,該中央部與該第一接地引腳導線之間的一距離隨著從該外部邊緣往該內部邊緣的方向遞減。
- 如請求項1所述的轉換結構,其中該傳輸線載體為一印刷電路板、一陶瓷基板、一半導體基板或一層壓印刷電路板。
- 一種高頻封裝,設置於一傳輸線載體,該高頻封裝包括:一晶片座;一晶片,設置於該晶片座;以及一轉換結構,包括:一第一接地引腳導線及一第二接地引腳導線;以及一訊號引腳導線,設置於該第一接地引腳導線與該第二接地引腳導線之間,其中該第一接地引腳導線及該第二接地引腳導線具有一外部邊緣以及一內部邊緣,該訊號引腳導線耦接於形成於一傳輸線載體的一金屬線以及該高頻封裝中該晶片的一訊號端;其中,該外部邊緣上該第一接地引腳導線與該第二接地引腳導線之間之一外部間隙寬於該內部邊緣上該第一接地引腳導線及該第二接地引腳導線之間之一內部間隙;其中,該第一接地引腳導線與該第二接地引腳導線之間的一間距從該外部邊緣往該內部邊緣逐漸變縮窄。
- 如請求項6所述的高頻封裝,其中該訊號引腳導線的一向外末端與該傳輸線載體形成一微帶線結構,而該訊號引腳導線的一向內末端與該第一接地引腳導線及該第二接地引腳導線於該內部邊緣一同形成一接地-訊號-接地的共平面波導結構。
- 如請求項6所述的高頻封裝,其中該第一接地引腳導線及該第二接地引腳導線透過接地接合線連接於該晶片,該訊號引腳導線透過一訊號接合線連接於該晶片,該接地接合線與訊號接合線形成形成一接地-訊號-接地結構。
- 如請求項6所述的高頻封裝,其中該訊號引腳導線包括一突出部,該突出部自該訊號引腳導線的一中央部朝向一第一方向突出,該第一方向平行於該內部邊緣或該外部邊緣。
- 如請求項6所述的高頻封裝,其中該訊號引腳導線包括一中央部,該中央部與該第一接地引腳導線之間的一距離隨著從該外部邊緣往該內部邊緣的方向遞減。
- 如請求項6所述的高頻封裝,其中該晶片的一頂面與該訊號引腳導線的一頂面共平面。
- 如請求項6所述的高頻封裝,其中該晶片座連接於該第一接地引腳導線及該第二接地引腳導線。
- 如請求項6所述的高頻封裝,其中該傳輸線載體為一印刷電路板、一陶瓷基板、一半導體基板或一層壓印刷電路板。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/890,360 US10665555B2 (en) | 2018-02-07 | 2018-02-07 | Transition structure and high-frequency package |
US15/890,360 | 2018-02-07 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201935653A TW201935653A (zh) | 2019-09-01 |
TWI675447B true TWI675447B (zh) | 2019-10-21 |
Family
ID=67475145
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW107113381A TWI675447B (zh) | 2018-02-07 | 2018-04-19 | 轉換結構及高頻封裝 |
Country Status (2)
Country | Link |
---|---|
US (1) | US10665555B2 (zh) |
TW (1) | TWI675447B (zh) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200742164A (en) * | 2006-04-17 | 2007-11-01 | Yeong-Her Wang | PCB-compatible 3dB coupler using microstrip-to-CPW via-hole transitions |
TW201501251A (zh) * | 2013-03-09 | 2015-01-01 | Adventive Ipbank | 低厚度引線半導體封裝 |
CN106449582A (zh) * | 2015-08-13 | 2017-02-22 | 稳懋半导体股份有限公司 | 高频封装结构 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AU2001227912A1 (en) * | 2000-01-13 | 2001-07-24 | Alpha Industries, Inc. | Microwave ic package with dual mode wave guide |
US6639322B1 (en) * | 2001-09-17 | 2003-10-28 | Applied Micro Circuits Corporation | Flip-chip transition interface structure |
US7088489B2 (en) * | 2002-10-04 | 2006-08-08 | Jds Uniphase Corporation | Launch interface electrode structure for suppressing coupling to substrate modes for electro-optic modulator |
AU2003289129A1 (en) * | 2002-12-05 | 2004-06-23 | Matsushita Electric Industrial Co., Ltd. | High-frequency circuit and high-frequency package |
CN1751412A (zh) * | 2003-02-21 | 2006-03-22 | 松下电器产业株式会社 | 高频电路 |
JP5707879B2 (ja) * | 2010-11-10 | 2015-04-30 | 富士通オプティカルコンポーネンツ株式会社 | 光送信器及び中継基板 |
US11101533B2 (en) * | 2016-10-13 | 2021-08-24 | Win Semiconductors Corp. | Radio frequency device |
-
2018
- 2018-02-07 US US15/890,360 patent/US10665555B2/en active Active
- 2018-04-19 TW TW107113381A patent/TWI675447B/zh not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200742164A (en) * | 2006-04-17 | 2007-11-01 | Yeong-Her Wang | PCB-compatible 3dB coupler using microstrip-to-CPW via-hole transitions |
TW201501251A (zh) * | 2013-03-09 | 2015-01-01 | Adventive Ipbank | 低厚度引線半導體封裝 |
CN106449582A (zh) * | 2015-08-13 | 2017-02-22 | 稳懋半导体股份有限公司 | 高频封装结构 |
Also Published As
Publication number | Publication date |
---|---|
US20190244917A1 (en) | 2019-08-08 |
TW201935653A (zh) | 2019-09-01 |
US10665555B2 (en) | 2020-05-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4835334B2 (ja) | 高周波信号伝送装置 | |
US9972587B2 (en) | Signal transmission device using electromagnetic resonance coupler | |
US8035203B2 (en) | Radio frequency over-molded leadframe package | |
JP6074695B2 (ja) | 高周波増幅回路 | |
CN112018066B (zh) | 基于htcc的高频垂直互联结构及封装结构 | |
US9532475B2 (en) | High-frequency module | |
TWI594380B (zh) | 封裝結構及三維封裝結構 | |
JP2011124913A (ja) | 信号変換器及び高周波回路モジュール | |
TWI663785B (zh) | 電子裝置、射頻裝置及其訊號傳輸構件 | |
US20120319913A1 (en) | Antenna device and wireless apparatus | |
CN111224629B (zh) | 射频功率放大器堆组、固态烹饪装置和发射器 | |
TWI656694B (zh) | 射頻裝置 | |
TWI675447B (zh) | 轉換結構及高頻封裝 | |
US6762493B2 (en) | Microwave integrated circuit | |
CN115693080B (zh) | 一种基于厚薄膜电路基板的大功率合成器实现方法 | |
JP5361024B2 (ja) | 配線基板 | |
US8766714B2 (en) | Amplifier component comprising a compensation element | |
US7064627B2 (en) | Signal transmission structure having a non-reference region for matching to a conductive ball attached to the signal transmission structure | |
JP5181424B2 (ja) | 高出力増幅器 | |
TWI627713B (zh) | 高頻封裝結構 | |
CN215070354U (zh) | 一种电缆与微带转换电路 | |
WO2022111149A1 (zh) | 一种封装结构、封装方法 | |
JP4760257B2 (ja) | 高周波デバイス | |
TWI720717B (zh) | 功率扁平無引腳封裝結構 | |
KR20180016052A (ko) | 내부 정합 회로를 포함하는 고출력 증폭기용 GaN 반도체 패키지의 내부 정합 회로 정합 방법 및 그 보정 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |