TWI662347B - Pixel structure - Google Patents

Abstract

A pixel structure includes a thin film transistor and a pixel electrode electrically connected to a drain electrode of the thin film transistor. The thin film transistor includes a source electrode, a drain electrode, a semiconductor layer, a first insulating layer, a second insulating layer, and a gate electrode. The semiconductor layer is located on the source and the drain and has a channel. The channel is disposed between the source and the drain and has a first through hole. The first insulating layer is located on the semiconductor layer and has a second through hole overlapping the first through hole. The second insulating layer is located on the first insulating layer and in the first through hole and the second through hole. The gate is located on the second insulating layer.

Description

Pixel structure

The present invention relates to a semiconductor structure, and more particularly to a pixel structure.

The display panel has the advantages of thinness, small size, and power saving, and thus has been widely used in daily life. The display panel includes a pixel array substrate, an opposite substrate opposite to the pixel array substrate, and a display medium disposed between the pixel array substrate and the opposite substrate. The pixel array substrate includes a substrate, a plurality of thin-film transistors disposed on the substrate, a plurality of pixel electrodes electrically connected to the plurality of thin-film transistors, a plurality of data lines, and a plurality of scanning lines. The electrical properties of the transistor affect the performance of the display panel most.

Generally speaking, a thin film transistor includes a source, a drain, a semiconductor layer, a gate, and at least one insulating layer disposed between the gate and the semiconductor layer. If the breakdown voltage of the gate insulating layer of a thin film transistor (for example, an organic gate insulating layer) is low, a thick insulating layer or a multi-layer insulating layer is usually provided between the gate and the semiconductor layer. However, if a thick insulating layer or a multi-layer insulating layer is provided between the gate and the semiconductor layer, the distance between the gate and the semiconductor layer will increase, which will cause problems such as excessively small turn-on current and poor subcritical swing.

The invention provides a pixel structure, and the thin film transistor has good electrical properties.

The pixel structure of the present invention includes a thin film transistor and a pixel electrode electrically connected to a drain electrode of the thin film transistor. The thin film transistor includes a source electrode, a drain electrode, a semiconductor layer, a first insulating layer, a second insulating layer, and a gate electrode. The semiconductor layer is located on the source and the drain and has a channel. The channel is disposed between the source and the drain and has a first through hole. The first insulating layer is located on the semiconductor layer and has a second through hole overlapping the first through hole. The second insulating layer is located on the first insulating layer and in the first through hole and the second through hole. The gate is located on the second insulating layer.

In an embodiment of the present invention, the channel has a plurality of sidewalls defined by at least one first through hole. The second insulating layer includes a first portion located in the at least one first through hole and the at least one second through hole and covering a sidewall of the channel.

In an embodiment of the present invention, the first insulating layer has a plurality of sidewalls defined by at least one second through hole, and the first portion of the second insulating layer directly covers the sidewall of the first insulating layer.

In an embodiment of the present invention, a sidewall of the first insulating layer is aligned with a sidewall of the channel.

In an embodiment of the present invention, the first portion of the second insulating layer has a recess. The gate includes a first sub-gate portion. The first sub-gate portion is located in the recess of the second insulating layer and overlaps at least a portion of the sidewall of the channel.

In an embodiment of the present invention, the second insulating layer further includes a second portion. The second portion is located on the first insulating layer outside the at least one first through hole and the at least one second through hole. The gate further includes a second sub-gate portion. The second sub-gate portion is located on the second portion of the second insulating layer.

In an embodiment of the present invention, the relative dielectric constant of the second insulating layer is greater than or equal to the relative dielectric constant of the first insulating layer.

In an embodiment of the present invention, the relative dielectric constant of the first insulating layer is ε ₁ , and 2 ≦ ε ₁ ≦ 3.

In an embodiment of the present invention, the relative dielectric constant of the second insulating layer is ε ₂ , and 2.5 ≦ ε ₂ ≦ 15.

In one embodiment of the present invention, the semiconductor layer includes an organic semiconductor material.

In an embodiment of the present invention, the pixel structure further includes a data line and a scan line. The data line is electrically connected to the source of the thin film transistor. The scanning line is electrically connected to the gate of the thin film transistor. The gate electrode and the source electrode, the drain electrode, the at least one first through-hole of the channel and the at least one second through-hole of the first insulating layer are overlapped.

Based on the above, the thin-film transistor with a pixel structure according to an embodiment of the present invention is provided with the first through hole of the semiconductor layer. The gate of the thin-film transistor can not only attract carriers to the top surface of the semiconductor layer to form a main channel. It is more able to attract carriers to move to the sidewall of the semiconductor layer to form a secondary channel. Thereby, the number of channels of the thin film transistor is increased, so that the turn-on current of the thin film transistor is increased, and the subcritical swing is improved.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. Throughout the description, the same reference numerals denote the same elements. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and / or electrical connection. Furthermore, "electrically connected" and "coupled" may mean that there are other components between the two components.

As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within an acceptable deviation range of a particular value determined by one of ordinary skill in the art, taking into account the measurements in question and A specific number of measurement-related errors (ie, limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the stated value, or within ± 30%, ± 20%, ± 10%, ± 5%. Furthermore, "about", "approximately" or "substantially" as used herein may select a more acceptable range of deviations or standard deviations based on optical properties, etching properties, or other properties, and all properties can be applied without one standard deviation .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the related art and the present invention, and will not be interpreted as idealized or excessive Formal meaning unless explicitly defined as such in this article.

Exemplary embodiments are described herein with reference to cross-sectional views that are schematic views of idealized embodiments. Accordingly, variations in the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Therefore, the embodiments described herein should not be construed as limited to the particular shape of the area as shown herein, but include shape deviations caused by, for example, manufacturing. For example, a region shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, the acute angles shown may be round. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

FIG. 1 is a schematic top view of a pixel structure according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present invention. In particular, Fig. 2 corresponds to the section line I-I 'of Fig. 1. For the sake of clear examples, some drawings are marked with xyz rectangular coordinate system, where the directions x, y, and z are perpendicular.

Please refer to FIG. 1 and FIG. 2, the pixel structure 100 is disposed on the substrate 110. For example, in this embodiment, the substrate 110 may be provided with an insulating flat layer 120, and the pixel structure 100 may be disposed on the flat layer 120. However, the present invention is not limited thereto. In other embodiments, the pixel structure 100 may be directly disposed on the substrate 110. The substrate 110 is mainly used for carrying the pixel structure 100. In this embodiment, the material of the substrate 110 may be glass, quartz, organic polymers, or opaque / reflective materials (such as wafers, ceramics, or other applicable materials), or other applicable materials. material.

The pixel structure 100 includes a thin film transistor T1 and a pixel electrode 160 (shown in FIG. 1) electrically connected to the drain electrode D of the thin film transistor T1. The thin film transistor T1 includes a source S, a drain D, a semiconductor layer 130, a first insulating layer 140, a second insulating layer 150, and a gate G. The source S and the drain D are separated from each other. In this embodiment, the source S and the drain D can be selectively disposed on the flat layer 120, but the present invention is not limited thereto. In this embodiment, the pixel structure 100 further includes a data line DL (shown in FIG. 1). The data line DL is electrically connected to the source S of the thin film transistor T1. For example, in this embodiment, the source S may be a branch extending outward from the data line DL. However, the present invention is not limited to this. In other embodiments, the source S may be a part of the data line DL. In this embodiment, the pixel structure 100 further includes a scan line SL (shown in FIG. 1). The scan line SL is electrically connected to the gate G of the thin film transistor T1. For example, in this embodiment, the gate G may be a branch extending outward from the scan line SL. However, the present invention is not limited thereto. In other embodiments, the gate G may be a part of the scan line SL.

In this embodiment, the data line DL, the source S and the drain D can be selectively formed on the same first conductive layer. However, the present invention is not limited thereto. In other embodiments, the data line DL, the source S and the drain D may also belong to different film layers. In this embodiment, the scan lines SL and the gate G can be selectively formed on the same second conductive layer. However, the present invention is not limited to this. In other embodiments, the scan line SL and the gate electrode G may belong to different film layers. Based on considerations of electrical conductivity, the data lines DL, scan lines SL, gate G, source S, and drain D are generally made of metal materials. However, the present invention is not limited to this. In other embodiments, the data line DL, the scan line SL, the gate G, the source S, and / or the drain D may also use other conductive materials, such as nitrogen of alloys and metal materials. Metal oxides, metal oxides, nitrogen oxides, or stacked layers of metal materials and other conductive materials.

The semiconductor layer 130 is located on the source S and the drain D. The semiconductor layer 130 covers the source S and the drain D. The source S and the drain D are respectively electrically connected to different two regions of the semiconductor layer 130. The semiconductor layer 130 has a channel 132. The channel 132 is disposed between the source S and the drain D. In detail, in this embodiment, the channel 132 refers to a region of the semiconductor layer 130 located between the source S and the drain D and overlapping with the gate G in the direction z. In this embodiment, the material of the semiconductor layer 130 is, for example, an organic semiconductor material. However, the present invention is not limited to this. In other embodiments, the material of the semiconductor layer 130 may be amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, oxide semiconductor materials (such as indium zinc oxide, indium germanium zinc, etc.). Oxides, or other suitable materials, or combinations thereof), or other suitable materials, or containing dopants in the above materials, or combinations thereof.

FIG. 3 is a schematic perspective view of a source, a drain, and a channel of a thin film transistor according to an embodiment of the present invention. Please refer to FIGS. 1, 2 and 3. The channel 132 of the thin film transistor T1 has at least one first through hole 132 a. FIG. 1, FIG. 2 and FIG. 3 take three first through holes 132 a as an example, but the present invention is not limited thereto. The number of the first through holes 132 a in the channel 132 may be determined according to actual requirements. In other embodiments, The number of the first through holes 132a of the channel 132 may also be other appropriate values. The first through hole 132 a of the channel 132 defines a plurality of sidewalls 132 s 1 of the semiconductor layer 130. The channel 132 has a bottom surface 132s2 facing the substrate 110 and a top surface 132s3 facing away from the substrate 110, and the side wall 132s1 is connected between the bottom surface 132s2 and the top surface 132s3. For example, in this embodiment, the length direction of the channel 132 is substantially parallel to the direction x, the side wall 132s1 defined by the first through hole 132a of the channel 132 is located substantially on the xz plane, and the top surface 132s3 of the channel 132 is located substantially The xy plane (for example, the xy plane in the z direction away from the origin), but the present invention is not limited thereto.

Referring to FIGS. 1 and 2, the first insulating layer 140 is located on the semiconductor layer 130 and has at least one second through hole 140 a. 1 and 2 take three second through holes 140a as an example, but the present invention is not limited thereto. The number of the second through holes 140a of the first insulating layer 140 may be determined according to actual requirements. In other embodiments, The number of the second through holes 140a of the first insulating layer 140 may also be other appropriate values.

The second through hole 140a of the first insulating layer 140 and the first through hole 132a of the channel 132 substantially overlap. In other words, the second through hole 140 a of the first insulating layer 140 is in communication with the first through hole 132 a of the channel 132. In this embodiment, the first insulating layer 140 has a plurality of sidewalls 140s1 defined by the second through hole 140a, the channel 132 has a plurality of sidewalls 132s1 defined by the first through hole 132a, and the sidewalls 140s1 of the first insulating layer 140 The side wall 132s1 of the channel 132 may be substantially aligned. For example, in the manufacturing process of the pixel structure 100 in this embodiment, a semiconductor material layer (not shown) and a first insulating material layer (not shown) can be sequentially formed on the substrate 110; then, the same mask is used. A cover that simultaneously patterns the semiconductor material layer and the first insulating material layer to form a semiconductor layer 130 and a first insulating layer 140. Therefore, in this embodiment, the semiconductor layer 130 and the first insulating layer 140 can be substantially aligned (or overlapped), but the present invention is not limited thereto. In other embodiments, the side wall 140s1 of the first insulating layer 140 may be retracted within the side wall 132s1 of the channel 132 or the side wall 140s1 of the first insulating layer 140 may protrude from the side wall 132s1 of the channel 132, and the first insulating layer 140 The side wall 140s1 may be located in a portion of the first through hole 132a.

The second insulating layer 150 is located on the first insulating layer 140 and in the second through hole 140 a of the first insulating layer 140 and the first through hole 132 a of the channel 132. For example, in this embodiment, the second insulating layer 150 includes a first portion 152 and a second portion 154; the first portion 152 is located in the second through hole 140a of the first insulating layer 140 and the first through hole 132a of the channel 132 The second portion 154 is located outside the second through hole 140a of the first insulating layer 140 and the first through hole 132a of the channel 132, and is located on the first insulating layer 140. The first portion 152 of the second insulating layer 150 covers the sidewall 140s1 defined by the second through hole 140a of the first insulating layer 140 and the sidewall 132s1 defined by the first through hole 132a of the channel 132. Preferably, in this embodiment, the first portion 152 of the second insulating layer 150 may directly cover the side walls 140s1 and 132s1 and contact the side walls 140s1 and 132s1, but the invention is not limited thereto.

In this embodiment, the thickness d2 of the second insulating layer 150 may be smaller than the thickness d1 of the first insulating layer 140, but is not limited thereto. The thickness d2 may refer to a thickness of a portion of the second insulating layer 150 located directly above the source S and / or the drain D. The thickness d1 may refer to a thickness of a portion of the first insulating layer 140 directly above the source S and / or the drain D. In this embodiment, the relative dielectric constant of the second insulating layer 150 may be greater than the relative dielectric constant of the first insulating layer 140. The relative dielectric constant of the second insulating layer 150 refers to the dielectric constant relative to vacuum; similarly, the relative dielectric constant of the first insulating layer 140 refers to the dielectric constant relative to vacuum. For example, in this embodiment, the relative dielectric constant of the first insulating layer 140 is ε ₁ , and the relative dielectric constant of the second insulating layer 150 is ε ₂ , 2 ≦ ε ₁ ≦ 3, 2.5 ≦ ε ₂ ≦ 15, but the invention is not limited to this. In this embodiment, the material of the first insulating layer 140 includes, for example, polymethylmethacrylate (PMMA), polyisobutylene (PIB), polyethylene (PE), polypropylene (PP), and polymer. Polystyrene (PS), poly-4-vinylphenol (PVP), polyvinyl alcohol (PVA) or copolymers thereof, or other appropriate organic materials, or other suitable materials, The material of the second insulating layer 150 includes, for example, parylene, or other suitable organic materials, or other suitable inorganic materials, or other suitable materials, but the invention is not limited thereto.

The gate electrode G is located on the second insulating layer 150. The gate G is overlapped with the source S, the drain D, the first through hole 132 a of the channel 132 and the second through hole 140 a of the first insulating layer 140. In this embodiment, the second insulating layer 150 can conformally cover the semiconductor layer 130, the first insulating layer 140, the first through hole 132a, and the second through hole 140a, and is located in the first through hole 132a and the first through hole 132a. The first portion 152 of the second insulating layer 150 in the through hole 140a has a recess 152a. In this embodiment, the gate G includes a first sub-gate portion Gs and a second sub-gate portion Gm. A portion of the first sub-gate portion Gs is located in the recess 152 a of the first portion 152 of the second insulating layer 150. The first sub-gate part Gs overlaps at least part of the side wall 132s1 of the channel 132 in the direction y. The first sub-gate part Gs covers at least part of the sidewall 132s1 of the channel 132 and is used to attract carriers (not shown) to the sidewall 132s1 of the channel 132. The side wall 132s1 of the channel 132 can be regarded as a secondary channel for transmitting carriers, and the first sub-gate portion Gs can be regarded as a secondary gate portion. The second sub-gate portion Gm is located on the second portion 154 of the second insulating layer 150. The second sub-gate part Gm covers the top surface 132s3 of the channel 132 and is used to attract carriers to the top surface 132s3 of the channel 132. The top surface 132s3 of the channel 132 can be regarded as a main channel for transmitting carriers, and the second sub-gate part Gm can be regarded as a main gate part.

Through the setting of the first through hole 132a of the channel 132, the gate G can not only attract carriers to move to the top surface 132s3 of the semiconductor layer 130 to form a main channel, but also attract carriers to move to the sidewall 132s1 of the semiconductor layer 130 to form a secondary channel. To channel. Thereby, the number of channels of the thin film transistor T1 is increased, so that the turn-on current of the thin film transistor T1 is increased, and the subcritical swing is improved. In addition, in this embodiment, a second insulating layer 150 is interposed between the first sub-gate portion Gs (ie, the secondary gate portion) and the side wall 132s1 of the channel 132 without the first insulating layer 140. Therefore, the first A sub-gate portion Gs can more effectively attract carriers to the side wall 132s1 of the semiconductor layer 130, and further increase the turn-on current of the thin-film transistor T1 and improve the subcritical swing.

FIG. 4 is a schematic top view of a pixel structure of a comparative example. 5 is a schematic cross-sectional view of a thin film transistor of a comparative example. In particular, Fig. 5 corresponds to the section line II-II 'of Fig. 4. Please refer to FIGS. 4 and 5. The pixel structure 200 of the comparative example is similar to the pixel structure 100 described above, and the same reference numerals are used to indicate the same or similar parts in the drawings and description. The pixel structure 200 of the comparative example includes a thin film transistor T2 and a pixel electrode 160 electrically connected to the thin film transistor T2. The thin film transistor T2 of the comparative example also includes a source S2, a gate G2, a drain D2, and a semiconductor layer 230. The difference between the pixel structure 200 of the comparative example and the pixel structure 100 described above is that the channel 232 of the thin film transistor T2 of the pixel structure 200 does not have the first through hole 132a or the second through hole 140a.

FIG. 6 shows a comparison between the threshold voltage Vth2 of the thin film transistor T2 of the pixel structure 200 of the comparative example and the threshold voltage Vth1 of the thin film transistor T1 of the pixel structure 100 of an embodiment of the present invention. Referring to FIG. 6, the average value of the threshold voltage Vth2 of each thin film transistor T2 in the comparative example is -4.43 V, and the average value of the threshold voltage Vth1 of each thin film transistor T1 in this embodiment is -3.23 V. It can be proved from FIG. 6 that, through the design of the above multi-channel (ie, primary and secondary channels), compared with the thin film transistor T2 of the comparative example, the absolute value of the average value of the threshold voltage of the thin film transistor T1 of this embodiment Smaller and better electrical.

FIG. 7 shows the times of the subthreshold swing (SS) SS2 of the thin film transistor T2 of the pixel structure 200 of the comparative example and the times of the thin film transistor T1 of the pixel structure 100 of an embodiment of the present invention. Comparison of critical swing SS1. Please refer to FIG. 7. The average value of the subcritical swing of the thin film transistor T2 in the comparative example is about 1078.65 mV / decade. The average value of the subcritical swing of the thin film transistor T1 in this embodiment is about It is 683.02 mV / decade. It can be proved from FIG. 7 that, through the design of the above multi-channel (ie, primary and secondary channels), compared with the thin film transistor T2 of the comparative example, the average value of the subcritical swing SS1 of the thin film transistor T1 of this embodiment Small and good electrical properties.

FIG. 8 shows the relationship between the gate voltage and the uniformized drain current of the thin film transistor T2 of the pixel structure 200 of the comparative example and the gate voltage and the uniformity of the thin film transistor T1 of the pixel structure 100 of an embodiment of the present invention The relationship of the drain current. Please refer to FIG. 8. The curve S11 and the curve S12 represent the relationship between the gate voltage and the uniform drain current of the thin film transistor T1 of the pixel structure 100 of an embodiment of the present invention, and the curves S21 and S22 represent the drawing of the comparative example. The relationship between the gate voltage of the thin film transistor T2 of the element structure 200 and the uniformized drain current. The drain driving voltages (Vd) of the curves S11 and S21 are about -10.1 volts, and the drain driving voltages (Vd) of the curves S12 and S22 are about -0.1 volts. As shown in FIG. 8, when the drain driving voltage (Vd) is about -10.1 volts, the thin film transistor T1 (curve) of the multi-channel (ie, primary and secondary) design of the pixel structure 100 according to an embodiment of the present invention S11) Compared with the thin film transistor T2 of the comparative example (curve S21), the thin film transistor T1 of this embodiment has a larger turn-on current and a better subcritical swing, and has good electrical properties; when the drain driving voltage When (Vd) is about -0.1 volts, the thin film transistor T1 (curve S12) of the multi-channel (ie, primary and secondary channel) design of the pixel structure 100 according to an embodiment of the present invention is compared with that of the comparative example. Crystal T2 (curve S22). The thin film transistor T1 of this embodiment has a larger turn-on current and a better subcritical swing, and has good electrical properties.

FIG. 9 shows the relationship between the channel length L (labeled in FIG. 4) of the thin film transistor T2 of the pixel structure 200 of the comparative example and the threshold voltage offset, and the The relationship between the channel length L (labeled in Figure 1) and the threshold voltage offset. Referring to FIG. 9, curve S13 represents the relationship between the channel length L and the threshold voltage deviation of the thin film transistor T1 of the pixel structure 100 according to an embodiment of the present invention, and curve S23 represents the thin film transistor of the pixel structure 200 of the comparative example. The relationship between the channel length L of T2 and the threshold voltage offset. It can be proved from FIG. 9 that the threshold voltage of the thin film transistor T1 in this embodiment is less likely to vary with the channel length L than in the thin film transistor T2 of the comparative example through the design of the multiple channels (ie, the primary channel and the secondary channel). Change and shift excessively, and the electrical property is good.

In summary, a pixel structure according to an embodiment of the present invention includes a thin film transistor and a pixel electrode electrically connected to a drain electrode of the thin film transistor. The thin film transistor includes a source electrode, a drain electrode, a semiconductor layer, a first insulating layer, a second insulating layer, and a gate electrode. The semiconductor layer is located on the source and the drain and has a channel. The channel is disposed between the source and the drain and has a first through hole. The first insulating layer is located on the semiconductor layer and has a second through hole overlapping the first through hole. The second insulating layer is located on the first insulating layer and in the first through hole and the second through hole. The gate is located on the second insulating layer. Through the arrangement of the first through hole in the semiconductor layer, the gate electrode can not only attract carriers to the top surface of the semiconductor layer to form a primary channel, but also attract carriers to move to the sidewall of the semiconductor layer to form a secondary channel. Thereby, the number of channels of the thin film transistor is increased, so that the turn-on current of the thin film transistor is increased, and the subcritical swing is improved.

In addition, in an embodiment of the present invention, a second insulating layer is sandwiched between the first sub-gate portion (ie, the secondary gate portion) and the side wall of the channel without the first insulating layer; thereby, the first The sub-gate part can be close to the side wall of the channel to more effectively attract carriers to the side wall of the channel, and further increase the turn-on current of the thin film transistor and improve the subcritical swing.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

100, 200‧‧‧ pixel structure

110‧‧‧ substrate

120‧‧‧ flat layer

130, 230‧‧‧Semiconductor layer

132, 232‧‧‧ channels

132a‧‧‧The first through hole

132s1, 140s1‧‧‧ sidewall

132s2‧‧‧ Underside

132s3‧‧‧Top

140‧‧‧first insulating layer

140a‧‧‧Second through hole

150‧‧‧Second insulation layer

152‧‧‧Part I

152a‧‧‧ sunken

154‧‧‧Part Two

160‧‧‧pixel electrode

D, D2‧‧‧ Drain

DL‧‧‧Data Line

d1, d2‧‧‧thickness

G, G2‧‧‧Gate

Gs‧‧‧The first sub-gate part

Gm‧‧‧Second Sub-Gate

L‧‧‧channel length

S, S2‧‧‧ source

SL‧‧‧scan line

S11, S12, S13, S21, S22, S23‧‧‧ curves

SS1, SS2 ‧‧‧ critical swings

T1, T2‧‧‧Thin-film transistors

Vth1, Vth2‧‧‧ critical voltage

x, y, z‧‧‧ directions

Ⅰ-Ⅰ ’, Ⅱ-Ⅱ’‧‧‧ hatching

FIG. 1 is a schematic top view of a pixel structure according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present invention. FIG. 3 is a schematic perspective view of a source, a drain, and a channel of a thin film transistor according to an embodiment of the present invention. FIG. 4 is a schematic top view of a pixel structure of a comparative example. 5 is a schematic cross-sectional view of a thin film transistor of a comparative example. FIG. 6 shows a comparison of a threshold voltage of a thin film transistor with a pixel structure of a comparative example and a threshold voltage of a thin film transistor with a pixel structure of an embodiment of the present invention. FIG. 7 shows a comparison of the sub-critical swing of several thin-film transistors with a pixel structure in a comparative example and the sub-critical swing of several thin-film transistors with a pixel structure in an embodiment of the present invention. FIG. 8 shows the relationship between the gate voltage and the uniformized drain current of the thin film transistor of the pixel structure of the comparative example, and the gate voltage and the uniformized drain current of the thin film transistor of the pixel structure of an embodiment of the present invention Relationship. FIG. 9 shows the relationship between the channel length and the threshold voltage offset of the thin film transistor of the pixel structure of the comparative example and the relationship between the channel length and the threshold voltage offset of the thin film transistor of the pixel structure according to an embodiment of the present invention.

Claims (10)

A pixel structure includes: a thin film transistor including: a source electrode and a drain electrode; a semiconductor layer covering the source electrode and the drain electrode and having a channel disposed on the source electrode and the drain electrode; Between the electrodes and having a channel length, wherein the channel has at least a first through hole; a first insulating layer, wherein a top surface of the semiconductor layer is substantially completely covered by the first insulating layer, and the first insulating layer A layer is overlapped with the source electrode and the drain electrode, the first insulating layer has at least one second through hole, the at least one second through hole overlaps with the at least one first through hole; a second insulating layer is located in the On the first insulation layer and in the at least one first through hole and the at least one second through hole, and the relative dielectric constant of the second insulation layer is greater than the relative dielectric constant of the first insulation layer; and a gate electrode Located on the second insulating layer, wherein the gate electrode protrudes from the semiconductor layer along an extending direction perpendicular to the length of the channel; and a pixel electrode is electrically connected to the drain electrode of the thin film transistor, wherein The channel has a defined by the at least one first through hole Side walls, the first insulating layer having a plurality of side walls at least one second through hole defined, and the gate to cover the plurality of sidewalls of the passage and the sidewall of the first insulating layer. The pixel structure according to item 1 of the scope of the patent application, wherein the second insulating layer includes a first portion located in the at least one first through hole and the at least one second through hole, and covering the channels The sidewall and the sidewalls of the first insulation layer. The pixel structure according to item 1 of the scope of patent application, wherein the side walls of the channel covered by the gate electrode are arranged along an extending direction perpendicular to the length of the channel. The pixel structure according to item 1 of the scope of patent application, wherein the sidewalls of the first insulation layer are aligned with the sidewalls of the channel. The pixel structure according to item 2 of the scope of patent application, wherein the first portion of the second insulating layer has a recess, and the gate includes a first sub-gate portion located on the second insulating layer. In the recess and overlapping at least part of the side walls of the channel. The pixel structure according to item 5 of the scope of patent application, wherein the second insulation layer further comprises: a second portion, the first insulation located outside the at least one first through hole and the at least one second through hole. Layer, wherein the gate further includes a second sub-gate portion, and the second sub-gate portion of the gate is located on the second portion of the second insulating layer. The pixel structure according to item 1 of the scope of the patent application, wherein the relative dielectric constant of the first insulating layer is ε ₁ , and 2 ≦ ε ₁ ≦ 3. The pixel structure according to item 1 of the scope of the patent application, wherein the relative dielectric constant of the second insulating layer is ε ₂ , and 2.5 ≦ ε ₂ ≦ 15. The pixel structure according to item 1 of the patent application scope, wherein the semiconductor layer comprises an organic semiconductor material. The pixel structure according to item 1 of the patent application scope further includes: a data line electrically connected to the source of the thin film transistor; and a scan line electrically connected to the gate of the thin film transistor. The connection, wherein the gate electrode is overlapped with the source electrode, the drain electrode, the at least one first through hole of the channel, and the at least second through hole of the first insulation layer.