TWI591411B - Pixel structure and manufacturing method thereof - Google Patents

Description

Pixel structure and its manufacturing method

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a pixel structure and a method of fabricating the same.

In recent years, display panels have been widely used in consumer electronics such as televisions, computers, mobile phones, and digital cameras. The display panel includes an active device array substrate, an opposite substrate, and a display medium disposed between the active device array substrate and the opposite substrate. The active device array substrate has a plurality of pixel structures. Each pixel structure includes a thin film transistor and a pixel electrode electrically connected to the thin film transistor. The thin film transistor is used to control the switching of the pixel structure. The performance of thin film transistors has a critical impact on the quality of the display panel. The thin film transistor includes a source, a drain, a gate, and a semiconductor pattern as a channel. In general, when the size of the gate is reduced, the edge of the gate is close to the edge of the semiconductor pattern, and the characteristic curve of the gate current and the gate voltage of the thin film transistor has a hump phenomenon, which is disadvantageous to the display panel. Quality.

The invention provides a pixel structure with good performance.

The invention provides a method for manufacturing a pixel structure, which can reduce the manufacturing cost of the pixel structure.

The pixel structure of the present invention includes a thin film transistor and a pixel electrode. The thin film transistor includes a source, a drain, a semiconductor layer, and a gate. The semiconductor layer is on the source and the drain and has a channel disposed between the source and the drain. The gate includes a main portion and an auxiliary portion. The main part is overlapped with the source, drain and channel. The auxiliary part is located outside the main part and is electrically connected to the main part. There is a gap between the main part and the auxiliary part. The pixel electrode is electrically connected to the drain.

The method for fabricating a pixel structure of the present invention comprises the steps of: forming a source and a drain separated from each other on a substrate; forming a first etch barrier pattern covering the source and the drain and exposing the source and the drain An upper surface; a semiconductor material layer formed on the first etch barrier pattern and the upper surface of the portion of the source and the drain; an insulating material layer formed on the semiconductor material layer; a conductive layer formed on the insulating material layer; and patterned conductive a layer to form a gate having at least one opening; patterning the layer of insulating material and the layer of semiconductor material with a gate to form an insulating layer having at least one opening and a semiconductor layer having at least one opening, wherein the gate At least one opening, at least one opening of the insulating layer, and at least one opening of the semiconductor layer communicate and expose the first etch barrier pattern.

Based on the above, the pixel structure of the present invention includes a thin film transistor having a source, a drain, a semiconductor layer, and a gate, and a pixel electrode. The gate of the thin film transistor includes a main portion and an auxiliary portion. The main part of the gate is overlapped with the source, the drain and the channel. The auxiliary part is located outside the main part and is electrically connected to the main part. There is a gap between the main part and the auxiliary part. With the auxiliary part, the gate can increase the ability of the carrier in the control channel, thereby suppressing the hump phenomenon and improving the electrical properties of the thin film transistor.

The above described features and advantages of the invention will be apparent from the following description.

1A to 1H are schematic top views of a method of fabricating a pixel structure according to an embodiment of the present invention. 2A to 2H are schematic cross-sectional views showing a method of fabricating a pixel structure according to an embodiment of the present invention. In particular, Figs. 2A to 2H correspond to the cross-sectional lines A-A' and B-B' of Figs. 1A to 1H. Referring to FIG. 1A and FIG. 2A, first, a substrate 10 is provided to carry a pixel structure 100 (labeled in FIGS. 1H and 2H). In this embodiment, the material of the substrate 10 may be glass, quartz, organic polymer, or an opaque/reflective material (eg, wafer, ceramic, etc.), or other applicable materials.

Referring to FIG. 1A and FIG. 2A, a source 112 and a drain 114 separated from each other are formed on the substrate 10. In the present embodiment, when the source 112 and the drain 114 are formed, the data line 116 electrically connected to the source 112 can be simultaneously formed. In other words, in the present embodiment, the source 112, the drain 114, and the data line 116 may be formed on the same film layer, but the invention is not limited thereto. Based on the matching considerations of the source 112, the drain 114, and the semiconductor layer 132 (labeled in FIGS. 1H and 2H), in the present embodiment, the source 112 and the drain 114 may be made of silver, but the invention is not limited thereto. Therefore, in other embodiments, the material of the source 112 and the drain 114 may also be selected from other conductive materials, such as other metal materials, alloys, nitrides of metal materials, oxides of metal materials, and oxynitrides of metal materials. Or a stacked layer of metal material and other conductive materials.

Referring to FIG. 1B and FIG. 2B, next, a first etch barrier pattern 120 is formed. The first etch barrier pattern 120 covers the source 112 and the drain 114 and exposes a portion of the upper surface 112a-1, 114a-1 of the source 112 and the drain 114. In detail, in the present embodiment, the first etch barrier pattern 120 exposes the upper surface 112a-1 of the end 112-1 of the source 112, the sidewall 112b of the end 112-1 of the source 112, and the drain 114. The upper surface 114a-1 of the end portion 114-1 and the side wall 114b of the end portion 114-1 of the drain electrode 114 cover the upper surface 112a-2 of the remaining portion of the source electrode 112 and the sidewall of the remaining portion of the source electrode 112. The upper surface 114a-2 of the remaining portion of the drain 114 and the sidewall of the remaining portion of the drain 114. In addition, the etch barrier pattern 120 also covers the data line 116. In detail, the first etch barrier pattern 120 may cover all of the upper surface 116a of the data line 116 and all of the sidewalls 116b, but the invention is not limited thereto.

It is worth mentioning that the setting of the first etch barrier pattern 120 can reduce the probability of the source 112, the drain 114 and the data line 116 causing machine contamination in subsequent processes, and can reduce the source 112, the drain 114 and the data. The probability of line 116 being damaged in subsequent processes. The material of the first etch barrier pattern 120 is preferably selected to have both conductivity and etch resistance. In this embodiment, the material of the first etch barrier pattern 120 may include a metal oxide such as indium tin oxide or indium zinc. Oxide, aluminum tin oxide, aluminum zinc oxide, indium antimony zinc oxide, or other suitable oxide, or a stacked layer of at least two of the above, but the invention is not limited thereto.

Referring to FIG. 1C and FIG. 2C, a semiconductor material layer 130 is formed on the first etch barrier pattern 120 and the source 112 and the partial upper surfaces 112a-1, 114a-1 of the drain 114. In the present embodiment, the semiconductor material layer 130 can cover the substrate 10 in a comprehensive manner, but the invention is not limited thereto. In this embodiment, the material of the semiconductor material layer 130 is, for example, an organic semiconductor material, but the invention is not limited thereto. In other embodiments, the material of the semiconductor material layer 130 may also be amorphous germanium, polycrystalline germanium, microcrystalline germanium, Single crystal germanium, an oxide semiconductor material (for example, indium zinc oxide, indium antimony zinc oxide, etc.), or other suitable material.

Referring to FIG. 1D and FIG. 2D, an insulating material layer 140 is formed on the semiconductor material layer 130. In this embodiment, the insulating material layer 140 may include a plurality of insulating material sub-layers 142, 144 sequentially formed on the semiconductor material layer 130, but the invention is not limited thereto. In this embodiment, the material of the insulating material layer 140 may be an inorganic material (for example, tantalum oxide, tantalum nitride, niobium oxynitride, or a stacked layer of at least two materials described above), an organic material, or a combination thereof.

Referring to FIG. 1D and FIG. 2D, a conductive layer 150 is formed on the insulating material layer 140. In the present embodiment, the conductive layer 150 may include a metal layer 152 and an etch barrier layer 154 sequentially formed on the insulating material layer 140. In the present embodiment, the material of the metal layer 152 is, for example, silver, and the material of the etching stopper layer 154 is, for example, a metal oxide (for example, indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium). Zinc oxide, or other suitable oxide, or a stacked layer of at least two of the above, but the invention is not limited thereto.

Referring to FIG. 1E and FIG. 2E, the conductive layer 150 is patterned to form a gate 156 having at least one opening 156a. In the present embodiment, the gate 156 includes a metal pattern 152a and a second etch barrier pattern 154a covering the metal pattern 152a. The metal pattern 152a and the second etch barrier pattern 154a are substantially tangable. In addition, in the present embodiment, when the gate 156 is formed, the scan line 158 electrically connected to the gate 156 can be simultaneously formed. In other words, the gate 156 and the scan line 158 can be formed on the same film layer, but the invention is not limited thereto. In the present embodiment, the metal layer 152 and the etch barrier layer 154 are simultaneously patterned by a wet etching process to form the gate 156 and the scan line 158, but the invention is not limited thereto.

Referring to FIG. 1F and FIG. 2F, the insulating material layer 140 and the semiconductor material layer 130 are patterned by using the gate 156 as a mask to form an insulating layer 146 having at least one opening 146a and a semiconductor layer having at least one opening 132a. 132. The gate 156 is disposed on the insulating layer 146. The insulating layer 146 covers the semiconductor layer 132. The opening 156a of the gate 156, the opening 146a of the insulating layer 146, and the opening 132a of the semiconductor layer 132 communicate to form a via hole 190, and expose the first etch barrier pattern 120. In this embodiment, the gate 156, the insulating layer 146, and the semiconductor layer 132 are substantially tangible, and the opening 156a, the opening 142a, and the opening 132a are substantially tangential; in other words, the vertical projection of the gate 156 on the substrate 10, The vertical projection of the insulating layer 146 on the substrate 10 and the vertical projection of the semiconductor layer 132 on the substrate 10 are similar patterns; further, the vertical projection of the gate 156 on the substrate 10, the insulating layer 146 on the substrate 10 The vertical projection and the vertical projection of the semiconductor layer 132 on the substrate 10 are substantially the same pattern and overlap each other, but the invention is not limited thereto.

In the present embodiment, the insulating material layer 140 and the semiconductor material layer 130 are patterned, for example, by a dry etching process to form the insulating layer 146 and the semiconductor layer 132. The first etch barrier pattern 120 can protect the source 112, the drain 114 and the data line 116 from damage during the dry etch process. It is worth mentioning that since the semiconductor layer 132 is formed by patterning the semiconductor material layer 130 with the gate 156 as a mask, it is not necessary to pattern the semiconductor material layer 130 with an additional mask. Thereby, the number of required masks for producing the pixel structure 100 (labeled in FIGS. 1H and 2H) can be reduced, which is advantageous for the cost reduction of the pixel structure 100. In addition, since the semiconductor layer 132 is formed by patterning the semiconductor material layer 130 with the gate 156 as a mask, there is no alignment problem between the gate 156 and the semiconductor layer 132, which contributes to the yield and power of the pixel structure 100. Sexual improvement.

Referring to FIG. 1G and FIG. 2G, a flat material layer 160 is formed on the substrate 10 to cover the gate 156 and a portion of the first etch barrier pattern 120. Referring to FIGS. 1H and 2H, next, the planar material layer 160 is patterned to form a planar layer 162 having a contact window 162a. The contact window 162a is offset from the opening 156a and exposes a portion of the first etch barrier pattern 120 above the drain 114. In this embodiment, the material of the flat layer 162 may be an inorganic material (for example, yttria, tantalum nitride, ytterbium oxynitride, or a stacked layer of at least two materials described above), an organic material, or a combination thereof. Then, a pixel electrode 170 is formed on the flat layer 162, and the pixel electrode 170 is filled in the contact window 162a to be electrically connected to the drain electrode 114 through the first etch barrier pattern 120. Here, the pixel structure 100 of the present embodiment is completed.

Referring to FIGS. 1H and 2H , the pixel structure 100 includes a thin film transistor T and a pixel electrode 170 electrically connected to the drain 114 of the thin film transistor T. The thin film transistor T includes a source 112, a drain 114, a semiconductor layer 132, and a gate 156. The semiconductor layer 132 is located on the source 112 and the drain 114 and has a channel 132c. Channel 132c is disposed between source 112 and drain 114. The gate 156 includes a main portion 156-1 and an auxiliary portion 156p. The main portion 156-1 is disposed to overlap the source 112, the drain 114, and the channel 132c. The auxiliary portion 156p is located outside the main portion 156-1. The pixel structure 100 also includes a connection portion 159. The auxiliary portion 156p is electrically connected to the main portion 156-1 through the connection portion 159. There is a gap (i.e., opening 156a) between the main portion 156-1 and the auxiliary portion 156p. The gate 156 can increase the ability of the carrier in the control channel 132c by the auxiliary portion 156p, thereby suppressing the hump phenomenon and improving the electrical properties of the thin film transistor T.

2I is a perspective schematic view of a gate 156, a source 112, and a drain 114 of a pixel structure 100 in accordance with an embodiment of the present invention. Referring to FIG. 1H, FIG. 2H and FIG. 2I, in the embodiment, the channel 132c of the semiconductor layer 132 has a channel width extending direction y, and the source electrode 112 has opposite edges 112-1a, 112 in the channel width extending direction y. -1b, the drain 114 has opposite edges 114-1a, 114-1b in the channel width extension direction y, and the main portion 156-1 of the gate 156 may protrude from the edge 112-1a, 112 of the source 112. 1b and the edges 114-1a, 114-1b of the drain 114.

Please continue to refer to Figures 1H and 2H. In the present embodiment, the auxiliary portion 156p includes a plurality of first auxiliary sub-portions 156-2. There is a gap (i.e., opening 156a) between each of the first auxiliary sub-sections 156-2 and the main portion 156-1. A plurality of first auxiliary sub-sections 156-2 are respectively located on opposite sides of the main portion 156-1. The plurality of first auxiliary sub-portions 156-2 and main portion 156-1 are arranged in the channel width extending direction y. The vertical projection of the plurality of first auxiliary sub-portions 156-2 on the substrate 10 is outside the vertical projection of the channel 132c on the substrate 10. The first auxiliary sub-portion 156-2 does not overlap the channel 132c. Further, in this embodiment, at least one first auxiliary sub-portion 156-2 may be located between the scan line 158 and the main portion 156-1 and spaced apart from the scan line 158, but the present invention does not limit.

In the embodiment, the auxiliary portion 156p further includes a plurality of second auxiliary sub-sections 156-3. A plurality of second auxiliary sub-sections 156-3 are respectively located on the other opposite sides of the main portion 156-1. The plurality of second auxiliary sub-sections 156-3 and the main portion 156 are arranged in the direction x. In this embodiment, there may be a gap (ie, opening 156a) between each of the second auxiliary sub-sections 156-3 and the main portion 156-1, but the invention is not limited thereto. In general, in the present embodiment, the first auxiliary sub-portion 156-2 and the second auxiliary sub-portion 156-3 can be connected to form a ring-shaped structure disposed around the main portion 156-1. The pixel structure 100 also includes at least one connection portion 159. The connecting portion 159 is electrically connected between the first auxiliary sub-portion 156-2 and the main portion 156-1. In this embodiment, the connecting portion 159 is also electrically connected between the second auxiliary sub-section 156-2 and the main portion 156-1, but the invention is not limited thereto.

3 is a cross-sectional view showing a pixel structure according to another embodiment of the present invention. 4 is a top plan view of a pixel structure in accordance with another embodiment of the present invention. In particular, Fig. 3 corresponds to the cross-sectional lines A-A' and B-B' of Fig. 4. Referring to FIGS. 3 and 4, the pixel structure 100A is similar to the pixel structure 100, and thus the same or corresponding elements are denoted by the same or corresponding reference numerals. The main difference between the pixel structure 100A and the pixel structure 100 is that the semiconductor layer 132A and the insulating layer 146A of the pixel structure 100A are different from the semiconductor layer 132 and the insulating layer 146 of the pixel structure 100. In addition, the pixel structure 100A is smaller than the pixel structure 100 by the first etch barrier pattern 120 and the second etch barrier pattern 154a, and the conductive pattern 182 is added. The following mainly explains the difference, the two are the same or corresponding, please refer to the above description, and will not be repeated here.

Referring to FIGS. 3 and 4 , the pixel structure 100A includes a thin film transistor T and a pixel electrode 170 electrically connected to the drain 114 of the thin film transistor T. The thin film transistor T includes a source 112, a drain 114, a semiconductor layer 132A, and a gate 156A. The semiconductor layer 132A is located on the source 112 and the drain 114 and has a via 132c. Channel 132c is disposed between source 112 and drain 114. The gate 156 includes a main portion 156-1 and an auxiliary portion 156p. The main portion 156-1 is disposed to overlap the source 112, the drain 114, and the channel 132c. The auxiliary portion 156p is located outside the main portion 156-1, and the auxiliary portion 156p is electrically connected to the main portion 156-1 through the connecting portion 159. There is a gap (i.e., opening 156a) between the main portion 156-1 of the gate 156 and the auxiliary portion 156p of the gate 156.

Unlike the pixel structure 100, the semiconductor layer 132A does not have an opening that is aligned with the opening 156a of the gate 156. In the embodiment of FIGS. 3 and 4, a portion of the opening 156a of the gate 156 may overlap a portion of the semiconductor layer 132A. The insulating layer 146A also does not have an opening that is aligned with the opening 156a of the gate 156. In detail, the insulating layer 146A may include an insulator layer 142A that covers the semiconductor layer 132A and is substantially aligned with the semiconductor layer 132A, and another insulator layer 144A that covers the insulator layer 142A. The pixel structure 100 also includes a conductive pattern 182. The drain electrode 114 covers a portion of the conductive pattern 182 and is electrically connected to the conductive pattern 182. The insulator layer 144A has an opening 144a. The opening 144a communicates with the contact window 162a to form the communication hole 192. The pixel electrode 170 is electrically connected to the drain electrode 114 of the thin film transistor T through the contact via hole 192 and through the conductive pattern 182 of the other portion not covered by the drain electrode 114.

In addition, it should be noted that the shape of the gate 156 shown in FIGS. 1H and 3 is for exemplifying the invention and is not intended to limit the invention. In other embodiments, the gate 156 can also be designed in other suitable shapes, as exemplified in conjunction with FIGS. 5-10.

5 is a top plan view showing a gate, a semiconductor layer, a source and a drain, a connection portion, and a conductive pattern of a thin film transistor of a pixel structure according to an embodiment of the present invention. The thin film transistor TB, the connection portion 159B, and the conductive pattern 182 of FIG. 5 are similar to the thin film transistor T, the connection portion 159, and the conductive pattern 182 of the pixel structure 100A of FIGS. 3 and 4, and thus the same or corresponding elements are the same. Or the corresponding label is indicated. The main difference between the two is that the gate 156B of the thin film transistor T-B is different from the gate 156 of the thin film transistor T of the pixel structure 100A. The following mainly explains the difference. If the two are the same or correspond, please refer to the above description, and the description will not be repeated here.

Referring to FIG. 5, the thin film transistor T-B includes a source 112, a drain 114, a semiconductor layer 132A, and a gate 156B. Semiconductor layer 132A is over source 112 and drain 114 and has a channel 132c. The channel 132c is disposed between the source 112 and the drain 114. The gate 156B includes a main portion 156-1 and an auxiliary portion 156p. The main portion 156-1 is disposed to overlap the source 112, the drain 114, and the channel 132c. The auxiliary portion 156p includes a first auxiliary sub-portion 156-2 and a second auxiliary sub-portion 156-3 that are located outside the main portion 156-1 and are electrically connected to the main portion 156-1. There is a gap (i.e., opening 156a) between the main portion 156-1 and the auxiliary portion 156p. Unlike the thin film transistor T of the pixel structure 100A, in the embodiment of FIG. 5, the connecting portion 159B is located between the main portion 156-1 and the second auxiliary sub-section 156-3. Further, the plurality of connecting portions 159B may not be aligned in the direction x. In the channel width extending direction y, the connecting portion 159B is not provided on the outer side of the channel 132c. The pixel structure including the thin film transistor T-B also has similar effects and advantages as the pixel structure 100, and will not be repeated here.

6 is a top plan view showing a gate, a semiconductor layer, a source and a drain, a connection portion, and a conductive pattern of a thin film transistor of a pixel structure according to another embodiment of the present invention. The thin film transistor TC, the connection portion 159C, and the conductive pattern 182 of FIG. 6 are similar to the thin film transistor T, the connection portion 159, and the conductive pattern 182 of FIGS. 3 and 4, and therefore the same or corresponding elements have the same or corresponding reference numerals. Said. The main difference between the two is that the gate 156C of the thin film transistor T-C is different from the gate 156A of the thin film transistor T of the pixel structure 100A. The following mainly explains the difference. If the two are the same or the corresponding ones, please refer to the above description, and the description and description will not be repeated here.

Referring to FIG. 6, the thin film transistor T-C includes a source 112, a drain 114, a semiconductor layer 132A, and a gate 156C. Semiconductor layer 132A is over source 112 and drain 114 and has a channel 132c. The channel 132c is disposed between the source 112 and the drain 114. The gate 156C includes a main portion 156-1 and an auxiliary portion 156p. The main portion 156-1 is disposed to overlap the source 112, the drain 114, and the channel 132c. The auxiliary portion 156p includes a first auxiliary sub-portion 156-2 and a second auxiliary sub-portion 156-3B that are located outside the main portion 156-1 and are electrically connected to the main portion 156-1. There is a gap (i.e., opening 156a) between the main portion 156-1 and the auxiliary portion 156p. Unlike the thin film transistor T of the pixel structure 100A, in the embodiment of FIG. 6, the second auxiliary sub-section 156-3B of the gate 156C can be directly connected to the main portion 156-1. The pixel structure including the thin film transistor T-C also has similar effects and advantages as the pixel structure 100, and will not be repeated here.

7 is a top plan view showing a gate, a semiconductor layer, a source, a drain, and a conductive pattern of a thin film transistor of a pixel structure according to still another embodiment of the present invention. The thin film transistor T-D and the conductive pattern 182 of FIG. 7 are similar to the thin film transistor T-C and the conductive pattern 182 of FIG. 6, and therefore the same or corresponding elements are denoted by the same or corresponding reference numerals. The main difference between the two is that the first auxiliary sub-portion 156-2 of the gate 156D of the thin film transistor TD can be electrically connected to the main portion 156-1 without connecting through the connecting portion 159C of FIG. 6, and the first auxiliary of the gate 156D. The sub-portion 156-2 can be electrically connected to the main portion 156-1 through the second auxiliary sub-portion 156-3B. In the channel width extending direction y, no connection portion is provided on the outer side of the channel 132c. The pixel structure including the thin film transistor T-D also has similar effects and advantages as the pixel structure 100, and will not be repeated here.

8 is a top plan view showing a gate, a semiconductor layer, a source and a drain, a connection portion, and a conductive pattern of a thin film transistor of a pixel structure according to still another embodiment of the present invention. The thin film transistor T-E, the connection portion 159E, and the conductive pattern 182 of FIG. 8 are similar to the thin film transistor T-C, the connection portion 159C, and the conductive pattern 182 of FIG. 6, and therefore the same or corresponding elements are denoted by the same or corresponding reference numerals. The main difference between the two is that the gate 156E of the thin film transistor T-E is different from the gate 156C of the thin film transistor T-C. In particular, in the embodiment of FIG. 8, each of the second auxiliary sub-sections 156-3E is coupled to one of the first auxiliary sub-sections 156-2 and to the other of the first auxiliary sub-sections 156-2. A first auxiliary sub-portion 156-2 connected to the second auxiliary sub-portion 156-3E can be electrically connected to the main portion 156-1 through the second auxiliary sub-portion 156-3E. The other first auxiliary sub-section 156-2 spaced apart from the second auxiliary sub-section 156-3E can be electrically connected to the main portion 156-1 through the connection portion 159E. The pixel structure including the thin film transistor T-E also has similar effects and advantages as the pixel structure 100, and will not be repeated here.

FIG. 9 is a top plan view showing a gate, a semiconductor layer, a source and a drain, a connection portion, and a conductive pattern of a thin film transistor of a pixel structure according to an embodiment of the present invention. The thin film transistor T-F, the connection portion 159F, and the conductive pattern of FIG. 9 are similar to the thin film transistor T-C of FIG. 6, the connection portion 159C, and the conductive pattern 182, and thus the same or corresponding elements are denoted by the same or corresponding reference numerals. The main difference between the two is that the gate 156F of the thin film transistor T-F is different from the gate 156C of the thin film transistor T-C. In particular, in the embodiment of FIG. 9, gate 156F may not include second auxiliary sub-section 156-3B of gate 156C. The plurality of first auxiliary sub-portions 156-2 of the gate 156F are electrically connected to the main portion 156-1 through the plurality of connecting portions 159F, respectively. The pixel structure including the thin film transistor T-F also has similar effects and advantages as the pixel structure 100, and will not be repeated here.

FIG. 10 is a top plan view showing a gate, a semiconductor layer, a source and a drain, a connection portion, and a conductive pattern of a thin film transistor of a pixel structure according to another embodiment of the present invention. The thin film transistor TG, the connection portion 159, and the conductive pattern 182 of FIG. 10 are similar to the thin film transistor T, the connection portion 159, and the conductive pattern 182 of FIGS. 3 and 4, and thus the same or corresponding elements are the same or corresponding. The label indicates. The main difference between the two is that the gate 156G of the thin film transistor T-G is different from the gate 156A of the thin film transistor T-B of the pixel structure 100A. In detail, in the embodiment of FIG. 10, the auxiliary portion 156p of the gate 156G includes a first auxiliary sub-section 156-2 and two second auxiliary sub-sections 156- located on the upper side of the source 112 and the drain 114. 3. A first auxiliary sub-section 156-2, two second auxiliary sub-sections 156-3, and two connection portions 159 on the upper side of the source 112 and the drain 114 may be located on the upper side of the source 112 and the drain 114. The main portion 156-1 can be enclosed in a ring structure. In addition, the auxiliary portion 156p of the gate 156G further includes a first auxiliary sub-section 156-2 and two second auxiliary sub-sections 156-3 on the lower side of the source 112 and the drain 114. A first auxiliary sub-section 156-2, two second auxiliary sub-sections 156-3, and two connection portions on the lower side of the source 112 and the drain 114 are located on the lower side of the source 112 and the drain 114. The 159 can be enclosed with another main ring structure 156-1. In the channel width extending direction y, the connecting portion 159 is not provided on the outer side of the channel 132c. The pixel structure including the thin film transistor T-G has similar effects and advantages as the pixel structure 100, and will not be repeated here.

In summary, the pixel structure of one embodiment of the present invention includes a thin film transistor having a source, a drain, a semiconductor layer, and a gate, and a pixel electrode. The gate of the thin film transistor includes a main portion and an auxiliary portion. The main part of the gate is overlapped with the source, the drain and the channel. The auxiliary part is located outside the main part and is electrically connected to the main part. There is a gap between the main part and the auxiliary part. With the auxiliary part, the gate can increase the ability of the carrier in the control channel, thereby suppressing the hump phenomenon and improving the electrical properties of the thin film transistor.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Substrate

100, 100A‧‧‧ pixel structure

112‧‧‧ source

112-1, 114-1‧‧‧ end

114-1 112-1a, 112-1b, 114-1a, 114-1b‧‧‧ edge

Upper surface of 112a-1, 114a-1, 112a-2, 114a-2, 116a‧‧

112b, 114b, 116b‧‧‧ side wall

114‧‧‧汲polar

116‧‧‧Information line

120‧‧‧First etch barrier pattern

130‧‧‧Semiconductor material layer

132, 132A‧‧‧ semiconductor layer

132a, 144a, 146a‧‧

132c‧‧‧ channel

140‧‧‧Insulation layer

142, 142A, 144, 144A‧‧‧ insulating material sublayer

146, 146A‧‧‧ insulation

150‧‧‧ Conductive layer

152‧‧‧metal layer

152a‧‧‧ metal pattern

154‧‧‧etch barrier

154a‧‧‧second etch barrier pattern

156, 156B ~ 156G‧‧ ‧ gate

156-1‧‧‧ Main Department

156p‧‧Auxiliary Department

156-2‧‧‧First Auxiliary Division

156-3, 156-3B, 156-3E‧‧‧second auxiliary subsection

159, 159B, 159C, 159E, 159F‧‧‧ Connections

156a‧‧‧ openings (gap)

158‧‧‧ scan line

160‧‧‧flat material layer

162‧‧‧flat layer

162a‧‧‧Contact window

170‧‧‧ pixel electrodes

182‧‧‧ conductive pattern

190, 192‧‧‧Connected holes

A-A’, B-B’‧‧‧ cut line

T, T-B, T-C, T-D, T-E, T-F, T-G‧‧‧ film transistors

x, y‧‧‧ direction

1A to 1H are schematic top views of a method of fabricating a pixel structure according to an embodiment of the present invention. 2A to 2H are schematic cross-sectional views showing a method of fabricating a pixel structure according to an embodiment of the present invention. 2I is a perspective schematic view of a gate, a source and a drain of a pixel structure according to an embodiment of the invention. 3 is a cross-sectional view showing a pixel structure according to another embodiment of the present invention. 4 is a top plan view of a pixel structure in accordance with another embodiment of the present invention. 5 is a top plan view showing a gate, a semiconductor layer, a source and a drain, a connection portion, and a conductive pattern of a thin film transistor of a pixel structure according to an embodiment of the present invention. 6 is a top plan view showing a gate, a semiconductor layer, a source and a drain, a connection portion, and a conductive pattern of a thin film transistor of a pixel structure according to another embodiment of the present invention. 7 is a top plan view showing a gate, a semiconductor layer, a source, a drain, and a conductive pattern of a thin film transistor of a pixel structure according to still another embodiment of the present invention. 8 is a top plan view showing a gate, a semiconductor layer, a source and a drain, a connection portion, and a conductive pattern of a thin film transistor of a pixel structure according to still another embodiment of the present invention. FIG. 9 is a top plan view showing a gate, a semiconductor layer, a source and a drain, a connection portion, and a conductive pattern of a thin film transistor of a pixel structure according to an embodiment of the present invention. FIG. 10 is a top plan view showing a gate, a semiconductor layer, a source and a drain, a connection portion, and a conductive pattern of a thin film transistor of a pixel structure according to another embodiment of the present invention.

10‧‧‧Substrate

100‧‧‧ pixel structure

112‧‧‧ source

112-1, 114-1‧‧‧ end

Upper surface of 112a-1, 114a-1, 112a-2, 114a-2, 116a‧‧

112b, 114b, 116b‧‧‧ side wall

114‧‧‧汲polar

116‧‧‧Information line

120‧‧‧First etch barrier pattern

132‧‧‧Semiconductor layer

132a, 146a‧‧

132c‧‧‧ channel

146‧‧‧Insulation

152a‧‧‧ metal pattern

154a‧‧‧second etch barrier pattern

156‧‧‧ gate

156-1‧‧‧ Main Department

156p‧‧Auxiliary Department

156-2‧‧‧First Auxiliary Division

156-3‧‧‧Second auxiliary subsection

159‧‧‧Connecting Department

156a‧‧‧ openings (gap)

162‧‧‧flat layer

162a‧‧‧Contact window

170‧‧‧ pixel electrodes

190‧‧‧Connected holes

A-A’, B-B’‧‧‧ cut line

T‧‧‧film transistor

Claims (17)

A pixel structure includes: a thin film transistor comprising: a source and a drain; a semiconductor layer on the source and the drain and having a channel, the channel being disposed at the source and the drain And an insulating layer covering the semiconductor layer; a gate disposed on the insulating layer, the gate comprising: a main portion overlapping the source, the drain and the channel; an auxiliary portion , outside the main portion and electrically connected to the main portion, wherein the main portion and the auxiliary portion have a gap; and at least one connecting portion electrically connected between the main portion and the auxiliary portion; A pixel electrode is electrically connected to the drain of the thin film transistor. The pixel structure of claim 1, further comprising: a data line electrically connected to the source of the thin film transistor; and a scan line and the gate electrical property of the thin film transistor Connected, wherein at least a portion of the auxiliary portion is located between the scan line and the main portion and spaced apart from the scan line. The pixel structure of claim 1, further comprising: a scan line electrically connected to the gate of the thin film transistor, wherein the auxiliary portion includes a plurality of first auxiliary sub-sections respectively located The opposite sides of the main part The gap exists between the first auxiliary sub-portion and the main portion in a first direction, the first direction is staggered with the length direction of the scan line, and the at least one connecting portion is electrically The connection is between the first auxiliary subsection and the main part. The pixel structure of claim 3, wherein the auxiliary portion further comprises a plurality of second auxiliary sub-sections respectively located on opposite sides of the main portion, the second auxiliary sub-section and the main portion Arranged in a second direction perpendicular to the first direction. The pixel structure according to claim 1, wherein the auxiliary portion has a ring structure disposed at a periphery of the main portion. The pixel structure of claim 1, wherein the channel of the semiconductor layer has a channel width extending direction, the pixel structure further comprising: a scan line, and the gate electrical property of the thin film transistor Connecting, wherein the auxiliary portion includes at least one first auxiliary sub-section located in the extending direction of the channel width and located on at least one side of the main portion, the gap exists between the at least one first auxiliary sub-portion and the main portion, The at least one connecting portion is electrically connected between the at least one first auxiliary sub-portion and the main portion. The pixel structure of claim 6, wherein the auxiliary portion further includes a second auxiliary sub-section located on the other side of the main portion, the second auxiliary sub-section being perpendicular to the main portion The channel width is arranged in the direction in which it extends. The pixel structure of claim 1, wherein the channel of the semiconductor layer has a channel width extending direction, and the source is at the channel width The extending direction has opposite edges, and the drain has opposite edges in the extending direction of the width of the channel, and the main portion protrudes from the edges of the source and the edges of the drain. The pixel structure of claim 1, wherein the gate is aligned with the semiconductor layer. The pixel structure of claim 1, further comprising: a data line electrically connected to the source; and a first etch barrier pattern covering an upper surface of the data line, the data line a sidewall, a sidewall of the source, a sidewall of the drain, a portion of the upper surface of the source, and a portion of the upper surface of the drain, wherein the semiconductor layer is disposed on the first etch barrier pattern, The upper surface of the portion of the source and the upper surface of the portion of the drain. The pixel structure of claim 10, further comprising: a flat layer covering the gate and having a contact window, wherein the pixel electrode passes through the contact window and the first etch barrier pattern and Bungee electrical connection. The pixel structure of claim 1, wherein the gate comprises a metal pattern and a second etch barrier pattern covering the metal pattern. The pixel structure of claim 1, further comprising: a data line electrically connected to the source, wherein the semiconductor layer covers the data line, the source, and the drain. The pixel structure of claim 1, wherein the insulating layer has an opening that is aligned with the gap. A method for fabricating a pixel structure includes: forming a source and a drain separated from each other on a substrate; forming a first etch barrier pattern covering the source and the drain, and exposing the source and the a portion of the upper surface of the drain; forming a layer of semiconductor material on the first etch barrier pattern and a portion of the source and the surface of the drain; forming a layer of insulating material on the layer of semiconductor material; Forming a conductive layer on the insulating material layer; patterning the conductive layer to form a gate having at least one opening; and patterning the insulating material layer and the semiconductor material layer with the gate mask to form An insulating layer having at least one opening and a semiconductor layer having at least one opening, wherein the at least one opening of the gate, the at least one opening of the insulating layer, and the at least one opening of the semiconductor layer are in contact with each other and exposing the first Etching the barrier pattern. The method for fabricating a pixel structure according to claim 15, wherein the conductive layer is patterned by a wet etching process, and the insulating material layer and the semiconductor material layer are patterned by a dry etching process. The method for manufacturing a pixel structure according to claim 15 of the patent application, further comprising: Forming a data line and a scan line, the data line is electrically connected to the source, and the scan line is electrically connected to the gate, wherein the first etch barrier pattern covers the data line.