TWI721736B - Semiconductor substrate - Google Patents

Abstract

A semiconductor substrate includes a base, a thin film transistor, an organic insulating layer and an electrode. The thin film transistor is disposed on the base. The organic insulating layer is disposed on the base. The electrode is disposed on the organic insulating layer and is electrically connected to the thin film transistor. The electrode includes a first metal oxide layer, a metal layer and a second metal oxide layer. The first metal oxide layer is disposed on the organic insulating layer. The metal layer is disposed on the first metal oxide layer, covers a sidewall of the first metal oxide layer, and contacts with the organic insulating layer. The second metal oxide layer is disposed on the metal layer. An edge of the second metal oxide layer is within an edge of the metal layer.

Description

Semiconductor substrate

The present invention relates to a substrate, and particularly relates to a semiconductor substrate.

Flat-panel displays have the advantages of lightness, thinness, small size and low volume. Therefore, they have been widely used in daily life. The flat panel display includes a pixel array substrate. The pixel array substrate has a plurality of thin film transistors, a plurality of pixel electrodes electrically connected to the plurality of thin film transistors, and a display medium. One pixel electrode includes a plurality of conductive patterns stacked in sequence. Generally, the same photomask is used to make a plurality of conductive patterns of a pixel electrode, and at least two of the plurality of conductive patterns are etched in the same process. However, the material of the conductive pattern sandwiched in the middle is different from the material of the plurality of conductive patterns located on the upper and lower sides, and the material of the conductive pattern sandwiched in the middle has a faster etching rate. Therefore, the fabricated pixel electrode is prone to dangling and/or loose structures at its boundaries, and the dangling and/or loose structures are easily peeled off and scattered around, forming a source of pollution particles. Conductive pollution particles may form a conductive path between the pixel electrode and other electrodes, causing short circuits and causing dead spots on the flat panel display.

The invention provides a semiconductor substrate, the electrode structure of which is stable and not easy to peel off to form pollutant particles.

The semiconductor substrate of the present invention includes a substrate, a thin film transistor, an organic insulating layer and an electrode. The thin film transistor is arranged on the substrate. The organic insulating layer is disposed on the substrate. The electrode is arranged on the organic insulating layer and is electrically connected to the thin film transistor. The electrode includes a first metal oxide layer, a metal layer, and a second metal oxide layer. The first metal oxide layer is disposed on the organic insulating layer. The metal layer is disposed on the first metal oxide layer, covers the sidewall of the first metal oxide layer, and is in contact with the organic insulating layer. The second metal oxide layer is disposed on the metal layer. The edge of the second metal oxide layer is within the edge of the metal layer.

In an embodiment of the present invention, the edge of the above-mentioned first metal oxide layer is within the edge of the metal layer.

In an embodiment of the present invention, the edge of the above-mentioned first metal oxide layer is within the edge of the second metal oxide layer.

In an embodiment of the present invention, the above-mentioned vertical projection of the edge of the second metal oxide layer on the substrate is located between the vertical projection of the edge of the metal layer on the substrate and the vertical projection of the edge of the first metal oxide layer on the substrate. Between projections.

In an embodiment of the present invention, the edge of the metal layer and the edge of the first metal oxide layer have a distance L1 in a direction parallel to the substrate, and the edge of the second metal oxide layer is parallel to the edge of the metal layer. There is a distance L2 in the direction of the base, and 0.1 ≤ (L2/L1) ≤ 10.

In an embodiment of the present invention, the above-mentioned metal layer has a first part and a second part, and the first part is sandwiched between the first metal oxide layer and the second metal oxide layer and is located in the first metal oxide layer. Within the area of the first metal oxide layer and the second metal oxide layer, the second part is in contact with the organic insulating layer and is located outside the area of the first metal oxide layer and the second metal oxide layer, and the thickness of the second part is smaller than that of the first part thickness.

Reference will now be made in detail to the exemplary embodiments of the present invention, and examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and descriptions to indicate the same or similar parts.

It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connection" can refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that there are other elements between two elements.

As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within the acceptable deviation range of the specific value determined by a person of ordinary skill in the art, taking into account the measurement in question and the The specific amount of measurement-related error (ie, the limitation of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "about", "approximately" or "substantially" as used herein can be based on optical properties, etching properties or other properties to select a more acceptable range of deviation or standard deviation, and not one standard deviation can be applied to all properties .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of related technologies and the present invention, and will not be interpreted as idealized or excessive The formal meaning, unless explicitly defined as such in this article.

FIG. 1 is a schematic cross-sectional view of a semiconductor substrate 10 according to an embodiment of the invention.

FIG. 2 is an enlarged schematic diagram of a part of the electrode 180 according to an embodiment of the present invention. Figure 2 corresponds to the area R of Figure 1.

3 is a schematic top view of the first metal oxide layer 182, the metal layer 184, the second metal oxide layer 186, and the substrate 110 of the electrode 180 according to an embodiment of the present invention. Figure 2 corresponds to the line segment A-A' of Figure 3.

Please refer to FIG. 1, the semiconductor substrate 10 includes a base 110. For example, in this embodiment, the material of the substrate 110 may be glass, quartz, organic polymers, or opaque/reflective materials (for example, wafers, ceramics, etc.), or other applicable materials.

The semiconductor substrate 10 includes a thin film transistor T and is disposed on a base 110. The thin film transistor T includes a semiconductor pattern 120, a gate insulating layer 130, a gate electrode G, a source electrode 152, and a drain electrode 154. The gate insulating layer 130 is disposed between the gate electrode G and the semiconductor pattern 120, and the source electrode 152 and the drain electrode 154 is electrically connected to two different regions of the semiconductor pattern 120, respectively.

For example, in this embodiment, the semiconductor pattern 120 is disposed on the substrate 110, the gate insulating layer 130 is disposed on the semiconductor pattern 120, the gate electrode G is disposed on the gate insulating layer 130, and the interlayer dielectric layer 140 is disposed on the gate electrode. On the G and gate insulating layer 130, the source electrode 152 is disposed on the interlayer dielectric layer 140 and is electrically connected to the semiconductor pattern 120 through the contact window 142 of the interlayer dielectric layer 140 and the contact window 132 of the gate insulating layer 130, and the drain electrode 154 The contact window 144 disposed on the interlayer dielectric layer 140 and the contact window 134 of the gate insulating layer 130 are electrically connected to the semiconductor pattern 120 through the contact window 144 of the interlayer dielectric layer 140. However, the present invention is not limited to this, and according to other embodiments, the thin film transistor T may also have other configurations.

In this embodiment, the material of the semiconductor pattern 120 is, for example, polysilicon. However, the present invention is not limited to this. In other embodiments, the material of the semiconductor pattern 120 may also be amorphous silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials, or other suitable materials, or contain Dopant in the above materials, or a combination of the above.

In this embodiment, the material of the gate electrode G, the source electrode 152 and/or the drain electrode 154 is, for example, metal. However, the present invention is not limited to this. In other embodiments, the material of the gate electrode G, the source electrode 152 and/or the drain electrode 154 may also be other conductive materials, such as alloys, nitrides of metal materials, and oxidation of metal materials. Metal materials, oxynitride of metal materials, or stacked layers of metal materials and other conductive materials.

The semiconductor substrate 10 includes an organic insulating layer 170 and is disposed on the base 110. For example, in this embodiment, the semiconductor substrate 10 may optionally include a barrier protection layer 160 disposed on the thin film transistor T, and the organic insulating layer 170 may be disposed on the barrier protection layer 160 and located on the thin film transistor T. Above, but the present invention is not limited to this.

For example, in this embodiment, the material of the organic insulating layer 170 may be polyimide, polyester, benzocyclobutene (BCB), polymethylmethacrylate (PMMA), polyethylene Phenol (4-vinylphenol), PVP, polyvinyl alcohol (PVA), polytetrafluoroethene (PTFE), hexamethyldisiloxane (HMDSO), or other suitable organic insulation material.

The semiconductor substrate 10 further includes an electrode 180 disposed on the organic insulating layer 170 and electrically connected to the thin film transistor T. For example, in this embodiment, the organic insulating layer 170 may have a contact window 172 that overlaps the opening 162 of the barrier protection layer 160, and the electrode 180 may be electrically connected to the thin film circuit through the contact window 172 of the organic insulating layer 170. Drain 154 of crystal T. However, the present invention is not limited to this. According to other embodiments, the electrode 180 may also be electrically connected to the thin film transistor T in other ways.

1, 2 and 3, the electrode 180 includes a first metal oxide layer 182, a metal layer 184 and a second metal oxide layer 186. The first metal oxide layer 182 is disposed on the organic insulating layer 170. The metal layer 184 is disposed on the first metal oxide layer 182. The second metal oxide layer 186 is disposed on the metal layer 184. In short, the first metal oxide 182, the metal layer 184, and the second metal oxide layer 186 are sequentially stacked on the organic insulating layer 170.

It is worth noting that the metal layer 184 covers the sidewall 182a of the first metal oxide layer 182, and the portion of the metal layer 184 beyond the first metal oxide layer 182 directly contacts the organic insulating layer 170. The edge 182e of the first metal oxide layer 182 is within the edge 184e of the metal layer 184, and the edge 184e of the metal layer 184 and the edge 182e of the first metal oxide layer 182 have a distance in a direction x parallel to the substrate 110 L1. In addition, the edge 186e of the second metal oxide layer 186 is within the edge 184e of the metal layer 184. The edge 186e of the second metal oxide layer 186 and the edge 184e of the metal layer 184 have a distance L2 in a direction x parallel to the substrate 110.

In this embodiment, 0.1≤(L2/L1)≤10. For example, in this embodiment, 0.1≤(L2/L1)>1. That is to say, in this embodiment, the edge 182e of the first metal oxide layer 182 is within the edge 186e of the second metal oxide layer 186, and the edge 186e of the second metal oxide layer 186 is on the substrate 110. The vertical projection is between a vertical projection of the edge 184e of the metal layer 184 on the substrate 110 and a vertical projection of the edge 182e of the first metal oxide layer 182 on the substrate 110, but the invention is not limited thereto.

In addition, referring to FIG. 2, in this embodiment, the metal layer 184 has a first portion 184-1 and a second portion 184-2. The first portion 184-1 is sandwiched between the first metal oxide layer 182 and the second portion 184-2. Between the metal oxide layer 186 and within the area of the first metal oxide layer 182 and the second metal oxide layer 186, the second portion 184-2 is in contact with the organic insulating layer 170 and is located between the first metal oxide layer 182 and the second metal oxide layer 186. The area of the second metal oxide layer 186 is not included; in particular, the thickness T2 of the second portion 184-2 is smaller than the thickness T1 of the first portion 184-1.

2 and 3, it is worth noting that the metal layer 184 covers the sidewall 182a of the first metal oxide layer 182 (marked in FIG. 2), and the metal layer 184 is in contact with the organic insulating layer 170. In other words, the metal layer 184 covers the first metal oxide layer 182. Since the adhesion between the metal layer 184 and the organic insulating layer 170 is good, the first metal oxide layer 182 will not be exposed by the metal layer 184 during the process of forming the electrode 180 and the subsequent processes, and it is not easy to cause problems. Part of the first metal oxide layer 182 is peeled off and caused a short circuit problem.

In addition, it is worth noting that the edge 186e of the second metal oxide layer 186 is within the edge 184e of the metal layer 184. That is to say, in the process of forming the second metal oxide layer 186, the second portion 184- of the metal oxide material layer (not shown) used to form the second metal oxide layer 186 is suspended from the metal layer 184 The upper part of 2 has been removed, and the short circuit problem caused by the peeling of the metal oxide material layer suspended above the second part 184-2 is not easy to occur.

1, in this embodiment, the semiconductor substrate 10 may also optionally include a pixel definition layer 190, an organic light emitting diode layer 200, a support 210, and an electrode 220. The pixel definition layer 190 is disposed on the organic insulating layer 170 and part of the electrode 180. The pixel definition layer 190 has an opening 192 overlapping the electrode 180. The organic light emitting diode layer 200 is disposed in the opening 192 of the pixel definition layer 190. The support 210 is disposed on the pixel definition layer 190. The electrode 220 is disposed on the organic light emitting diode layer 200.

FIG. 4 is an enlarged schematic diagram of a part of an electrode 180 according to another embodiment of the present invention. Fig. 4 corresponds to the area R of Fig. 1. The electrode 180 in FIG. 4 is similar to the electrode 180 in FIG. 2, the difference between the two is: in the embodiment of FIG. 4, the edge 186e of the second metal oxide layer 186 can also be at the edge 182e of the first metal oxide layer 182. In other words, the vertical projection of the edge 182e of the first metal oxide layer 182 on the substrate 110 can also be substantially overlapped with the edge 186e of the second metal oxide layer 186.

FIG. 5 is an enlarged schematic diagram of a part of an electrode 180 according to another embodiment of the present invention. FIG. 5 corresponds to the area R in FIG. 1. The electrode 180 in FIG. 5 is similar to the electrode 180 in FIG. 2. The difference between the two is: in the embodiment of FIG. 5, the edge 186e of the second metal oxide layer 186 may be within the edge 182e of the first metal oxide layer 182 ; That is to say, the second metal oxide layer 186 can be indented in the first metal oxide layer 182, and the vertical projection of the edge 182e of the first metal oxide layer 182 on the substrate 110 can also be located on the edge of the metal layer 184 Between the vertical projection of 184e on the substrate 110 and the vertical projection of the edge 186e of the second metal oxide layer 186 on the substrate 110.

In the foregoing embodiments, the electrode 180 is used as a pixel electrode of an organic light emitting diode display panel. However, the present invention is not limited to this. In other embodiments, the electrode 180 can also be used for other applications. For example, in one embodiment, the electrode 180 may also be used as an electrode electrically connected to a micro LED.

10: Semiconductor substrate 110: Base 120: Semiconductor pattern 130: gate insulation 132, 134: Contact window 140: Interlayer dielectric layer 142, 144: Contact window 152: Source 154: Dip pole 160: barrier protection layer 162: open 170: organic insulating layer 172: contact window 180: Electrode 182: first metal oxide layer 182a: side wall 182e: Edge 184: Metal layer 184e: Edge 184-1: The first part 184-2: The second part 186: second metal oxide layer 186e: Edge 190: Pixel Definition Layer 192: open 200: organic light-emitting diode layer 210: support 220: Electrode A-A’: Line segment G: Gate L1, L2: distance R: area T: Thin film transistor T1, T2: thickness x: direction

FIG. 1 is a schematic cross-sectional view of a semiconductor substrate 10 according to an embodiment of the invention. FIG. 2 is an enlarged schematic diagram of a part of the electrode 180 according to an embodiment of the present invention. 3 is a schematic top view of the first metal oxide layer 182, the metal layer 184, the second metal oxide layer 186, and the substrate 110 of the electrode 180 according to an embodiment of the present invention. FIG. 4 is an enlarged schematic diagram of a part of an electrode 180 according to another embodiment of the present invention. FIG. 5 is an enlarged schematic diagram of a part of an electrode 180 according to another embodiment of the present invention.

170: organic insulating layer

180: Electrode

182: first metal oxide layer

182a: side wall

182e: Edge

184: Metal layer

184e: Edge

184-1: The first part

184-2: The second part

186: second metal oxide layer

186e: Edge

190: Pixel Definition Layer

L1, L2: distance

R: area

T1, T2: thickness

x: direction

Claims (6)

A semiconductor substrate, including: A base A thin film transistor arranged on the substrate; An organic insulating layer disposed on the substrate; and An electrode disposed on the organic insulating layer and electrically connected to the thin film transistor, wherein the electrode includes: A first metal oxide layer disposed on the organic insulating layer; A metal layer disposed on the first metal oxide layer, covering a sidewall of the first metal oxide layer, and contacting the organic insulating layer; and A second metal oxide layer is disposed on the metal layer, wherein an edge of the second metal oxide layer is within an edge of the metal layer. The semiconductor substrate according to claim 1, wherein an edge of the first metal oxide layer is within the edge of the metal layer. The semiconductor substrate according to claim 1, wherein an edge of the first metal oxide layer is within the edge of the second metal oxide layer. The semiconductor substrate according to claim 1, wherein a vertical projection of the edge of the second metal oxide layer on the substrate is located between a vertical projection of the edge of the metal layer on the substrate and the first An edge of a metal oxide layer is between a vertical projection on the substrate. The semiconductor substrate according to claim 1, wherein the edge of the metal layer and an edge of the first metal oxide layer have a distance L1 in a direction parallel to the substrate, and the second metal oxide An edge of the layer and the edge of the metal layer have a distance L2 in the direction parallel to the substrate, and 0.1≤(L2/L1)≤10. The semiconductor substrate according to claim 1, wherein the metal layer has a first part and a second part, and the first part is sandwiched between the first metal oxide layer and the second metal oxide layer Between and within the area of the first metal oxide layer and the second metal oxide layer, the second part is in contact with the organic insulating layer and is located between the first metal oxide layer and the second metal oxide layer , And the thickness of the second part is smaller than the thickness of the first part.

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