TWI721736B - Semiconductor substrate - Google Patents
Semiconductor substrate Download PDFInfo
- Publication number
- TWI721736B TWI721736B TW108148085A TW108148085A TWI721736B TW I721736 B TWI721736 B TW I721736B TW 108148085 A TW108148085 A TW 108148085A TW 108148085 A TW108148085 A TW 108148085A TW I721736 B TWI721736 B TW I721736B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- metal oxide
- oxide layer
- edge
- metal
- Prior art date
Links
Images
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
本發明是有關於一種基板,且特別是有關於一種半導體基板。The present invention relates to a substrate, and particularly relates to a semiconductor substrate.
平面顯示器具有輕薄、體積小低等優點,因此,已廣泛被應用在日常生活中。平面顯示器包括畫素陣列基板。畫素陣列基板具有多個薄膜電晶體、電性連接至多個薄膜電晶體的多個畫素電極以及顯示介質。一個畫素電極包括依序堆疊的多個導電圖案。一般而言,會使用同一個光罩製作一個畫素電極的多個導電圖案,且多個導電圖案的至少兩者會於同一道製程中被蝕刻。然而,夾設於中間之導電圖案的材質與位於上側及下側的多個導電圖案的材質不同,且夾設於中間之導電圖案的材質的蝕刻速率較快。因此,所製作出的畫素電極在其邊界處易出現懸空及/或鬆散的結構,懸空及/或鬆散的結構很容易剝離而四處散落,形成污染粒子的來源。導電的污染粒子可能會形成畫素電極與其它電極之間的導電路徑,造成短路,使得平面顯示器上出現壞點。Flat-panel displays have the advantages of lightness, thinness, small size and low volume. Therefore, they have been widely used in daily life. The flat panel display includes a pixel array substrate. The pixel array substrate has a plurality of thin film transistors, a plurality of pixel electrodes electrically connected to the plurality of thin film transistors, and a display medium. One pixel electrode includes a plurality of conductive patterns stacked in sequence. Generally, the same photomask is used to make a plurality of conductive patterns of a pixel electrode, and at least two of the plurality of conductive patterns are etched in the same process. However, the material of the conductive pattern sandwiched in the middle is different from the material of the plurality of conductive patterns located on the upper and lower sides, and the material of the conductive pattern sandwiched in the middle has a faster etching rate. Therefore, the fabricated pixel electrode is prone to dangling and/or loose structures at its boundaries, and the dangling and/or loose structures are easily peeled off and scattered around, forming a source of pollution particles. Conductive pollution particles may form a conductive path between the pixel electrode and other electrodes, causing short circuits and causing dead spots on the flat panel display.
本發明提供一種半導體基板,其電極的構造穩固,不易剝離而形成污染粒子。The invention provides a semiconductor substrate, the electrode structure of which is stable and not easy to peel off to form pollutant particles.
本發明的半導體基板,包括基底、薄膜電晶體、有機絕緣層及電極。薄膜電晶體設置於基底上。有機絕緣層設置於基底上。電極設置於有機絕緣層上且電性連接至薄膜電晶體。電極包括第一金屬氧化物層、金屬層及第二金屬氧化物層。第一金屬氧化物層設置於有機絕緣層上。金屬層設置於第一金屬氧化物層上,覆蓋第一金屬氧化物層的側壁,且接觸於有機絕緣層。第二金屬氧化物層設置於金屬層上。第二金屬氧化物層的邊緣在金屬層的邊緣以內。The semiconductor substrate of the present invention includes a substrate, a thin film transistor, an organic insulating layer and an electrode. The thin film transistor is arranged on the substrate. The organic insulating layer is disposed on the substrate. The electrode is arranged on the organic insulating layer and is electrically connected to the thin film transistor. The electrode includes a first metal oxide layer, a metal layer, and a second metal oxide layer. The first metal oxide layer is disposed on the organic insulating layer. The metal layer is disposed on the first metal oxide layer, covers the sidewall of the first metal oxide layer, and is in contact with the organic insulating layer. The second metal oxide layer is disposed on the metal layer. The edge of the second metal oxide layer is within the edge of the metal layer.
在本發明的一實施例中,上述的第一金屬氧化物層的邊緣在金屬層的邊緣以內。In an embodiment of the present invention, the edge of the above-mentioned first metal oxide layer is within the edge of the metal layer.
在本發明的一實施例中,上述的第一金屬氧化物層的邊緣在第二金屬氧化物層的邊緣以內。In an embodiment of the present invention, the edge of the above-mentioned first metal oxide layer is within the edge of the second metal oxide layer.
在本發明的一實施例中,上述的第二金屬氧化物層的邊緣於基底上的垂直投影位於金屬層的邊緣於基底上的垂直投影與第一金屬氧化物層的邊緣於基底上的垂直投影之間。In an embodiment of the present invention, the above-mentioned vertical projection of the edge of the second metal oxide layer on the substrate is located between the vertical projection of the edge of the metal layer on the substrate and the vertical projection of the edge of the first metal oxide layer on the substrate. Between projections.
在本發明的一實施例中,上述的金屬層的邊緣與第一金屬氧化物層的邊緣在平行於基底的方向上具有距離L1,第二金屬氧化物層的邊緣與金屬層的邊緣在平行於基底的方向上具有一距離L2,且0.1 ≤(L2/L1)≤ 10。In an embodiment of the present invention, the edge of the metal layer and the edge of the first metal oxide layer have a distance L1 in a direction parallel to the substrate, and the edge of the second metal oxide layer is parallel to the edge of the metal layer. There is a distance L2 in the direction of the base, and 0.1 ≤ (L2/L1) ≤ 10.
在本發明的一實施例中,上述的金屬層具有第一部及第二部,第一部夾設於第一金屬氧化物層與第二金屬氧化物層之間且位於第一金屬氧化物層和第二金屬氧化物層的面積以內,第二部接觸於有機絕緣層且位於第一金屬氧化物層及第二金屬氧化物層的面積以外,且第二部的厚度小於第一部的厚度。In an embodiment of the present invention, the above-mentioned metal layer has a first part and a second part, and the first part is sandwiched between the first metal oxide layer and the second metal oxide layer and is located in the first metal oxide layer. Within the area of the first metal oxide layer and the second metal oxide layer, the second part is in contact with the organic insulating layer and is located outside the area of the first metal oxide layer and the second metal oxide layer, and the thickness of the second part is smaller than that of the first part thickness.
現將詳細地參考本發明的示範性實施例,示範性實施例的實例說明於附圖中。只要有可能,相同元件符號在圖式和描述中用來表示相同或相似部分。Reference will now be made in detail to the exemplary embodiments of the present invention, and examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and descriptions to indicate the same or similar parts.
應當理解,當諸如層、膜、區域或基板的元件被稱為在另一元件“上”或“連接到”另一元件時,其可以直接在另一元件上或與另一元件連接,或者中間元件可以也存在。相反,當元件被稱為“直接在另一元件上”或“直接連接到”另一元件時,不存在中間元件。如本文所使用的,“連接”可以指物理及/或電性連接。再者,“電性連接”或“耦合”可以是二元件間存在其它元件。It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connection" can refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that there are other elements between two elements.
本文使用的“約”、“近似”、或“實質上”包括所述值和在本領域普通技術人員確定的特定值的可接受的偏差範圍內的平均值,考慮到所討論的測量和與測量相關的誤差的特定數量(即,測量系統的限制)。例如,“約”可以表示在所述值的一個或多個標準偏差內,或±30%、±20%、±10%、±5%內。再者,本文使用的“約”、“近似”或“實質上”可依光學性質、蝕刻性質或其它性質,來選擇較可接受的偏差範圍或標準偏差,而可不用一個標準偏差適用全部性質。As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within the acceptable deviation range of the specific value determined by a person of ordinary skill in the art, taking into account the measurement in question and the The specific amount of measurement-related error (ie, the limitation of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "about", "approximately" or "substantially" as used herein can be based on optical properties, etching properties or other properties to select a more acceptable range of deviation or standard deviation, and not one standard deviation can be applied to all properties .
除非另有定義,本文使用的所有術語(包括技術和科學術語)具有與本發明所屬領域的普通技術人員通常理解的相同的含義。將進一步理解的是,諸如在通常使用的字典中定義的那些術語應當被解釋為具有與它們在相關技術和本發明的上下文中的含義一致的含義,並且將不被解釋為理想化的或過度正式的意義,除非本文中明確地這樣定義。Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of related technologies and the present invention, and will not be interpreted as idealized or excessive The formal meaning, unless explicitly defined as such in this article.
圖1為本發明一實施例之半導體基板10的剖面示意圖。FIG. 1 is a schematic cross-sectional view of a
圖2為本發明一實施例之電極180局部的放大示意圖。圖2對應圖1的區域R。FIG. 2 is an enlarged schematic diagram of a part of the
圖3為本發明一實施例之電極180的第一金屬氧化物層182、金屬層184、第二金屬氧化物層186及基底110的上視示意圖。圖2對應圖3的線段A-A’。3 is a schematic top view of the first
請參照圖1,半導體基板10包括基底110。舉例而言,在本實施例中,基底110的材質可以是玻璃、石英、有機聚合物、或不透光/反射材料(例如:晶圓、陶瓷等)、或是其它可適用的材料。Please refer to FIG. 1, the
半導體基板10包括薄膜電晶體T,設置於基底110上。薄膜電晶體T包括半導體圖案120、閘絕緣層130、閘極G、源極152與汲極154,其中閘絕緣層130設置於閘極G與半導體圖案120之間,且源極152與汲極154分別與半導體圖案120的不同兩區電性連接。The
舉例而言,在本實施例中,半導體圖案120設置於基底110上,閘絕緣層130設置於半導體圖案120上,閘極G設置於閘絕緣層130上,層間介電層140設置於閘極G及閘絕緣層130上,源極152設置於層間介電層140上且透過層間介電層140的接觸窗142及閘絕緣層130的接觸窗132電性連接至半導體圖案120,汲極154設置於層間介電層140上且透過層間介電層140的接觸窗144及閘絕緣層130的接觸窗134電性連接至半導體圖案120。然而,本發明不限於此,根據其它實施例,薄膜電晶體T也可以是其它構造。For example, in this embodiment, the
在本實施例中,半導體圖案120的材質例如是多晶矽。然而,本發明不限於此,在其它實施例中,半導體圖案120的材質也可以是非晶矽、微晶矽、單晶矽、有機半導體材料、氧化物半導體材料、或其它合適的材料、或含有摻雜物(dopant)於上述材料中、或上述之組合。In this embodiment, the material of the
在本實施例中,閘極G、源極152及/或汲極154的材質例如是金屬。然而,本發明不限於此,在其它實施例中,閘極G、源極152及/或汲極154的材質也可以是其他導電材料,例如:合金、金屬材料的氮化物、金屬材料的氧化物、金屬材料的氮氧化物、或是金屬材料與其它導電材料的堆疊層。In this embodiment, the material of the gate electrode G, the
半導體基板10包括有機絕緣層170,設置於基底110上。舉例而言,在本實施例中,半導體基板10可選擇性地包括設置於薄膜電晶體T上的屏障保護層160,有機絕緣層170可設置於屏障保護層160上而位於薄膜電晶體T的上方,但本發明不以此為限。The
舉例而言,在本實施例中,有機絕緣層170的材質可以是聚亞醯胺、聚酯、苯環丁烯(benzocyclobutene,BCB)、聚甲基丙烯酸甲酯(polymethylmethacrylate,PMMA)、聚乙烯苯酚(poly(4-vinylphenol),PVP)、聚乙烯醇(polyvinyl alcohol,PVA)、聚四氟乙烯(polytetrafluoroethene,PTFE)、六甲基二矽氧 (hexamethyldisiloxane,HMDSO)、或其它適合之有機絕緣材料。For example, in this embodiment, the material of the
半導體基板10還包括電極180,設置於有機絕緣層170上,且電性連接至薄膜電晶體T。舉例而言,在本實施例中,有機絕緣層170可具有與屏障保護層160之開口162重疊的一接觸窗172,而電極180可透過有機絕緣層170的接觸窗172電性連接至薄膜電晶體T的汲極154。然而,本發明不限於此,根據其他實施例,電極180也可用其它方式與薄膜電晶體T電性連接。The
請參照圖1、圖2及圖3,電極180包括第一金屬氧化物層182、金屬層184及第二金屬氧化物層186。第一金屬氧化物層182設置於有機絕緣層170上。金屬層184設置於第一金屬氧化物層182上。第二金屬氧化物層186設置於金屬層184上。簡言之,第一金屬氧化物182、金屬層184及第二金屬氧化物層186是依序堆疊於有機絕緣層170上。1, 2 and 3, the
值得注意的是,金屬層184覆蓋第一金屬氧化物層182的側壁182a,且金屬層184之超出第一金屬氧化物層182的部分直接接觸於有機絕緣層170。第一金屬氧化物層182的邊緣182e在金屬層184的邊緣184e以內,且金屬層184的邊緣184e與第一金屬氧化物層182的邊緣182e在平行於基底110的一方向x上具有一距離L1。此外,第二金屬氧化物層186的邊緣186e在金屬層184的邊緣184e以內。第二金屬氧化物層186的邊緣186e與金屬層184的邊緣184e在平行於基底110的一方向x上具有一距離L2。It is worth noting that the
在本實施例中,0.1≤(L2/L1)≤ 10。舉例而言,在本實施例中,0.1 ≤(L2/L1)> 1。也就是說,在本實施例中,第一金屬氧化物層182的邊緣182e在第二金屬氧化物層186的邊緣186e以內,且第二金屬氧化物層186的邊緣186e於基底110上的一垂直投影位於金屬層184的邊緣184e於基底110上的一垂直投影與第一金屬氧化物層182的邊緣182e於基底110上的一垂直投影之間,但本發明不以此為限。In this embodiment, 0.1≤(L2/L1)≤10. For example, in this embodiment, 0.1≤(L2/L1)>1. That is to say, in this embodiment, the
此外,請參照圖2,在本實施例中,金屬層184具有第一部184-1及第二部184-2,第一部184-1夾設於第一金屬氧化物層182與第二金屬氧化物層186之間且位於第一金屬氧化物層182及第二金屬氧化物層186的面積以內,第二部184-2接觸於有機絕緣層170且位於第一金屬氧化物層182及第二金屬氧化物層186的面積以外;特別是,第二部184-2的厚度T2小於第一部184-1的厚度T1。In addition, referring to FIG. 2, in this embodiment, the
請參照圖2及圖3,值得注意的是,金屬層184覆蓋第一金屬氧化物層182的側壁182a(標示於圖2),且金屬層184接觸於有機絕緣層170。也就是說,金屬層184包覆第一金屬氧化物層182。由於金屬層184與有機絕緣層170的黏著(adhesion)佳,因此,在形成電極180的過程及其後續的製程中,第一金屬氧化物層182不會被金屬層184裸露,而不易發生因部分之第一金屬氧化物層182剝落所造成的短路問題。2 and 3, it is worth noting that the
另外,值得注意的是,第二金屬氧化物層186的邊緣186e是在金屬層184的邊緣184e以內。也就是說,在形成第二金屬氧化物層186的過程中,用以形成第二金屬氧化物層186之金屬氧化物材料層(未繪示)之懸在金屬層184之第二部184-2上方的一部分已被去除,而不易發生因懸在第二部184-2上方之所述金屬氧化物材料層剝落所造成的短路問題。In addition, it is worth noting that the
請參照圖1,在本實施例中,半導體基板10還可選擇性地包括畫素定義層190、有機發光二極體層200、支撐物210及電極220。畫素定義層190設置於有機絕緣層170及部分的電極180上。畫素定義層190具有與電極180重疊的開口192。有機發光二極體層200設置於畫素定義層190的開口192中。支撐物210設置於畫素定義層190上。電極220設置於有機發光二極體層200上。1, in this embodiment, the
圖4為本發明另一實施例之電極180局部的放大示意圖。圖4對應圖1的區域R。圖4的電極180與圖2的電極180類似,兩者的差異在於:在圖4的實施例中,第二金屬氧化物層186的邊緣186e也可以在第一金屬氧化物層182的邊緣182e上;也就是說,第一金屬氧化物層182之邊緣182e於基底110上的垂直投影也可以和第二金屬氧化物層186之邊緣186e可實質上重疊。FIG. 4 is an enlarged schematic diagram of a part of an
圖5為本發明又一實施例之電極180局部的放大示意圖。圖5對應圖1的區域R。圖5的電極180與圖2的電極180類似,兩者的差異在於:在圖5的實施例中,第二金屬氧化物層186的邊緣186e可以在第一金屬氧化物層182的邊緣182e以內;也就是說,第二金屬氧化物層186可以內縮於第一金屬氧化物層182,而第一金屬氧化物層182之邊緣182e於基底110上的垂直投影也可以位於金屬層184之邊緣184e於基底110上的垂直投影與第二金屬氧化物層186之邊緣186e於基底110上的垂直投影之間。FIG. 5 is an enlarged schematic diagram of a part of an
在前述的各實施例中,電極180是做為有機發光二極體顯示面板的畫素電極使用。然而,本發明不限於此,在其它實施例中,電極180也可做其它應用。舉例而言,在一實施例中,電極180也可以做為與微型發光二極體元件(micro LED)電性連接的電極使用。In the foregoing embodiments, the
10:半導體基板
110:基底
120:半導體圖案
130:閘絕緣層
132、134:接觸窗
140:層間介電層
142、144:接觸窗
152:源極
154:汲極
160:屏障保護層
162:開口
170:有機絕緣層
172:接觸窗
180:電極
182:第一金屬氧化物層
182a:側壁
182e:邊緣
184:金屬層
184e:邊緣
184-1:第一部
184-2:第二部
186:第二金屬氧化物層
186e:邊緣
190:畫素定義層
192:開口
200:有機發光二極體層
210:支撐物
220:電極
A-A’:線段
G:閘極
L1、L2:距離
R:區域
T:薄膜電晶體
T1、T2:厚度
x:方向10: Semiconductor substrate
110: Base
120: Semiconductor pattern
130:
圖1為本發明一實施例之半導體基板10的剖面示意圖。
圖2為本發明一實施例之電極180局部的放大示意圖。
圖3為本發明一實施例之電極180的第一金屬氧化物層182、金屬層184、第二金屬氧化物層186及基底110的上視示意圖。
圖4為本發明另一實施例之電極180局部的放大示意圖。
圖5為本發明另一實施例之電極180局部的放大示意圖。
FIG. 1 is a schematic cross-sectional view of a
170:有機絕緣層 170: organic insulating layer
180:電極 180: Electrode
182:第一金屬氧化物層 182: first metal oxide layer
182a:側壁 182a: side wall
182e:邊緣 182e: Edge
184:金屬層 184: Metal layer
184e:邊緣 184e: Edge
184-1:第一部 184-1: The first part
184-2:第二部 184-2: The second part
186:第二金屬氧化物層 186: second metal oxide layer
186e:邊緣 186e: Edge
190:畫素定義層 190: Pixel Definition Layer
L1、L2:距離 L1, L2: distance
R:區域 R: area
T1、T2:厚度 T1, T2: thickness
x:方向 x: direction
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW108148085A TWI721736B (en) | 2019-12-27 | 2019-12-27 | Semiconductor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW108148085A TWI721736B (en) | 2019-12-27 | 2019-12-27 | Semiconductor substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI721736B true TWI721736B (en) | 2021-03-11 |
TW202125861A TW202125861A (en) | 2021-07-01 |
Family
ID=76036007
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW108148085A TWI721736B (en) | 2019-12-27 | 2019-12-27 | Semiconductor substrate |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI721736B (en) |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1575063A (en) * | 2003-05-28 | 2005-02-02 | 索尼株式会社 | Laminated structure, and manufacturing method, display device, and display unit employing same |
TW200830547A (en) * | 2007-01-04 | 2008-07-16 | Samsung Sdi Co Ltd | Organic light emitting diode display device and method of fabricating the same |
KR100862555B1 (en) * | 2007-11-27 | 2008-10-09 | 엘지전자 주식회사 | Organic light emitting display |
CN101499516A (en) * | 2003-03-26 | 2009-08-05 | 索尼株式会社 | Light-emitting device, method of manufacturing the same, and display unit |
US20140035456A1 (en) * | 2012-08-01 | 2014-02-06 | Semiconductor Energy Laboratory Co., Ltd. | Display Device |
CN106206648A (en) * | 2015-05-28 | 2016-12-07 | 乐金显示有限公司 | Organic light-emitting display device and manufacture method thereof |
CN107026189A (en) * | 2016-02-02 | 2017-08-08 | 株式会社日本显示器 | Display device and its manufacture method |
-
2019
- 2019-12-27 TW TW108148085A patent/TWI721736B/en active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101499516A (en) * | 2003-03-26 | 2009-08-05 | 索尼株式会社 | Light-emitting device, method of manufacturing the same, and display unit |
CN1575063A (en) * | 2003-05-28 | 2005-02-02 | 索尼株式会社 | Laminated structure, and manufacturing method, display device, and display unit employing same |
TW200830547A (en) * | 2007-01-04 | 2008-07-16 | Samsung Sdi Co Ltd | Organic light emitting diode display device and method of fabricating the same |
KR100862555B1 (en) * | 2007-11-27 | 2008-10-09 | 엘지전자 주식회사 | Organic light emitting display |
US20140035456A1 (en) * | 2012-08-01 | 2014-02-06 | Semiconductor Energy Laboratory Co., Ltd. | Display Device |
CN106206648A (en) * | 2015-05-28 | 2016-12-07 | 乐金显示有限公司 | Organic light-emitting display device and manufacture method thereof |
CN107026189A (en) * | 2016-02-02 | 2017-08-08 | 株式会社日本显示器 | Display device and its manufacture method |
Also Published As
Publication number | Publication date |
---|---|
TW202125861A (en) | 2021-07-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20180145094A1 (en) | Display device | |
US9312353B2 (en) | Double gate type thin film transistor and organic light emitting diode display including the same | |
US10290822B2 (en) | Thin film transistor including recessed gate insulation layer and its manufacturing method, array substrate, and display device | |
US10957718B2 (en) | Pixel structure | |
TW201533891A (en) | Display panel and display device | |
US9748397B2 (en) | Thin film transistor substrate and display device comprising the same | |
US9806106B2 (en) | Thin film transistor array substrate and manufacture method thereof | |
TWI555183B (en) | Thin film transistor and pixel structure | |
CN103972299A (en) | Thin film transistor, manufacturing method of thin film transistor, display substrate and display device | |
CN111969132B (en) | Display substrate, manufacturing method thereof, display panel and display device | |
US9711602B2 (en) | Method of making thin film transistor array and source/drain contact via-interconnect structures formed thereby | |
US8169428B2 (en) | Display substrate, method of manufacturing the same and display device having the same | |
TWI721736B (en) | Semiconductor substrate | |
TWI703371B (en) | Display panel | |
TWI690838B (en) | Pixel array substrate | |
CN108663862B (en) | Display panel | |
TW202123471A (en) | Active device substrate and manufacturing method thereof | |
KR20170112582A (en) | Flexible color filter and flexible liquid crystal display | |
TW202036720A (en) | Semiconductor structure and manufacturing method thereof | |
TWI774532B (en) | Semiconductor apparatus | |
TWI691762B (en) | Pixel structure | |
WO2019071824A1 (en) | Display panel and fabrication method therefor | |
US20110156041A1 (en) | Polymer substrate and method of forming the same and display device including the polymer substrate and method of manufacturing the display device | |
TWI688888B (en) | Display apparatus | |
TWI605284B (en) | Pixel structure |