CN108663862B

CN108663862B - Display panel

Info

Publication number: CN108663862B
Application number: CN201810457553.8A
Authority: CN
Inventors: 李冠锋; 王惠洁
Original assignee: Innolux Display Corp
Current assignee: Innolux Corp
Priority date: 2014-02-25
Filing date: 2014-02-25
Publication date: 2020-02-07
Anticipated expiration: 2034-02-25
Also published as: CN104865761B; CN104865761A; CN108663862A

Abstract

The invention provides a display panel, which comprises a substrate, a scanning line, a data line, a thin film transistor, a first insulating layer, a planarization layer and a pixel electrode layer. The scanning line is arranged on the substrate and is provided with a concave part. The data lines are arranged on the substrate and are staggered with the scanning lines. The thin film transistor is arranged on the substrate and is provided with a grid electrode and a drain electrode, the grid electrode is electrically connected with the scanning line, and the drain electrode is electrically connected with the data line. And a first insulating layer disposed on the drain electrode and exposing a portion of the drain electrode, wherein the recess of the scan line is disposed corresponding to the exposed portion of the drain electrode. A planarization layer is disposed on the first insulating layer. The pixel electrode layer is arranged on the planarization layer and is electrically connected with the exposed part of the drain electrode.

Description

Display panel

This application is a division of the chinese patent application entitled "display panel and display device" with application number 201410064232.3, filed on 25/2/2014

Technical Field

The present invention relates to a display panel and a display device including the same.

Background

With the progress of technology, flat panel display devices have been widely used in various fields, especially liquid crystal display devices, and have superior characteristics of being light and thin, low power consumption and being non-radiative, so that they have gradually replaced conventional cathode ray tube display devices and have been applied to various electronic products, such as mobile phones, portable multimedia devices, notebook computers, liquid crystal televisions, liquid crystal screens, and the like.

A conventional liquid crystal display device includes a thin film transistor substrate having a thin film transistor and a pixel electrode disposed on a substrate. In the process, a through hole is arranged above the drain electrode of the thin film transistor in an etching mode, and a transparent conducting layer is arranged on the inner wall of the through hole to electrically connect the drain electrode of the thin film transistor with the pixel electrode. In addition, the grid electrode of the thin film transistor is electrically connected with a scanning line, and the source electrode of the thin film transistor is electrically connected with a data line. When a scanning signal is input to the grid electrode of the thin film transistor by the scanning line, the data voltage of the data line can be input to the pixel electrode through the source electrode, the drain electrode and the transparent conducting layer by controlling the thin film transistor, thereby controlling the rotation direction of the liquid crystal to display images.

In addition, the existing polysilicon thin film transistor has about 100cm²The mobility of the order of/Vs, however, since it is required to be produced at a temperature of 450 ℃ or higher, it can be formed only on a substrate having high heat resistance, and is not suitable for application to a large-area or flexible substrate. In addition, although the conventional amorphous silicon thin film transistor can be manufactured at a low temperature of about 300 ℃, the amorphous silicon thin film transistor has a thickness of about 1cm²The mobility of the order of/Vs cannot be applied to a high-definition panel. In contrast, metal oxide semiconductors, such as Indium Gallium Zinc Oxide (IGZO), have been proposed as channel layers of thin film transistors.

Although the indium gallium zinc oxide thin film transistor has the advantage of mobility superior to that of an amorphous silicon thin film transistor, and the process of the transistor is simpler than that of a crystalline silicon thin film transistor, the indium gallium zinc oxide is very sensitive to light, water and oxygen.

In order to protect the channel layer of the tft, a protective layer (made of silicon dioxide, for example) is disposed on the channel layer of the mos to protect the channel layer. As shown in fig. 1A, the electrical characteristic curve of the thin film transistor is schematically shown after a protective layer is disposed on the mos channel layer. Although a passivation layer is disposed to protect the channel layer, after a certain period of time (or after a heat treatment), as shown in fig. 1B, the characteristic curve of the tft still deviates from the original curve of fig. 1A, so that the performance of the tft is reduced, and the display quality of the display panel and the display device is affected.

Therefore, it is an important subject to provide a display panel and a display device, which have stable tft performance and stable display quality.

Disclosure of Invention

In view of the foregoing, it is an object of the present invention to provide a display panel and a display device having stable display quality by providing a stable thin film transistor performance.

The technical scheme of the invention is as follows: a display panel is provided, which includes a substrate, a scan line, a data line, a thin film transistor, a first insulating layer, a planarization layer, and a pixel electrode layer. The scanning line is arranged on the substrate and is provided with a concave part. The data lines are arranged on the substrate and are staggered with the scanning lines. The thin film transistor is arranged on the substrate and is provided with a grid electrode and a drain electrode, the grid electrode is electrically connected with the scanning line, and the drain electrode is electrically connected with the data line. And a first insulating layer disposed on the drain electrode and exposing a portion of the drain electrode, wherein the recess of the scan line is disposed corresponding to the exposed portion of the drain electrode. A planarization layer is disposed on the first insulating layer. The pixel electrode layer is arranged on the planarization layer and is electrically connected with the exposed part of the drain electrode.

Drawings

Fig. 1A is a schematic diagram illustrating an electrical characteristic curve of a thin film transistor when a protective layer is disposed on a channel layer of the thin film transistor in a conventional thin film transistor substrate.

Fig. 1B is a schematic diagram of an electrical characteristic curve of the tft substrate of fig. 1A after a certain period of time.

Fig. 2A is a schematic top view of a thin film transistor substrate according to the present invention.

Fig. 2B is an enlarged schematic view of a region C of fig. 2A.

FIG. 2C is a cross-sectional view taken along section line B-B of FIG. 2B.

Fig. 2D is a partially enlarged schematic view of fig. 2C.

Fig. 2E is a schematic cross-sectional view of a thin film transistor substrate according to another embodiment.

Fig. 3A to 3D are schematic diagrams illustrating a method for fabricating the through hole of fig. 2C.

FIG. 4 is a diagram of data lines and scan lines relative to each other at an overlap.

Fig. 5A is a schematic view of an electrical characteristic curve of a thin film transistor when a first sublayer and a second sublayer are disposed on a channel layer of the thin film transistor in a thin film transistor substrate according to a preferred embodiment of the invention.

Fig. 5B is a schematic diagram of electrical characteristics of the tft substrate of fig. 5A after a certain period of time.

Fig. 6 is a schematic cross-sectional view of a display panel according to a preferred embodiment of the invention.

Fig. 7 is a schematic cross-sectional view of a display device according to a preferred embodiment of the invention.

Description of the main elements

1. 1 a: thin film transistor substrate 11: gate dielectric layer

12: channel layer 13: a first insulating layer

131: first sublayer 132: second sub-layer

14: the planarization layer 15: a second insulating layer

16: pixel electrode layer 18: common electrode layer

2: display panel 3: display device

A: an alignment film B: backlight module

B-B: section line BM: black matrix layer

C: and (3) area D: drain electrode

E: electrode layer ES: etch stop layer

F: a color filter G: grid electrode

L: display layer O: at the overlapping position

O1: first opening O2: second opening

P1: first side wall P2: second side wall

S: source S1: substrate

S2: the counter substrate T: thin film transistor

U: concave portion V1: first through hole

V2: second through hole w 1: first width

w 2: second width w 3: distance between two adjacent plates

Detailed Description

Hereinafter, a display panel and a display device according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings, in which like elements will be described with like reference numerals.

The display panel of the preferred embodiment of the present invention is an active matrix (active matrix) liquid crystal display panel, and includes a thin film transistor substrate 1, and the structure of the thin film transistor substrate 1 will be described in detail below.

Referring to fig. 2A to 2D, fig. 2A is a schematic top view of the thin film transistor substrate 1, fig. 2B is an enlarged schematic view of a region C of fig. 2A, fig. 2C is a cross-sectional view taken along a section line B-B of fig. 2B, and fig. 2D is a partially enlarged schematic view of fig. 2C. It should be noted that, for convenience of description, the dimensional relationships (ratios) between the heights and the widths of the elements shown in fig. 2A to 2D are only schematic and do not represent actual dimensional relationships.

As shown in fig. 2A, the tft substrate 1 may have a plurality of scan lines, a plurality of data lines and a plurality of pixels (fig. 2A only shows two scan lines and four data lines). The scan lines and the data lines may be arranged in an interlaced manner to form the pixel arrays. When the scanning lines receive a scanning signal, the scanning lines can be respectively conducted, and a data signal corresponding to each row of pixels is transmitted to the pixels through the data lines, so that the display panel can display pictures. In FIG. 2A, the data lines are shown as cross-hatching, but in other arrangements, the data lines can be straight or have other shapes. In addition, the tft substrate 1 may further include a black matrix layer BM disposed on the scan lines for shielding the scan lines and preventing light leakage of the pixels. Of course, the black matrix layer BM may be provided on a counter substrate of the liquid crystal display panel. Here, the black matrix layer BM is disposed on the thin film transistor substrate 1 as an example.

As shown in fig. 2C, the tft substrate 1 includes a substrate S1, a tft T, a first insulating layer 13 (shown in fig. 2D), a planarization layer 14, a second insulating layer 15, a pixel electrode layer 16, and a common electrode layer 18.

The thin film transistor T is disposed on the substrate S1. In practice, the substrate S1 may be a transparent material for transmissive display devices, such as glass, quartz or the like, plastic, rubber, fiberglass or other polymer material, preferably a borate alkali-free glass substrate. The substrate S1 may also be an opaque material for self-emissive or reflective display devices, such as metal-glass fiber composite panels, metal-ceramic composite panels.

The thin film transistor T of the present embodiment has a gate G, a gate dielectric layer 11, a channel layer 12, a source S and a drain D. The gate G is disposed on the substrate S1, and the material of the gate G may be a single-layer or multi-layer structure made of metal (e.g., aluminum, copper, silver, molybdenum, or titanium) or an alloy thereof. Some of the conductive lines for transmitting driving signals may be electrically connected to each other, such as scan lines, using the same process structure as the gate G. The gate dielectric layer 11 is disposed on the gate G, and the gate dielectric layer 11 may be an organic material such as an organosilicone compound, or an inorganic material such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, hafnium oxide, or a multi-layer structure thereof. The gate dielectric layer 11 is required to completely cover the gate G, and may optionally partially or completely cover the substrate S1.

The channel layer 12 is disposed on the gate dielectric layer 11 at a position opposite to the gate G. In practice, the channel layer 12 may comprise, for example, an oxide semiconductor. The Oxide semiconductor includes an Oxide, and the Oxide includes Indium, Gallium, Zinc, tin or one of them, such as Indium Gallium Zinc Oxide (IGZO).

The source S and the drain D are respectively disposed on the channel layer 12, and the source S and the drain D are respectively in contact with the channel layer 12, and when the channel layer 12 of the thin film transistor T is not turned on, the source S and the drain D are electrically separated. The source S and the drain D may be a single-layer or multi-layer structure made of metal (e.g., aluminum, copper, silver, molybdenum, or titanium) or an alloy thereof. In addition, a portion of the conductive lines for transmitting driving signals may use the same process structure as the source S and the drain D, such as data lines.

It should be noted that the source S and the drain D of the thin film transistor T of the present embodiment are disposed on an etch stop layer ES, and one end of the source S and one end of the drain D may respectively contact the channel layer 12 from an opening of the etch stop layer ES. The etch stop layer ES may be an organic material such as an organosilicone compound, or a single-layer inorganic material such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, hafnium oxide, or a multi-layer structure of a combination thereof, but is not limited thereto. However, in other embodiments, as shown in fig. 2E, the source S and the drain D may be directly disposed on the channel layer 12 without the etching stop layer ES.

In addition, referring to fig. 2B to 2D, the first insulating layer 13 has a first sub-layer 131 and a second sub-layer 132, and the first sub-layer 131 and the second sub-layer 132 are sequentially disposed on the drain D and at least partially cover the drain D. Herein, the first sub-layer 131 is disposed on the drain D and has a first opening O1 with a first width w1, and the second sub-layer 132 has a second opening O2 with a second width w2 located on the first opening O1. The first opening O1 and the second opening O2 form a first through hole V1, and the second width w2 is greater than the first width w 1. In other words, since the second opening O2 of the second sub-layer 132 is larger than the first opening O1 of the first sub-layer 131, the first via V1 of the first insulating layer 13 (the first sub-layer 131 and the second sub-layer 132) is stepped.

The first sub-layer 131 and the second sub-layer 132 may use a deposition rate, for example, less thanIs formed by the thickness of (a). The material of the first sub-layer 131 may include silicon oxide (SiOx) or silicon nitride (SiNx). This example is silicon dioxide (SiO)₂) For example, the thickness may be in the rangeTo 3000 angstroms

Preferably, for example, it is

In addition, the material of the second sub-layer 132 may include silicon nitride or aluminum oxide (AlxOx). The present embodiment is exemplified by silicon nitride, and the thickness thereof may be in the range

ToBetween

Wherein the second sub-layer 132 preferably has a thickness of

To

In the meantime.

In practice, the openings O1 and O2 may be etched in the first sub-layer 131 and the second sub-layer 132 by an etching process, respectively, so that the first via V1 is stepped because the second sub-layer 132 (silicon nitride) is etched more and the first sub-layer 131 (silicon oxide) is etched less. In addition, in the embodiment, the first sub-layer 131 has an inclined surface, and the second sub-layer 132 also has an inclined surface. In addition, the first width w1 of the first sub-layer 131 of the present embodiment is the smallest width of the first opening O1, and the second width w2 of the second sub-layer 132 is also the smallest width of the second opening O2. Furthermore, the distance w3 between one side edge of the first sub-layer 131 and the same side edge of the second sub-layer 132 may be, for example, between 0.1 micrometer (μm) and 0.5 micrometer (0.1 μm ≦ distance w3 ≦ 0.5 μm).

The planarization layer 14 is disposed on the first insulating layer 13, and has a second via V2 on the drain D, and the sizes of the first via V1 and the second via V2 may be the same or different, and are not limited. Here, the shapes of the first through hole V1 and the second through hole V2 in plan view are each square as an example. The first via V1 and the second via V2 are partially overlapped and form an overlap O, that is, the first via V1 formed by the first opening O1 and the second opening O2 and the projection of the second via V2 of the planarization layer 14 on the substrate S1 of the tft substrate 1 are at least partially overlapped, and the area of the overlap O may be between 4 and 49 μm.

In addition, the ratio of the area of the overlapping portion O of the first through hole V1 and the second through hole V2 to the area of the first through hole V1 may be between 0.14 and 0.78, and the ratio of the area of the overlapping portion O of the first through hole V1 and the second through hole V2 to the area of the second through hole V2 may be between 0.14 and 0.78, where the areas may be cross-sectional areas or projected areas, for example, the area of the overlapping portion O is 9 square micrometers, and the area of the first through hole V1 is 36 square micrometers. Compared with the prior art of etching another via in a larger via, the area of the overlapping portion O of the first via V1 and the second via V2 is smaller than that of the via in the prior art, and there is no alignment problem of another via in a large via. In addition, since the area of the overlapping portion O is smaller than that of the through hole in the prior art, when the black matrix layer BM is disposed on the scan line, the relative coverage width can be smaller than that in the prior art, so that the pixel aperture ratio of the display panel can be increased. It is particularly noted that the size O of the overlapping portion of the first via V1 and the second via V2 is between 2 and 8 micrometers, so as to facilitate the subsequent processes.

Referring to fig. 3A to 3D, a method for manufacturing the through hole of fig. 2C will be described.

First, as shown in fig. 3A, a first insulating layer 13 and a planarization layer 14 are sequentially deposited on the source S and the drain D. The first insulating layer 13 has a first sub-layer 131 and a second sub-layer 132.

Next, as shown in fig. 3B, a photolithography process is performed by using a mask (not shown), so as to form a second via hole V2 on the planarization layer 14 and expose the first insulating layer 13.

Next, as shown in fig. 3C, a second insulating layer 15 is formed to cover the first insulating layer 13 and the planarization layer 14.

Then, as shown in fig. 3D, a photolithography process is performed on the second insulating layer 15 and the first insulating layer 13 by using a mask to form a first via V1 to expose the drain D.

The shapes of the first through hole V1 and the second through hole V2 may include a polygon, a circular ellipse, or an irregular shape, respectively, for example. The overlap between the first via V1 and the second via V2 is preferably that the first via V1 and the second via V2 are both rectangular, and the overlap O between the first via V1 and the second via V2 is at the center. Therefore, the problem of the alignment of the small through holes in the existing large through hole is avoided, and the electrical conduction of the transparent conductive layer in the subsequent process is not affected (if the alignment is not good, the arrangement of the transparent conductive layer may be affected, and the electrical connection between the drain electrode and the pixel electrode is affected).

Referring to fig. 2C, the second insulating layer 15 is disposed on the planarization layer 14, and the pixel electrode layer 16 is disposed on the second insulating layer 15, wherein the pixel electrode layer 16 is comb-shaped. In addition, the pixel electrode layer 16 fills the first via hole V1 and the second via hole V2 formed by the first opening O1 and the second opening O2, and can be electrically connected to the drain D through the overlapping portion O of the first via hole V1 and the second via hole V2. The pixel electrode layer 16 can be made of Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Aluminum Zinc Oxide (AZO), Cadmium Tin Oxide (CTO), or tin oxide (SnO)₂) Or a transparent conductive material such as zinc oxide (ZnO).

Particularly, when the insulating layer is etched in the prior art, the sidewall of the through hole is prone to generate a right angle or a chamfer, and a break exists, so that when the transparent conductive layer is disposed in the through hole, a disconnection condition is prone to occur, and the yield is affected. However, in the first sidewall P1 of the overlapping portion O of the first via hole V1 and the second via hole V2, a portion of the pixel electrode layer 16 filled in the overlapping portion O is located on the first sidewall P1 and directly contacts the planarization layer 14 (as shown in the right sidewall of the via hole of fig. 2C). In addition, in the second sidewall P2 of the overlapping portion O of the first via V1 and the second via V2 of the present embodiment, a portion of the second insulating layer 15 filled in the overlapping portion O is located on the second sidewall P2 and directly contacts with the planarization layer 14 (as shown in the left sidewall of the via in fig. 2C), and the second insulating layer 15 of the second sidewall P2 can connect the insulating layers (the second sub-layer 132 and the second insulating layer 15) located above and below the planarization layer 14, so the number of possible break differences is small compared to the prior art, and the planarization layer 15 is generally gentler after etching, and the different stacking relationship of the two sidewalls makes the probability of breaking lines when the pixel electrode layer 16 is disposed relatively small, thereby indirectly increasing the yield of the process.

In addition, the common electrode layer 18 is disposed between the planarization layer 14 and the second insulating layer 15. In another embodiment, as shown in fig. 4, since the area of the overlapping portion O of the first via V1 and the second via V2 is smaller than that of the via of the prior art, the scanning line may have a recess U at the intersection of the adjacent data lines (the scanning line of the recess U is hollowed), and the recess U may be correspondingly disposed at the overlapping portion O of the first via V1 and the second via V2 (fig. 4 only shows the overlapping portion O of the first via V1 and the second via V2, but does not show the top view shape of the first via V1 and the second via V2). As described above, since the area of the overlapping portion O of the first via V1 and the second via V2 is smaller than that of the via of the prior art, the recess U on the scan line is not too large to cause the scan line to be broken, and only the line width of the scan line having the recess U is small, so that the coupling capacitance between the scan line and the data line can be reduced.

Referring to fig. 5A and 5B, fig. 5A is a schematic diagram illustrating an electrical characteristic curve of the tft T when the first sub-layer 131 and the second sub-layer 132 are disposed on the channel layer 12 of the tft T in the tft substrate 1 according to the preferred embodiment of the invention, and fig. 5B is a schematic diagram illustrating an electrical characteristic curve of the tft T after a period of time in the tft substrate 1 of fig. 5A. In fig. 5A and 5B, 4 characteristic curves of the tft T are obtained under 4 different measurement conditions.

As can be seen from fig. 5A and 5B, the curve change of fig. 5B is much smaller than that of fig. 1B after a period of time compared to the prior art due to the arrangement of the first sub-layer 131 and the second sub-layer 132. In addition, the curve change of fig. 5B is not very different from that of fig. 5A. In other words, the first sub-layer 131 and the second sub-layer 132 are sequentially disposed on the drain D of the tft T and the channel layer 12, so that the performance of the tft T is maintained stable, and the display quality of the display panel and the display device is not affected.

Next, please refer to fig. 6, which is a schematic cross-sectional view of a display panel 2 according to a preferred embodiment of the invention.

The display panel 2 includes a thin film transistor substrate 1, an opposite substrate S2 and a display layer L. The opposite substrate S2 is disposed opposite to the tft substrate 1 and may optionally have an electrode layer E and an alignment film a. The opposite substrate S2 may be a transparent material, such as glass, quartz or the like. In practical use, the substrate S1 and the opposite substrate S2 of the tft substrate 1 may be made of different materials, for example, the opposite substrate S2 may be made of potassium glass, and the substrate S1 may be made of borate alkali-free glass. In addition, the electrode layer E is disposed on the side of the opposite substrate S2 facing the tft substrate 1, and the alignment film a is disposed under the electrode layer E. In addition, a color filter F may be inserted between the opposite substrate S2 and the electrode layer E for displaying colors. In addition, a display layer L is disposed between the thin film transistor substrate 1 and the opposite substrate S2, wherein the display layer L may be a liquid crystal layer or an organic light emitting layer. The tft substrate 1 has been described in detail above, and will not be described herein. Of course, the thin film transistor substrate 1 may be replaced with the thin film transistor substrate 1a shown in fig. 2E.

Fig. 7 is a schematic cross-sectional view of a display device 3 according to a preferred embodiment of the invention.

The display device 3 includes a display panel 2 and a backlight module B. The display panel 2 includes a thin film transistor substrate 1, an opposite substrate S2 and a display layer L. The tft substrate 1 has been described in detail above, and will not be described herein.

The opposite substrate S2 is disposed opposite to the tft substrate 1 and may optionally have an electrode layer E and an alignment film a. The opposite substrate S2 may be a transparent material, such as glass, quartz or the like. In practical use, the substrate S1 and the opposite substrate S2 of the tft substrate 1 may be made of different materials, for example, the opposite substrate S2 may be made of potassium glass, and the substrate S1 may be made of borate alkali-free glass. In addition, the electrode layer E is disposed on the side of the opposite substrate S2 facing the tft substrate 1, and the alignment film a is disposed under the electrode layer E. In addition, a color filter F may be inserted between the opposite substrate S2 and the electrode layer E for displaying colors. In addition, the display layer L is disposed between the thin film transistor substrate 1 and the opposing substrate S2. It should be noted that the source S and the drain D of the tft T of fig. 6 and 7 are disposed on the etching stop layer ES, and one end of the source S and one end of the drain D are respectively in contact with the channel layer 12 from the opening of the etching stop layer ES. The etch stop layer ES may be an organic material such as an organosilicone compound, or a single-layer inorganic material such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, hafnium oxide, or a multi-layer structure of a combination thereof. However, in other embodiments, the source S and the drain D may be directly disposed on the channel layer 12 and contact the channel layer 12.

In addition, the backlight module B is disposed on the other side of the tft substrate 1 opposite to the opposite substrate S2, and emits light, so that the light passes through the display layer L from the substrate S1 of the tft substrate 1 and then exits from the opposite substrate S2. It should be noted that, in this embodiment, the display layer L is a liquid crystal layer, and thus is collocated with the backlight module B, and if the display layer L is an organic light emitting layer, the collocation with the backlight module B is not required.

In summary, in the display panel and the display device according to the invention, the first insulating layer of the tft substrate has a first sub-layer and a second sub-layer, and the first sub-layer and the second sub-layer are sequentially disposed on the drain electrode of the tft. The first sub-layer has a first opening with a first width, the second sub-layer has a second opening with a second width on the first opening, the first opening and the second opening can form a first through hole, and the second width can be larger than the first width. In addition, the pixel electrode layer of the thin film transistor substrate is arranged on the second insulating layer and is filled in the first through hole to be connected with the drain electrode. Therefore, compared with the prior art, the first sublayer and the second sublayer are sequentially arranged on the drain electrode of the thin film transistor, so that the efficiency of the thin film transistor after a period of time can still be kept stable, and the display quality of the display panel and the display device can not be influenced.

In addition, in an embodiment of the invention, projections of the first through hole formed by the first opening and the second through hole of the planarization layer on the substrate of the thin film transistor substrate overlap each other, and an area of the overlapping portion may be between 4 and 49 μm square. Therefore, compared with the prior art of etching another through hole in a larger through hole, the area of the overlapped part of the first through hole and the second through hole can be smaller than that of the through hole in the prior art, and the alignment problem of aligning the other through hole in the larger through hole can be avoided. In addition, because the area of the overlapped part is smaller than that of the through hole in the prior art, when the black matrix layer is arranged on the scanning line, the relative coverage width can be smaller than that in the prior art, and the pixel aperture ratio of the display panel and the display device can also be improved.

The foregoing is by way of example only, and not limiting. It is intended that all equivalent modifications or variations not departing from the spirit and scope of the present invention be included in the claims.

Claims

1. A display panel, comprising:

a substrate;

a scanning line, disposed on the substrate and having a concave portion;

a data line arranged on the substrate, wherein the data line and the scanning line are arranged in a staggered manner;

a thin film transistor disposed on the substrate and having a gate and a drain, the gate being electrically connected to the scan line, the drain being electrically connected to the data line;

a first insulating layer disposed on the drain electrode and exposing a portion of the drain electrode, wherein the recess of the scan line is disposed corresponding to the exposed portion of the drain electrode, and the first insulating layer has a through hole;

a planarization layer disposed on the first insulating layer, the planarization layer having another through hole, wherein the recess is correspondingly disposed at the overlapping position of the through hole and the another through hole; and

and the pixel electrode layer is arranged on the planarization layer and is electrically connected with the exposed part of the drain electrode.

2. The display panel according to claim 1, wherein the first insulating layer has an opening.

3. The display panel according to claim 2, wherein the opening of the first insulating layer has a step shape.

4. The display panel according to claim 2, wherein the opening of the first insulating layer has a slope.

5. The display panel according to claim 2, wherein the pixel electrode layer is filled in the opening and electrically connected to the portion of the drain electrode exposed.

6. The display panel of claim 1, wherein the another via hole has a first sidewall, and a portion of the pixel electrode layer is in direct contact with the first sidewall.

7. The display panel of claim 1, further comprising:

a second insulating layer disposed on the planarization layer.

8. The display panel of claim 7, wherein the another via has a second sidewall, and a portion of the second insulating layer is on and in direct contact with the second sidewall.

9. The display panel according to claim 8, wherein the second insulating layer is connected to the first insulating layer.