CN108231802A - Pixel structure - Google Patents
Pixel structure Download PDFInfo
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- CN108231802A CN108231802A CN201810134336.5A CN201810134336A CN108231802A CN 108231802 A CN108231802 A CN 108231802A CN 201810134336 A CN201810134336 A CN 201810134336A CN 108231802 A CN108231802 A CN 108231802A
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- insulating layer
- hole
- channel
- film transistor
- thin film
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- 239000010409 thin film Substances 0.000 claims abstract description 80
- 239000004065 semiconductor Substances 0.000 claims abstract description 49
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- 239000000758 substrate Substances 0.000 description 18
- 230000010355 oscillation Effects 0.000 description 16
- 239000010408 film Substances 0.000 description 8
- 238000010304 firing Methods 0.000 description 8
- 238000000265 homogenisation Methods 0.000 description 6
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- PPBRXRYQALVLMV-UHFFFAOYSA-N Styrene Chemical compound C=CC1=CC=CC=C1 PPBRXRYQALVLMV-UHFFFAOYSA-N 0.000 description 2
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- HXDOZKJGKXYMEW-UHFFFAOYSA-N 4-ethylphenol Chemical class CCC1=CC=C(O)C=C1 HXDOZKJGKXYMEW-UHFFFAOYSA-N 0.000 description 1
- 229920001665 Poly-4-vinylphenol Polymers 0.000 description 1
- RQIPKMUHKBASFK-UHFFFAOYSA-N [O-2].[Zn+2].[Ge+2].[In+3] Chemical compound [O-2].[Zn+2].[Ge+2].[In+3] RQIPKMUHKBASFK-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 125000000732 arylene group Chemical group 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
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- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
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- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
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- NJWNEWQMQCGRDO-UHFFFAOYSA-N indium zinc Chemical compound [Zn].[In] NJWNEWQMQCGRDO-UHFFFAOYSA-N 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Abstract
A pixel structure comprises a thin film transistor and a pixel electrode electrically connected with a drain electrode of the thin film transistor. The thin film transistor includes a source electrode, a drain electrode, a semiconductor layer, a first insulating layer, a second insulating layer, and a gate electrode. The semiconductor layer is located on the source electrode and the drain electrode and is provided with a channel. The channel is arranged between the source electrode and the drain electrode and is provided with a first through hole. The first insulating layer is located on the semiconductor layer and has a second via overlapping the first via. The second insulating layer is located on the first insulating layer and in the first through hole and the second through hole. The gate is located on the second insulating layer.
Description
Technical field
The present invention relates to a kind of semiconductor structure, and more particularly to a kind of dot structure.
Background technology
Display panel has many advantages, such as ultrathin, small and power saving, therefore has widely been used in daily life.
Display panel include image element array substrates, relative to image element array substrates opposite substrate and be set to image element array substrates with
Display medium between opposite substrate.Image element array substrates include substrate, be configured on substrate multiple thin film transistor (TFT)s, with it is more
The components such as multiple pixel electrodes, multiple data lines and the multi-strip scanning line that a thin film transistor (TFT) is electrically connected, wherein again with thin
The electrical good and bad performance for influencing display panel of film transistor is most acute.
In general, thin film transistor (TFT) includes source electrode, drain electrode, semiconductor layer, grid and is set to grid and semiconductor
An at least insulating layer between layer.If thin film transistor (TFT) gate insulating layer (such as：Organic grid insulating layer) breakdown voltage
It is relatively low, thicker insulating layer or multilayer dielectric layer would generally be set between grid and semiconductor layer.However, in grid and semiconductor
Thicker insulating layer or multilayer dielectric layer are set between layer, the increase of the distance between grid and semiconductor layer can be made, in turn resulted in
The problems such as firing current is too small, the subcritical amplitude of oscillation is poor.
Invention content
The present invention provides a kind of dot structure, thin film transistor (TFT) it is electrical good.
The dot structure of the present invention includes thin film transistor (TFT) and the pixel electricity with the drain electrode electric connection of thin film transistor (TFT)
Pole.Thin film transistor (TFT) includes source electrode, drain electrode, semiconductor layer, the first insulating layer, second insulating layer and grid.Semiconductor layer is located at
Source electrode is upper with drain electrode and with channel.Channel is set between source electrode and drain electrode and with first through hole (perforation).First insulation
Layer is located on semiconductor layer and with second through-hole Chong Die with first through hole.Second insulating layer be located on the first insulating layer and
In first through hole and the second through-hole.Grid is located in second insulating layer.
In one embodiment of this invention, above-mentioned channel has multiple side walls defined in an at least first through hole.The
Two insulating layers include being located in an at least first through hole and at least one second through-hole and the first part of the side wall of covering channel.
In one embodiment of this invention, the first above-mentioned insulating layer has multiple sides at least defined in one second through-hole
Wall, and the first part of second insulating layer also directly covers the side wall of the first insulating layer.
In one embodiment of this invention, the above-mentioned side wall of the first insulating layer and the side wall of channel trim.
In one embodiment of this invention, the first part of above-mentioned second insulating layer has a recess.Grid includes
First sub- gate portion.First sub- gate portion is located in the recess of second insulating layer and Chong Die with the side wall of at least part of channel.
In one embodiment of this invention, above-mentioned second insulating layer further includes second part.Second part is located at least
On the first insulating layer outside one first through hole and at least one second through-hole.Grid further includes the second sub- gate portion.Second sub- grid
Portion is located on the second part of second insulating layer.
In one embodiment of this invention, the relative dielectric constant of above-mentioned second insulating layer is more than or whats first is waited to insulate
The relative dielectric constant of layer.
In one embodiment of this invention, the relative dielectric constant of the first above-mentioned insulating layer is ε1, and 2≤ε1≤3。
In one embodiment of this invention, the relative dielectric constant of above-mentioned second insulating layer is ε2, and 2.5≤ε2≤15。
In one embodiment of this invention, above-mentioned semiconductor layer includes organic semiconducting materials.
In one embodiment of this invention, above-mentioned dot structure further includes data line and scan line.Data line and film
The source electrode of transistor is electrically connected.The grid of scan line and thin film transistor (TFT) is electrically connected.Grid and source electrode, drain electrode, channel
At least one second through-hole of an at least first through hole and the first insulating layer overlaps.
Based on above-mentioned, first through hole that the thin film transistor (TFT) of the dot structure of one embodiment of the invention passes through semiconductor layer
Setting, the grid of thin film transistor (TFT) can not only attract carrier to be moved to the top surface of semiconductor layer and then form main thoroughfare, more can
Carrier is attracted to be moved to the side wall of semiconductor layer and then forms secondary channel.Therefore, the number of channels of thin film transistor (TFT) increases, and
The firing current of thin film transistor (TFT) is made to become larger, the subcritical amplitude of oscillation improves.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and coordinate specification attached
Figure is described in detail below.
Description of the drawings
Fig. 1 is the vertical view of the dot structure of one embodiment of the invention.
Fig. 2 is the diagrammatic cross-section of the thin film transistor (TFT) of one embodiment of the invention.
Stereoscopic schematic diagrams of the Fig. 3 for the source electrode of the thin film transistor (TFT) of one embodiment of the invention, drain electrode and channel.
Fig. 4 is the vertical view of the dot structure of comparative example.
Fig. 5 is the diagrammatic cross-section of the thin film transistor (TFT) of comparative example.
Fig. 6 shows the critical voltage and one embodiment of the invention of the thin film transistor (TFT)s of several dot structures of comparative example
The comparison of the critical voltage of the thin film transistor (TFT) of several dot structures.
Fig. 7 shows the subcritical amplitude of oscillation and one embodiment of the invention of the thin film transistor (TFT) of several dot structures of comparative example
Several dot structures thin film transistor (TFT) the subcritical amplitude of oscillation comparison.
Fig. 8 show the relationship of the grid voltage of the thin film transistor (TFT) of the dot structure of comparative example and homogenization drain current with
And the relationship of the grid voltage of the thin film transistor (TFT) of the dot structure of one embodiment of the invention and homogenization drain current.
Fig. 9 show the passage length of the thin film transistor (TFT) of the dot structure of comparative example and critical voltage offset relationship and
The passage length of the thin film transistor (TFT) of the dot structure of one embodiment of the invention and the relationship of critical voltage offset.
Reference sign：
100、200：Dot structure
110：Substrate
120：Flatness layer
130、230：Semiconductor layer
132、232：Channel
132a：First through hole
132s1、140s1：Side wall
132s2：Bottom surface
132s3：Top surface
140：First insulating layer
140a：Second through-hole
150：Second insulating layer
152：First part
152a：Recess
154：Second part
160：Pixel electrode
D、D2：Drain electrode
DL：Data line
d1、d2：Thickness
G、G2：Grid
Gs：First sub- gate portion
Gm：Second sub- gate portion
L：Passage length
S、S2：Source electrode
SL：Scan line
S11、S12、S13、S21、S22、S23：Curve
SS1、SS2：The subcritical amplitude of oscillation
T1、T2：Thin film transistor (TFT)
Vth1、Vth2：Critical voltage
x、y、z：Direction
Ⅰ-Ⅰ’、Ⅱ-Ⅱ’：Hatching line
Specific embodiment
In the accompanying drawings, for the sake of clarity, it is exaggerated the thickness in layer, film, panel, region etc..Throughout the specification, phase
With the identical element of reference numeral expression.It should be appreciated that ought the element of such as layer, film, region or substrate be referred to as another
Element " on " or during " being connected to " another element, can connect directly on another element or with another element or also may be used
With there are intermediary elements.On the contrary, when element is referred to as " directly on another element " or " being directly connected to " another element, no
There are intermediary elements.As it is used herein, " connection " can refer to physics and/or electric connection.Furthermore " electric connection " with
" coupling " can there are other elements between two element.
" about " used herein, " approximation " or " substantial " determine including described value and in those of ordinary skill in the art
Particular value acceptable deviation range in average value, it is contemplated that the measurement that is discussed and the spy with measuring relevant error
Fixed number amount (that is, limitation of measuring system).For example, " about " can represent in one or more standard deviations of described value or
± 30%, in ± 20%, ± 10%, ± 5%.Furthermore " about " used herein, " approximation " or " substantial " can be according to optical
Matter, etching property or other properties to select more acceptable deviation range or standard deviation, and can not have to a standard deviation
It is applicable in whole property.
Unless otherwise defined, all terms (including technical and scientific term) used herein have and neck belonging to the present invention
The normally understood identical meaning of those of ordinary skill in domain.It will be further appreciated that such as in usually used dictionary
Those terms of definition should be interpreted as having consistent with their meanings in the relevant technologies and context of the invention
Meaning, and will not be interpreted Utopian or excessively formal meaning, unless clearly definition so herein.
Exemplary embodiment is described herein with reference to the sectional view of the schematic diagram as idealized embodiments.It therefore, can be with
Anticipate the change in shape of the diagram of the result as such as manufacturing technology and/or tolerance.Therefore, embodiment as described herein is not
The specific shape in region as illustrated herein should be construed as limited to, but including the form variations for example as caused by manufacture.Example
Such as, coarse and/or nonlinear characteristic can usually be had by being illustrated and described as flat region.In addition, shown acute angle can be with
It is round.Therefore, region shown in figure is substantially schematical, and their shape is not intended to the essence for showing region
True shape, and not it is intended to limitation the scope of the claims.
Fig. 1 is the vertical view of the dot structure of one embodiment of the invention.Fig. 2 is the thin film transistor (TFT) of one embodiment of the invention
Diagrammatic cross-section.Particularly, Fig. 2 corresponds to the hatching line I-I ' of Fig. 1.For the sake of clearly illustrating, the acceptance of the bid of part attached drawing
There are xyz rectangular coordinate systems, wherein direction x, y, z is perpendicular.
Fig. 1 and Fig. 2 is please referred to, dot structure 100 is configured on substrate 110.For example, in the present embodiment, substrate
The flatness layer 120 of insulation can be equipped on 110, and dot structure 100 may be disposed on flatness layer 120.However, the present invention is not limited to
This, in other embodiments, dot structure 100 can also be set up directly on substrate 110.Substrate 110 mainly carries pixel
Structure 100 is used.In the present embodiment, the material of substrate 110 can be glass, quartz, organic polymer or light tight/
Reflecting material (such as：Wafer, ceramics or other materials applicatory) or other materials applicatory.
Dot structure 100 includes thin film transistor (TFT) T1 and the pixel electricity with the drain D electric connection of thin film transistor (TFT) T1
Pole 160 (is illustrated in Fig. 1).Thin film transistor (TFT) T1 includes source S, drain D, semiconductor layer 130, the first insulating layer 140, second absolutely
Edge layer 150 and grid G.Source S is separated from each other with drain D.In the present embodiment, source S is optionally set with drain D
In on flatness layer 120, but the present invention is not limited.In the present embodiment, dot structure 100 further includes data line DL and (shows
In Fig. 1).The source S of data line DL and thin film transistor (TFT) T1 is electrically connected.For example, in the present embodiment, source S can be with
It is by the outwardly extending branches of data line DL.However, the present invention is not limited thereto, in other embodiments, source S can also be data
A part of line DL.In the present embodiment, dot structure 100 further includes scan line SL (being illustrated in Fig. 1).Scan line SL and film
The grid G of transistor T1 is electrically connected.For example, in the present embodiment, grid G can be outwardly extending by scan line SL
Branch.However, the present invention is not limited thereto, in other embodiments, grid G can also be a parts of scan line SL.
In the present embodiment, data line DL, source S and drain D can be selectively formed at same first conductive layer.So
And the present invention is not limited thereto, in other embodiments, data line DL, source S may belong to different film layers from drain D.In this reality
It applies in example, scan line SL can be selectively formed at same second conductive layer with grid G.However, the present invention is not limited thereto,
In other embodiments, scan line SL may belong to different film layers from grid G.Considering based on electric conductivity, data line DL, scan line
SL, grid G, source S and drain D are usually to use metal material.However, the present invention is not limited thereto, and in other embodiments, number
Other conductive materials can also be used according to line DL, scan line SL, grid G, source S and/or drain D, such as：Alloy, metal material
The heap of the nitride of material, the oxide of metal material, the nitrogen oxides of metal material or metal material and other conductive materials
Lamination.
Semiconductor layer 130 is located in source S and drain D.Semiconductor layer 130 covers source S and drain D.Source S and drain electrode
Twoth area different from semiconductor layer 130 are electrically connected D respectively.Semiconductor layer 130 has channel 132.Channel 132 is arranged on source electrode
Between S and drain D.In detail, in the present embodiment, channel 132 refer between source S and drain D and on the z of direction with
One region of the semiconductor layer 130 of grid G overlapping.In the present embodiment, the material of semiconductor layer 130 is, for example, organic semiconductor
Material.However, the present invention is not limited thereto, in other embodiments, the material of semiconductor layer 130 can also be non-crystalline silicon, polycrystalline
Silicon, microcrystal silicon, monocrystalline silicon, oxide semiconductor material (such as：Indium-zinc oxide, indium germanium zinc oxide or other suitable
Material or combinations of the above) or other suitable materials or in above-mentioned material or above-mentioned containing dopant (dopant)
Combination.
Stereoscopic schematic diagrams of the Fig. 3 for the source electrode of the thin film transistor (TFT) of one embodiment of the invention, drain electrode and channel.Please refer to figure
1st, the channel 132 of Fig. 2 and Fig. 3, thin film transistor (TFT) T1 have an at least first through hole 132a.Fig. 1, Fig. 2 and Fig. 3 are with three first
Through-hole 132a be example, however, the present invention is not limited thereto, the visual actual demand of the quantity of first through hole 132a possessed by channel 132
Depending on；In other embodiments, the quantity of the first through hole 132a of channel 132 can also be other appropriate numerical value.Channel 132
First through hole 132a defines multiple side wall 132s1 of semiconductor layer 130.Channel 132 has the bottom surface 132s2 towards substrate 110
And the top surface 132s3 backwards to substrate 110, and side wall 132s1 is connected between bottom surface 132s2 and top surface 132s3.Citing and
Speech, in the present embodiment, the length direction and direction x of channel 132 are substantial parallel, and the first through hole 132a of channel 132 determines
The side wall 132s1 of justice is located substantially in xz planes, the top surface 132s3 of channel 132 be located substantially in x/y plane (such as：Far from former
X/y plane on the z directions of point), but the present invention is not limited.
Fig. 1 and Fig. 2 is please referred to, the first insulating layer 140 is located on semiconductor layer 130 and at least one second through-hole
140a.Fig. 1 and Fig. 2 is using three the second through-hole 140a as example, however, the present invention is not limited thereto, possessed by the first insulating layer 140
Depending on the visual actual demand of quantity of second through-hole 140a；In other embodiments, the second through-hole 140a of the first insulating layer 140
Quantity be alternatively other appropriate numerical value.
The the second through-hole 140a and the first through hole 132a of channel 132 of first insulating layer 140 are substantially be overlapped.In other words,
Second through-hole 140a of the first insulating layer 140 is connected with the first through hole 132a of channel 132.In the present embodiment, the first insulation
Layer 140 has multiple side wall 140s1 defined in the second through-hole 140a, and channel 132 has more defined in first through hole 132a
A side wall 132s1, and the side wall 140s1 of the first insulating layer 140 and the side wall 132s1 of channel 132 can substantially be trimmed.Citing and
Speech, can be in sequentially forming semiconductor material layer (not shown) in the technique of the dot structure 100 of the present embodiment on substrate 110
And the first insulation material layer (not shown)；Then, using same shade, while the semiconductor material layer and described is patterned
First insulation material layer, to form 130 and first insulating layer 140 of semiconductor layer.Therefore, in the present embodiment, semiconductor layer 130
It can substantially trim and (in other words, overlap), but the present invention is not limited with the first insulating layer 140.In other embodiments, the
The side wall 140s1 of one insulating layer 140 can be recessed in the range of the side wall 132s1 of channel 132 or the side wall of the first insulating layer 140
140s1 can protrude from the side wall 132s1 of channel 132, and the side wall 140s1 of the first insulating layer 140 can be located at part first through hole
In 132a.
Second insulating layer 150 is located on the first insulating layer 140 and the second through-hole 140a and channel of the first insulating layer 140
In 132 first through hole 132a.For example, in the present embodiment, second insulating layer 150 includes first part 152 and second
Part 154；First part 152 is located in the second through-hole 140a of the first insulating layer 140 and first through hole 132a of channel 132；
Second part 154 is located at outside the second through-hole 140a of the first insulating layer 140 and the first through hole 132a of channel 132, and positioned at the
On one insulating layer 140.The second through-hole 140a that the first part 152 of second insulating layer 150 covers the first insulating layer 140 is defined
Side wall 140s1 and channel 132 first through hole 132a defined in side wall 132s1.Preferably, in the present embodiment,
The first part 152 of two insulating layers 150 can directly cover side wall 140s1 and side wall 132s1, and with side wall 140s1 and side wall
132s1 is contacted, but the present invention is not limited.
In the present embodiment, the thickness d 2 of second insulating layer 150 is smaller than the thickness d 1 of the first insulating layer 140, but not with
This is limited.Thickness d 2 can refer to the thickness for being located at the part second insulating layer 150 of the surface of source S and/or drain D.Thickness d 1
It can refer to the thickness for being located at the first insulating layer of part 140 of the surface of source S and/or drain D.In the present embodiment, second absolutely
The relative dielectric constant of edge layer 150 can be more than the relative dielectric constant of the first insulating layer 140.The phase of above-mentioned second insulating layer 150
Refer to the dielectric constant relative to vacuum to dielectric constant；Similarly, the relative dielectric constant of the first insulating layer 140 refers to relatively
In the dielectric constant of vacuum.For example, in the present embodiment, the relative dielectric constant of the first insulating layer 140 is ε1, second absolutely
The relative dielectric constant of edge layer 150 is ε2, 2≤ε1≤ 3,2.5≤ε2≤ 15, but the present invention is not limited.In the present embodiment
In, the material of the first insulating layer 140 is for example including polyacids methyl esters (polymethylmethacrylate, PMMA), polyisobutene
(po lyi sobutylene, PIB), polyethylene (polyethylene, P E), gather polypropylene (polypropylene, PP)
Styrene (po lystyrene, P S), poly- 4- ethyl -phenols (poly-4-vinylphenol, PVP), polyvinyl alcohol
(polyvinylalcohol, PVA) or its copolymer or other appropriate organic materials or other appropriate materials, second absolutely
The material of edge layer 150 is for example including Parylene (p arylene) or other appropriate organic materials or other appropriate
Inorganic material or other suitable materials, but the present invention is not limited.
Grid G is located in second insulating layer 150.Grid G and source S, drain D, channel 132 first through hole 132a and
Second through-hole 140a of the first insulating layer 140 is overlapped.In the present embodiment, second insulating layer 150 can be conformally
(conformably) semiconductor layer 130, the first insulating layer 140, first through hole 132a and the second through-hole 140a are covered, and is located at
The first part 152 of first through hole 132a and the second insulating layer 150 in the second through-hole 140a has recess 152a.In this implementation
In example, grid G includes the first sub- sub- gate portion Gm of gate portion Gs and second.The first partial sub- gate portion Gs is located at the second insulation
In the recess 152a of the first part 152 of layer 150.The side wall 132s1 of first sub- gate portion Gs and at least part of channel 132 exist
It is overlapped on the y of direction.First sub- gate portion Gs covers the side wall 132s1 of at least part of channel 132, and to attract carrier (not
Show) to the side wall 132s1 of channel 132.The side wall 132s1 of channel 132 can be considered the secondary channel of transmission carrier, and first is sub
Gate portion Gs can be considered secondary gate portion.Second sub- gate portion Gm is located on the second part 154 of second insulating layer 150.Second
The top surface 132s3 of sub- gate portion Gm coverings channel 132, and to attract carrier to the top surface 132s3 of channel 132.Channel 132
Top surface 132s3 can be considered the main thoroughfare of transmission carrier, and the second sub- gate portion Gm can be considered main gate portion.
By the setting of the first through hole 132a of channel 132, grid G not only can attract carrier to be moved to semiconductor layer 130
Top surface 132s3 so that formed main thoroughfare, carrier can more be attracted to be moved to side wall 132s1 and then the formation of semiconductor layer 130
Secondary channel.Therefore, the number of channels of thin film transistor (TFT) T1 increases, and the firing current of thin film transistor (TFT) T1 is made to become larger, secondary is faced
Boundary's amplitude of oscillation improves.In addition, in the present embodiment, the first sub- gate portion Gs (i.e. secondary gate portion) and the side wall 132s1 of channel 132
Between accompany second insulating layer 150 and do not accompany the first insulating layer 140, therefore the first sub- gate portion Gs can more effectively attract load
Son to semiconductor layer 130 side wall 132s1, and further promoted thin film transistor (TFT) T1 firing current, improve it is subcritical
The amplitude of oscillation.
Fig. 4 is the vertical view of the dot structure of comparative example.Fig. 5 is the diagrammatic cross-section of the thin film transistor (TFT) of comparative example.It is special
It is not that Fig. 5 corresponds to the hatching line II-II ' of Fig. 4.Please refer to Fig. 4 and Fig. 5, the dot structure 200 of comparative example and aforementioned pixel
Structure 100 is similar, and identical label is used for representing same or similar part in the accompanying drawings and the description.The dot structure of comparative example
200 include thin film transistor (TFT) T2 and the pixel electrode 160 being electrically connected with thin film transistor (TFT) T2.The thin film transistor (TFT) of comparative example
T2 also includes source S 2, grid G 2, drain D 2 and semiconductor layer 230.The dot structure 200 of comparative example and aforementioned pixel knot
The difference of structure 100 is that the channel 232 of the thin film transistor (TFT) T2 of dot structure 200 does not have first through hole 132a, does not also have
Second through-hole 140a.
Fig. 6 shows the critical voltage Vth2 and the present invention of the thin film transistor (TFT) T2 of several dot structures 200 of comparative example
The comparison of the critical voltage Vth1 of the thin film transistor (TFT) T1 of several dot structures 100 of one embodiment.Please refer to Fig. 6, comparative example
Thin film transistor (TFT) T2 each position critical voltage Vth2 average value for -4.43V, the thin film transistor (TFT) T1 of the present embodiment exists
The average value of the critical voltage Vth1 of each position is -3.23V.Can be demonstrate,proved by Fig. 6, by above-mentioned multichannel (i.e. main thoroughfare with time
Want channel) design, compared to the thin film transistor (TFT) T2 of comparative example, the critical voltage of the thin film transistor (TFT) T1 of the present embodiment it is flat
The absolute value of mean value is smaller, and electrically good.
Fig. 7 shows the subcritical amplitude of oscillation (Subthreshold of the thin film transistor (TFT) T2 of several dot structures 200 of comparative example
Swing；S.S.) the subcritical amplitude of oscillation of the thin film transistor (TFT) T1 of SS2 and several dot structures 100 of one embodiment of the invention
The comparison of SS1.Fig. 7 is please referred to, the thin film transistor (TFT) T2 of comparative example is about in the average value of the subcritical amplitude of oscillation of each position
1078.65mV/decade, the thin film transistor (TFT) T1 of the present embodiment are about in the average value of the subcritical amplitude of oscillation of each position
683.02mV/decade.Can be demonstrate,proved by Fig. 7, by the design of above-mentioned multichannel (i.e. main thoroughfare and secondary channel), compared to than
Compared with the thin film transistor (TFT) T2 of example, the average value of the subcritical amplitude of oscillation SS1 of the thin film transistor (TFT) T1 of the present embodiment is small, and electrically good.
Fig. 8 shows the grid voltage of the thin film transistor (TFT) T2 of the dot structure 200 of comparative example and homogenization drain current
The grid voltage of the thin film transistor (TFT) T1 of the dot structure 100 of relationship and one embodiment of the invention and homogenization drain current
Relationship.Please refer to the thin film transistor (TFT) T1 that Fig. 8, curve S11 and curve S12 represent the dot structure 100 of one embodiment of the invention
Grid voltage and homogenization drain current relationship, and curve S21 and curve S22 represent the dot structure 200 of comparative example
The relationship of the grid voltage of thin film transistor (TFT) T2 and homogenization drain current.The wherein drain drives of curve S11 and curve S21 electricity
It is about -10.1 volts to press (Vd), and the drain drives voltage (Vd) of curve S12 and curve S22 is about -0.1 volt.It is shown by Fig. 8
Show, when drain drives voltage (Vd) is about -10.1 volts, the multichannel of the dot structure 100 of one embodiment of the invention is (i.e. main
Want channel and secondary channel) design thin film transistor (TFT) T1 (curve S11) compared to comparative example thin film transistor (TFT) T2 (curves
S21), the thin film transistor (TFT) T1 of the present embodiment has larger firing current and the preferred subcritical amplitude of oscillation, and electrically good；Work as leakage
When pole driving voltage (Vd) is about -0.1 volt, the multichannel of the dot structure 100 of one embodiment of the invention (i.e. main thoroughfare with
Secondary channel) design thin film transistor (TFT) T1 (curve S12) compared to the thin film transistor (TFT) T2 (curve S22) of comparative example, this reality
Applying the thin film transistor (TFT) T1 of example has larger firing current and the preferred subcritical amplitude of oscillation, and electrically good.
Fig. 9 show the passage length L (being shown in Fig. 4) of the thin film transistor (TFT) T2 of the dot structure 200 of comparative example with it is critical
The passage length L of the thin film transistor (TFT) T1 of the relationship of variation and the dot structure 100 of one embodiment of the invention (is shown in
Fig. 1) the relationship deviated with critical voltage.Fig. 9 is please referred to, curve S13 represents the thin of the dot structure 100 of one embodiment of the invention
The passage length L of film transistor T1 and the relationship of critical voltage offset, and curve S23 represents the dot structure 200 of comparative example
The passage length L of thin film transistor (TFT) T2 and the relationship of critical voltage offset.It can be demonstrate,proved by Fig. 9, it is (i.e. main logical by above-mentioned multichannel
Road and secondary channel) design, compared to the thin film transistor (TFT) T2 of comparative example, the critical electricity of the thin film transistor (TFT) T1 of the present embodiment
Pressure is less susceptible to passage length L variations and over-deflection, and electrically good.
In conclusion the dot structure of one embodiment of the invention includes thin film transistor (TFT) and the drain electrode with thin film transistor (TFT)
The pixel electrode of electric connection.Thin film transistor (TFT) includes source electrode, drain electrode, semiconductor layer, the first insulating layer, second insulating layer and grid
Pole.Semiconductor layer is located at source electrode with drain electrode above and with channel.Channel is set between source electrode and drain electrode and with first through hole.
First insulating layer is located on semiconductor layer and with second through-hole Chong Die with first through hole.Second insulating layer is located at the first insulation
On layer and in first through hole and the second through-hole.Grid is located in second insulating layer.Pass through setting for the first through hole of semiconductor layer
It puts, grid can not only attract carrier to be moved to the top surface of semiconductor layer and then form main thoroughfare, can more carrier be attracted to be moved to
The side wall and then formation secondary channel of semiconductor layer.Therefore, the number of channels of thin film transistor (TFT) increases, and makes thin film transistor (TFT)
Firing current becomes larger, the subcritical amplitude of oscillation improves.
In addition, in an embodiment of the present invention, the first sub- gate portion (i.e. secondary gate portion) is pressed from both sides between the side wall of channel
There is second insulating layer and do not accompany the first insulating layer；Therefore, the first sub- gate portion can be close to the side wall of channel, more effectively to inhale
Draw carrier to the side wall of channel, and further promote the firing current of thin film transistor (TFT), improve the subcritical amplitude of oscillation.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field
Middle technical staff, without departing from the spirit and scope of the invention, when can make a little variation and retouching, therefore the protection of the present invention
Range is when subject to as defined in claim.
Claims (11)
1. a kind of dot structure, including：
One thin film transistor (TFT), including：
One source electrode and a drain electrode；
Semi-conductor layer, in the source electrode and the drain electrode and with a channel, the channel be set to the source electrode and the drain electrode it
Between, wherein the channel has an at least first through hole；
One first insulating layer, on the semiconductor layer and at least one second through-hole, at least one second through-hole with this extremely
Few first through hole overlapping；
One second insulating layer, on first insulating layer and in an at least first through hole and at least one second through-hole；
And
One grid, in the second insulating layer；And
One pixel electrode, the drain electrode with the thin film transistor (TFT) are electrically connected.
2. dot structure as described in claim 1, the wherein channel have multiple sides defined in an at least first through hole
Wall, and the second insulating layer includes：
One first part in an at least first through hole and at least one second through-hole, and covers the described more of the channel
A side wall.
3. dot structure as claimed in claim 2, wherein first insulating layer have defined at least one second through-hole
Multiple side walls, and the first part of the second insulating layer also directly covers the multiple side wall of first insulating layer.
4. the multiple side wall of dot structure as claimed in claim 3, wherein first insulating layer is described with the channel
Multiple side walls trim.
5. the first part of dot structure as claimed in claim 2, the wherein second insulating layer has a recess, and is somebody's turn to do
Grid includes：
One first sub- gate portion, in the recess of the second insulating layer and with the multiple side of at least part of channel
Wall is overlapped.
6. dot structure as claimed in claim 5, the wherein second insulating layer further include：
One second part, on first insulating layer outside an at least first through hole and at least one second through-hole, wherein
The grid further includes one second sub- gate portion, and the second sub- gate portion of the grid is located at the second part of the second insulating layer
On.
7. the relative dielectric constant of dot structure as described in claim 1, the wherein second insulating layer be greater than or equal to this
The relative dielectric constant of one insulating layer.
8. dot structure as described in claim 1, the wherein relative dielectric constant of first insulating layer are ε1, and 2≤ε1≤3。
9. the relative dielectric constant of dot structure as described in claim 1, the wherein second insulating layer is ε2, and 2.5≤ε2≤
15。
10. dot structure as described in claim 1, the wherein semiconductor layer include organic semiconducting materials.
11. dot structure as described in claim 1, further includes：
One data line is electrically connected with the source electrode of the thin film transistor (TFT)；And
Scan line is electrically connected with the grid of the thin film transistor (TFT), wherein the grid and the source electrode, the drain electrode, the channel
At least this of a first through hole and first insulating layer at least second through-hole overlap.
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| TW106143961A TWI662347B (en) | 2017-12-14 | 2017-12-14 | Pixel structure |
| TW106143961 | 2017-12-14 |
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| CN1435864A (en) * | 2002-01-28 | 2003-08-13 | 株式会社半导体能源研究所 | Semiconductor device and mfg. method thereof |
| US20120193620A1 (en) * | 2011-02-02 | 2012-08-02 | Semiconductor Energy Laboratory Co., Ltd. | Transistor and semiconductor device |
| CN103000808A (en) * | 2011-09-12 | 2013-03-27 | 索尼公司 | Thin-film transistor and electronic unit |
| CN106663391A (en) * | 2013-12-02 | 2017-05-10 | 株式会社半导体能源研究所 | Display device and method for manufacturing the same |
| CN106898621A (en) * | 2017-01-25 | 2017-06-27 | 友达光电股份有限公司 | Pixel structure and manufacturing method thereof |
| CN107204362A (en) * | 2016-03-18 | 2017-09-26 | 株式会社日本显示器 | Semiconductor device |
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| US7358121B2 (en) * | 2002-08-23 | 2008-04-15 | Intel Corporation | Tri-gate devices and methods of fabrication |
| JP5656049B2 (en) * | 2010-05-26 | 2015-01-21 | ソニー株式会社 | Thin film transistor manufacturing method |
| US8871565B2 (en) * | 2010-09-13 | 2014-10-28 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| US8232164B2 (en) * | 2010-10-29 | 2012-07-31 | International Business Machines Corporation | Damascene method of forming a semiconductor structure and a semiconductor structure with multiple fin-shaped channel regions having different widths |
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| CN1435864A (en) * | 2002-01-28 | 2003-08-13 | 株式会社半导体能源研究所 | Semiconductor device and mfg. method thereof |
| US20120193620A1 (en) * | 2011-02-02 | 2012-08-02 | Semiconductor Energy Laboratory Co., Ltd. | Transistor and semiconductor device |
| CN103000808A (en) * | 2011-09-12 | 2013-03-27 | 索尼公司 | Thin-film transistor and electronic unit |
| CN106663391A (en) * | 2013-12-02 | 2017-05-10 | 株式会社半导体能源研究所 | Display device and method for manufacturing the same |
| CN107204362A (en) * | 2016-03-18 | 2017-09-26 | 株式会社日本显示器 | Semiconductor device |
| CN106898621A (en) * | 2017-01-25 | 2017-06-27 | 友达光电股份有限公司 | Pixel structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
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| CN108231802B (en) | 2020-07-10 |
| TWI662347B (en) | 2019-06-11 |
| TW201928484A (en) | 2019-07-16 |
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