CN108231802B - Pixel structure - Google Patents
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- CN108231802B CN108231802B CN201810134336.5A CN201810134336A CN108231802B CN 108231802 B CN108231802 B CN 108231802B CN 201810134336 A CN201810134336 A CN 201810134336A CN 108231802 B CN108231802 B CN 108231802B
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- 239000004065 semiconductor Substances 0.000 claims abstract description 49
- 239000010409 thin film Substances 0.000 claims abstract description 40
- 239000000463 material Substances 0.000 claims description 17
- 230000000052 comparative effect Effects 0.000 description 21
- 239000000758 substrate Substances 0.000 description 18
- 239000000969 carrier Substances 0.000 description 12
- 238000005259 measurement Methods 0.000 description 3
- 229920001665 Poly-4-vinylphenol Polymers 0.000 description 2
- 229920002367 Polyisobutene Polymers 0.000 description 2
- 239000004743 Polypropylene Substances 0.000 description 2
- 239000004372 Polyvinyl alcohol Substances 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
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- 229920002451 polyvinyl alcohol Polymers 0.000 description 2
- 239000004698 Polyethylene Substances 0.000 description 1
- 239000004793 Polystyrene Substances 0.000 description 1
- RQIPKMUHKBASFK-UHFFFAOYSA-N [O-2].[Zn+2].[Ge+2].[In+3] Chemical compound [O-2].[Zn+2].[Ge+2].[In+3] RQIPKMUHKBASFK-UHFFFAOYSA-N 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229920001577 copolymer Polymers 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
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- 229920000620 organic polymer Polymers 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- NRNFFDZCBYOZJY-UHFFFAOYSA-N p-quinodimethane Chemical group C=C1C=CC(=C)C=C1 NRNFFDZCBYOZJY-UHFFFAOYSA-N 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Abstract
A pixel structure comprises a thin film transistor and a pixel electrode electrically connected with a drain electrode of the thin film transistor. The thin film transistor includes a source electrode, a drain electrode, a semiconductor layer, a first insulating layer, a second insulating layer, and a gate electrode. The semiconductor layer is located on the source electrode and the drain electrode and is provided with a channel. The channel is arranged between the source electrode and the drain electrode and is provided with a first through hole. The first insulating layer is located on the semiconductor layer and has a second via overlapping the first via. The second insulating layer is located on the first insulating layer and in the first through hole and the second through hole. The gate is located on the second insulating layer.
Description
Technical Field
The present invention relates to semiconductor structures, and more particularly to a pixel structure.
Background
Display panels have advantages of ultra-thin, small size and power saving, and thus have been widely used in daily life. The display panel comprises a pixel array substrate, an opposite substrate opposite to the pixel array substrate and a display medium arranged between the pixel array substrate and the opposite substrate. The pixel array substrate comprises a substrate, a plurality of thin film transistors arranged on the substrate, a plurality of pixel electrodes electrically connected with the thin film transistors, a plurality of data lines, a plurality of scanning lines and other components, wherein the performance of the display panel is influenced most severely by the advantages and disadvantages of the electrical properties of the thin film transistors.
Generally, a thin film transistor includes a source electrode, a drain electrode, a semiconductor layer, a gate electrode, and at least one insulating layer disposed between the gate electrode and the semiconductor layer. If the breakdown voltage of the gate insulating layer (e.g., organic gate insulating layer) of the thin film transistor is low, a thicker insulating layer or layers are usually disposed between the gate and the semiconductor layer. However, the thicker insulating layer or multiple insulating layers disposed between the gate and the semiconductor layer may increase the distance between the gate and the semiconductor layer, which may cause the problems of too small on-current and poor sub-critical swing.
Disclosure of Invention
The invention provides a pixel structure, and a thin film transistor of the pixel structure has good electrical property.
The pixel structure comprises a thin film transistor and a pixel electrode electrically connected with the drain electrode of the thin film transistor. The thin film transistor includes a source electrode, a drain electrode, a semiconductor layer, a first insulating layer, a second insulating layer, and a gate electrode. The semiconductor layer is located on the source electrode and the drain electrode and is provided with a channel. The channel is arranged between the source electrode and the drain electrode and is provided with a first through hole (through hole). The first insulating layer is located on the semiconductor layer and has a second via overlapping the first via. The second insulating layer is located on the first insulating layer and in the first through hole and the second through hole. The gate is located on the second insulating layer.
In an embodiment of the invention, the channel has a plurality of sidewalls defined by at least one first through hole. The second insulating layer includes a first portion in the at least one first via and the at least one second via and covering sidewalls of the channel.
In an embodiment of the invention, the first insulating layer has a plurality of sidewalls defined by at least one second via, and the first portion of the second insulating layer directly covers the sidewalls of the first insulating layer.
In an embodiment of the invention, a sidewall of the first insulating layer is aligned with a sidewall of the channel.
In an embodiment of the invention, the first portion of the second insulating layer has a recess. The gate includes a first sub-gate portion. The first sub-gate portion is located in the recess of the second insulating layer and overlaps with at least a portion of the sidewall of the channel.
In an embodiment of the invention, the second insulating layer further includes a second portion. The second portion is located on the first insulating layer outside the at least one first via and the at least one second via. The gate further includes a second sub-gate portion. The second sub-gate portion is on a second portion of the second insulating layer.
In an embodiment of the present invention, the relative dielectric constant of the second insulating layer is greater than or equal to the relative dielectric constant of the first insulating layer.
In an embodiment of the invention, the relative dielectric constant of the first insulating layer is1And 2 is less than or equal to1≤3。
In an embodiment of the invention, the relative permittivity of the second insulating layer is2And 2.5 is less than or equal to2≤15。
In an embodiment of the invention, the semiconductor layer includes an organic semiconductor material.
In an embodiment of the invention, the pixel structure further includes a data line and a scan line. The data line is electrically connected with the source electrode of the thin film transistor. The scanning line is electrically connected with the grid electrode of the thin film transistor. The grid electrode is overlapped with the source electrode, the drain electrode, at least one first through hole of the channel and at least one second through hole of the first insulating layer.
Based on the above, in the thin film transistor of the pixel structure according to the embodiment of the invention, through the arrangement of the first through hole of the semiconductor layer, the gate of the thin film transistor can attract carriers to move to the top surface of the semiconductor layer to form the primary channel, and can further attract carriers to move to the sidewall of the semiconductor layer to form the secondary channel. Therefore, the number of channels of the thin film transistor is increased, so that the turn-on current of the thin film transistor is increased, and the sub-critical swing is improved.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a top view of a pixel structure according to an embodiment of the invention.
Fig. 2 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the invention.
Fig. 3 is a schematic perspective view of a source, a drain and a channel of a thin film transistor according to an embodiment of the invention.
Fig. 4 is a plan view of a pixel structure of a comparative example.
Fig. 5 is a schematic cross-sectional view of a thin film transistor of a comparative example.
Fig. 6 shows a comparison of threshold voltages of tfts of a plurality of pixel structures according to a comparative example and threshold voltages of tfts of a plurality of pixel structures according to an embodiment of the present invention.
Fig. 7 shows a comparison of the sub-threshold swing of the tfts of the pixel structures of the comparative example and the sub-threshold swing of the tfts of the pixel structures of the embodiment of the invention.
Fig. 8 shows the relationship between the gate voltage and the uniform drain current of the thin film transistor of the pixel structure of the comparative example and the relationship between the gate voltage and the uniform drain current of the thin film transistor of the pixel structure of the embodiment of the present invention.
Fig. 9 shows the relationship between the channel length of the tft of the pixel structure and the threshold voltage shift of the pixel structure of the comparative example and the relationship between the channel length of the tft of the pixel structure and the threshold voltage shift of the pixel structure of the embodiment of the present invention.
Description of reference numerals:
100. 200: pixel structure
110: substrate
120: planarization layer
130. 230: semiconductor layer
132. 232: channel
132 a: first through hole
132s1, 140s 1: side wall
132s 2: bottom surface
132s 3: the top surface
140: a first insulating layer
140 a: second through hole
150: a second insulating layer
152: the first part
152 a: depressions
154: the second part
160: pixel electrode
D. D2: drain electrode
D L data line
d1, d 2: thickness of
G. G2: grid electrode
Gs: first sub-gate part
Gm: second sub-gate part
L channel length
S, S2: source electrode
S L scanning line
S11, S12, S13, S21, S22, S23: curve line
SS1, SS 2: sub-critical amplitude of oscillation
T1, T2: thin film transistor
Vth1, Vth 2: critical voltage
x, y, z: direction of rotation
I-I ', II-II': cutting line
Detailed Description
In the drawings, the thickness of layers, films, panels, regions, etc. have been exaggerated for clarity. Like reference numerals refer to like elements throughout the specification. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connections. Further, "electrically connected" and "coupled" may mean that there are additional elements between the elements.
As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within an acceptable range of deviation of the specified value as determined by one of ordinary skill in the art, taking into account the measurement in question and the specified amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the stated value, or within ± 30%, ± 20%, ± 10%, ± 5%. Further, as used herein, "about", "approximately" or "substantially" may be selected based on optical properties, etch properties, or other properties, with a more acceptable range of deviation or standard deviation, and not all properties may be applied with one standard deviation.
Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region shown or described as flat may generally have rough and/or nonlinear features. Further, the acute angles shown may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.
Fig. 1 is a top view of a pixel structure according to an embodiment of the invention. Fig. 2 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the invention. In particular, FIG. 2 corresponds to section line I-I' of FIG. 1. For clarity of illustration, some of the figures are labeled with an xyz rectangular coordinate system, where directions x, y, z are perpendicular.
Referring to fig. 1 and 2, the pixel structure 100 is disposed on a substrate 110. For example, in the present embodiment, an insulating planarization layer 120 may be disposed on the substrate 110, and the pixel structure 100 may be disposed on the planarization layer 120. However, the invention is not limited thereto, and in other embodiments, the pixel structure 100 may be directly disposed on the substrate 110. The substrate 110 is mainly used for carrying the pixel structure 100. In the present embodiment, the substrate 110 may be made of glass, quartz, organic polymer, or opaque/reflective material (e.g., wafer, ceramic, or other suitable material), or other suitable material.
The pixel structure 100 includes a tft T1 and a pixel electrode 160 (shown in fig. 1) electrically connected to a drain D of the tft T1, the tft T1 includes a source S, a drain D, a semiconductor layer 130, a first insulating layer 140, a second insulating layer 150, and a gate G, the source S and the drain D are separated from each other, in this embodiment, the source S and the drain D may be selectively disposed on the planarization layer 120, but the present invention is not limited thereto, in this embodiment, the pixel structure 100 further includes a data line D L (shown in fig. 1), the data line D L is electrically connected to the source S of the tft T1, for example, in this embodiment, the source S may be a branch extending outward from the data line D L, but the present invention is not limited thereto, in other embodiments, the source S may also be a portion of the data line D L, in this embodiment, the pixel structure 100 further includes a scan line S L (shown in fig. 1), the scan line S L is electrically connected to the gate G of the tft T634, in this embodiment, the present invention may also be a branch extending from the gate S L, but may also be a branch extending from the gate S L.
However, the invention is not limited thereto, and in other embodiments, the scan line S L and the gate G may also belong to different layers.
The semiconductor layer 130 is disposed on the source S and the drain D. The semiconductor layer 130 covers the source S and the drain D. The source S and the drain D are electrically connected to two different regions of the semiconductor layer 130, respectively. The semiconductor layer 130 has a channel 132. The channel 132 is disposed between the source S and the drain D. In detail, in the present embodiment, the channel 132 refers to a region of the semiconductor layer 130 located between the source S and the drain D and overlapping the gate G in the direction z. In the present embodiment, the material of the semiconductor layer 130 is, for example, an organic semiconductor material. However, the invention is not limited thereto, and in other embodiments, the material of the semiconductor layer 130 may also be amorphous silicon, polycrystalline silicon, microcrystalline silicon, monocrystalline silicon, an oxide semiconductor material (for example, indium zinc oxide, indium germanium zinc oxide, or other suitable materials, or combinations thereof), or other suitable materials, or contain a dopant (dopant) therein, or combinations thereof.
Fig. 3 is a schematic perspective view of a source, a drain and a channel of a thin film transistor according to an embodiment of the invention. Referring to fig. 1, 2 and 3, the channel 132 of the tft T1 has at least one first via 132 a. Fig. 1, fig. 2 and fig. 3 illustrate three first through holes 132a, but the invention is not limited thereto, and the number of the first through holes 132a of the channel 132 may be determined according to actual requirements; in other embodiments, the number of the first through holes 132a of the channel 132 may be other suitable values. The first via 132a of the via 132 defines a plurality of sidewalls 132s1 of the semiconductor layer 130. The channel 132 has a bottom surface 132s2 facing the substrate 110 and a top surface 132s3 facing away from the substrate 110, and the sidewalls 132s1 are connected between the bottom surface 132s2 and the top surface 132s 3. For example, in the present embodiment, the length direction of the channel 132 is substantially parallel to the direction x, the sidewall 132s1 defined by the first through hole 132a of the channel 132 is substantially located on the xz plane, and the top surface 132s3 of the channel 132 is substantially located on the xy plane (e.g., the xy plane in the z direction away from the origin), but the invention is not limited thereto.
Referring to fig. 1 and 2, the first insulating layer 140 is disposed on the semiconductor layer 130 and has at least one second via 140 a. Fig. 1 and fig. 2 illustrate three second through holes 140a, but the invention is not limited thereto, and the number of the second through holes 140a of the first insulating layer 140 may depend on actual requirements; in other embodiments, the number of the second through holes 140a of the first insulating layer 140 may be other suitable values.
The second via 140a of the first insulating layer 140 substantially overlaps the first via 132a of the channel 132. In other words, the second through hole 140a of the first insulating layer 140 communicates with the first through hole 132a of the channel 132. In the present embodiment, the first insulating layer 140 has a plurality of sidewalls 140s1 defined by the second via 140a, the via 132 has a plurality of sidewalls 132s1 defined by the first via 132a, and the sidewalls 140s1 of the first insulating layer 140 and the sidewalls 132s1 of the via 132 are substantially aligned. For example, in the process of the pixel structure 100 of the present embodiment, a semiconductor material layer (not shown) and a first insulating material layer (not shown) may be sequentially formed on the substrate 110; then, the semiconductor material layer and the first insulating material layer are simultaneously patterned by using the same mask to form a semiconductor layer 130 and a first insulating layer 140. Therefore, in the present embodiment, the semiconductor layer 130 and the first insulating layer 140 can be substantially aligned (or overlapped), but the invention is not limited thereto. In other embodiments, the sidewall 140s1 of the first insulating layer 140 may be recessed within the sidewall 132s1 of the channel 132 or the sidewall 140s1 of the first insulating layer 140 may protrude from the sidewall 132s1 of the channel 132, and the sidewall 140s1 of the first insulating layer 140 may be located in a portion of the first via 132 a.
The second insulating layer 150 is located on the first insulating layer 140 and in the second via 140a of the first insulating layer 140 and the first via 132a of the channel 132. For example, in the present embodiment, the second insulating layer 150 includes a first portion 152 and a second portion 154; the first portion 152 is located in the second via 140a of the first insulating layer 140 and the first via 132a of the channel 132; the second portion 154 is located outside the second via 140a of the first insulating layer 140 and the first via 132a of the channel 132, and is located on the first insulating layer 140. The first portion 152 of the second insulating layer 150 covers the sidewall 140s1 defined by the second via 140a of the first insulating layer 140 and the sidewall 132s1 defined by the first via 132a of the channel 132. Preferably, in the present embodiment, the first portion 152 of the second insulating layer 150 may directly cover the sidewall 140s1 and the sidewall 132s1, and contact the sidewall 140s1 and the sidewall 132s1, but the invention is not limited thereto.
In the present embodiment, the thickness d2 of the second insulating layer 150 can be smaller than the thickness d1 of the first insulating layer 140, but not limited thereto. The thickness D2 may refer to the thickness of the portion of the second insulating layer 150 directly above the source S and/or drain D. The thickness D1 may refer to the thickness of the portion of the first insulating layer 140 directly above the source S and/or the drain D. In the present embodiment, the relative permittivity of the second insulating layer 150 may be greater than that of the first insulating layer 140. The relative permittivity of the second insulating layer 150 is a permittivity relative to vacuum; similarly, the relative permittivity of the first insulating layer 140 refers to a permittivity relative to vacuum. For example, in the present embodiment, the relative dielectric constant of the first insulating layer 140 is1The second insulating layer 150 has a relative dielectric constant of2，2≤1≤3，2.5≤215 or less, but the invention is not limited thereto. In the embodiment, the material of the first insulating layer 140 includes, for example, polymethyl methacrylate (PMMA), Polyisobutylene (PIB), polyethylene (P E), polypropylene (PP), polystyrene (P S), poly-4-vinylphenol (PVP), polyvinyl alcohol (PVA) or its copolymer, or other suitable organic material, or other suitable material, the material of the second insulating layer 150 includes, for example, parylene (p-xylylene), or other suitable organic materialMaterials, or other suitable inorganic materials, or other suitable materials, but the invention is not limited thereto.
The gate G is on the second insulating layer 150. The gate G overlaps the source S, the drain D, the first via 132a of the channel 132, and the second via 140a of the first insulating layer 140. In the present embodiment, the second insulating layer 150 may conformally (conformally) cover the semiconductor layer 130, the first insulating layer 140, the first via 132a and the second via 140a, and the first portion 152 of the second insulating layer 150 in the first via 132a and the second via 140a has a recess 152 a. In the present embodiment, the gate G includes a first sub-gate portion Gs and a second sub-gate portion Gm. Part of the first sub-gate portion Gs is located in the recess 152a of the first portion 152 of the second insulating layer 150. The first sub-gate portion Gs overlaps with at least part of the side wall 132s1 of the channel 132 in the direction y. The first sub-gate Gs covers at least a portion of the sidewall 132s1 of the channel 132 and is used to attract carriers (not shown) to the sidewall 132s1 of the channel 132. The sidewall 132s1 of the channel 132 may be regarded as a secondary channel for transporting carriers, and the first sub-gate portion Gs may be regarded as a secondary gate portion. The second sub-gate portion Gm is located on the second portion 154 of the second insulating layer 150. The second sub-gate portion Gm covers the top surface 132s3 of the channel 132 and is used to attract carriers to the top surface 132s3 of the channel 132. The top surface 132s3 of the channel 132 may be regarded as a main channel for transporting carriers, and the second sub-gate portion Gm may be regarded as a main gate portion.
By providing the first via 132a of the channel 132, the gate G can attract carriers to move to the top surface 132s3 of the semiconductor layer 130 to form a main channel, and can attract carriers to move to the sidewall 132s1 of the semiconductor layer 130 to form a sub-channel. Therefore, the number of channels of the tft T1 increases, and the on current of the tft T1 increases, thereby improving the sub-threshold swing. In addition, in the present embodiment, the second insulating layer 150 is sandwiched between the first sub-gate portion Gs (i.e. the sub-gate portion) and the sidewall 132s1 of the channel 132 without sandwiching the first insulating layer 140, so that the first sub-gate portion Gs can more effectively attract carriers to the sidewall 132s1 of the semiconductor layer 130, thereby further increasing the on-current of the thin film transistor T1 and improving the sub-threshold swing.
Fig. 4 is a plan view of a pixel structure of a comparative example. Fig. 5 is a schematic cross-sectional view of a thin film transistor of a comparative example. In particular, fig. 5 corresponds to the section line ii-ii' of fig. 4. Referring to fig. 4 and 5, a pixel structure 200 of a comparative example is similar to the pixel structure 100, and the same reference numerals are used to indicate the same or similar parts in the drawings and the description. The pixel structure 200 of the comparative example includes a thin film transistor T2 and a pixel electrode 160 electrically connected to the thin film transistor T2. The thin film transistor T2 of the comparative example also includes a source electrode S2, a gate electrode G2, a drain electrode D2, and a semiconductor layer 230. The pixel structure 200 of the comparative example is different from the pixel structure 100 in that the channel 232 of the tft T2 of the pixel structure 200 does not have the first via 132a nor the second via 140 a.
Fig. 6 shows a comparison of the threshold voltage Vth2 of the tft T2 of the pixel structures 200 and the threshold voltage Vth1 of the tft T1 of the pixel structure 100 according to the embodiment of the invention. Referring to fig. 6, the average value of the threshold voltage Vth2 of the tft T2 of the comparative example at each position is-4.43V, and the average value of the threshold voltage Vth1 of the tft T1 of the present embodiment at each position is-3.23V. As can be seen from fig. 6, by the multi-channel (i.e., the main channel and the sub-channel) design, the average value of the threshold voltages of the tft T1 of the present embodiment is smaller in absolute value and better in electrical performance than the tft T2 of the comparative example.
Fig. 7 shows a comparison of the sub-threshold swing SS2 of the tft T2 of the pixel structures 200 and the sub-threshold swing SS1 of the tft T1 of the pixel structure 100 according to an embodiment of the present invention. Referring to FIG. 7, the average of the sub-threshold swing of the TFT T2 at each position is about 1078.65mV/decade, and the average of the sub-threshold swing of the TFT T1 at each position is about 683.02 mV/decade. As can be seen from fig. 7, by the multi-channel (i.e., the main channel and the sub-channel) design, the average value of the sub-threshold swing SS1 of the tft T1 of the present embodiment is smaller and better than that of the tft T2 of the comparative example.
Fig. 8 shows the relationship between the gate voltage and the uniform drain current of the tft T2 of the pixel structure 200 according to the comparative example and the relationship between the gate voltage and the uniform drain current of the tft T1 of the pixel structure 100 according to the embodiment of the present invention. Referring to fig. 8, curves S11 and S12 represent the relationship between the gate voltage and the uniform drain current of the tft T1 of the pixel structure 100 according to the embodiment of the invention, and curves S21 and S22 represent the relationship between the gate voltage and the uniform drain current of the tft T2 of the pixel structure 200 according to the comparative example. Wherein the drain driving voltage (Vd) of the curves S11 and S21 is about-10.1 volts, and the drain driving voltage (Vd) of the curves S12 and S22 is about-0.1 volts. As shown in fig. 8, when the drain driving voltage (Vd) is about-10.1 v, the tft T1 (curve S11) of the multi-channel (i.e., the major channel and the minor channel) design of the pixel structure 100 according to an embodiment of the present invention has a larger turn-on current and a preferred sub-threshold swing and is electrically better than the tft T2 (curve S21) of the comparative example; when the drain driving voltage (Vd) is about-0.1 v, the tft T1 (curve S12) of the multi-channel (i.e., the primary channel and the secondary channel) design of the pixel structure 100 according to the embodiment of the invention has a larger turn-on current and a preferred sub-threshold swing and is better than the tft T2 (curve S22) of the comparative example, and the tft T1 of the embodiment has a better electrical performance.
Fig. 9 shows a relationship between a channel length L (labeled in fig. 4) of the tft T2 of the pixel structure 200 and a threshold voltage shift, and a relationship between a channel length L (labeled in fig. 1) of the tft T1 of the pixel structure 100 according to an embodiment of the present invention and a threshold voltage shift, referring to fig. 9, a curve S13 represents a relationship between a channel length L of the tft T1 of the pixel structure 100 according to an embodiment of the present invention and a curve S23 represents a relationship between a channel length L of the tft T2 of the pixel structure 200 according to a comparative example and a threshold voltage shift, it can be demonstrated from fig. 9 that, through the above-mentioned multi-channel (i.e., the main channel and the sub-channel) design, the threshold voltage of the tft T1 of the present embodiment is less prone to shift excessively with a change in the channel length L, and is better in electrical performance than the tft T2 of the comparative example.
In summary, the pixel structure of the embodiment of the invention includes a thin film transistor and a pixel electrode electrically connected to the drain of the thin film transistor. The thin film transistor includes a source electrode, a drain electrode, a semiconductor layer, a first insulating layer, a second insulating layer, and a gate electrode. The semiconductor layer is located on the source electrode and the drain electrode and is provided with a channel. The channel is arranged between the source electrode and the drain electrode and is provided with a first through hole. The first insulating layer is located on the semiconductor layer and has a second via overlapping the first via. The second insulating layer is located on the first insulating layer and in the first through hole and the second through hole. The gate is located on the second insulating layer. Through the arrangement of the first through hole of the semiconductor layer, the grid electrode can attract carriers to move to the top surface of the semiconductor layer so as to form a main channel, and can attract the carriers to move to the side wall of the semiconductor layer so as to form a secondary channel. Therefore, the number of channels of the thin film transistor is increased, so that the turn-on current of the thin film transistor is increased, and the sub-critical swing is improved.
In addition, in an embodiment of the present invention, the first sub-gate portion (i.e., the sub-gate portion) and the sidewall of the channel sandwich the second insulating layer therebetween without sandwiching the first insulating layer; therefore, the first sub-gate portion can be close to the sidewall of the channel to more effectively attract carriers to the sidewall of the channel, thereby further increasing the on-current of the thin film transistor and improving the sub-threshold swing.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (11)
1. A pixel structure, comprising:
a thin film transistor, comprising:
a source and a drain;
a semiconductor layer located on the source electrode and the drain electrode and having a channel disposed between the source electrode and the drain electrode, wherein the channel has at least one first through hole;
a first insulating layer on the semiconductor layer and having at least one second via overlapping the at least one first via;
a second insulating layer on the first insulating layer and in the at least one first via and the at least one second via; and
a gate electrode covered along the second insulating layer; and
and the pixel electrode is electrically connected with the drain electrode of the thin film transistor.
2. The pixel structure of claim 1, wherein the via has sidewalls defined by the at least one first via, and the second insulating layer comprises:
a first portion disposed in the at least one first via and the at least one second via and covering the sidewalls of the channel.
3. The pixel structure of claim 2, wherein the first insulating layer has sidewalls defined by the at least one second via, and the first portion of the second insulating layer further directly covers the sidewalls of the first insulating layer.
4. The pixel structure of claim 3, wherein said sidewalls of said first insulating layer are aligned with said sidewalls of said channel.
5. The pixel structure of claim 2, wherein said first portion of said second insulating layer has a recess, and said gate comprises:
a first sub-gate portion in the recess of the second insulating layer and overlapping at least a portion of the sidewalls of the channel.
6. The pixel structure of claim 5, wherein the second insulating layer further comprises:
a second portion on the first insulating layer outside the at least one first via and the at least one second via, wherein the gate further comprises a second sub-gate portion, the second sub-gate portion of the gate being on the second portion of the second insulating layer.
7. The pixel structure of claim 1, wherein the relative permittivity of the second insulating layer is greater than or equal to the relative permittivity of the first insulating layer.
8. The pixel structure of claim 1, wherein the first insulating layer has a relative dielectric constant of1And 2 is less than or equal to1≤3。
9. The pixel structure of claim 1, wherein the second insulating layer has a relative dielectric constant of2And 2.5 is less than or equal to2≤15。
10. The pixel structure of claim 1, wherein said semiconductor layer comprises an organic semiconductor material.
11. The pixel structure of claim 1, further comprising:
a data line electrically connected to the source of the TFT; and
and the scanning line is electrically connected with the grid electrode of the thin film transistor, wherein the grid electrode is overlapped with the source electrode, the drain electrode, the at least one first through hole of the channel and the at least one second through hole of the first insulating layer.
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| TW106143961A TWI662347B (en) | 2017-12-14 | 2017-12-14 | Pixel structure |
| TW106143961 | 2017-12-14 |
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| CN1435864A (en) * | 2002-01-28 | 2003-08-13 | 株式会社半导体能源研究所 | Semiconductor device and mfg. method thereof |
| CN103000808A (en) * | 2011-09-12 | 2013-03-27 | 索尼公司 | Thin-film transistor and electronic unit |
| CN106663391A (en) * | 2013-12-02 | 2017-05-10 | 株式会社半导体能源研究所 | Display device and method for manufacturing the same |
| CN106898621A (en) * | 2017-01-25 | 2017-06-27 | 友达光电股份有限公司 | Pixel structure and manufacturing method thereof |
| CN107204362A (en) * | 2016-03-18 | 2017-09-26 | 株式会社日本显示器 | Semiconductor device |
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| US7358121B2 (en) * | 2002-08-23 | 2008-04-15 | Intel Corporation | Tri-gate devices and methods of fabrication |
| JP5656049B2 (en) * | 2010-05-26 | 2015-01-21 | ソニー株式会社 | Thin film transistor manufacturing method |
| US8871565B2 (en) * | 2010-09-13 | 2014-10-28 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| US8232164B2 (en) * | 2010-10-29 | 2012-07-31 | International Business Machines Corporation | Damascene method of forming a semiconductor structure and a semiconductor structure with multiple fin-shaped channel regions having different widths |
| US9799773B2 (en) * | 2011-02-02 | 2017-10-24 | Semiconductor Energy Laboratory Co., Ltd. | Transistor and semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1435864A (en) * | 2002-01-28 | 2003-08-13 | 株式会社半导体能源研究所 | Semiconductor device and mfg. method thereof |
| CN103000808A (en) * | 2011-09-12 | 2013-03-27 | 索尼公司 | Thin-film transistor and electronic unit |
| CN106663391A (en) * | 2013-12-02 | 2017-05-10 | 株式会社半导体能源研究所 | Display device and method for manufacturing the same |
| CN107204362A (en) * | 2016-03-18 | 2017-09-26 | 株式会社日本显示器 | Semiconductor device |
| CN106898621A (en) * | 2017-01-25 | 2017-06-27 | 友达光电股份有限公司 | Pixel structure and manufacturing method thereof |
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| TWI662347B (en) | 2019-06-11 |
| CN108231802A (en) | 2018-06-29 |
| TW201928484A (en) | 2019-07-16 |
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