TWI661323B - 模擬方法，模擬程式，製程控制系統，模擬器，製程設計方法及光罩設計方法 - Google Patents

模擬方法，模擬程式，製程控制系統，模擬器，製程設計方法及光罩設計方法 Download PDF

Info

Publication number
TWI661323B
TWI661323B TW103136187A TW103136187A TWI661323B TW I661323 B TWI661323 B TW I661323B TW 103136187 A TW103136187 A TW 103136187A TW 103136187 A TW103136187 A TW 103136187A TW I661323 B TWI661323 B TW I661323B
Authority
TW
Taiwan
Prior art keywords
wafer
mask
etching
aperture ratio
rate
Prior art date
Application number
TW103136187A
Other languages
English (en)
Chinese (zh)
Other versions
TW201520803A (zh
Inventor
Nobuyuki Kuboi
久保井信行
Takashi Kinoshita
木下隆
Original Assignee
Sony Semiconductor Solutions Corporation
索尼半導體解決方案公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Semiconductor Solutions Corporation, 索尼半導體解決方案公司 filed Critical Sony Semiconductor Solutions Corporation
Publication of TW201520803A publication Critical patent/TW201520803A/zh
Application granted granted Critical
Publication of TWI661323B publication Critical patent/TWI661323B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32917—Plasma diagnostics
    • H01J37/32926—Software, data control or modelling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32—Processing objects by plasma generation
    • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
    • H01J2237/334—Etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/203—Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Plasma Technology (AREA)
TW103136187A 2013-11-28 2014-10-20 模擬方法，模擬程式，製程控制系統，模擬器，製程設計方法及光罩設計方法 TWI661323B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013245647A JP6173889B2 (ja) 2013-11-28 2013-11-28 シミュレーション方法、シミュレーションプログラム、加工制御システム、シミュレータ、プロセス設計方法およびマスク設計方法
JP2013-245647 2013-11-28

Publications (2)

Publication Number Publication Date
TW201520803A TW201520803A (zh) 2015-06-01
TWI661323B true TWI661323B (zh) 2019-06-01

Family

ID=53183798

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103136187A TWI661323B (zh) 2013-11-28 2014-10-20 模擬方法，模擬程式，製程控制系統，模擬器，製程設計方法及光罩設計方法

Country Status (3)

Country Link
US (1) US9431310B2 (https=)
JP (1) JP6173889B2 (https=)
TW (1) TWI661323B (https=)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7802917B2 (en) * 2005-08-05 2010-09-28 Lam Research Corporation Method and apparatus for chuck thermal calibration
JP6516603B2 (ja) * 2015-04-30 2019-05-22 東京エレクトロン株式会社 エッチング方法及びエッチング装置
US9865471B2 (en) * 2015-04-30 2018-01-09 Tokyo Electron Limited Etching method and etching apparatus
US10534257B2 (en) * 2017-05-01 2020-01-14 Lam Research Corporation Layout pattern proximity correction through edge placement error prediction
WO2019162346A1 (en) * 2018-02-23 2019-08-29 Asml Netherlands B.V. Methods for training machine learning model for computation lithography
US10572697B2 (en) 2018-04-06 2020-02-25 Lam Research Corporation Method of etch model calibration using optical scatterometry
US11921433B2 (en) 2018-04-10 2024-03-05 Lam Research Corporation Optical metrology in machine learning to characterize features
WO2019199697A1 (en) 2018-04-10 2019-10-17 Lam Research Corporation Resist and etch modeling
WO2020049974A1 (ja) 2018-09-03 2020-03-12 株式会社Ｐｒｅｆｅｒｒｅｄ Ｎｅｔｗｏｒｋｓ 学習装置、推論装置、学習モデルの生成方法及び推論方法
KR102541743B1 (ko) 2018-09-03 2023-06-13 가부시키가이샤 프리퍼드 네트웍스 학습 장치, 추론 장치 및 학습 완료 모델
JP7345382B2 (ja) * 2018-12-28 2023-09-15 東京エレクトロン株式会社 プラズマ処理装置及び制御方法
KR102565831B1 (ko) * 2019-01-28 2023-08-09 양쯔 메모리 테크놀로지스 씨오., 엘티디. 더미 패턴을 설계하는 시스템 및 방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030015660A1 (en) * 2001-07-19 2003-01-23 Chie Shishido Method and system for monitoring a semiconductor device manufacturing process
US20030230551A1 (en) * 2002-06-14 2003-12-18 Akira Kagoshima Etching system and etching method
US7363099B2 (en) * 2002-06-07 2008-04-22 Cadence Design Systems, Inc. Integrated circuit metrology
US20110082577A1 (en) * 2009-08-24 2011-04-07 Sony Corporation Shape simulation apparatus, shape simulation program, semiconductor production apparatus, and semiconductor device production method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5050830B2 (ja) * 2007-12-19 2012-10-17 ソニー株式会社 ドライエッチング装置および半導体装置の製造方法
JP5732843B2 (ja) * 2010-12-21 2015-06-10 ソニー株式会社 シミュレータ、加工装置、ダメージ評価方法、及び、ダメージ評価プログラム

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030015660A1 (en) * 2001-07-19 2003-01-23 Chie Shishido Method and system for monitoring a semiconductor device manufacturing process
US7363099B2 (en) * 2002-06-07 2008-04-22 Cadence Design Systems, Inc. Integrated circuit metrology
US20030230551A1 (en) * 2002-06-14 2003-12-18 Akira Kagoshima Etching system and etching method
US20110082577A1 (en) * 2009-08-24 2011-04-07 Sony Corporation Shape simulation apparatus, shape simulation program, semiconductor production apparatus, and semiconductor device production method

Also Published As

Publication number Publication date
US9431310B2 (en) 2016-08-30
JP6173889B2 (ja) 2017-08-02
JP2015103769A (ja) 2015-06-04
US20150149970A1 (en) 2015-05-28
TW201520803A (zh) 2015-06-01

Similar Documents

Publication Publication Date Title
TWI661323B (zh) 模擬方法，模擬程式，製程控制系統，模擬器，製程設計方法及光罩設計方法
US11101138B2 (en) Etching method
KR102329354B1 (ko) 시뮬레이션 방법, 시뮬레이션 프로그램, 가공 장치, 시뮬레이터 및 설계 방법
US10998174B2 (en) Dry etching equipment and method for producing semiconductor device
KR102422230B1 (ko) 엔드포인트 검출을 위한 에칭 계측 민감도
JP7182565B2 (ja) エッジ配置誤差予測を用いた設計レイアウトパターン近接効果補正
TWI611478B (zh) 藉由修整時間和溫度逐晶圓控制臨界尺寸及臨界尺寸均勻性
US9859103B2 (en) Process control device, recording medium, and process control method
US9411914B2 (en) Simulator, processing system, damage evaluation method and damage evaluation program
TWI732440B (zh) 電漿處理方法及電漿處理裝置
CN103514318A (zh) 模拟方法、计算机可读介质、处理装置及模拟器
JP5397215B2 (ja) 半導体製造装置、半導体装置の製造方法、シミュレーション装置及びシミュレーションプログラム
CN103809462A (zh) 模拟方法及程序、模拟器、加工设备和制造半导体装置的方法
US10534355B2 (en) Information processing device, processing device, prediction method, and processing method
Kim et al. Application of Plasma Information-Based Virtual Metrology (PI-VM) for Etching in C₄F₈/Ar/O₂ Plasma
WO2017049175A1 (en) Systems and methods for controlling an etch process
US10403516B2 (en) Etching characteristic estimation method, program, information processing apparatus, processing apparatus, designing method, and production method
JP6886016B2 (ja) 粒子線を用いて表面を処理する方法
US20190080923A1 (en) Plasma etching method and method of fabricating semiconductor device
JP2013115354A (ja) シミュレーション方法、シミュレーションプログラム、半導体製造装置
JP2007193037A (ja) フォトマスクの製造方法
CN116092919A (zh) 一种晶圆控片的重复使用方法
US20170364624A1 (en) Method of calculating processed depth and storage medium storing processed-depth calculating program

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees