TWI658936B - 覆蓋膜及其應用 - Google Patents

覆蓋膜及其應用 Download PDF

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Publication number
TWI658936B
TWI658936B TW107104265A TW107104265A TWI658936B TW I658936 B TWI658936 B TW I658936B TW 107104265 A TW107104265 A TW 107104265A TW 107104265 A TW107104265 A TW 107104265A TW I658936 B TWI658936 B TW I658936B
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Taiwan
Prior art keywords
layer
polyimide layer
polyimide
cover film
conductor structures
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TW107104265A
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English (en)
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TW201934342A (zh
Inventor
林聖欽
吳耀明
陳彥翔
陳憶明
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台虹科技股份有限公司
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Priority to TW107104265A priority Critical patent/TWI658936B/zh
Priority to CN201810204635.1A priority patent/CN110117418B/zh
Priority to US15/942,583 priority patent/US20190244927A1/en
Application granted granted Critical
Publication of TWI658936B publication Critical patent/TWI658936B/zh
Publication of TW201934342A publication Critical patent/TW201934342A/zh

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    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • C08G—MACROMOLECULAR COMPOUNDS OBTAINED OTHERWISE THAN BY REACTIONS ONLY INVOLVING UNSATURATED CARBON-TO-CARBON BONDS
    • C08G73/00—Macromolecular compounds obtained by reactions forming a linkage containing nitrogen with or without oxygen or carbon in the main chain of the macromolecule, not provided for in groups C08G12/00 - C08G71/00
    • C08G73/06—Polycondensates having nitrogen-containing heterocyclic rings in the main chain of the macromolecule
    • C08G73/10—Polyimides; Polyester-imides; Polyamide-imides; Polyamide acids or similar polyimide precursors
    • C08G73/1042—Copolyimides derived from at least two different tetracarboxylic compounds or two different diamino compounds
    • C—CHEMISTRY; METALLURGY
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    • C08G73/10—Polyimides; Polyester-imides; Polyamide-imides; Polyamide acids or similar polyimide precursors
    • C08G73/1075—Partially aromatic polyimides
    • C08G73/1082—Partially aromatic polyimides wholly aromatic in the tetracarboxylic moiety
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Abstract

一種覆蓋膜，包括離型層以及設置於離型層上的聚醯亞胺層，聚醯亞胺層包括相對設置之內表面和外表面，外表面係直接暴露於大氣中，聚醯亞胺層係經由包括二胺單體和四羧酸二酐單體的一聚醯亞胺組成物反應所形成，且該聚醯亞胺層還包括架橋劑以及起始劑，其中該二胺單體係選自總碳數大於等於36的脂肪族二胺單體，且在溫度介於60℃至160℃之間時，聚醯亞胺層之最低黏度係小於20000Pa·s。

Description

覆蓋膜及其應用
本發明是有關於一種覆蓋膜以及其應用方法。
隨著電子工業蓬勃發展，聚醯亞胺層因為具有極佳的熱穩定性、高耐化性等優異性質，如今已被廣泛應用於電子工業上，例如IC晶片保護膜、金屬層間絕緣材料、軟性電路板及封裝材料等。然而，隨著電腦、通訊、光電產業之相關產品逐漸朝向輕薄的趨勢發展，產業無不追求更高性能表現的材料，因此聚醯亞胺層仍然具有介電性質不佳、吸濕性不佳以及楊氏模數高以致反發力強的缺點需要克服。此外，傳統半導體封裝結構所使用之聚醯亞胺層還具有不易壓合加工、環化溫度高以及環化時體積收縮率過大的缺點。又，對於使用聚醯亞胺層作為半導體元件表面之導體結構間的絕緣層的情況，目前產業中所使用的聚醯亞胺層仍無法填充高深寬比的孔洞（例如：深寬比高於2的孔洞），此實為目前產業中亟待克服的課題。
本發明提供一種覆蓋膜，包括離型層及設置於該離型層上的聚醯亞胺層。聚醯亞胺層包括相對設置之內表面和外表面，其外表面係直接暴露於大氣中。聚醯亞胺層係經由包括二胺單體和四羧酸二酐單體的聚醯亞胺組成物反應所形成，且聚醯亞胺層還包括架橋劑以及起始劑。聚醯亞胺組成物的二胺單體係選自總碳數大於等於36以上的脂肪族二胺單體。在溫度介於60℃至160℃之間時，聚醯亞胺層之最低黏度係小於20000 Pa·s。
本發明另提供一種半導體元件表面的絕緣層的製作方法，包括以下步驟。首先，提供一第一半導體元件，該第一半導體元件的表面具有複數個第一導體結構。接著，將第一半導體元件直接接觸覆蓋膜的聚醯亞胺層。之後，對覆蓋膜進行熱壓製程，使聚醯亞胺層填滿第一導體結構之間的至少一縫隙，使得第一導體結構被該聚醯亞胺層環繞。在進行熱壓製程之後，移除離型層。
為了使本領域通常知識者能理解並實施本發明，下文中將配合圖式，詳細說明本發明之覆蓋膜及半導體元件表面的絕緣層的製作方法。需注意的是，本發明之保護範圍當以後附之申請專利範圍所界定者為準，而非以揭露於下文之實施例為限。因此，在不違背本發明之發明精神和範圍之狀況下，當可對下述實施例作變化與修飾。此外，為了簡潔與清晰起見，相同或類似之元件或裝置係以相同之元件符號表示，且部分習知的結構和製程細節將不會被揭露於下文中。需注意的是，圖式係以說明為目的，並未完全依照原尺寸繪製。
本發明提供一種覆蓋膜，包括離型層以及設置於離型層上的聚醯亞胺層。聚醯亞胺層包括相對設置之內表面和外表面，其外表面係直接暴露於大氣中。換句話說，本發明的覆蓋膜可以為僅包括離型層以及聚醯亞胺層的雙層結構，且聚醯亞胺層相反於離型層的表面未被任何層覆蓋。此外，聚醯亞胺層係經由聚醯亞胺組成物反應所形成，該聚醯亞胺組成物包括二胺單體、含有選自羥基、羧基及C=C(烯烴基)的基團的單體及四羧酸二酐單體。此外，聚醯亞胺層中還另殘留有架橋劑以及起始劑。其中，聚醯亞胺組成物的二胺單體可採用一種或多種二胺單體，且至少包括長碳鏈脂肪族的二胺單體，例如是選自總碳數大於等於36的脂肪族二胺單體。由於本發明的聚醯亞胺層透過使用選自總碳數大於等於36的脂肪族二胺單體而被加以合成，因而可達成在溫度介於60℃至160℃之間時，聚醯亞胺層之最低黏度係小於20000 Pa·s的目的。此外，透過使用選自總碳數大於等於36的脂肪族二胺單體，而使得相應製得的聚醯亞胺層能夠同時具有低介電常數、低介電損耗、低吸濕率、低楊氏模數及提高可溶性的性質。以下，將對上述各種組分進行詳細說明。
上述的二胺單體包括含有環己烷基的二胺單體，例如是4,4'-二氨基二環己基甲烷(4,4'-diaminodicyclohexyl methane，簡稱MBCHA)、1,3-二氨甲基環己烷(1,3-diaminomethylcyclohexane)、1,4-二氨甲基環己烷(1,4-diaminomethylcyclohexane)、雙氨甲基雙環[2.2.1]庚烷(bis(aminomethyl)bicyclo[2.2.1]heptane)、二氨甲基環己基甲烷(4,4'-methylenebis(2-methylcyclohexylamine))。另外，用以反應形成聚醯亞胺層的二胺單體更包括其他的二胺單體，例如2,2’-雙[4-(4-氨基苯氧基苯基)]丙烷(2,2’-bis[4-(4-aminophenoxy)phenyl]propane，簡稱BAPP)、4,4’-二氨基二苯甲烷(4,4’-methylene dianiline)、α,α’-二(4-氨基苯基)-1,4-二異丙基苯(α,α’-bis(4-aminophenyl)-1,4-diisopropylbenzene)、4,4’-二氨基二苯醚(4,4’-oxydianiline)、3,3’-二甲基-4,4’-二氨基聯苯(3,3’-dimethyl-4,4’-diaminobiphenyl)或1,4-雙(4-氨基苯氧基)苯(1,4-Bis(4-aminophenoxy)benzene)。較佳而言，上述的二胺單體可包括總碳數大於等於36的脂肪族二胺單體，其係由油酸等不飽和脂肪酸的二聚體之二聚酸(dimer acid)所衍生的化合物。
上述的聚醯亞胺組成物還包括選自羥基、羧基及C=C的基團的單體，其中包括含有羥基的二胺單體、含有羧基的酸酐單體、含有羧基的二胺單體及含有C=C基團的二胺單體。並且，前述所列舉的單體可單獨使用或混合使用。值得一提的是，當用以反應形成聚醯亞胺層的聚醯亞胺組成物具有羥基、羧基或C=C的基團時，可以提高聚醯亞胺層的可溶解性，並且能夠再交聯。
具體而言，含有羥基的二胺單體包括但不限於：3,3’-二 羥基-4,4’-二氨基聯苯(3,3’-Dihydroxy-4,4’-diamino-biphenyl，簡稱HAB)；含有羧基的酸酐單體包括但不限於：偏苯三甲酸酐(trimellitic acidanhydride，簡稱TMA)；含有羧基的二胺單體包括但不限於：3,5-二氨基苯甲酸(3,5-diaminobenzoic acid，簡稱DABZ)、6,6’-雙氨基-3,3’-甲叉基二苯甲酸(methylene bis(anthranilic acid)，簡稱MBAA)；含有C=C基團的、包括但不限於： 2-乙烯基-4,6-二氨基-1,3,5-三嗪(2-vinyl-4,6-diamino-1,3,5-triazine)、2,4-二氨基-6-(異丁烯醯氧基)乙基-1,3,5-三嗪(2,4-diamino-6-(methacryloyloxy)ethyl-1,3,5-triazine)。在另一實施方式中，含有選自羥基、羧基及C=C的基團的單體例如包括偏苯三甲酸酐及3,5-二氨基苯甲酸。
另外，上述用以反應形成聚醯亞胺層的聚醯亞胺組成物中的四羧酸二酐單體可以是所屬領域中具有通常知識者所周知的任一四羧酸二酐化合物。具體而言，四羧酸二酐單體包括但不限於：4,4’-氧雙鄰苯二甲酸酐(Bis-(3-phthalyl anhydride)ether，簡稱ODPA)、3,3’,4,4’-二苯甲酮四甲酸二酐(3,3’,4,4’-Benzophenonetetracarboxylic dianhydride，簡稱BTDA)、均苯四甲酸二酐(Pyromellitic Dianhydride，簡稱PMDA)、雙酚A型二醚二酐(4,4’-(4,4’-isopropylidenediphenoxy)bis(phthalic anhydride)，簡稱BPADA)或3,3’,4,4’-聯苯四羧酸二酐(3,3’,4,4’-Biphenyltetracarboxylic dianhydride，簡稱BPDA)。進一步而言，在本發明中，前述所列舉的四羧酸二酐單體可單獨使用或混合使用。
本發明之聚醯亞胺層還包括架橋劑以及起始劑。架橋劑包括含有環氧基、異氰酸酯基或烯烴基的化合物。具體而言，架橋劑包括但不限於：酚醛型環氧樹脂(phenolnovolac type epoxy resin)、萘型環氧樹脂(naphthalene type epoxy resin)或雙酚A型環氧樹脂(bisphenolA type epoxy resin)。另外，作為含有環氧基的架橋劑可使用市售產品，例如CNE-200EL或PNE-177(CCP長春公司製造)、EPOXY 4700(DIC公司製造)或ESCV-90CR(新日鐵化學公司製造)；以及作為含有異氰酸酯基的架橋劑可使用市售產品，例如Desmodur N 3600或Desmodur VK10(Bayer公司製造)；以及作為含有烯烴基的架橋劑，例如三烯丙基異三聚氰酸酯(triallyl isocyanurate，簡稱TAIC)。起始劑包括過氧化物及光起始劑。具體而言，起始劑包括但不限於：過氧化苯甲醯(benzoyl peroxide，簡稱BPO)、過氧化叔丁醇(tert-Butylhydroperoxide，簡稱TBH)或過氧化雙月桂醯(Dilauroyl peroxide)。
值得說明的是，本發明中架橋劑能夠與含有羥基或羧基的單體中的羥基或羧基進行交聯反應，而起始劑能夠協助含有C=C的單體中的C=C進行交聯反應。也就是說，若上述用以反應形成聚醯亞胺層的聚醯亞胺組成物使用了含有羥基或羧基的單體，則選擇使用架橋劑；而若上述用以反應形成聚醯亞胺層的聚醯亞胺組成物使用了含有C=C的單體，則選擇使用起始劑及加入包含C=C基團的架橋劑。如此一來，用以形成可溶性聚醯亞胺的組成物透過包括含有選自羥基、羧基及C=C的基團的單體以及架橋劑或起始劑，使得經其製得的聚醯亞胺層能夠具有良好的耐化性及耐熱性。
結合以上所述，本發明之覆蓋膜的聚醯亞胺層除了係經由上述二胺單體、含有選自羥基、羧基及C=C的基團的單體、四羧酸二酐單體的聚醯亞胺組成物反應而形成，並且還透過上述架橋劑或起始劑進行交聯反應。此外，須注意的是，由於聚醯亞胺層中還包括未鍵結的架橋劑和起始劑，因此在後續的熱壓製程中，聚醯亞胺層可以具有適當的流動性，且可以進一步發生聚合反應。也就是說，本發明之覆蓋膜的聚醯亞胺層是一種分子量較低的預聚物，其尚未和全部的架橋劑及起始劑進行交聯反應並提升分子量。舉例而言，上述尚未與聚醯亞胺層完全進行鍵結的架橋劑和起始劑佔聚醯亞胺層中全部樹脂的範圍為大於0重量百分比且小於或等於50重量百分比，但不以此為限。
另外，在不損及本發明的聚醯亞胺層的效果範圍內，用以形成聚醯亞胺層的聚醯亞胺組成物可依需要加入添加劑。所述添加劑包括耐燃劑、著色劑、填充劑或其組合物。值得一提的是，填充劑包括二氧化矽及碳酸鈣，能夠提升聚醯亞胺層在後續製程步驟中的流變性及壓合製程中的壓合流動性。
本發明的覆蓋膜的聚醯亞胺層是由上述聚醯亞胺組成物反應所形成。以下，將對反應步驟進行詳細說明。首先，將二胺單體、含有選自羥基、羧基及C=C的基團的單體以及四羧酸二酐單體溶於溶劑中，並進行反應以形成聚醯胺酸溶液。溶劑包括所屬領域中具有通常知識者所周知的任一溶劑，包括但不限於：甲苯、二甲苯、環己烷、環己酮、N-甲基吡咯烷酮(NMP)、二甲基乙醯胺、二甲基甲醯胺或其混合物。其中，進行反應的時間例如是介於1小時至6小時之間；聚醯胺酸溶液的固含量例如是介於10%至50%之間，但不限於此。接著，對聚醯胺酸溶液進行環化製程以形成聚醯亞胺溶液。在此步驟中，環化製程的製程溫度例如是介於160℃至200℃之間；製程時間例如是介於1小時至6小時之間；聚醯亞胺溶液的固含量例如是介於10%至50%之間，但不限於此。之後，將上述架橋劑或起始劑加入聚醯亞胺溶液，以形成聚醯亞胺混合溶液。在一實施例中，聚醯亞胺混合溶液可包括可溶性聚醯亞胺、架橋劑、起始劑及溶劑。
接著，將聚醯亞胺混合溶液塗佈於離型層上，並以介於100℃至160℃之間的溫度乾燥3分鐘至5分鐘，以於離型層上形成本發明之聚醯亞胺層。其中，塗佈方式包括但不限於刮刀式塗佈、線棒式塗佈或網版印刷。另外，離型層例如是以對於後續步驟中形成的聚醯亞胺層提供足夠支撐力的離型膜來實現，具有良好的尺寸安定性。離型層可為平光或是啞光，藉以調整於後續步驟中形成的聚醯亞胺層的表面粗糙度及光澤度。
根據上述，可以得到本發明的覆蓋膜。其結構如第1圖所示，覆蓋膜10包括離型層12及形成於離型層12上的聚醯亞胺層14。由於本發明的覆蓋膜10之聚醯亞胺層14是先利用塗佈方式而將聚醯亞胺混合溶液形成在離型層12上，之後才進行加熱製程，故相比於習知上利用旋塗法製作的聚醯亞胺層而言，本發明的聚醯亞胺層可滿足更廣的膜厚範圍的需求，例如但不限於在1μm至20μm之間。藉由塗佈方式及塗液固含量的調整，甚至可得到厚度100μm以上的聚醯亞胺層，此為習知旋塗法無法容易得到的厚度。
根據本發明之一實施例，上述的覆蓋膜可以用於製作半導體元件表面的絕緣層，尤其是適用於表面具有多個突出導電結構的半導體元件，以下就此實施例加以敘述之。
請參考第2圖至第5圖。第2圖至第4圖為本發明第一應用例覆蓋膜用以製作半導體元件表面的絕緣層的製作方法的示意圖。第5圖為本發明第一應用例覆蓋膜用以製作封裝結構的示意圖。如第2圖所示，首先提供第一半導體元件100，包括第一部件102及設置於第一部件102上的複數個第一導體結構104，且該等第一導體結構104之間具有至少一縫隙105。第一部件102包括但不限於晶片(chip)、處理器(processor)、晶粒(die)、積體電路(IC)或其他主/被動元件相關的元件，且該第一部件102為所屬領域中具有通常知識者所周知的上述結構中表面該等第一導體結構104以外的部份。第一導體結構104包括但不限於選自銅、銀、錫或及上述至少兩者所組成的合金的組合所構成之群組。進一步而言，第一導體結構104可為任何符合半導體元件之機械強度要求的導體結構。
接著，參考第3圖，將第一導體結構104直接接觸本發明覆蓋膜106的聚醯亞胺層108。之後，對覆蓋膜106進行熱壓製程，使聚醯亞胺層108填滿第一導體結構104之間的至少一縫隙105，使得第一導體結構104被聚醯亞胺層108環繞。其中，熱壓製程的溫度可例如介於60°C至160°C之間，藉此使聚醯亞胺層108的黏度小於20000Pa·s，而具有適當之流動性。在熱壓後，再以160℃至200℃的固化溫度使聚醯亞胺層108中的架橋劑以及起始劑進一步產生反應，使得高分子鏈彼此之間進一步產生交聯，因而生成熱固性的聚醯亞胺層108。
根據上述，本發明半導體元件表面的絕緣層的製作方法係透過熱壓製程，致使覆蓋膜106的聚醯亞胺層108具有足夠的壓合流動性，而能夠填滿第一導體結構104之間深寬比大於等於3的縫隙。值得說明的是，覆蓋膜106填滿第一導體結構104之間深寬比之上限取決於第一導體結構104能夠承受熱壓製程且不被破壞的強度範圍。
接著，移除覆蓋膜106的離型層110以暴露出第一導體結構104的上表面104a，而獲得如第4圖所示之結構。在本實施方式中，移除離型層110後，可藉由電漿蝕刻或研磨等方式，使第一導體結構上表面104a和聚醯亞胺層上表面108b彼此共平面。
在完成第4圖所示之步驟後，可以進一步在第一導體結構104及聚醯亞胺層108上形成其他導電結構，其具體實施方式請參照下述。
請參考第5圖。如第5圖所示，在完成上述步驟後，可接著在聚醯亞胺層108上形成重佈線層112(redistribution layer)，且該重佈線層112和第一導體結構上表面104a接觸並電性連接。其中，重佈線層112包括至少一圖案化導電層114、至少一重佈導線116、至少一介電層118與至少一通孔118a，並且重佈導線116是設置於該通孔118a中。也就是說，重佈線層112可包含複數個介電層118與對應的複數個圖案化導電層114、重佈導線116及通孔118a，以使線路重佈。本實施例中，介電層118係使用本發明覆蓋膜106的聚醯亞胺層108作為材料，並以上述的熱壓製程製得。第5圖僅繪示一層介電層118和一層圖案化導電層114，但本發明不以此為限。接著，選擇性地在重佈線層112上形成複數個彼此分離的導電墊120，並且於各導電墊120上分別形成一錫球122或一金屬柱凸塊(metal pillar bump)，但不以此為限。其中，導電墊120例如為底部凸塊金屬(under bump metallization，簡稱UBM)層，用以提升重佈導線116與錫球122之間的黏著性、擴散阻障、銲錫潤濕與防止氧化等功能。綜上所述，第一部件102內部的導電線路與第一導體結構104、重佈線層112以及錫球122電性連接；該等第一導體結構104之間可具有深寬比大於等於3的縫隙並且被聚醯亞胺層108填充；介電層118可選擇性地使用本發明的聚醯亞胺層108，以此形成一封裝結構。
本發明的覆蓋膜並不以上述實施例為限，以下就其他的實施例加以介紹。為了更容易地比較實施例之間的差異，以下將詳細描述不同實施例之間的不同之處，並不再對相同的特徵作贅述。
請參考第6圖至第8圖。第6圖至第8圖為本發明第二應用例覆蓋膜用以製作半導體元件表面的絕緣層的製作方法的示意圖。本應用例中，覆蓋膜可用以形成覆晶封裝結構或藉由熱壓結合的封裝結構。如第6圖所示，首先提供第一半導體元件200，其包括第一部件202以及複數個第一導體結構204。第一半導體元件200可包括一基板，該基板包括印刷電路板、中介板(interposer)、矽基板以及玻璃基板，但不限於此。第一導體結構204可例如為接觸墊(contact pad)。接著，將第一導體結構204直接接觸本發明覆蓋膜106的聚醯亞胺層108，並且對該覆蓋膜106進行如前述的熱壓製程，使聚醯亞胺層108填滿第一導體結構204之間的至少一縫隙205，並且使得第一導體結構204被聚醯亞胺層108環繞。如第7圖所示，在進行熱壓製程之後，移除離型層110。接著，如第8圖所示，提供第二半導體元件210，包括第二部件214及設置於該第二部件214上的複數個第二導體結構212，且該等第二導體結構212係對應於該等第一導體結構204而設置。其中，第二部件214包括但不限於晶片、處理器、晶粒、積體電路或其他主/被動元件相關的元件。舉例而言，第二半導體元件210可以是本發明第一應用例所述的封裝結構，但不以此為限。將第一半導體元件200與第二半導體元件210彼此接合，並排開設置於該等第一導體結構204以及該等第二導體結構212之間的聚醯亞胺層108，致使該等第一導體結構204電連接對應的該等第二導體結構212。需要說明的是，將第一半導體元件200與第二半導體元件210彼此接合時，例如是使用所屬領域中具有通常知識者所周知的接合製程，例如熔融接合(fusion bonding)、金屬熱壓接合(metal thermal compression bonding)等，但不以此為限，熱壓時間180秒內，溫度為200℃至300℃。在本應用例中，第一導體結構204以及第二導體結構212之間的縫隙被本發明具有良好壓合流動性的聚醯亞胺層108填充。熱壓接合後，再以160℃至200℃的固化溫度，例如，使用壓力烘箱排除氣泡，並且使聚醯亞胺層108中的架橋劑以及起始劑進一步產生反應，使得高分子鏈彼此之間進一步產生交聯，因而生成熱固性的聚醯亞胺層108。
為了製作出易薄型化、介電性質佳、楊氏模數低且適合應用於本發明的覆蓋膜中的聚醯亞胺層，本發明提出一種聚醯亞胺的組成物，並且以此所製得的聚醯亞胺層可達到上述優點。以下，特舉實施例作為本發明確實能夠據以實施的範例。
以下藉由實施例與比較例來說明本發明覆蓋膜的製作方法，以進一步闡明本發明之技術特徵。
製備實施例1~2及比較例1的聚醯亞胺層及覆蓋膜所使用之主要材料的資訊如下所示。
四羧酸二酐單體：均苯四甲酸二酐(pyromellitic dianhydride，簡稱PMDA)。
長碳鏈脂肪族的二胺單體：商品名為PriamineTM 1074-Dimer diamine，日本禾大公司製造，其中主鏈的碳數為36。
含有選自羥基、羧基及C=C的基團的單體：3,5-二氨基苯甲酸(簡稱DABZ)，購自錦聿公司；4,4'-二氨基二環己基甲烷(簡稱MBCHA)，購自TCI公司；2-乙烯基-4,6-二氨基-1,3,5-三嗪(簡稱VT)，購自四國化成公司。
其他的二胺單體：2,2’-雙[4-(4-氨基苯氧基苯基)]丙烷(以下簡稱BAPP)，購自東信公司。
架橋劑：三環氧丙基異氰脲酸酯(tris(2, 3-epoxy propyl) isocyanurate，簡稱TEPIC)；三烯丙基異三聚氰酸酯(triallyl isocyanurate，簡稱TAIC)。
起始劑：過氧化苯甲醯(簡稱BPO)，見欣實業製造。
溶劑：環己酮，購自勝一化工公司；N-甲基吡咯烷酮(簡稱NMP)，購自波律公司。
離型膜：商品名為PET-50-SHP-A，購自Fujiko公司。
實施例1：
首先，將10莫耳的四羧酸二酐單體PMDA、6莫耳的總碳數為36的脂肪族二胺單體P1074及3莫耳的二胺單體MBCHA以及0.5莫耳的二胺單體2-乙烯基-4,6-二氨基-1,3,5-三嗪溶入環己酮和NMP的混合物中。接著將所得之混合溶液進行反應2小時，以得到固含量約20%的聚醯胺酸溶液。接著，將該聚醯胺酸溶液在180℃下進行醯亞胺化反應3小時，以得到聚醯亞胺溶液。之後，取出含聚醯亞胺固形物100克的聚醯亞胺溶液並加入5克的架橋劑TEPIC、5克的架橋劑TAIC以及5克的起始劑BPO，以製成聚醯亞胺混合溶液。接著，將聚醯亞胺混合溶液塗佈於上述離型層上，並且以約160℃的溫度進行乾燥3分鐘，以製成本發明之聚醯亞胺層。其中，聚醯亞胺層屬於預聚物，其尚未和全部的架橋劑和起始劑進行交聯反應並提升分子量。
實施例2：
實施例2製備本發明覆蓋膜的製作方法與實施例1相同，不同處在於將6莫耳的總碳數為36的脂肪族二胺單體P1074改為9莫耳並且不添加二胺單體MBCHA。
比較例1：
比較例1製備聚醯亞胺層的製作方法與實施例1部分類似，不同處在於將6莫耳的總碳數為36的脂肪族二胺單體P1074改為3莫耳並且不添加二胺單體MBCHA；3莫耳的二胺單體MBCHA改為6莫耳。此外，由於比較例1所形成的聚醯胺酸溶液在180℃下進行醯亞胺化反應3小時之後所生成的聚醯亞胺溶解性不佳，也就是說脫水環化後所形成的該聚醯亞胺無法和前述架橋劑以及起始劑形成聚醯亞胺混合溶液，所以也無法將其塗佈於上述離型層。因此，比較例1的聚醯亞胺層是將聚醯胺酸溶液進行脫水環化後直接生成。
之後，分別對實施例1及實施例2的聚醯亞胺層進行楊氏模數、溫度流變曲線、介電常數、介電損耗及吸濕率的測定。前述各測試的說明如下，且測試的結果顯示於表1中。
依據ASTM-D638的規定，使用測試樣板第五類型(type V)，進行拉伸強度、楊氏模數以及伸長率的測定。進行拉伸強度測試時，持續紀錄拉力和聚醯亞胺層伸長量之關係，直到聚醯亞胺層斷裂。在表1中，將聚醯亞胺層斷裂時所承受之拉力除以原始樣品的截面積便可求得到聚醯亞胺層的拉伸強度；將聚醯亞胺層斷裂時的長度減去聚醯亞胺層的原始長度，並除以聚醯亞胺層的原始長度，便可求得拉伸伸長率；根據聚醯亞胺層斷裂前所承受之拉力和相應的伸長量以求得拉伸楊氏模數。楊氏模數的數值越低表示聚醯亞胺層的剛性越小。
依據IPC-TM-650 2.5.5.5.1B的規定，使用網路分析儀(型號為ZVB20，由羅德史瓦茲公司(ROHDE & SCHWARZ)製造)分別量測實施例1、實施例2及比較例1的聚醯亞胺層的介電常數及介電損耗，其中量測頻率為10GHz。在表1中，數值越低表示聚醯亞胺層的介電性質越好。
接著，以TA廠牌DHR2之旋轉式流變儀，選用半徑2.5mm之平行板，分別量測實施例1、實施例2的溫度流變曲線，並且求得最低的黏度值，如表1所示。
另外，表1中的填膠性是指將上述乾燥後的聚醯亞胺層在130℃下，以5kgf/cm 2的壓力與線距約3密耳(mil)的線路之間進行真空快壓約3分鐘，並觀測聚醯亞胺層填充該線路之間縫隙的能力。其中，當填充線路之間縫隙無氣泡產生，定義為通過測試。
表1
實施例1 實施例2 比較例1
PMDA(mol) 10 10 10
P1074(mol) 6 9 3
MBCHA(mol) 3 0 6
VT(mol) 0.5 0.5 0.5
拉伸強度(MPa) 58 52 溶解性不佳
楊氏模數(GPa) 1.5 0.8
伸長率(%) 50 80
黏度Pa·s (於120℃) 15000 12000
介電係數 2.7 2.7
介電損耗 0.006 0.004
填膠性 通過 通過
由實施例1、2、比較例1及表1可知，實施例1、2的聚醯亞胺具有可溶性，因此能夠塗佈於離型層並以160℃的溫度進行乾燥3分鐘以形成聚醯亞胺層，並得到本發明之覆蓋膜。此外，實施例1、2的聚醯亞胺層可通過填膠性測試，並且具有可接受的拉伸強度、楊氏模數、伸長率、介電係數以及介電損耗。因此，實施例1、2的聚醯亞胺層能夠進一步利用上述應用例的方法用以製備半導體元件表面的絕緣層。並且，本發明實施例1、2的聚醯亞胺層在熱壓製程溫度環境下具有良好的壓合流動性，能夠取代習知底膠(underfill)點塗到晶片和基板間再藉由毛細作用力流入空隙的覆晶製程，並且相比使用底膠的覆晶製程，製作時間較短、填充縫隙能力較佳，也不容易產生氣泡。並且，透過上述熱壓製程還可以使本發明覆蓋膜的聚醯亞胺層填滿導體結構之間深寬比大於等於3的縫隙，可應用於半導體封裝的介電層、封裝體或底膠材料。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10、106‧‧‧覆蓋膜
12、110‧‧‧離型層
14、108‧‧‧聚醯亞胺層
100、200‧‧‧第一半導體元件
102、202‧‧‧第一部件
104、204‧‧‧第一導體結構
105、205‧‧‧縫隙
104a‧‧‧第一導體結構上表面
108b‧‧‧聚醯亞胺層上表面
112‧‧‧重佈線層
114‧‧‧圖案化導電層
116‧‧‧重佈導線
118‧‧‧介電層
118a‧‧‧通孔
120‧‧‧導電墊
122‧‧‧錫球
210‧‧‧第二半導體元件
212‧‧‧第二導體結構
214‧‧‧第二部件
第1圖為本發明一實施例的覆蓋膜。 第2圖至第4圖為本發明第一應用例覆蓋膜用以製作半導體元件表面的絕緣層的製作方法的示意圖。 第5圖為本發明第一應用例覆蓋膜用以製作封裝結構的示意圖。 第6圖至第8圖為本發明第二應用例覆蓋膜用以製作半導體元件表面的絕緣層的製作方法的示意圖。

Claims (14)

  1. 一種覆蓋膜，包括：一離型層；以及一聚醯亞胺層，設置於該離型層上，該聚醯亞胺層包括相對設置之一內表面和一外表面，該外表面係直接暴露於大氣中，該聚醯亞胺層係經由包括二胺單體和四羧酸二酐單體的一聚醯亞胺組成物反應所形成，其中該二胺單體係選自總碳數為36以上的脂肪族二胺單體，且在溫度介於60℃至160℃之間時，該聚醯亞胺層之最低黏度係小於20000Pa．s。
  2. 如請求項1所述的覆蓋膜，其中該聚醯亞胺層還包括未與聚醯亞胺組成物鍵結的架橋劑以及起始劑。
  3. 如請求項1所述的覆蓋膜，其中用以生成該聚醯亞胺層的該二胺單體還包括選自羥基、羧基及C=C的基團的二胺單體所組成的群組中的至少一者。
  4. 如請求項1所述的覆蓋膜，其中用以生成該聚醯亞胺層的該二胺單體還包括4,4’-二氨基二環己基甲烷。
  5. 如請求項1所述的覆蓋膜，其中該聚醯亞胺層在60℃至160℃的熱壓下，會被填充至深寬比為3的縫隙中。
  6. 如請求項2所述的覆蓋膜，其中該架橋劑包括含有環氧基、異氰酸脂基或烯烴基的化合物且該起始劑包括過氧化物。
  7. 一種半導體元件表面的絕緣層的製作方法，其中包括：提供一第一半導體元件，包括一第一部件及設置於該第一部件上的複數個第一導體結構；將該等第一導體結構直接接觸如請求項1至6中任一項所述的該覆蓋膜的該聚醯亞胺層；進行一熱壓製程，使該聚醯亞胺層填滿該等第一導體結構之間的至少一縫隙，使得該等第一導體結構被該聚醯亞胺層環繞；以及在進行該熱壓製程之後，移除該離型層，再以160℃至200℃的溫度固化。
  8. 如請求項7所述之半導體元件表面的絕緣層的製作方法，其中該熱壓製程的溫度介於60℃至160℃之間。
  9. 如請求項7所述之半導體元件表面的絕緣層的製作方法，其中該等第一導體結構之間的該等縫隙的深寬比大於等於3。
  10. 如請求項7所述之半導體元件表面的絕緣層的製作方法，其中該第一部件包括晶片。
  11. 如請求項10所述之半導體元件表面的絕緣層的製作方法，其中該等第一導體結構的組成係選自銅、銀、錫及上述至少兩者所組成的合金所構成之群組。
  12. 如請求項7所述之半導體元件表面的絕緣層的製作方法，其中在移除該離型層的步驟後，該些第一導體結構係被包覆於該聚醯亞胺層中，且在移除該離型層的步驟後，該製作方法另包括：提供一第二半導體元件，包括一第二部件及設置於該第二部件上的複數個第二導體結構，且該等第二導體結構係對應於該等第一導體結構而設置；以及將該第一半導體元件與該第二半導體元件彼此接合，以排開設置於該等第一導體結構以及該等第二導體結構之間的該聚醯亞胺層，致使該等第一導體結構電連接對應的該等第二導體結構。
  13. 如請求項12所述之半導體元件表面的絕緣層的製作方法，其中該第一部件係為印刷電路板、中介板、矽基板或玻璃基板。
  14. 如請求項12所述之半導體元件表面的絕緣層的製作方法，其中該第二部件包括晶片。
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TW201641597A (zh) * 2015-05-27 2016-12-01 台虹科技股份有限公司 用以形成可溶性聚醯亞胺的組成物、覆蓋膜及其製造方法

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