TWI650796B - Transformer coupling capacitor tuning matching circuit and plasma etching chamber with transformer coupling capacitance tuning matching circuit - Google Patents

Abstract

A matching circuit includes the following components: a power input circuit coupled to an RF source; The coil input circuit is coupled between the power input circuit and the input terminal of the inner coil. The inner coil input circuit includes an inductor and a capacitor coupled in series with the inductor. The inductor is connected to the power input circuit and the capacitor is connected to the input terminal of the inner coil. The first node is defined between the power input circuit and the inner coil input circuit; an inner coil output circuit is coupled between the output end of the inner coil and the ground; the inner coil output circuit defines a direct path connection to ground; The outer coil input circuit is coupled between the first node and the input end of the outer coil; and an outer coil output circuit is coupled between the output end of the outer coil and the ground.

Description

Transformer coupling capacitor tuning matching circuit and transformer coupling capacitor tuning capacitor Plasma etching chamber with circuit

[Claim of priority]

This application claims the priority of US Patent Provisional Application No. 61/747919, filed on December 31, 2012 and named "TCCT Match Circuit for Plasma Etch Chambers". This application claims the priority of continuing the application as part of US Patent Application No. 13/658652, filed on October 23, 2012 and named "Faraday Shield Having Plasma Density Decoupling Structure Between TCP Coiling Zones"; This application claims to be part of U.S. Patent Application No. 13/198683, filed on August 4, 2011 and entitled `` Internal Faraday Shield Having Distributed Chevron Patterns and Correlated Positioning Relative to External Inner and Outer TCP Coil '' Renews the priority of the application; this application claims that the application of the US Patent Provisional Application on April 28, 2011 and named "Internal Faraday Shield Having Distributed Chevron Patterns and Correlated Positioning Relative to External Inner and outer TCP Coil" 61/480314 priority. The disclosures of these applications are hereby incorporated by reference in their entirety.

The present invention relates generally to semiconductor fabrication, and more particularly to a TCCT matching circuit for a plasma etching chamber.

In semiconductor manufacturing, the etching process is common and repeated. As known to those skilled in the art, there are two types of etching processes: wet etching and dry etching. One type of dry etching is plasma etching performed using inductively coupled plasma etching equipment.

Plasma contains various types of free radicals, as well as positive and negative ions. Chemical reactions of various free radicals, positive ions, and negative ions are used to etch the features, surfaces, and materials of the wafer. During the etching process, the chamber coil performs a function similar to the primary coil in a transformer, and the plasma performs a function similar to the secondary coil in a transformer.

The existing transformer coupled capacitive tuning (TCCT) matching design suffers from some problems, especially when it is used to perform the manufacturing process of magnetoresistive random access memory (MRAM). These issues include limited TCCT range, limited transformer coupled plasma (TCP) power, high coil voltage, and coil arc effects. As a result, the process window of the reactor chamber may be quite limited, which means that the various formulations cannot be met. If you force a recipe beyond the process window, it may fail due to overvoltage and / or overcurrent interlocking, and even worse, it may cause arcing of the TCP coils and ceramic windows and ceramic crosses. damage. In addition, when the terminal voltage is not properly balanced, the spattering effect of the ceramic window due to the capacitive coupling of the TCP coil may gradually develop over time. The result is that particles sputtered from the ceramic window are subsequently deposited on the wafer, which may result in lost yield. This effect can limit the operating life of the reactor to, for example, 500 RF hours of operation.

In view of the above, there is a need for an improved TCCT matching circuit for a plasma etching chamber.

The disclosure is a device used to etch a semiconductor and the layers formed thereon during the manufacture of a semiconductor device. This equipment is defined by the TCCT matching circuit. The TCCT matching circuit controls the operation of the TCP coil in the plasma processing chamber. The etching step is performed in the plasma processing chamber.

In one embodiment, a matching circuit is provided, which is coupled between the RF source and the plasma chamber. The matching circuit includes the following components: a power input circuit, the power input circuit is coupled to an RF source; an inner coil input The circuit is coupled between the power input circuit and the input of the inner coil. The inner coil input circuit includes an inductor and a capacitor coupled in series with the inductor. The inductor is connected to the power input circuit and the capacitor is connected to the input of the inner coil. A node is defined between the power input circuit and the inner coil input circuit; an inner coil output circuit is coupled between the inner coil output and the ground. The inner coil output circuit defines a direct pass-through connection ) To ground; an outer coil input circuit is coupled between the first node and the input end of the outer coil; an outer coil output circuit is coupled between the output end of the outer coil and the ground.

In one embodiment, the capacitance is a variable capacitance having a value between about 150 pF and about 1500 pF; and the inductance has a value between about 0.3 uH and about 0.5 uH.

In one embodiment, the outer coil input circuit includes a second capacitor.

In one embodiment, the second capacitor is a variable capacitor having a rated value of about 150 pF to about 1500 pF.

In one embodiment, the outer coil output circuit includes a second capacitor. In one embodiment, the second capacitor has a value of about 80 pF to about 120 pF. In another embodiment, the second capacitor has a value of about 100 pF ± about 1%.

In one embodiment, the power input circuit includes: a second capacitor coupled to the RF source; a second inductor coupled to the inner coil input circuit; a third capacitor coupled between the second capacitor and the second inductor; A second node is defined between the second capacitor and the third capacitor; and a fourth capacitor is coupled between the second node and the ground. In one embodiment, the second capacitor has an amount of about 5 pF to about 500 pF. The third capacitor has a value of about 0.3 uH to about 0.5 uH; and the fourth capacitor has a value of about 200 pF to about 300 pF. In one embodiment, the fourth capacitor has a value of about 250 pF ± about 1%.

In another embodiment, a matching circuit is provided. The matching circuit includes the following components: a power input circuit coupled to an RF source; an inner coil input circuit coupled between the power input circuit and the input of the inner coil; Between terminals, the inner coil input circuit includes an inductor and a first capacitor coupled in series with the inductor. The inductor is connected to the power input circuit and the first capacitor is connected to the input terminal of the inner coil. The first node is defined between the power input circuit and the An inner coil output circuit is coupled between the output end of the inner coil and ground. The inner coil output circuit defines a direct path connection to ground; an outer coil input circuit is coupled between the first node and Between the input terminals of the outer coil; an outer coil output circuit coupled between the output end of the outer coil and ground; the output circuit of the outer coil includes a second capacitor having a value greater than about 85 pF. In an alternative embodiment, the second capacitor has a value greater than about 100 pF.

In one embodiment, the first capacitor is a variable capacitor having a value between about 150 pF and about 1500 pF; and the inductor has a value of about 0.3 uH to about 0.5 uH.

In one embodiment, the outer coil input circuit includes a third capacitor. In one embodiment, the third capacitor is a variable capacitor having a rated value of about 150 pF to about 1500 pF.

In an embodiment, the power input circuit includes: a third capacitor coupled to the RF source; a second inductor coupled to the inner coil input circuit; a fourth capacitor coupled between the third capacitor and the second inductor; A second node is defined between the third capacitor and the fourth capacitor; and a fifth capacitor is coupled between the second node and the ground. In one embodiment, the third capacitor has a rated value of about 5 pF to about 500 pF; the fourth capacitor has a rated value of about 50 pF to about 500 pF; the second inductor has a value of about 0.3 uH to about 0.5 uH; and The five capacitors have a value of about 200 pF to about 300 pF. In one embodiment, the fifth capacitor has a value of about 250 pF ± about 1%.

In another embodiment, a matching circuit is provided. The matching circuit includes the following components: a power input circuit coupled to an RF source; an inner coil input circuit coupled between the power input circuit and the input of the inner coil; Between terminals, the inner coil input circuit includes an inductor and a first capacitor coupled in series with the inductor. The inductor is connected to the power input circuit and the first capacitor is connected to the input terminal of the inner coil. The first node is defined between the power input circuit and An inner coil output circuit is coupled between the output end of the inner coil and ground. The inner coil output circuit defines a direct path connection to ground; an outer coil input circuit is coupled between the first node and Between the input terminals of the outer coil, the outer coil input circuit includes a second capacitor; an outer coil output circuit is coupled between the output terminal of the outer coil and the ground; the outer coil output circuit includes a third capacitor.

In one embodiment, the first capacitor is a variable capacitor having a rated value between about 150 pF and about 1500 pF; and wherein the inductor has a value of about 0.3 uH to about 0.5 uH.

In one embodiment, the second capacitor is a variable capacitor having a rated value of about 150 pF to about 1500 pF.

In one embodiment, the third capacitor has a value of about 80 pF to about 120 pF. In one embodiment, the third capacitor has a value of about 100 pF ± about 1%.

In one embodiment, the power input circuit includes: a fourth capacitor coupled to the RF source; a second inductor coupled to the inner coil input circuit; a fifth capacitor coupled between the fourth capacitor and the second inductor; A second node is defined between the fourth capacitor and the fifth capacitor; and a sixth capacitor is coupled between the second node and the ground. In an embodiment, the fourth capacitor has a rated value of about 5 pF to about 500 pF; wherein the fifth capacitor has a rated value of about 50 pF to about 500 pF; wherein the second inductor has a value of about 0.3 uH to about 0.5 uH; And the sixth capacitor has a value of about 200 pF to about 300 pF. In one embodiment, the sixth capacitor has a value of about 250 pF ± about 1%.

102‧‧‧ Chamber

104‧‧‧Chuck

106‧‧‧ Dielectric window

120‧‧‧outer coil

122‧‧‧Inner coil

124‧‧‧TCCT matching circuit

140, 142, 146, 148‧‧‧ nodes

160‧‧‧RF generator

162‧‧‧ bias matching circuit

300, 302, 308, 310‧‧‧ input

304, 306, 312, 314‧‧‧ output

320‧‧‧TCCT input circuit

322‧‧‧RF Power

324‧‧‧TCCT output circuit

400‧‧‧power input circuit

402‧‧‧Inner coil input circuit

404‧‧‧outer coil input circuit

406‧‧‧Inner coil output circuit

408‧‧‧Outer coil output circuit

410, 412‧‧‧node

The invention and its further advantages can be best understood by referring to the following description in conjunction with the accompanying drawings.

FIG. 1 shows a plasma processing system for an etching operation according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a plasma processing chamber according to an embodiment of the present invention.

FIG. 3 shows a top view schematically showing an inner coil and an outer coil according to an embodiment of the present invention.

FIG. 4A is a schematic diagram showing a circuit topology of a TCCT matching circuit according to an embodiment of the present invention.

FIG. 4B is a simplified schematic diagram showing components of a TCCT matching circuit according to an embodiment of the present invention.

FIG. 5 is a graph showing ion density versus TCP power for various top configurations according to an embodiment of the present invention.

FIG. 6 shows four graphs according to an embodiment of the present invention, each graph showing ion density versus radial distance.

The present disclosure is a TCCT matching circuit for etching a semiconductor substrate and a layer formed thereon during the manufacture of a semiconductor device. The TCCT matching circuit controls the operation of the TCP coil, which is disposed above the dielectric window of the chamber in which the etching step is performed.

In the following description, numerous specific details are provided to provide a thorough understanding of the present invention. However, it will be apparent to one having ordinary skill in the art that the present invention may be practiced without some of these specific details. In other cases, in order to avoid unnecessarily obscuring the present invention, well-known process operation and implementation details have not been described in detail.

FIG. 1 illustrates a plasma processing system for an etching operation according to an embodiment of the present invention. The system includes a chamber 102 including a chuck 104 and a dielectric window 106. The chuck 104 may be an electrostatic chuck for supporting the substrate when the substrate is present.

The figure further shows a bias RF generator 160, which can be defined by one or more generators. If most generators are provided, different frequencies can be used to achieve various tuning characteristics. The bias matching circuit 162 is coupled between the RF generator 160 and the conductive plate of the component, and the conductive plate defines the chuck 104. The chuck 104 also includes electrostatic electrodes so as to be able to chuck and dechuck the wafer. Basically, filters and DC clamp power can be set. Other control systems for releasing the wafer from the chuck 104 may also be provided. Although not shown, a pump system is connected to the chamber 102, which enables vacuum control and removal of gas by-products from the chamber during the plasma treatment operation.

The dielectric window 106 may be defined by a ceramic-based material. As long as it can withstand the conditions of the semiconductor etching chamber, other dielectric materials can also be used. Typically, the chamber is operated at elevated temperatures ranging between about 50 degrees Celsius and about 120 degrees Celsius. This temperature will depend on the etch process operation and the specific formulation. The chamber 102 will also operate under vacuum conditions ranging between about 1 millitorr (mT) and about 100 millitorr (mT). Although not shown, the chamber 102 is typically coupled to a plurality of devices when installed in a clean room or manufacturing facility. These devices include pipelines that provide process gas, vacuum, temperature control, and environmental particle control.

When installed at the target manufacturing site, these devices are coupled to the chamber 102. In addition, the chamber 102 may be coupled to a transfer chamber that will enable a robotic arm to move semiconductor wafers into and out of the chamber 102 using typical automation.

FIG. 2 is a cross-sectional view of a plasma processing chamber according to an embodiment of the present invention. It is shown that the TCP coil includes an inner coil (IC) 122 and an outer coil (OC) 120. The TCP coils are arranged and arranged above the dielectric window 106.

The TCCT matching circuit 124 enables dynamic tuning of the power provided to the inner and outer coils. The TCP coil system is coupled to a TCCT matching circuit 124. The TCCT matching circuit 124 includes an inner coil 122 And a connection portion to which the outer coil 120 is connected. In one embodiment, the TCCT matching circuit 124 is configured to tune the TCP coil to provide more power to the inner coil 122 (relative to the outer coil 120). In another embodiment, the TCCT matching circuit 124 is configured to tune the TCP coil to provide less power to the inner coil 122 (relative to the outer coil 120). In another embodiment, the power provided to the inner and outer coils will provide an even distribution of power and / or a radially distributed ion density above the control substrate (ie, the wafer present). In yet another embodiment, the power tuning between the outer coil and the inner coil is adjusted based on processing parameters that are defined for the etching performed on the semiconductor wafer disposed above the chuck 104.

In an implementation, a TCCT matching circuit with a variable capacitance (as further detailed below) may be configured to automatically adjust to achieve a predetermined ratio of the current in the two coils. It should be understood that the circuit shown here provides tuning and adjustment to the desired current ratio. In one embodiment, the ratio of the current may range from 0.1 to 1.5. This ratio is commonly referred to as the transformer coupled capacitor tuning (TCCT) ratio. However, the TCCT ratio is set based on the desired process for a particular wafer or multiple wafers.

It should be understood that by providing an adjustable TCP coil, the chamber 102 can provide flexibility in controlling ion density to TCP power and a radial ion density profile depending on the processing operation being performed.

In addition, it should be noted that although the entire content of this disclosure refers to a TCCT matching circuit, the use of this term should not limit the scope of this circuit (this circuit is defined to achieve the desired matching function and provide tuning). In other embodiments, without a TCCT function or a fixed TCCT ratio, it is expected that a matching circuit based on the principles and embodiments described herein can be applied to achieve the desired matching function of the plasma processing system.

FIG. 3 shows a top view schematically depicting the inner coil 122 and the outer coil 120 according to an embodiment of the present invention. The top view shown depicts the connection part connected to the coil. As mentioned previously, the coil includes an outer coil 120 and an inner coil 122 as an example. The inner coil 122 will include an inner coil 1 (IC1) and an inner coil 2 (IC2). The outer coil 120 includes an outer coil 1 (OC1) and an outer coil 2 (OC2). The connection portions between the coil ends are relatively shown in a circuit provided in the TCCT matching circuit 124. The legend in Figure 3 The loop windings are provided to show the respective inner and outer coils of the TCP coils used in the chamber 102 according to an embodiment of the present invention. As shown in the figure, the inner coils IC1 and IC2 are arranged in parallel spirals that intersect with each other. As shown, ICI and IC2 are similar to a pair of arithmetic or Archimedean spirals that are substantially the same shape but one of which is rotated about 180 degrees relative to the other about its axis. The input terminal 300 of IC1 is located at the diameter relative to the input terminal 302 of IC2. In addition, the output terminal 304 of IC1 is located at a diameter relative to the output terminal 306 of IC2. The configuration of the outer coils OC1 and OC2 is similar to the configuration of the inner coils IC1 and IC2, which is defined as substantially parallel spirals interleaved with each other and rotated about 180 degrees relative to each other. The input terminal 308 of OC1 is diameter-relative to the input terminal 310 of OC2, and the output terminal 312 of OC1 is diameter-relative to the output terminal 314 of OC2. In one embodiment, the input and output ends of the inner coil and the outer coil are arranged in a substantially linear configuration. It should be understood that other types of coil configurations can also be used. For example, a dimensional coil that provides a hemispherical structure, and other coil type structures other than a planar coil distribution can be provided.

As noted, the TCP coil is coupled to the TCCT matching circuit 124, which includes a connection portion connected to the outer coil 120 and the inner coil 122. As shown, the input terminals 308 and 310 of the outer coil 120 are coupled to the node 146, which in turn is connected to the TCCT input circuit 320. The output of the outer coil 120 is connected to the node 142, and the node 142 is connected to the TCCT output circuit 324. The inner coil 122 has input terminals 300 and 302 connected to a node 140, and the node 140 is further connected to a TCCT input circuit 320. The output terminals 304 and 306 of the inner coil 122 are connected to the node 148, and the node 148 is connected to the TCCT output circuit 324. The TCCT input circuit receives power from the RF power source 322. The TCCT output circuit is connected to ground.

FIG. 4A is a schematic diagram showing a circuit topology of a TCCT matching circuit according to an embodiment of the present invention. The RF source 322 provides power to the power input circuit 400. The variable capacitor C1 is coupled between the RF source 322 and the node 410. The node 410 is connected to the capacitor C2, and the capacitor C2 is further connected to the ground. The node 410 is also connected to the variable capacitor C3, which is further connected to the inductor L5. Inductor L5 is coupled to the node 412. In one embodiment, the power input circuit 400 is defined by the variable capacitor C1, the node 410, the capacitor C2, the variable capacitor C3, and the inductor L5, which are set as described above.

The node 412 is coupled to each of the inner coil input circuit 402 and the outer coil input circuit 404. In one embodiment, the inner coil input circuit 402 is defined by an inductor L3 and a variable capacitor C5 that are coupled to each other. The inductor L3 is coupled between the node 412 and the variable capacitor C5. The variable capacitor C5 is connected to the node 140 (shown in FIG. 3), and the node 140 is further connected to the input of the inner coil.

With continued reference to FIG. 4A, the node 412 is also connected to the outer coil input circuit 404. In one embodiment, the outer coil input circuit 404 is defined by a variable capacitor C4 coupled to the node 412. The variable capacitor C4 is also connected to the node 146 (shown in FIG. 3), which in turn is connected to the input of the outer coil.

In addition, FIG. 4A also shows a TCCT output circuit 324, which is defined by the inner coil output circuit 406 and the outer coil output circuit 408. The inner coil output circuit 406 is connected to the node 148 (shown in FIG. 3), and the node 148 is further connected to the output of the inner coil. In one embodiment, the inner coil output circuit 406 is defined by a ground path. The outer coil output circuit 408 is connected to the node 142 (shown in FIG. 3), and the node 142 is further connected to the output of the outer coil. In one embodiment, the outer coil output circuit is defined by a capacitor C7 coupled between the node 142 and the ground.

In one embodiment, the variable capacitor C1 is rated at about 5 to 500 pF. In one embodiment, the capacitor C2 is rated at about 250 pF. In one embodiment, the variable capacitor C3 is rated at about 5 to 500 pF. In one embodiment, the inductance L5 is rated at about 0.3uH. In one embodiment, the variable capacitor C4 is rated at about 150 to 1500 pF. In one embodiment, the inductance L3 is rated at about 0.55uH. In one embodiment, the variable capacitor C5 is rated at about 150 to 1500 pF. In one embodiment, the capacitor C7 is rated at about 100 pF.

The TCCT matching circuit 124 enables dynamic tuning of the variable capacitors C1, C3, C4, and C5 to tune the power provided to the inner and outer coils. In one embodiment, the variable capacitors C1, C3, C4, and C5 are controlled by a processing controller of an electronic board connected to the chamber 102. Electronic board can be coupled to operate specific A network system that handles routine tasks that depend on processing operations expected during a particular cycle. The electronic board can thus control the etching operation performed in the chamber 102 and control the special settings of the variable capacitors C1, C3, C4, and C5.

FIG. 4B is a simplified schematic diagram showing components of a TCCT matching circuit according to an embodiment of the present invention. As shown, the power input circuit 400 receives power from an RF power source 322. The power input circuit 400 is connected to the node 412. The inner coil input circuit 402 is coupled between the node 412 and the inner coil 122. The outer coil input circuit 404 is coupled between the node 412 and the outer coil 120. The inner coil 122 is connected to an inner coil output circuit 406, and the inner coil output circuit 406 is connected to ground. The outer coil 120 is connected to an outer coil output circuit 408, and the outer coil output circuit 408 is connected to ground.

In summary, the TCCT matching circuit design described so far provides improvements in power efficiency. It is believed that this is due to the optimization of the design to minimize the influence of stray capacitance on the coil on the plasma. The influence of stray capacitance on RF power efficiency has been published in "Power Efficiency Oriented Optimal Design of High Density CCP and ICP Sources for Semiconductor RF" by Maolin Long in "IEEE Transactions on Plasma Science, Vol. 34, No. 2, April 2006". Plasma Processing Equipment, "which is hereby incorporated by reference.

Regarding the inner coil, the conventional TCCT matching circuit design already includes output-side inductance, and the output-side inductance increases the stray capacitance and thus reduces power efficiency. However, in the embodiment described herein, the inner coil output circuit is configured as a ground path, and the inner coil input circuit is configured to include an inductor L3. This reduces stray capacitance, thus improving power efficiency and contributing to lower voltages on the inner coil.

Regarding the outer coil, the conventional TCCT matching circuit design has provided relatively low output-side capacitance. However, in the embodiment described herein, the outer coil output circuit is configured to provide a higher capacitance, which reduces the impedance of a specific frequency and provides a lower voltage drop.

Table 1 shown below provides RF characterization data comparing the original top RF design with the top RF design modified according to an embodiment of the present invention.

As shown by the data in Table 1, under the condition of no load (no plasma), the Q value of the inner coil of the modified top end has been improved compared to the Q value of the inner coil of the original top end. As a result, RF power efficiency has also improved. Therefore, under no-load conditions, since the outer coil is dominant at lower TCCT, the TCP coil The overall Q value improved at higher TCCT. In addition, this data shows that the overall RF power efficiency is significantly improved under load (with plasma).

In summary, the currently disclosed TCCT matching circuit provides high power efficiency, which means that given a charge, a higher density plasma is achieved. In addition, due to achieving high power efficiency, the disclosed TCCT matching circuit allows a relatively low voltage level at the coil terminals. The ability to operate at lower voltages at the coil terminals reduces the acceleration of ions (these ions may hit the surface of the dielectric window). As a result, the generation of particles caused by particles sprayed from the dielectric window is reduced. Table 2 below shows a comparison of the terminal voltage between a conventional TCCT matching circuit design and a TCCT matching circuit design according to an embodiment of the present invention.

The data in Table 2 shows a comparison of the measured RF voltage between the TCCT matching circuit according to the embodiment of the present invention and the existing TCCT matching circuit. A voltage V3 (shown in FIG. 4A) is measured between the variable capacitor C5 and the node 140, and the voltage V3 represents the voltage at the input terminal of the inner coil. The voltage V4 (also shown in Figure 4A) is measured between the output of the outer coil and the capacitor C7, and the voltage V4 represents the voltage of the output of the outer coil.

The data shown in Table 2 illustrates that in the TCCT matching circuit design according to the embodiment of the present invention, the coil terminal voltage is significantly reduced. Because the coil terminal voltage is reduced, embodiments of the present invention can be used in various conductor etching chambers to minimize dielectric window spattering and also eliminate coil arc effects caused by overvoltage from terminals to ground.

FIG. 5 is a graph showing ion density versus TCP power for various top configurations according to an embodiment of the present invention. In this chart, line graphs with different top configurations are represented by different shapes. A circle corresponds to a line drawing of the original top with a coil window interval of 0.1 inches. The experimental conditions are as follows: TCCT = 1, SF6 = 50sccm, Ar = 200sccm, Ch.P = 9mT, and tip = 160mm. The diamond shape corresponds to a line graph having a top end of the TCCT matching circuit according to the embodiment described herein, and the top end of this modification also has a coil window interval of 0.1 inches. The square corresponds to a line drawing of the original top with a coil window spacing of 0.4 inches. The triangle corresponds to the line graph of the original top end without the Faraday shield (FS), which also has a coil window interval of 0.4 inches.

Comparing the line graph (represented by a circle) of the original top with a 0.1 inch coil window interval to the line graph (represented by a diamond) of a modified top with a 0.1 inch coil window interval, it can be seen that the modified top RF design provides an Higher power efficiency than the original top RF design. That is, for a given TCP power, the modified tip provides significantly higher ion density. By providing higher power efficiency, equivalent plasma density can be achieved with lower power as in the conventional top TCCT matching design. This capability provides an improvement in the lifetime of the TCCT matching circuit (because the component suffers from lower power) and also reduces the generation of particles due to splashing of the dielectric window as previously described.

Figure 6 shows four graphs, each graph showing ion density versus radial distance. In the graph shown in the upper right of FIG. 6, the line graph shows various TCCT values applied to the original tip with a coil window interval of 0.1 inch. For each line graph, TCP power = 1000W. The line graph represented by the diamond corresponds to TCCT = 1. The line graph represented by the square corresponds to TCCT = 0.5. The line graph represented by the triangle corresponds to TCCT = 1.3.

In the graph shown at the upper left of FIG. 6, a line graph shows various TCCT values applied to a tip having a modification of the TCCT matching circuit according to an embodiment of the present invention, and the tip has a coil window interval of 0.1 inch. For each line graph, TCP power = 1000W. The line graph represented by the diamond corresponds to TCCT = 1. The line graph represented by the square corresponds to TCCT = 0.5. The line graph represented by the triangle corresponds to TCCT = 1.3.

In the graph shown at the bottom right of Figure 6, the line graph shows various TCCT values applied to the original tip with a coil window interval of 0.4 inches. The line graph represented by the diamond corresponds to TCCT = 1. The line graph represented by the square corresponds to TCCT = 0.5. The line graph represented by the triangle corresponds to TCCT = 1.3.

In the graph shown at the bottom left of Figure 6, the line graph shows various TCCT values applied to the top of the baseline without a Faraday shield but with a coil window spacing of 0.4 inches. The line graph represented by the diamond corresponds to TCCT = 1. The line graph represented by the square corresponds to TCCT = 0.5. The line graph represented by the triangle corresponds to TCCT = 1.3.

The line diagram shown in FIG. 6 illustrates that the increased plasma density due to the inclusion of a TCCT matching circuit according to an embodiment of the present invention is more evenly distributed throughout the wafer.

Although the present invention has been described in terms of several embodiments, it should be understood that those skilled in the art will understand various changes, additions, substitutions, and equivalents after reading the foregoing description and research drawings. It is therefore intended that the present invention include all such variations, additions, permutations, and equivalents as fall within the true spirit and scope of the present invention.

Claims (13)

A matching circuit for a plasma chamber includes: a power input circuit; an inner coil input circuit coupled between the power input circuit and an input terminal of an inner coil; the inner coil input circuit It includes an inductor and a capacitor coupled in series with the inductor. The inductor is connected to the power input circuit and the capacitor is connected to the input terminal of the inner coil. The first node is defined between the power input circuit and the inner coil input. Between circuits; an inner coil output circuit coupled between an output end of the inner coil and ground; the inner coil output circuit defines a direct path connection portion that does not include inductance or capacitance, and the direct path connection portion is to A direct connection to ground; an outer coil input circuit coupled between the first node and an input end of an outer coil; and an outer coil output circuit coupled between an output end of the outer coil and ground, The outer coil output circuit includes a second capacitor; the power input circuit includes: a third capacitor coupled to an RF source; a second inductor coupled To the input circuit of the inner coil; a fourth capacitor coupled between the third capacitor and the second inductor; a second node defined between the third capacitor and the fourth capacitor; and a fifth capacitor Is coupled between the second node and the ground. For example, the matching circuit of the first patent application range, wherein the input circuit of the outer coil includes a sixth capacitor. For example, the matching circuit of the first patent application range, wherein the first node shunts power from the power input circuit for distribution to the inner coil input circuit and the outer coil input circuit. For example, the matching circuit of the first patent application range, wherein the capacitance of the inner coil input circuit defines a first variable capacitance. For example, the matching circuit of claim 4 in the patent application, wherein the outer coil input circuit includes a second variable capacitor, and the outer coil input circuit is further coupled to the power input circuit through the first node. For example, the matching circuit of claim 5 in which the first and second variable capacitors provide tuning of the current ratio between the inner coil and the outer coil. A plasma chamber includes: a chuck for supporting a substrate for plasma processing; a dielectric window disposed above the chuck; a TCP coil disposed above the dielectric window; the TCP The coil system is defined by an inner coil and an outer coil; and a matching circuit including: a power input circuit; an inner coil input circuit coupled between the power input circuit and an input end of the inner coil; the inner coil The input circuit includes an inductor and a capacitor coupled in series with the inductor. The inductor is connected to the power input circuit and the capacitor is connected to the input terminal of the inner coil. The first node is defined between the power input circuit and the Between the coil input circuits; an inner coil output circuit coupled between an output end of the inner coil and ground; the inner coil output circuit defines a direct path connection portion that does not include inductance or capacitance, and the direct path connection portion Is a direct connection to ground; an outer coil input circuit is coupled between the first node and an input end of the outer coil; and an outer coil output circuit is coupled to the Between an output end of the coil and ground, wherein the output circuit of the outer coil includes a second capacitor; wherein the power input circuit includes: a third capacitor coupled to an RF source; and a second inductor coupled to the inner coil An input circuit; a fourth capacitor coupled between the third capacitor and the second inductor; a second node defined between the third capacitor and the fourth capacitor; and a fifth capacitor coupled between the third capacitor and the fourth capacitor Between the second node and ground. For example, the plasma chamber of claim 7 in which the input circuit of the outer coil includes a sixth capacitor. For example, the plasma chamber of item 7 of the patent application scope, wherein the first node shunts power from the power input circuit for distribution to the inner coil input circuit and the outer coil input circuit. For example, the plasma chamber of item 7 of the patent application scope, wherein the capacitance of the inner coil input circuit defines a first variable capacitance. For example, the plasma chamber of claim 10, wherein the outer coil input circuit includes a second variable capacitor, and the outer coil input circuit is further coupled to the power input circuit via the first node. For example, the plasma chamber of claim 11 in which the first and second variable capacitors provide tuning of the current ratio between the inner coil and the outer coil. For example, the plasma chamber of item 7 of the patent application scope further includes: a bias matching circuit connected to the chuck.