TWI645447B - 高密度電容器結構及方法 - Google Patents
高密度電容器結構及方法 Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本發明涉及高密度電容器結構及方法,具體提供的是基於半導體奈米柱的陣列的高密度電容器結構。該高密度電容器結構可以是複數個電容器,其中各該半導體奈米柱充當該複數個電容器其中一者的底電極,或者該高密度電容器結構可以是大面積金屬-絕緣體-金屬(MIM)電容器,其中該半導體奈米柱充當後續所形成用於該MIM電容器的底電極的支撐結構。
Description
本申請案是關於電容器製作,並且更尤指使用奈米結構形成高密度電容器。
電容器是記憶體、邏輯與模擬電路中的重要組件。由於每單位面積的電容有限,電容器在整個電路佈局中一直佔據相當大的晶片面積。隨著積體電路系統(cirtuitry)密度增加,用於電容器的可用晶粒面積跟著減少。更稠密電路中的電容器面積減少,因而更難以包括具有夠高電容的電容器。因此,在晶片上的電容器面積固定的情況下,可增加電容的結構及方法的需求依然存在。
本申請案提供基於半導體奈米柱的陣列的高密度電容器結構。該高密度電容器結構可以是複數個電容器,其中各該半導體奈米柱充當該複數個電容器其中一者的底電極,或者該高密度電容器結構可以是大面積金屬-絕緣體-金屬(MIM)電容器,其中該半導體奈米柱充當後續所形成用於該MIM電容器的底電極的支撐結構。
在本申請案的一項態樣中,提供一種形成複
數個電容器的方法。本方法包括首先在半導體基板上形成複數個半導體奈米柱。該複數個半導體奈米柱取向為垂直於該半導體基板的頂面。在該半導體基板及該複數個半導體奈米柱的曝露表面上方保形沉積介電材料層之後,在該介電材料層上方形成導電材料層。該導電材料層填充介於該複數個半導體奈米柱之間的空間。
在本申請案的另一態樣中,提供一種包含複數個電容器的半導體結構。該複數個電容器包含:複數個半導體奈米柱,其存在於半導體基材的頂面上,並取向為垂直於該半導體基板的頂面;保形介電材料層,其存在於該半導體基板的該頂面的曝露部分上,並圍繞該複數個半導體奈米柱的側壁;以及導電材料層,其位於該保形介電材料層上。該導電材料層橫向圍繞該複數個半導體奈米柱。
在本申請案的另一態樣中,提供一種包含電容器的半導體結構。該電容器包含複數個半導體奈米柱,其存在於半導體基板的頂面上,並取向為垂直於該半導體基板的頂面。該複數個半導體奈米柱各者的頂面上存在有觸媒點。該電容器更包括:保形第一導電材料層,其存在於該半導體基板的該頂面、該複數個半導體奈米柱、及該複數個觸媒點的曝露表面上;保形介電材料層,其存在於該保形第一導電材料層上;以及第二導電材料層,其存在於該保形介電材料層上。該第二導電材料層填充介於該複數個半導體奈米柱之間的空間,並在該保形介電材料層的最頂面上方具有頂面。
在本申請案的又另一態樣中,提供一種形成電容器的方法。本方法包括首先在半導體基板上形成複數個半導體奈米柱。該複數個奈米柱取向為垂直於該半導體基板的頂面。該複數個半導體奈米柱各者的頂面上存在有觸媒點。在該半導體基板、該複數個半導體奈米柱、及該個觸媒點的曝露表面上方保形沉積第一導電材料層之後,在該第一導電材料層上方保形沉積介電材料層。其次,在該介電材料層上方形成第二導電材料,該第二導電材料層填充介於該複數個半導體奈米柱之間的空間。
10‧‧‧半導體基板
12‧‧‧觸媒點
16‧‧‧半導體奈米柱
18‧‧‧介電材料層
20‧‧‧導電材料層
22‧‧‧接觸階介電層
26‧‧‧第一接觸結構
28‧‧‧第二接觸結構
32‧‧‧第一導電材料層
34‧‧‧介電材料層
36‧‧‧第二導電材料層
40‧‧‧接觸階介電層
42‧‧‧第一接觸結構
44‧‧‧第二接觸結構
第1A圖是根據本申請案的第一具體實施例,包括半導體基板的第一例示性半導體結構的立體圖,複數個觸媒點是在該半導體基板上形成。
第1B圖是第1A圖的第一例示性半導體結構沿著線條B-B’的截面圖。
第2圖是第1B圖的第一例示性半導體結構在垂直於半導體基板的頂面生長半導體奈米柱之後的截面圖。
第3圖是第2圖的第一例示性半導體結構在半導體基板、半導體奈米柱及觸媒點的曝露表面上保形沉積介電材料層之後的截面圖。
第4圖是第3圖的第一例示性半導體結構在介電材料層上形成導電材料層以完全填充半導體奈米柱之間的空間之後的截面圖。
第5圖是第4圖的第一例示性半導體結構在形成接觸階(contact level)介電層、及該接觸階介電層內的接觸結構之後的截面圖。
第6圖是根據本申請案的第二具體實施例,可衍生自第2圖的第一例示性半導體結構,在半導體基板、半導體奈米柱及觸媒點的曝露表面上方保形沉積第一導電材料層之後的第二例示性半導體結構的截面圖。
第7圖是第6圖的第二例示性半導體結構在第一導電材料層上方保形沉積介電材料層之後的截面圖。
第8圖是第7圖的第二例示性半導體結構在介電材料層上形成第二導電材料層以填充半導體奈米柱之間的空間之後的截面圖。
第9圖是第8圖的第二例示性半導體結構在形成第二導電材料層上的接觸階介電層、及該接觸階介電層內的接觸結構之後的截面圖。
本申請案現將參照以下隨附本申請案的論述及圖式來更加詳述。注意到的是,本申請案的圖式僅是為了說明目的而提供,因此,圖式並未按照比例來繪製。也注意到的是,相似且對應的元件是以相似的參考元件符號來參照。
在以下說明中,提出許多具體細節,例如:特定結構、組件、材料、尺寸、處理步驟及技術,以便瞭解本申請案的各項具體實施例。然而,本領域的技術人員
將會領會的是,本申請案的各項具體實施例沒有這些具體細節也可予以實踐。在其它實例中,眾所周知的結構或處理步驟並未加以詳述,為的是要避免混淆本申請案。
請參閱第1A圖及第1B圖,根據本申請案的第一具體實施例的第一例示性半導體結構包括形成於半導體基板10上的複數個觸媒點(catalyst dot)12。半導體基板10可由任何合適的半導體材料所組成,舉例如Si、Ge、SiGe、SiC、SiGeC、以及包括InAs、GaAs及InP的III/V族化合物半導體。在一項具體實施例中,半導體基板10是由Si所構成。選擇的半導體基板10一般具有(111)晶向,以使得奈米柱生長將會垂直於基板表面出現。半導體基板10的厚度可以是自400μm至1000μm,而一般的厚度是自50μm至900μm。
觸媒點12是用於促使半導體奈米柱生長,並可包括舉例如金、鋁、鈦、銦、鐵或鎳的金屬。觸媒點12可分佈成在觸媒點12之間具有所欲間隔的規則圖案,或可分佈成隨機圖案。
在一項具體實施例中且如第1A圖所示,觸媒點12是均勻分佈於半導體基板10上。觸媒點12可藉由圖案化觸媒層來形成。觸媒層可先在半導體基板10上藉由習知的沉積技術來沉積,包括但不局限於化學氣相沉積(CVD)、濺鍍、及物理氣相沉積(PVD)。形成的觸媒層可具有範圍自10nm至50nm的厚度,但也可運用更小及更大的厚度。
隨後圖案化觸媒層以藉由微影及蝕刻程序來形成觸媒點12。微影步驟包括在觸媒層上塗敷光阻(圖未示),將光阻曝照成所欲輻射(radiation)的圖案,然後利用習知的阻劑顯影劑將曝照的光阻顯影。蝕刻程序包含乾蝕刻及/或濕化學蝕刻。本申請案中可使用的合適的乾蝕刻程序包括反應性離子蝕刻(RIE)、離子束蝕刻、電漿蝕刻或雷射剝蝕。一般使用的是RIE程序。蝕刻程序利用半導體基板10當作蝕刻終止物,將圖案自圖案化光阻轉移至觸媒層。將圖案轉移至觸媒層之後,殘餘的光阻可利用舉例如灰化(ashing)的習知的阻劑剝除程序來移除。
在另一具體實施例中,觸媒點12可利用自組裝(self-assembly)程序來形成。“自組裝”一詞在本文中是用於表示讓材料自發組織成規則圖案。自組裝程序利用所屬技術領域眾所周知的嵌段共聚物(block copolymers)及技術。舉例而言,嵌段共聚物層(圖未示)首先藉由旋轉塗布在半導體基板10上方形成。嵌段共聚物層可包括任何能夠自組裝成更大等級陣列結構的嵌段共聚物。在一項具體實施例中,此嵌段共聚物是PMMS-PS嵌段共聚物。嵌段共聚物一經退火處理,便受奈米尺度相位分離並配置成陣列結構,該陣列結構是由第二聚合物嵌段的基質(matrix)圍繞第一聚合物嵌段的週期性球域所組成。接著選擇性移除第一聚合物嵌段以在第二聚合物嵌段的基質內提供開口,以曝露半導體基板10的部分。藉由鍍覆使開口填充有導電材料以提供觸媒點12。形成觸媒點12之後,移除第二聚合
物嵌段的基質。
請參閱第2圖,半導體奈米柱16是垂直於半導體基板10的頂面來生長。半導體奈米柱16的生長是藉助於觸媒點12,並且一般是藉由CVD或電漿增強型化學氣相沉積(PECVD)來實行。在一項具體實施例中,利用半導體先驅物氣體(例如:用於矽奈米柱的矽烷(SiH4);用於鍺奈米柱的鍺烷(GeH4))藉由氣液固(vapor-liquii-solid;VLS)生長程序將半導體奈米柱16生長在半導體基板10上。在一項具體實施例中,半導體奈米柱16是矽奈米柱16。當VLS生長啟動時,金屬半導體(一般為金-矽)液體合金便形成。由於另外供應氣相(例如:SiH4)的半導體先驅物,金屬半導體微滴(droplet)變為有半導體材料的過飽和,而過量半導體材料沉積於固體-液體介面。結果是,液體微滴從原來的基板表面上升至生長中半導體奈米柱16的尖部。生長半導體奈米柱之後,金屬半導體液體合金將會在冷卻期間分離,不會形成金屬半導體固體合金。結果是,液體合金在冷卻之後回復成觸媒點12。
藉由VLS生長所形成的半導體奈米柱16是磊晶對準至半導體基板10。“磊晶對準”意味著半導體奈米柱與下層半導體基板具有相同的晶向。半導體奈米柱16可生長至任何合適的高度。在一項具體實施例中,半導體奈米柱16是生長成範圍自10μm至100μm的高度。VLS程序所製備的半導體奈米柱16的直徑是由觸媒點12的直徑來界定,並且可以是自1nm至100nm,但也可運用更
小及更大的長度。
所形成的半導體奈米柱16包含與下層半導體基板10相同的半導體材料。在一項具體實施例中,半導體奈米柱16是由矽所構成。
請參閱第3圖,介電材料層18是保形(conformally)沉積於半導體基板10、半導體奈米柱16及觸媒點12的曝露表面上。介電材料層18可包括所具有介電常數大於8.0的高介電常數(高k)材料。例示性的高k材料包括但不限於氮化矽、氧化鉿、氧化鋁、氧化鈦及氧化鉭。介電材料層18可藉由舉例如CVD或PVD的習知沉積程序來形成。介電材料層18的厚度可以是自1nm至10nm,但仍可運用更小及更大的厚度。
請參閱第4圖,導電材料層20是在介電材料層18上形成以完全填充介於半導體奈米柱16之間的空間。導電材料層20可包括金屬或經摻雜半導體材料。此金屬可以是諸如鎢、鈦、鉭、鋁或銅的元素金屬、至少兩種元素金屬的合金、導電金屬氮化物、或導電金屬氧化物。經摻雜半導體材料可以是經摻雜多晶矽。導電材料層20可藉由舉例如CVD、PVD、ALD或鍍覆的習知沉積程序來形成。導電材料層20是沉積至高於介電材料層18的最頂面的厚度。
導電材料層20及介電材料層18在觸媒點12的頂面上方形成的部分可藉由舉例如化學機械平坦化(CMP)的習知平坦化程序來移除。在一項具體實施例中,
平坦化程序也可移除觸媒區的上部分,使得觸媒點12具有平坦的頂面(圖未示)。在另一具體實施例中,平坦化程序可完全移除觸媒點12,使得導電材料層20具有與半導體奈米柱16的頂面共平面的頂面。
複數個離散電容器從而形成。各半導體奈米柱16形成底電極,介電材料層18形成電容器介電質,而導電材料層20形成電容器其中一者的頂電極。複數個離散電容器共用共通的電容器介電質(即介電材料層18)及共通的頂電極(即導電材料層20)。在本申請案的第一具體實施例中,各半導體奈米柱16充當電容器的主動組件(即底電極)。半導體奈米柱16的密集陣列容許達到電容器的高整合密度,每單位面積的電容因而變高。
請參閱第5圖,若觸媒點12已移除,則接觸階(contact level)介電層22是在導電材料層20、介電材料層18、及觸媒點12或半導體奈米柱16上方沉積。接觸階介電層22可包括諸如未摻雜氧化矽、經摻雜氧化矽、多孔或非多孔的有機矽酸鹽玻璃、多孔或非多孔的氮摻雜有機矽酸鹽玻璃、或其組合的介電材料。接觸階介電層22可藉由CVD、PVD、或旋轉塗布來形成。若接觸階介電層22未進行自平坦化,則接觸階介電層22的頂面可藉由舉例如CMP來平坦化。
包括與觸媒點12接觸的第一接觸結構26、及與導電材料層20接觸的第二接觸結構28的各個接觸結構是在接觸階介電層22內形成。在本申請案的一些具體實施
例中,若觸媒點12已移除,則第一接觸結構26可直接接觸半導體柱16的頂面。舉例而言,各個接觸結構(26、28)可使用微影圖案化與非等向性蝕刻的組合,藉由穿過接觸階介電層22形成第一接觸開口(圖未示)及第二接觸開口(圖未示)來形成。第一接觸開口曝露觸媒點12的頂面、或若觸媒點12已移除則半導體奈米柱16的頂面。第二接觸開口曝露導電材料層20的頂面的一部分。第一及第二接觸開口接著使用舉例如CVD、PVD、ALD或鍍覆的習知沉積程序,以導電材料來填充。例示性導電材料包括但不限於銅、鎢、鋁、鉭、氮化鈦、或氮化鉭。導電材料在接觸階介電層22上面的過量部分後續,可藉由舉例如凹陷蝕刻或CMP來移除。
請參閱第6圖,根據本申請案的第二具體實施例,本申請案的第二例示性半導體結構是衍生自第2圖的第一例示性半導體結構,藉由在半導體基板10、半導體奈米柱16及觸媒點12的曝露表面上方保形沉積第一導電材料層32。第一導電材料層32作用為金屬/絕緣體/金屬(MIM)電容器的底電極。第一導電材料層32可包括金屬或經摻雜半導體材料。此金屬可以是諸如鎢、鈦、鉭、鋁或銅的元素金屬、至少兩種元素金屬的合金、導電金屬氮化物、或導電金屬氧化物。經摻雜半導體材料可以是經摻雜多晶矽。第一導電材料層32可藉由舉例如CVD或ALD的習知沉積程序來形成。第一導電材料層32的厚度可以是自20nm至200nm,但也可運用更小及更大的厚度。
請參閱第7圖,介電材料層34是在第一導電材料層32上方以保形方式沉積。介電材料層34作用為MIM電容器的電容器絕緣體,並且可包括諸如氮化矽、氧化鉿、五氧化鉭、二氧化矽或氧化鋁的高k材料。介電材料層34可藉由舉例如CVD、ALD或其組合來沉積。所形成的介電材料層34的厚度可以是自約1nm至約10nm,但也可運用更小及更大的厚度。
請參閱第8圖,第二導電材料層36是在介電材料層34上形成以填充介於半導體奈米柱16之間的空間。第二導電材料層36作用為MIM電容器的頂電極。第二導電材料層36可包括與第一導電材料層32相同或不同的金屬。第二導電材料層36可包括金屬或經摻雜半導體材料。此金屬可以是諸如鎢、鈦、鉭、鋁或銅的元素金屬、至少兩種元素金屬的合金、導電金屬氮化物、或導電金屬氧化物。經摻雜半導體材料可以是經摻雜多晶矽。第二導電材料層36可藉由CVD或PECVD來形成。
從而形成MIM電容器。第一導電材料層32形成底電極,介電材料層34形成電容器介電質,而第二導電材料層36形成MIM電容器的頂電極。第一導電材料層32環繞半導體柱16,以使得底電極的表面面積增加,從而增加MIM電容器的電容。
請參閱第9圖,接觸階介電層40是藉由進行第5圖的處理步驟在第二導電材料層36上形成。隨後,各個接觸結構42、44是藉由進行第5圖的處理步驟來形成。
接觸結構包括延伸穿透該接觸階介電層40、第二導電材料層36及介電材料層34並接觸該第一導電材料層32的第一接觸結構42、以及延伸穿透該接觸階介電質40並接觸該第二導電材料層36的第二接觸結構44。在本申請案的一些具體實施例中,第一接觸結構可以是接觸半導體基板10的後觸結構(圖未示),用以實現複數個晶片的垂直堆疊。
本申請案的(多個)電容器可藉由將具有(多個)電容器形成於其上的半導體基板堆疊於具有諸如場效晶體管等複數個主動電路裝置的另一基板上,以形成三維的半導體裝置架構,而與其它電路整合。隨後,形成互連件以連接電容器與主動電路裝置。用於形成主動電路裝置及互連件的結構及程序在所屬技術領域中乃眾所周知,因此,本文中不進一步說明。
儘管本申請案已對照其各項具體實施例來具體展示並且說明,本領域的技術人員仍將瞭解的是,可施作前述及其它形式變更與細節而不會脫離本申請案的精神及範疇。因此,用意在於本申請案不受限於所述及所示的精准形式及細節,而是落於申請專利範圍的範疇內。
Claims (20)
- 一種形成複數個電容器的方法,其包含:在半導體基板上形成複數個半導體奈米柱,該複數個半導體奈米柱取向為垂直於該半導體基板的頂面;在該半導體基板及該複數個半導體奈米柱的曝露表面上方保形沉積介電材料層;以及在該介電材料層上方形成導電材料層,該導電材料層填充介於該複數個半導體奈米柱之間的空間。
- 如申請專利範圍第1項所述的方法,更包含平坦化該導電材料層,使得該導電材料層的頂面與該複數個半導體奈米柱的頂面共平面。
- 如申請專利範圍第2項所述的方法,更包含形成接觸該複數個半導體奈米柱的複數個第一接觸結構、及接觸該導電材料層的第二接觸結構。
- 如申請專利範圍第3項所述的方法,其中,形成該複數個第一接觸結構及該第二接觸結構包含:在該導電材料層、該介電材料層及該複數個半導體奈米柱上方形成接觸階介電層;形成延伸穿透該接觸階介電層用以曝露該複數個半導體奈米柱的該頂面的複數個第一開口、及延伸穿透該接觸階介電層用以曝露該導電材料層的該頂面的第二開口;以及以導電材料填充該複數個第一開口及該第二開口。
- 如申請專利範圍第4項所述的方法,更包含在形成該複 數個半導體奈米柱前,先在該半導體基板上形成複數個觸媒點。
- 如申請專利範圍第5項所述的方法,其中,形成該複數個觸媒點包含:在該半導體基板上形成觸媒層;以及圖案化該觸媒層以提供該複數個觸媒點。
- 如申請專利範圍第6項所述的方法,其中,該觸媒層包含金、鋁、鈦、銦、鐵或鎳。
- 如申請專利範圍第7項所述的方法,其中,該複數個半導體奈米柱是藉由該複數個觸媒點所引發的氣液固程序來形成,使得該複數個半導體奈米柱各者的頂面上存在有觸媒點,其中,該第一接觸結構與該複數個觸媒點直接接觸。
- 一種包含複數個電容器的半導體結構,該複數個電容器包含:複數個半導體奈米柱,其存在於半導體基板的頂面上,並取向為垂直於該半導體基板的該頂面;保形介電材料層,其存在於該半導體基板的該頂面的曝露部分上,並圍繞該複數個半導體奈米柱的側壁;以及導電材料層,其位於該保形介電材料層上,該導電材料層橫向圍繞該複數個半導體奈米柱及具有與該保形介電材料層的頂面共平面之頂面,其中,該導電材料層完全由電性導電材料組成。
- 如申請專利範圍第9項所述的半導體結構,其中,該複數個半導體奈米柱各者具有與該半導體基板相同的晶向。
- 如申請專利範圍第9項所述的半導體結構,其中,該複數個半導體奈米柱包含與該半導體基板的半導體材料相同的半導體材料。
- 如申請專利範圍第9項所述的半導體結構,其中,該保形介電材料層包含氮化矽、氧化鉿、氧化鋁、氧化鈦或氧化鉭。
- 如申請專利範圍第9項所述的半導體結構,其中,該導電材料層包含鎢、鈦、鉭、鋁、銅、其合金、導電金屬氮化物、導電金屬氧化物、或經摻雜多晶矽。
- 如申請專利範圍第9項所述的半導體結構,更包含延伸穿透接觸階介電層並接觸該複數個半導體奈米柱的複數個第一接觸結構、以及延伸穿透該接觸階介電層並接觸該導電材料層的第二接觸結構。
- 如申請專利範圍第14項所述的半導體結構,該複數個半導體奈米柱各者更包含存在於該複數個半導體奈米柱各者的頂面上的觸媒點,其中,該複數個第一接觸結構各者接觸該複數個觸媒點其中一者。
- 一種包含電容器的半導體結構,該電容器包含:複數個半導體奈米柱,其存在於半導體基板的頂面上,並取向為垂直於該半導體基板的該頂面,其中,該複數個半導體奈米柱各者的頂面上存在有觸媒點; 保形第一導電材料層,其存在於該半導體基板、該複數個半導體奈米柱及該觸媒點的曝露表面上;保形介電材料層,其存在於該保形第一導電材料層上;以及第二導電材料層,其存在於該保形介電材料層上,該第二導電材料層填充介於該複數個半導體奈米柱之間的空間,並在該保形介電材料層的最頂面上方具有頂面。
- 如申請專利範圍第16項所述的半導體結構,其中,該複數個半導體奈米柱包含與該半導體基板的半導體材料相同的半導體材料。
- 如申請專利範圍第16項所述的半導體結構,其中,該保形介電材料層包含氮化矽、氧化鉿、氧化鋁、氧化鈦或氧化鉭。
- 如申請專利範圍第16項所述的半導體結構,其中,該保形第一導電材料層及該第二導電材料層各包含鎢、鈦、鉭、鋁、銅、其合金、導電金屬氮化物、導電金屬氧化物、或經摻雜多晶矽。
- 如申請專利範圍第16項所述的半導體結構,其中,該觸媒點包含金、鋁、鈦、銦、鐵或鎳。
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