TWI627753B - Transistor apparatus and manufacturing method thereof,and system on a chip(soc) - Google Patents

Abstract

An embodiment includes an apparatus comprising: a non-planar transistor including a fin, the fin including a source region having a source region width and a source region height, a channel region having a channel region width and a channel region height, a drain region having a drain width and a drain height, and a gate dielectric formed on a sidewall of the channel region; wherein the device includes (a) the channel region width is wider than the source region width, and (b) The gate dielectric includes at least one of (a) and (b) a first gate dielectric thickness at a first location and a second gate dielectric thickness at a second location, first The position and the second position are located at an equal height on the sidewall, and the first gate dielectric thickness and the second gate dielectric thickness are not equal to each other. Other embodiments are also described herein.

Description

Transistor device and its manufacturing method, and system single chip (SoC)

Embodiments of the invention are in the field of semiconductor devices, and in particular non-planar transistors.

The FinFET is a transistor built around a thin strip of semiconductor material called a "fin". The transistor includes a node/component of a standard field effect transistor (FET): a gate, a gate dielectric, a source region, and a drain region. The conductive path of the device is on the outside of the fin below the gate dielectric. In particular, current flows along the two "side walls" of the fin and along the top side of the fin. Since the conductive vias are inherently present along three different outer planar regions of the fin, such FinFETs are typically referred to as "three-gate" FinFETs. There are other types of FinFETs (such as "dual gate" FinFETs in which the conductive vias are present primarily only along both sidewalls of the fin and not along the top side of the fin).

100‧‧‧Different fin transistor

105‧‧‧Fin

140‧‧‧Source zone width

135‧‧‧ source area height

110‧‧‧ source area

126‧‧‧Channel area width

127‧‧‧Channel zone height

115‧‧‧Channel area

125‧‧‧Bottom width

130‧‧ ‧ bungee height

120‧‧ ‧ bungee area

170‧‧‧gate dielectric

155‧‧‧Contacts

160‧‧‧Contacts

165‧‧‧Contacts

161‧‧‧ spacer dielectric

128‧‧‧Additional access zone width

129‧‧‧Additional access zone height

141‧‧‧Transition in the channel

170'‧‧‧First Dielectric Department

170"‧‧‧Second Dielectric Department

200‧‧‧ system single chip

201‧‧‧First non-planar transistor

202‧‧‧Second non-planar transistor

210‧‧‧First source area

215‧‧‧First Passage Area

225‧‧‧First source region width

230‧‧‧ Height of the first access zone

225‧‧‧First channel area width

230‧‧‧ Height of the first access zone

220‧‧‧First bungee area

225‧‧‧First bungee width

230‧‧‧First bungee height

210'‧‧‧Second source area

240‧‧‧Second source region width

235‧‧‧Second source region height

240‧‧‧second channel area width

235‧‧‧second access zone height

215'‧‧‧Second passage area

240‧‧‧Second bungee width

235‧‧‧second bungee height

220'‧‧‧Second bungee area

271'‧‧‧ long axis

270‧‧‧ gate oxide

270'‧‧‧ gate oxide

361‧‧‧ spacers

363‧‧‧Fin

350‧‧‧Substrate

362‧‧‧Interlayer dielectric

364‧‧‧ oblique ion implantation

365‧‧‧ hardened part of the BARC layer

366‧‧‧The hardened part of the BARC layer

367‧‧‧etched channel area

368‧‧‧Unetched channel area

450‧‧‧Substrate

463‧‧‧Fin

469‧‧‧ Epitaxial materials

470‧‧‧ length

469‧‧‧ Wide and/or higher material parts

467‧‧‧ forming part of thin fins

461‧‧‧ spacers

455‧‧ ‧ gate contact

460‧‧‧ source contact

465‧‧‧汲 contact

From the scope of the appended patent application, to the following or a plurality of exemplary embodiments The features and advantages of embodiments of the present invention will be apparent from the detailed description and the accompanying drawings in which: FIG. 1(a) includes a perspective view of an embodiment of a differential fin transistor. Figure 1 (b) includes a side view of the embodiment of Figure 1 (a). Figure 1 (c) includes different embodiments of differential gate oxides.

Figure 2 (a) includes a perspective view of an embodiment of a dual fin transistor. Figure 2(b) includes a perspective view of another embodiment of a dual fin transistor.

3(a)-(e) illustrate a process for fabricating a differential fin transistor using patterned etching of fins in an embodiment of the invention.

4(a)-(e) illustrate a process for fabricating a bifin transistor using deposition techniques in an embodiment of the invention.

SUMMARY OF THE INVENTION AND EMBODIMENT

Reference will now be made to the drawings, in which like reference FIGS To more clearly illustrate the structure of various embodiments, the drawings included herein are schematic representations of semiconductor/circuit structures. Thus, the actual appearance of the fabricated integrated circuit structure (as seen in microphotographing) will appear different, but still incorporate the structure claimed by the illustrated embodiments. In addition, the various figures may only show the structure of an embodiment that is helpful in understanding the description. Other structures of the prior art are not included in the drawings to maintain clarity of the drawings. For example, each layer of the semiconductor device is not necessarily shown. The "embodiments", "different embodiments", and the like are intended to include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular features, structures, or characteristics. Some embodiments may have other implementations Some, all, or none of the features described in the examples. "First", "second", "third", etc. describe common items and indicate different examples of the likes mentioned. These adjectives do not imply that the objects so described must be in the given order, whether in time, in space, in arrangement, or in any other manner. "Connected" may indicate that the elements are in direct physical or electrical contact with each other, and "coupled" may indicate that the elements cooperate or interact with each other, but they may or may not be in direct physical or electrical contact.

Some system-on-a-chip (SoC) process technologies use gate length (Lg) through a actively miniaturized FinFET architecture to provide performance and area miniaturization. Low leakage and high voltage devices are included in the SoC, so supporting both is important for a successful SoC process, but because of these low leakage/high voltage transistors compared to the minimum design rule (ie nominal size) low voltage transistors One of the adverse effects of lateral miniaturization (i.e., shortening Lg) is that it is difficult to support low leakage and high voltage devices (i.e., logic transistors). In other words, although the three-gate architecture provides a significant improvement in the subcritical and short-channel effects of low-voltage, high-speed logic devices, the increase in short-channel effects does not increase due to overdrive at the gate of the operating voltage. The performance of the voltage device. Furthermore, although the size of the further fins is important to maintain the subcritical characteristic when the gate length Lg is actively reduced, these miniaturized fin sizes show degraded channel resistance and adverse effects on high voltage performance. It can also be observed that under high voltage stress conditions, performance degradation increases rapidly with fin shrinkage.

In short, the SoC architecture requires large leakage and performance ranges, as well as a wide range of operating voltages to accommodate low voltage and high voltage devices in a single SoC. Set both. The low voltage high speed logic device on the SoC requires miniaturization of the fin size (eg, thinning the fin width and shortening the fin height) to enhance the short channel effect of the gate length via the miniature transistor. However, high voltage transistors on the same SoC suffer from high voltage performance degradation as the fins shrink (eg, thinned fin width) due to the increased threshold voltage being minimized at high gate overdrive.

Embodiments discussed herein address the issue of accommodating both low voltage switching devices (eg, low voltage logic transistors) and high voltage switching devices (eg, input/output (I/O) transistors) in a single SoC.

An embodiment includes a device structure having different fin widths and heights (i.e., varying fin width and fin height) that utilizes miniature fin sizes to support superior subcritical properties of the device and, at the same time, have better reliability The lower gate-induced drain leakage (GIDL), both of which are required for high voltage devices. The process flow used to establish the device structure is compatible with the conventional three gate formation process. In particular, an embodiment has a narrow fin width on the source side of the channel (to enhance the short channel effect) and a wider fin width on the drain side of the same channel (to lower the drain region in the drain region) The gate field thus reduces the GIDL, enhances the hot carrier effect under stress, and increases the collapse of the device due to the lower vertical electric field. In this context, this embodiment is sometimes referred to as a "difference fin" device because within such devices a portion of the fin has a different width than another portion of the same fin. The difference in fin width can occur within the channel of the device, wherein the channel includes a fin portion having a width transition. As discussed earlier, the wider portion can be closer to the bungee.

Another embodiment includes a controlled method of achieving different fin sizes (i.e., fins having different widths) on the SoC. This method can be used to fabricate embodiments of a transistor that includes fins having different widths (and thus different widths of the channels) in the circuit of the SoC. For example, an embodiment includes a first transistor having a channel that is wider than a channel of the second transistor, whereby both the first and second transistors are in the circuitry of the SoC. This is sometimes referred to herein as a "double fin" structure because the first and second transistors have different fin widths ("double fins") that form channels having different widths.

These embodiments (e.g., dual fin and differential fin devices) provide a number of advantages over conventional devices, and at least some advantages are now presented. First, the wider fin width greatly enhances the performance of high voltage devices. For example, with a matching leakage, each narrowing of the fin by 1 nm causes the drive current in the fin to drop by 10%. This is due to the deteriorated channel resistance of the narrower fins. Thus, in embodiments of the differential fin and double fin structures, the thickened fin portion can achieve significant performance gains compared to conventional high voltage device architectures. Second, high Vcc devices are typically subject to collisional freeness due to hot carriers, which can cause performance degradation over a period of time (eg, drive degradation). This problem increases as the fin width narrows. Since the collision freeness mainly occurs on the drain side of the channel, the wider fin width in the differential fin process (wider fins in the channel and/or drain) provides improved reliability for matching performance. degree. Third, the differential fins are integrated/compatible with the dual fin process (described in more detail below) and conventional CMOS processes. This integration does not affect the performance and sub-critical characteristics of low-voltage, high-speed logic devices (thus making high-speed, low-leakage processes feasible). Fourth, the use of patterned semiconductor growth / deposition process (proposed below) To form differential fins, the flexibility of using different semiconductor materials within the transistor channels is provided. For example, the transistor can include a widened channel region, since the fins are formed from the same material as the substrate (eg, germanium), but then the second material is epitaxially grown on the fins (eg, IV or III-V) Material) is thickened (for example, in the channel area). Fifth, the gated dielectric deposition can be used instead of patterned semiconductor growth to provide a method of achieving different gate dielectric thicknesses in the same channel. In other words, the channel can have a gate dielectric portion adjacent to the source that is thinner than the portion of the gate dielectric adjacent the drain. This thicker dielectric provides better breakdown and reliability characteristics, while a thinner dielectric with adjacent sources provides better short channel effects.

Various different embodiments are discussed in more detail below.

FIG. 1(a) includes a perspective view of an embodiment of a differential fin transistor 100. Figure 1 (b) includes a side view of the embodiment of Figure 1 (a). The non-planar transistor includes a fin 105 including a source region 110 having a source region width 140 and a source region height 135, a channel region 115 having a channel region width 126 and a channel region height 127, and a drain width of 125 A drain region 120 with a drain height 130 and a gate dielectric 170 formed on a sidewall of the channel region 115. The spacer dielectric 161 separates the contacts 155, 160, 165. For clarity purposes, the gate dielectric 170 shown in Figure 1(b) is not shown in Figure 1(a). The channel region width 126 is wider than the source region width 140. The channel zone height 127 is higher than the source zone height 135. For example, in an embodiment, the height 135 is between 40-150 nm (eg, 50, 70, 90, 110, 130 nm) and the height 127 is 1-10 nm higher than the height 135 (eg, 3, 6, 9 nm) The width 140 is between 4-15 nm (for example, 6, 8, 10, 12, 14 nm), and width 126 is 0.5-2 nm wider than width 140 (eg, 0.7, 0.9, 1.1, 1.3, 1.5, 1.7, 1.9 nm).

As shown in FIG. 1(a), the drain region width 125 is wider than the source region width 140, and the drain region height 130 is higher than the source region height 135 because the drain region width 125 is the same as the channel region width 126, and The bungee zone height 130 is the same as the channel zone height 127. However, this may not be the case in other embodiments, and the drain region width 125 may be wider than the source region width 140, but different from the channel region width 126 (ie, thicker or thinner). In other embodiments, the drain region height 130 can be higher than the source region height 135, but different from the channel region height 127 (ie, shorter or higher).

The embodiment has an additional channel region width 128 and an additional channel region height 129, and the channel region width 126 is wider than the additional channel region width 128. In addition, the channel zone height 127 is higher than the additional channel zone height 129. In other words, in the embodiment of Figure 1 (a), there is a difference or transition in width and height within the channel (see position 141), but in other embodiments, the width and height of the entire channel are substantially identical (and consistent) The width and height may be wider and higher than one or both of the source width 140 and the drain width 125 and/or one of the source height 135 and the drain height 130. In the embodiment of Figure 1 (a), the thinner channel region is located between the wider channel region and the source region. Between different embodiments, the transition 141 occurring within the channel can vary. For example, in some embodiments, the transition occurs along the middle of the channel, closer to the source, or closer to the drain.

There may be one or more transitions in some embodiments. For example, Figure 1 (a) shows a single fin transition at location 141, but other embodiments may include Two or more transitions. For example, embodiments include a thin channel portion adjacent the source, a thicker channel portion equidistant from the source and drain, and a thicker channel portion adjacent the drain. The transition can be steep such that the thicker portion of the channel includes a face that is generally orthogonal to the sidewalls of the thinner portion of the channel. However, in other embodiments, there may be a sloped transition that increases the thickness of the channel toward the drain and away from the source more slowly.

In an embodiment, the channel region includes a first material and a second material, and the widened channel region width is on a portion of the first material of the channel region that forms the second material. For example, in FIG. 1(a), the thickness of the channel region including the fin near the source is the same as the thickness of the fin including the source. The fins may include, for example, bismuth (Si). The thicker portion of the channel adjacent to the drain includes an epitaxial (EPI) material formed on the original fin to increase the thickness of the channel portion adjacent the drain. For example, the epitaxial material can include an IV or III-V material, such as SiGe. In this embodiment, there may be a barrier layer or the like between the fin and the EPI layer. However, in other embodiments, the entire channel portion may be monolithic and include, for example, helium. However, in this embodiment, the thinned portion can be etched to achieve the thinness. In another embodiment, the thicker portion of the channel region may comprise the same material as the original fin, forming a layer of the material (eg, germanium) only on the fin.

Figure 1 (c) includes another embodiment of the present invention. The device depicted in FIG. 1(c) includes a gate dielectric including a first dielectric portion 170' having a first gate dielectric height and a second gate dielectric having a higher first level a second dielectric portion 170" of a high quality. Although not shown in the side view of FIG. 1(c), the dielectric portion 170" may be thicker than the dielectric portion 170' up to and including Equal heights on the sidewalls of the fin portions of the channels. Thus, the embodiment of Figure 1 (c) may include channels having uniform fin heights and widths (i.e., fins that do not differ in the channel region), but with different gate dielectrics. In other words, the channel can have a portion of the gate dielectric adjacent to the source that is thinner than the portion of the gate dielectric adjacent the drain. This thicker dielectric provides better breakdown and reliability characteristics, while having a thinner dielectric adjacent to the source provides better short channel effects.

Other embodiments may include differential fins in the channel region and both gate dielectrics for the difference in channel regions.

An embodiment includes means having differential fins in the channel region on the SoC, the SoC comprising at least two logic transistors. Thus, embodiments include a single SoC that accommodates both low voltage logic devices and high voltage devices, such as the differential fin transistors of Figure 1 (a). In an embodiment, at least two of the logic transistors are collinear with the non-planar transistors. Thus, embodiments allow for a single original fin that is then processed to form two logic transistors and differential fin transistors. The three transistors are collinear because the single long axis intersects the source, drain, and channel of each transistor. In an embodiment, the non-planar transistor of FIG. 1(a) is coupled to the first voltage source, and one of the at least two logic transistors is coupled to a second voltage having a maximum operating voltage lower than the first voltage source. source. In an embodiment, the device coupled to the first voltage source is coupled to an input/output (I/O) node. This device is not a logical device.

Figure 2 (a) includes a perspective view of an embodiment of a dual fin transistor. The SoC 200 includes a first non-planar transistor 201, the first non-planar transistor 201 includes a first fin, and the first fin includes a first source region width 225 and a first a source region 210 of the source region height 230, a first channel region 215 having a first channel region width 225 and a first channel region height 230, and a first channel having a first drain width 225 and a first drain height 230 a polar region 220, and a first gate dielectric (not shown) formed on a sidewall of the first channel region. The second non-planar transistor 202 includes a second fin portion including a source region 210 ′ having a second source region width 240 and a second source region height 235 , and a second channel region width 240 and a second a second channel region 215' having a second channel region height 235, a second drain region 220' having a second drain width 240 and a second drain height 235, and a first sidewall formed on the sidewall of the second channel region 215' Two gate dielectric (not shown). In an embodiment, the first channel region width 225 is wider than the second channel region width 240 and/or the first channel region height 230 is higher than the second channel region height 235. Thus, Figure 2(a) reveals a dual fin architecture or fabric.

The first fin of the SoC 200 has a long axis 271 that intersects the first source region 210, the first channel region 215, and the first drain region 220, and the second fin includes the same long axis 271, which is The second source region 210', the second channel region 215', and the second drain region 220' intersect. Thus, the fin portions of devices 201 and 202 are collinear with each other. This reflects how the devices 201, 202 (and the fin portions formed thereon) in the embodiment are derived from a common monolithic fin.

In the embodiment of FIG. 2(a), the first source region width 225, the first channel region width 225, and the first drain width 225 are generally all equal to one another. However, in other embodiments (not shown), the first channel region 215 has a first channel region width that is greater than the width of the first source region 210. In the embodiment The channel region itself may have differential fins such that the channel region 215 has a varying width (eg, the channel region 215 is thicker near the drain 220 and thinner near the source 210).

Figure 2(b) includes a perspective view of an embodiment of a dual fin transistor. This figure is very similar to Figure 2(a), but the thickness of the fins included in device 201 is the same as the fin of device 202. In other words, in FIG. 2(b), the width 225 is equal to the width 240 and the height 230 is equal to the height 235. However, gate oxide 270 is thicker than gate oxide 270' and/or higher than gate oxide 270'.

There are also many ways to implement differential fin or double fin processes. For example, Figures 3(a)-(e) illustrate a process for fabricating differential fin transistors using patterned etching of fins. As yet another example, Figures 4(a)-(e) illustrate a process for fabricating a dual fin transistor using deposition techniques. Other possible technologies are also available.

With respect to Figures 3(a)-(e), these figures show differential fin patterning techniques using a bottom antireflective coating (BARC) process. This differential fin is created using patterned etching on the inside of the gate region of the transistor.

In particular, FIG. 3(a) depicts a stage in the transistor process in which the "virtual gate" has been removed, leaving holes between the spacers 361 and above the fins 363. The fin 363 is located above the substrate 350 and below the Inter-Layer Dielectric (ILD) 362. FIG. 3(b) depicts the spin-on BARC layer on fin 363. An oblique ion implantation 364 is then performed to harden a portion 365 of the BARC layer without hardening the portion 366 of the BARC layer. The BARC layer is only partially hardened due to the oblique orientation of the ion implantation. Shielding provided by the mass and ILD 362 with one of the spacers 361. Figure 3(c) depicts a point in the process in which the uncured BARC is removed leaving only the BARC portion 365. Next, FIG. 3(d) allows the fins 363 to be etched in region 367 such that portions of the channel/gate regions (eg, 50%) are etched and the remaining portions of the channel/gate regions are not etched. Figure 3(e) illustrates the removal of the BARC portion 365 to create an etched channel region 367, and another channel region 368 that is not etched. Thus, portion 367 is thinner and/or shorter than portion 368 to create a differential fin transistor that is then subjected to further processing (eg, a conventional CMOS process).

4(a)-(e) provide an overview of a process flow for making a differential fin transistor by epitaxial deposition to widen the fin material. This allows the flexibility of different semiconductors to be used in the source/drain regions and even replaces the semiconductor with a deposited dielectric to result in a different gate dielectric in the same gate.

In particular, in FIG. 4(a), a fin 463 is provided on the substrate 450. In FIG. 4(b), a material is formed on the fin 463 (which may or may not be the same material as that included in the fin 463). This material 469 can be formed epitaxially. The material may comprise a Group IV or III-V material or other material. The length 470 can be determined according to the design goals. For example, length 470 can only be used as part of a differential fin transistor to be used, wherein a wider and/or higher material portion 469 is used to include a sub-portion of the channel. The length 470 can be used to include some or all of the transistors that are to be differential fins, wherein the wider and/or higher material portion 469 is used to contain some or all of the channels (whether the source and/or the drain are Also includes any part 469). Another design goal may be to form a dual fin system. In this case, it can be long Degree 470 is long enough to form a source, channel, and drain for high or higher voltage devices (eg, transistors included in the I/O or clock portion of the circuit), and portion 467 can be used to form thin Conventional low or lower voltage devices (eg, logic transistors) of the fins. Although not shown, FIG. 4(b) should not be construed as necessarily indicating that portion 467 is immediately adjacent to material 469. For example, in a dual fin architecture, portion 467 may have a longer distance relative to material 469, although still originating from the same fins at earlier points in the self-contained process.

A spacer 461 is applied in FIG. 4(c). In the case presented in Figure 4(c), spacers are configured to form differential fin transistors, such as the embodiment shown in Figure 1 (a). A gate contact 455 is formed in FIG. 4(d), and a source contact 460 and a drain contact 465 are formed in FIG. 4(e).

As described above using several non-exhaustive examples, there are a variety of different ways to achieve different fins within the transistor. First, the process can include etching the semiconductor fins to create a thin fin region having a thinner/thicker fin transition that forms a distinct fin. Second, the process can include depositing a semiconductor in the thick fin region to create a differential fin. This allows different semiconductors to be used in the source and/or drain regions (eg, the source of the germanium, the drain, and the channel with the SiGe EPI layer on some or all of the channel portions of the fin). Third, the process can include deposition of a dielectric to form a thick dielectric region to obtain a different gate dielectric (wherein the fins can be uniform in width but in the source/drain node) Some of the gates near one of the dielectrics are thicker, while the gates near the other of the source/drain nodes are thinner. Fourth, patterned oxidation of fins (eg, skeletal fins) within the gate can consume some of the fins to create a thinner fin portion. This oxide can be removed later for manufacturing Different fins.

Various embodiments include a semiconductor substrate. The substrate can be a monolithic semiconductor material that is part of the wafer. In an embodiment, the semiconductor substrate is a monolithic semiconductor material that is part of a wafer that has been split from the wafer. In an embodiment, the semiconductor substrate is a semiconductor material that is formed over an insulator, such as a semiconductor-on-insulator (SOI) substrate. In an embodiment, the semiconductor substrate is a raised structure, such as a fin that extends over a monolithic semiconductor material.

The following examples belong to further embodiments.

The device included in Example 1 includes: a non-planar transistor including a fin, the fin portion including a source region having a source region width and a source region height, a channel region having a channel region width and a channel region height, and a gate width a drain dielectric region having a drain height and a gate dielectric formed on a sidewall of the via region; wherein the device includes (a) a channel region width wider than a source region width, and (b) a gate dielectric The quality includes at least one of (a) and (b) the first gate dielectric thickness at the first location and the second gate dielectric thickness at the second location, the first location and the second The location is at an isocenter on the sidewall, and the first gate dielectric thickness and the second gate dielectric thickness are not equal to each other.

In Example 2, the subject matter of Example 1 can be optionally included, wherein the device includes a channel region width that is wider than the width of the source region.

In Example 3, the subject matter of Example 1-2 can be optionally included, wherein the channel region height is higher than the source region height.

In Example 4, the subject matter of Examples 1-3 may be optionally included, wherein the width of the drain region is wider than the width of the source region, and the height of the drain region is higher than the source region. degree.

In Example 5, the subject matter of Examples 1-4 can be optionally included, wherein the channel region has an additional channel region width and an additional channel region height, and the channel region width is wider than the additional channel region width.

In Example 6, the subject matter of Examples 1-5 can be optionally included, wherein the channel zone height is higher than the additional channel zone height.

In Example 7, the subject matter of Examples 1-6 can be optionally included wherein the channel region width is at the first location and the additional channel region width is at a second location between the first location and the source region.

In Example 8, the subject matter of Examples 1-7 can be optionally included, wherein the channel region comprises a first material and a second material, and the channel region width is at a second material formation on the first material of the channel region. section.

In Example 9, the subject matter of Examples 1-8 can be selectively included, including a substrate comprising a first material, wherein the second material is epitaxially formed over the first material.

In Example 10, the subject matter of Examples 1-9 can be optionally included, wherein the additional channel region width is located in an additional portion of the channel region that does not include the second material.

In Example 11, the subject matter of Examples 1-10 can be selectively included, wherein the device includes a gate dielectric including a first gate dielectric thickness at the first location and a second location at the second location The gate dielectric thickness, the first position and the second position are at the same height on the sidewall, and the first gate dielectric thickness and the second gate dielectric thickness are not equal to each other.

In Example 12, the subject matter of Examples 1-11 can optionally be included in the system In a wafer (SoC), a system single wafer contains at least two logic transistors.

In Example 13, the subject matter of Examples 1-12 can be selectively included, wherein at least two of the logical electro-crystalline systems are collinear with the non-planar transistors.

In Example 14, the subject matter of Examples 1-13 can be selectively included, wherein the non-planar transistor is coupled to the first voltage source, and one of the at least two logic transistors is coupled to the second voltage source, The second voltage source has a lower operating voltage than the first voltage source.

In Example 15, the subject matter of Examples 1-14 can be selectively included, wherein the non-planar transistor is coupled to an input/output (I/O) node.

Example 16 includes a system single wafer (SoC) comprising: a first non-planar transistor including a first fin portion, the first fin portion including a source region having a first source region width and a first source region height, having a first channel region having a first channel region width and a first channel region height, a first drain region having a first drain width and a first drain height, and a first gate formed on a sidewall of the first channel region a dielectric material; and a second non-planar transistor including a second fin portion, the second fin portion including a second source region having a second source region width and a second source region height, having a second channel region a second channel region having a width and a second channel region height, a second drain region having a second drain width and a second drain height, and a second gate dielectric formed on the sidewall of the second channel region Wherein the SoC comprises (a) the first channel region is wider than the second channel region width, and (b) the first gate dielectric is thicker than at least one of the second gate dielectric.

In Example 17, the subject matter of Example 16 can be optionally included, wherein the SoC includes the first channel region width being wider than the second channel region width, and the first pass The height of the road zone is higher than the height of the second channel zone.

In Example 18, the subject matter of Examples 16-17 can be selectively included, wherein (a) the first fin includes a first length intersecting the first source region, the first channel region, and the first drain region a shaft, (b) the second fin includes a second major axis intersecting the second source region, the second channel region, and the second drain region, and (c) the first major axis and the second major axis are Line of.

In Example 19, the subject matter of Examples 16-18 can be selectively included, wherein the first fin and the second fin are derived from a common monolithic fin.

In Example 20, the subject matter of Examples 16-19 can be optionally included, wherein the first source region width, the first channel region width, and the first drain width are generally all equal to each other.

In Example 21, the subject matter of Examples 16-20 can be optionally included, wherein the first channel region has an additional first channel region width and the first channel region width is wider than the additional first channel region width.

The method of Example 22 includes: forming a fin on the substrate, the fin having first, second, and third regions, and the second region having a first position adjacent to the first region and a portion adjacent to the third region a second location; performing an action selected from the group consisting of: (a) removing a portion of the second region at the first location, and (b) forming a material at a second location on the fin; and; Forming a source region in the first region, forming a channel region in the second region, and forming a drain region in the third region; wherein the channel region has a first channel region width at a first location on the fin portion and a second channel width at a second location on the fin, the second channel width being wider than the first channel width.

In Example 23, the subject matter of Example 22 can optionally include removing the second region The part located in the first position.

In Example 24, the subject matter of Examples 21-23 can optionally include forming a material at a second location on the fin.

The description of the embodiments of the present invention has been presented above for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the invention. The description and the terms including the following claims, such as left, right, top, bottom, top, bottom, upper, lower, first, second, etc., are for illustrative purposes only and are not to be construed as limiting. For example, a term indicating a relative vertical position refers to the case where the device side (eg, active surface) of the substrate or integrated circuit is the "top" face of the substrate; in fact the substrate can be in any direction, thus, at a standard geodetic reference coordinate In the middle, the "top" side of the substrate may be lower than the "bottom" side, but still belongs to the meaning of the term "top". The term "on" in this document (including the scope of the claims) is not intended to indicate that the first layer is "on" the second layer directly on the second layer or the second layer. Intimate contact; it may have a third layer or other structure on the first layer between the first layer and the second layer. Embodiments of the devices or articles depicted herein can be manufactured, used, or shipped in a number of locations and orientations. It will be apparent to those skilled in the art that many modifications and variations are possible in light of the above teachings. Those skilled in the art will recognize various equivalent combinations and permutations of the various components shown in the various figures. Therefore, the scope of the invention is not limited by the embodiment, but is limited by the scope of the appended claims.

Claims (24)

A transistor device comprising: a non-planar transistor comprising a fin, the fin portion comprising a source region having a source region width and a source region height, a channel region having a channel region width and a channel region height, and a bungee a drain region having a width and a drain height, and a gate dielectric formed on a sidewall of the channel region; wherein the transistor device includes (a) the channel region has a width wider than the source region width, and b) the gate dielectric comprises at least one of a first gate dielectric thickness at a first location and a second gate dielectric thickness at a second location (a), (b) The first position and the second position are located at an equal height on the sidewall, and the first gate dielectric thickness and the second gate dielectric thickness are not equal to each other. The structure of claim 1, wherein the transistor device comprises the channel region having a width wider than the source region width. The structure of claim 2, wherein the channel zone height is higher than the source zone height. The structure of claim 3, wherein the width of the drain region is wider than the width of the source region, and the height of the drain region is higher than the height of the source region. The structure of claim 2, wherein the channel region has an additional channel region width and an additional channel region height, and the channel region width is wider than the additional channel region width. The structure of claim 5, wherein the channel zone height is higher than the additional channel zone height. The structure of claim 5, wherein the channel region width is at the first location, and the additional channel region width is at a second location between the first location and the source region. The structure of claim 5, wherein the channel region comprises a first material and a second material, and the channel region width is a portion of the first material on the first material forming portion of the channel region. The structure of claim 8 includes a substrate comprising the first material, wherein the second material is epitaxially formed over the first material. The structure of claim 8 wherein the additional channel region width is in an additional portion of the channel region that does not include the second material. The structure of claim 1, wherein the transistor device comprises the gate dielectric, the gate dielectric comprising a first gate dielectric thickness at a first location and a second location a second gate dielectric thickness, the first location and the second location being the same height on the sidewall, and the first gate dielectric thickness and the second gate dielectric thickness are opposite to each other not equal. The structure of claim 1 is included in a system-on-chip (SoC), wherein the system single wafer includes at least two logic transistors. The structure of claim 12, wherein the at least two logic electro-crystal systems are collinear with the non-planar transistor. For example, the structure of claim 12, wherein the non-flat The surface transistor is coupled to the first voltage source, and one of the at least two logic transistors is coupled to the second voltage source, the second voltage source having a lower operating voltage than the first voltage source. The structure of claim 12, wherein the non-planar transistor is coupled to an input/output (I/O) node. A system single chip (SoC) comprising: a first non-planar transistor including a first fin portion, the first fin portion including a source region having a first source region width and a first source region height, having a first a first channel region having a channel region width and a height of the first channel region, a first drain region having a first drain width and a first drain height, and a first gate formed on a sidewall of the first channel region a dielectric material; and a second non-planar transistor including a second fin portion, the second fin portion including a second source region having a second source region width and a second source region height, having a second channel a second channel region having a region width and a height of the second channel region, a second drain region having a second drain width and a second drain height, and a second gate formed on a sidewall of the second channel region The SoC includes (a) the first channel region has a width wider than the second channel region width, and (b) the first gate dielectric is thicker than the second gate dielectric; One of them. The SoC of claim 16, wherein the SoC includes the first channel region width being wider than the second channel region width, and the first channel region height is higher than the second channel region height. The SoC of claim 17, wherein (a) the first fin portion includes the first source region, the first channel region, and the first a first major axis intersecting the polar regions, (b) the second fin includes a second major axis intersecting the second source region, the second channel region, and the second drain region, and (c) The first major axis is collinear with the second major axis. The SoC of claim 17, wherein the first fin and the second fin are derived from a common monolithic fin. The SoC of claim 17, wherein the first source region width, the first channel region width, and the first drain width are generally all equal to each other. The SoC of claim 17, wherein the first channel region has an additional first channel region width, and the first channel region width is wider than the additional first channel region width. A method for fabricating a crystal device, comprising: forming a fin on a substrate, the fin having first, second, and third regions, and the second region having a first position adjacent to the first region And a second location adjacent to the third zone; performing an action selected from the group consisting of: (a) removing the portion of the second zone at the first location, and (b) at the fin Forming a material at the second location on the portion; forming a source region in the first region, forming a channel region in the second region, and forming a drain region in the third region; wherein the channel region a first channel region width at the first location on the fin and a second channel width at a second location on the fin, the second channel width being wider than the first channel width. The method of claim 22, including removing the first The second zone is located in the portion of the first location. The method of claim 22, comprising forming a material at the second location on the fin.