KR20090116481A - Omega gate semiconductor device and method of forming channel for omega gate of the same - Google Patents

Abstract

PURPOSE: An omega gate semiconductor device and a method of forming a channel for omega gate of the same are provided to form an omega type channel on a substrate by removing silicon oxide film on top of a silicon fin and SiGe layer of the substrate surface together. CONSTITUTION: In an omega gate semiconductor device and a method of forming a channel for omega gate of the same, a silicon oxide film(22) on a bulk silicon substrate(21). An Si-fin(25) is formed to be vertical to the substrate by patterning the silicon oxide film and the substrate. A germanium is injected into a substrate surface at both side of the Si-fin. An SiGe layer is formed on the substrate surface at the both sides of the Si-fin by acting a Ge inserted into the substrate with a silicon(Si) of the substrate. An annealing process for forming the SiGe layer is performed under 900°C in a nitrogen gas. The omega style channel is formed on a substrate by removing the silicon oxide film of the Si-fin top and the SiGe layer of the substrate surface together through a wet etching.

Description

Omega gate semiconductor device and method of forming channel for omega gate of the same

The present invention relates to an omega gate semiconductor device and a method for forming an omega gate channel of the omega gate semiconductor device, and more particularly, a channel of an omega gate semiconductor device having an omega gate shape on a bulk silicon substrate. A method for forming and an omega gate semiconductor device formed by such a method.

Metal-oxide-semiconductor field effect transistors (MOSFETs) continue to shrink in size to improve performance and integration, and to reduce the cost required to implement unit functions. However, as the size becomes smaller, the distance between the source and the drain becomes shorter, and a short channel effect, a phenomenon in which the drain electric field modulates an electric field applied to the channel by the gate, appears. For this reason, the channel control degree of a gate falls remarkably. Specifically, electrical properties such as punch through, drain-induced barrier lowering (DIBL) due to the drain electric field, and lowering of the threshold voltage appear. This short channel effect becomes more severe when the gate length is less than 65 nm, which is enough to undermine the switching function, which is the basic function of the transistor.

Therefore, various measures have been raised to improve the above-mentioned problem. Among them, a method of forming a gate in a three-dimensional structure to improve channel controllability (channel controllability) per unit area is under study. Representative transistors having such a three-dimensional gate include, for example, fin field effect transistors (FinFETs) having fish scale gates. However, FinFET has a problem that leakage occurs with DIBL due to electric field strengthening at the corners of the channel. In order to improve this problem, a fin shape having a higher height is proposed, but process uniformity is not secured in implementing a high aspect ratio fin.

Accordingly, an omega gate transistor has been proposed in which the corner portion of the channel is rounded and the width of the lower portion of the channel is further narrowed to increase the contact area between the channel and the gate. Such an omega gate transistor has a shape such as omega in which the channel is Greek. Omega gate transistors can improve many of the problems described above, but are still expensive to manufacture because they can only be implemented on silicon-on-insulator (SOI) substrates. Therefore, a method for implementing an omega gate transistor on a bulk silicon substrate needs to be developed in order to apply to actual production.

It is an object of the present invention to provide a method for forming a channel of an omega gate semiconductor device on a bulk silicon substrate, and an omega gate semiconductor device manufactured by the method.

A method of forming a channel for an omega gate according to one type of the present invention includes forming a silicon oxide film on a bulk silicon substrate; Patterning the silicon oxide film and the substrate to form silicon fins formed vertically on the substrate; Injecting germanium into a substrate surface on both sides of the silicon fin; Reacting germanium (Ge) injected into the substrate and silicon (Si) of the substrate through heat treatment to form a SiGe layer on the substrate surface on both sides of the silicon fin; And removing the silicon oxide film on the silicon fin and the SiGe layer on the surface of the substrate through wet etching to form an omega channel on the substrate.

According to the present invention, there is provided a method for forming a channel for an omega gate, comprising: forming an oxide film around the channel through heat treatment in an oxygen atmosphere; And rounding the corners of the channel by removing the oxide layer through wet etching.

According to the present invention, SiGe may be partially diffused to the lower part of the silicon fin when the SiGe layer is formed.

For example, the heat treatment for forming the SiGe layer may be performed at a temperature of 900 ℃ in a nitrogen atmosphere.

According to a preferred embodiment of the present invention, the composition of Ge in the SiGe layer is in the range of 10at% to 40at%, more preferably about 20at%.

According to the present invention, the etchant for removing the silicon oxide film and the SiGe layer together may use a mixed solution composed of hydrogen fluoride, hydrogen peroxide and acetic acid.

According to another aspect of the present invention, there is provided a method for forming a channel for an omega gate, comprising: forming a silicon oxide film on a bulk silicon substrate; Doping germanium (Ge) into the substrate through a reverse doping method; Reacting germanium (Ge) injected into the substrate and silicon (Si) of the substrate through a heat treatment to form a SiGe layer inside the substrate; Patterning the silicon oxide film and the substrate over the SiGe layer until the SiGe layer is exposed to form silicon fins formed vertically on the SiGe layer; And forming an omega channel on the substrate by removing the silicon oxide layer on the silicon fin and the SiGe layer on both sides of the silicon fin through wet etching.

According to a preferred embodiment of the present invention, the maximum composition of Ge in the SiGe layer may be less than or equal to 10 at%.

In this case, only a part of the SiGe layer directly under the silicon fin may be removed in the wet etching process.

On the other hand, the method of forming a channel for an omega gate according to another type of the present invention, forming an antioxidant film on a bulk silicon substrate; Patterning the antioxidant layer and the substrate to form silicon fins formed vertically on the substrate; Forming an anti-oxidation film on the side of the silicon fin; Etching the antioxidant film so that the antioxidant film remains only on a portion surrounding the silicon fin and the substrate on both sides of the silicon fin is exposed; Oxidizing the exposed substrate to form silicon oxide layers on both sides of the silicon substrate; Forming an omega channel over the substrate by removing the silicon oxide layer through wet etching; And removing the antioxidant layer surrounding the channel through wet etching.

According to the present invention, the silicon oxide layer may be partially formed on the lower portion of the silicon fin when the silicon oxide layer is formed.

For example, the antioxidant layer may be SiN.

According to the present invention, the step of forming the anti-oxidation film on the side of the silicon fin, may be made by additionally depositing an anti-oxidation film on the silicon fin and the thickness of about 200Å over the entire surface of the substrate.

Further, a method for forming an omega gate channel according to another type of the present invention includes: patterning a bulk silicon substrate to form silicon fins formed vertically on the substrate; Forming a silicon oxide layer on the substrate and the silicon fins; Planarizing the silicon oxide layer until the silicon fins are exposed; Using the exposed silicon fins to regrow a semiconductor material over the exposed silicon fins to form an omega channel over the substrate; And removing the silicon oxide layer through wet etching.

According to the present invention, after planarizing the silicon oxide layer, the step of partially removing the silicon oxide layer through wet etching may be further performed so that the silicon fin may protrude over the silicon oxide layer.

In addition, prior to regrowing the semiconductor material, the surface of the exposed silicon fins may be heat treated and cleaned to uniformly adjust the lattice arrangement of the silicon fin surface.

For example, the semiconductor material may be any one of silicon, SiGe, and group III-V semiconductors.

On the other hand, the method of manufacturing an omega gate semiconductor device according to the present invention, forming the channel for the omega gate by the above-described method; Forming a field oxide film inside the substrate on either side of the channel for providing electrical isolation between adjacent transistor cells; Depositing a dielectric material to surround the substrate and the channel to form a gate oxide film; And forming a gate electrode to surround the channel.

Hereinafter, an omega gate semiconductor device and a method of manufacturing the same according to exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A and 1B are a perspective view and a cross-sectional view schematically illustrating the structure of an omega gate semiconductor device 10 according to a preferred embodiment of the present invention, respectively. Generally, a semiconductor device is composed of an array of a plurality of transistor cells, but only one transistor cell is shown in FIGS. 1A and 1B for convenience. 1A and 1B, an omega gate semiconductor device 10 according to the present invention may include, for example, a substrate 11 made of silicon and a source 12 disposed to face each other on both sides of an upper surface of the substrate 11. Drain 13, channel 14 having a narrower width than source 12 and drain 13 and connected between source 12 and drain 13, channel 14 at the central portion of channel 14. A gate oxide film 15 surrounding the perimeter of the gate oxide, and a gate electrode 16 formed on the gate oxide film 15. In addition, a field oxide layer 17 may be further formed in the substrate 11 on both sides of the channel 14 to provide electrical insulation between adjacent transistor cells.

FIG. 1B illustrates a cross section of the omega gate semiconductor device 10 taken along line AA ′ of FIG. 1A. As shown in FIG. 1B, the cross-section of the channel 14 is approximately omega (Ω) in Greek. The gate oxide film 15 also surrounds the channel 14 in an omega shape, and a gate electrode 16 is formed on the surface of the gate oxide film 15. Here, the omega gate semiconductor device 10 according to the present invention having the above-described structure may be manufactured using a bulk silicon substrate. Therefore, both the substrate 11 and the channel 14 may be made of silicon.

As described above, in general, the omega gate semiconductor device can increase the contact area between the channel and the gate as much as possible, thereby improving the channel control per unit area. Conventionally, such an omega gate semiconductor device could be implemented only on an SOI substrate. When the omega gate semiconductor device is implemented as an SOI substrate according to a conventional method, the substrate 11 in FIGS. 1A and 1B may be formed of an insulator such as SiO ₂ instead of silicon. However, since the SOI substrate is relatively expensive, there has been a difficulty in mass production of an omega gate semiconductor device due to cost problems. According to the present invention, it is possible to mass-produce the omega gate semiconductor device 10 shown in FIGS. 1A and 1B using a bulk silicon substrate. Hereinafter, a method of manufacturing the omega gate semiconductor device 10 according to the present invention using a bulk silicon substrate will be described in detail.

First, FIGS. 2A to 2F sequentially illustrate a process of forming an omega gate channel according to a first embodiment of the present invention.

Referring to FIG. 2A, a silicon oxide film (SiO ₂ ) 22 is formed on the top surface of the bulk silicon substrate 21, for example. The silicon oxide layer 22 serves as a mask in a subsequent germanium (Ge) implantation process. Therefore, other materials may be used instead of the silicon oxide film 22 as long as it can act as a mask in Ge implantation. Thereafter, the photoresist 23 is formed on the silicon oxide film 22, and then the photoresist 23 is patterned in a predetermined pattern through, for example, a lithography process. The silicon oxide film 22 and the substrate 21 are etched to a predetermined depth by a dry etching method using the patterned photoresist 23 as a mask, thereby forming the silicon oxide film 22 in the same form as the pattern of the photoresist 23. ) And the substrate 21 are patterned. By doing so, as shown in FIG. 2B, vertically formed silicon fins 25 are formed on the substrate 21.

Next, after Ge is implanted into the surface of the substrate 21 on both sides of the silicon fin 25 by ion implantation, the Ge injected into the substrate 21 is diffused in the lateral direction through heat treatment. The heat treatment may be performed at a temperature of about 900 ° C. in a nitrogen (N ₂ ) atmosphere. In this case, since the distance in which the Ge is diffused in the lateral direction is about 80% of the distance in the vertical direction, the lateral diffusion distance of Ge can be expected. Therefore, it is possible to realize the desired side diffusion distance by adjusting the heat treatment time. At the end of the heat treatment, Ge and Si react to form a SiGe _x layer 24. As shown in FIG. 2C, the SiGe _x layer 24 is formed on the surface of the substrate 21 on both sides of the silicon fin 25, and is also diffused by a predetermined length under the silicon fin 25.

The SiGe _x layer 24 thus formed is removed along with the silicon oxide film 22 through wet etching. At this time, a mixed liquid (HF: H ₂ O ₃ : CH ₃ COOH) composed of hydrogen fluoride, hydrogen peroxide and acetic acid can be used as the etching solution. In this case, in order to have a desired selectivity, the composition of Si _0.8 Ge _0.2 is most suitable, but if necessary, the composition of Ge may be changed within the range of 10 to 40 at% to suitably adjust the etch rate. For example, when the composition of Ge is 20at%, the etching rate is about 200 mW / min, and the etching rate increases as the composition of Ge increases.

As a result, as shown in FIG. 2D, an omega (Ω) type channel 27 may be formed. Next, in order to round the corners of the channel 27, as shown in FIG. 2E, an oxide film 26 is formed around the channel 27 by heat treatment in an oxygen (O ₂ ) atmosphere. Then, the oxide film 26 is removed by wet etching using, for example, diluted hydrofluoric (DHF) as an etchant, thereby obtaining a rounded corner channel 27 as shown in FIG. 2F.

3A through 3E sequentially illustrate a process of forming an omega gate channel according to a second embodiment of the present invention.

In the case of the method according to the second embodiment, as shown in FIG. 3A, after the silicon oxide film 32 is formed on the bulk silicon substrate 31, the reverse doping method used in the semiconductor process is used. Thereby doping Ge into the substrate 31. According to this doping method, the doping concentration of Ge peaks at a point inside the substrate 31.

Then, when Ge and Si are reacted through heat treatment, a SiGe _x layer 33 is formed in the substrate 31 as shown in FIG. 3B. The SiGe _x layer 33 separates the substrate 31 into two parts. Here, the upper portion 34 of the substrate 31 on the upper surface of the SiGe _x layer 33 is a portion where a channel is formed through a subsequent process.

Next, as shown in FIG. 3C, the photoresist 35 is formed on the silicon oxide film 32, and then the photoresist 35 is patterned in a predetermined pattern through a lithography process. The silicon oxide film 32 and the upper portion 34 of the substrate are etched using the patterned photoresist 35 as a mask until the SiGe _x layer 33 is exposed by a dry etching method. Then, as illustrated in FIG. 3D, the silicon oxide film 32 and the upper portion 34 of the substrate are patterned in the same form as the pattern of the photoresist 35. As such, the upper portion 34 of the substrate becomes a silicon fin that is erected vertically over the SiGe _x layer 33.

Subsequently, wet etching removes the SiGe _x layer 33 on both sides of the upper portion 34 of the substrate along with the silicon oxide film 32. As described above, for example, a mixed solution (HF: H ₂ O ₃ : CH ₃ COOH) composed of hydrogen fluoride, hydrogen peroxide, and acetic acid may be used as the etching solution. In the case of this second embodiment, only a portion of the SiGe _x layer 33 directly below the upper portion 34 of the substrate needs to be removed in the wet etching process. In this case, therefore, the Ge amount in the SiGe _x layer 33 is at most 10 at% or less, which is suitable for obtaining an etching selectivity sufficient. Then, as shown in Figure 3e, the channel 36 in the form of omega (Ω) is formed. Then, additionally, the corner portion of the channel 36 may be rounded, according to the method described in FIGS. 2E-2F.

4A to 4G sequentially illustrate a process of forming an omega gate channel according to a third embodiment of the present invention.

First, referring to FIG. 4A, a SiN _x layer 42 is formed on a bulk silicon substrate 41. Here, SiN _x layer 42 acts as a barrier to prevent oxidation of silicon in subsequent processes. Thus, the SiN _x layer 42 is illustrative, and it is also possible to form another material suitable for the oxidation prevention on the silicon substrate 41.

Then, as shown in FIG. 4B, a silicon fin 43 formed vertically by patterning the substrate 41 and the SiN _x layer 42 is formed on the substrate 41. The method of patterning the substrate 41 and the SiN _x layer 42 is as already described with reference to FIGS. 2A and 3C. That is, after the photoresist is formed on the SiN _x layer 42, the photoresist is patterned through a lithography process, and the substrate 41 and the SiN _x layer 42 are etched using the patterned photoresist as a mask.

Next, SiN _x is further deposited on the entire surface of the substrate 41 and the SiN _x layer 42 to a thickness of, for example, about 200 mm 3. In this process, as shown in FIG. 4C, SiN _x is also formed on the side surface of the silicon fin 43. Then, when the SiN _x is etched until the surface of the substrate 41 on both sides of the silicon fin 43 is exposed, as shown in FIG. 4D, only SiN _x remains in the portion surrounding the silicon fin 43. . This remaining SiN _x serves as a barrier to prevent the silicon fin 43 from oxidizing in a subsequent oxygen diffusion process. As shown in FIG. 4E, when oxygen is diffused onto the exposed substrate 41 on both sides of the silicon fin 43, silicon is oxidized to form a silicon oxide layer (SiO ₂ ) 44 on the exposed surface of the substrate 41. Is formed. At this time, since oxygen diffuses not only in the vertical direction but also in the lateral direction, the silicon oxide layer 44 is partially formed at the portion directly below the silicon fin 43.

Subsequently, the silicon oxide layer 44 thus formed is removed through wet etching. Then, as shown in FIG. 4F, an omega-shaped channel 45 is formed on the substrate 41. Finally, for example, H ₃ PO ₄ is used as an etchant to completely remove SiN _x surrounding the channel 45 through wet etching. Then, as shown in FIG. 4G, only the omega-shaped channel 45 remains. Thereafter, the corner portion of the channel 45 may be rounded by the method shown in FIGS. 2E and 2F.

5A through 5G sequentially illustrate a process of forming an omega gate channel according to a fourth embodiment of the present invention.

Referring to FIG. 5A, after the photoresist 52 is formed on the bulk silicon substrate 51, the photoresist 52 is patterned through a lithography process, and the substrate is formed using the patterned photoresist 52 as a mask. 51). Then, as shown in FIG. 5B, a silicon fin 53 is formed on the etched substrate 51.

Then, as shown in FIG. 5C, a silicon oxide layer 54 is deposited on the substrate 51 and the silicon fins 53 by, for example, plasma chemical vapor deposition (PECVD). At this time, the region of the silicon oxide layer 54 corresponding to the region of the silicon fin 53 also protrudes. Next, as shown in FIG. 5D, the silicon oxide layer 54 is planarized until the silicon fins 53 are exposed using, for example, a CMP process. As shown in FIG. 5E, the silicon oxide layer 54 is partially removed by wet etching so that the silicon fins 53 may protrude over the silicon oxide layer 54.

Subsequently, as shown in FIG. 5F, the semiconductor material is regrown on the exposed silicon fins 53 to form a channel 55. Here, regrowth of the semiconductor material can be performed using, for example, an epitaxy process. In addition, in order to enable regrowth of the semiconductor material to be of high quality, the lattice arrangement of the surface of the silicon fins 53 may be uniformly adjusted by heat treatment and cleaning the exposed surfaces of the silicon fins 53. The cleaning may be performed using, for example, native oxide on the surface of the silicon fin 53 using DI water + SC1 (Standard cleaning 1; NH ₄ OH: H ₂ O ₂ : H ₂ O) + DHF mixture. After repeated removal of H ₂ gas, HCl gas is mixed with a high temperature chemical bake treatment at a temperature of about 850 ° C. or less to remove carbon or oxygen contaminants. Alternatively, carbon or oxygen contaminants may be removed through a Cl base plasma etching process.

In the present embodiment, as the semiconductor material to be the material of the channel 55, it is also possible to regrow not only silicon but also various other semiconductor materials. For example, SiGe _x or a III-V semiconductor or the like can be regrown as the channel 55. According to this embodiment, it is possible to regrow the semiconductor material with high mobility characteristics as the channel 55. Therefore, according to the present embodiment, it is possible to implement a transistor having a high mobility.

Finally, as shown in FIG. 5G, the remaining silicon oxide layer 54 is completely removed through wet etching. Then, an omega channel 55 is completed on the substrate 51. As an additional process, as described above, the corner portion of the channel 55 may be rounded by the method shown in FIGS. 2E and 2F.

On the other hand, as described above, the semiconductor device is composed of an array of a plurality of transistor cells, the adjacent transistor cells should be electrically insulated from each other. To this end, as shown in FIGS. 1A and 1B, a field oxide film 17 is formed inside the substrate 11 on both sides of the channel 14. 6A through 6D sequentially illustrate a method of forming a field oxide film 17 to isolate between cells after forming the channel for the omega gate according to the first to fourth embodiments of the present invention.

First, as shown in FIG. 6A, a SiN _x layer 18 is formed over the substrate 11 and the finished omega channel 14. Then, when etching a SiN _x layer 18 until reveal the surface of the substrate 11, the, the SiN _x layer 18, only the portion surrounding the channel 14, as shown in Figure 6b remains . Next, as shown in FIG. 6C, when oxygen is diffused into the substrate 11 through the exposed portion of the substrate 11, silicon is oxidized under the exposed portion of the substrate 11 to form SiO ₂ . A field oxide film 17 is formed. In this process, since oxygen diffuses not only in the vertical direction but also in the lateral direction, the field oxide film 17 can be extended to the region immediately below the channel 14. After the field oxide film 17 is formed in this manner, for example, H ₃ PO ₄ is used as an etchant to completely remove the SiN _x layer 18 surrounding the omega channel 14 by wet etching.

After the omega channel 14 and the field oxide layer 17 are formed as described above, gates, sources, and drains may be formed according to a general transistor manufacturing process. 7A-7D sequentially illustrate exemplary methods for forming an omega gate around a channel.

FIG. 7A shows a state in which a field oxide film 17 and an omega channel 14 are formed on the substrate 11. As shown in Fig. 7B, a dielectric material is formed as a gate oxide film 15 on the structure shown in Fig. 7A to a certain thickness. In this case, although SiO ₂ may be used as the dielectric material, a dielectric material having a high dielectric constant may be used to realize the gate length Lg of 45 nm or less. For example, as a dielectric material for the gate oxide film 15, a high dielectric material such as HfO ₂ , Al ₂ O ₃ , La ₂ O ₃ , ZrO ₂ , HfSiO, HfSiON, HfLaO, LaAlO, SrTiO, or the like may be used. Thereafter, as shown in FIG. 7C, the gate metal is entirely deposited on the gate oxide film 15 to form the gate electrode 16, and then the gate metal between the cells is removed by etching as shown in FIG. 7D. do. As a result, the gate electrode 16 surrounding the channel 14 is completed. Here, for example, TiAlN, MoN, TaCN, or the like may be used as the gate metal for pMOS, and W ₂ N, TaSiN, (RE) TaN, WC, or the like may be used as the gate metal for nMOS.

Thereafter, according to the known technique, an omega gate as shown in FIGS. 1A and 1B is formed by doping and heat-treating the substrate 11 connected to both sides of the channel 14 to form the source 12 and the drain 13, respectively. The semiconductor device 10 can be completed.

To date, exemplary embodiments have been described and illustrated in the accompanying drawings in order to facilitate understanding of the present invention. However, it should be understood that such embodiments are merely illustrative of the invention and do not limit it. And it is to be understood that the invention is not limited to the illustrated and described description. This is because various other modifications may occur to those skilled in the art.

1A and 1B are respectively a perspective view and a cross-sectional view showing a schematic structure of an omega gate semiconductor device according to the present invention.

2A through 2F sequentially illustrate a process of forming an omega gate channel according to an embodiment of the present invention.

3A through 3E sequentially illustrate formation of an channel for an omega gate according to another exemplary embodiment of the present invention.

4A through 4G sequentially illustrate a process of forming an omega gate channel according to another embodiment of the present invention.

5A through 5G sequentially illustrate a process of forming an omega gate channel according to another embodiment of the present invention.

6A-6D sequentially illustrate a method for electrically isolating between multiple transistor cells after forming a channel for an omega gate.

7A-7D sequentially illustrate a method of forming an omega gate around a channel after cell isolation.

<Description of Symbols for Main Parts of Drawings>

10 ..... semiconductor element 11 ..... silicon substrate

12 ..... source 13 ..... drain

14 ..... channel 15 ..... gate oxide

16 ..... gate electrode 17 ..... field oxide

Claims (25)

Forming a silicon oxide film on the bulk silicon substrate; Patterning the silicon oxide film and the substrate to form silicon fins formed vertically on the substrate; Injecting germanium into a substrate surface on both sides of the silicon fin; Reacting germanium (Ge) injected into the substrate and silicon (Si) of the substrate through heat treatment to form a SiGe layer on the substrate surface on both sides of the silicon fin; And Forming an omega channel on the substrate by removing the silicon oxide layer on the silicon fin and the SiGe layer on the surface of the substrate through wet etching. The method of claim 1, Forming an oxide film around the channel through heat treatment in an oxygen atmosphere; And rounding the corners of the channel by removing an oxide film through wet etching. The method of claim 1, And forming SiGe in the lower part of the silicon fin at the time of forming the SiGe layer. The method of claim 1, The heat treatment for forming the SiGe layer is a channel forming method for the omega gate, characterized in that carried out at a temperature of 900 ℃ in a nitrogen atmosphere. The method of claim 1, The composition of the Ge in the SiGe layer is a channel forming method for the omega gate, characterized in that in the range of 10at% to 40at%. The method of claim 5, wherein The method of forming a channel for an omega gate, characterized in that the composition of Ge in the SiGe layer is 20at%. The method of claim 1, The etching solution for removing the silicon oxide film and the SiGe layer together using a mixed solution composed of hydrogen fluoride, hydrogen peroxide and acetic acid. Forming a silicon oxide film on the bulk silicon substrate; Doping germanium (Ge) into the substrate through a reverse doping method; Reacting germanium (Ge) injected into the substrate and silicon (Si) of the substrate through a heat treatment to form a SiGe layer inside the substrate; Patterning the silicon oxide film and the substrate over the SiGe layer until the SiGe layer is exposed to form silicon fins formed vertically on the SiGe layer; And And forming an omega channel on the substrate by removing the silicon oxide layer on the silicon fin and the SiGe layer on both sides of the silicon fin through wet etching. 2. The method of claim 8, Forming an oxide film around the channel through heat treatment in an oxygen atmosphere; And rounding the corners of the channel by removing an oxide film through wet etching. The method of claim 8, The heat treatment for forming the SiGe layer is a channel forming method for the omega gate, characterized in that carried out at a temperature of 900 ℃ in a nitrogen atmosphere. The method of claim 8, And wherein the maximum composition of Ge in said SiGe layer is less than or equal to 10at%. The method of claim 8, The etching solution for removing the silicon oxide film and the SiGe layer together using a mixed solution composed of hydrogen fluoride, hydrogen peroxide and acetic acid. The method of claim 8, And a portion of the SiGe layer directly below the silicon fin is removed in the wet etching process. Forming an anti-oxidation film on the bulk silicon substrate; Patterning the antioxidant layer and the substrate to form silicon fins formed vertically on the substrate; Forming an anti-oxidation film on the side of the silicon fin; Etching the antioxidant film so that the antioxidant film remains only on a portion surrounding the silicon fin and the substrate on both sides of the silicon fin is exposed; Oxidizing the exposed substrate to form silicon oxide layers on both sides of the silicon substrate; Forming an omega channel over the substrate by removing the silicon oxide layer through wet etching; And Removing the antioxidant layer surrounding the channel by wet etching; and forming a channel for an omega gate. The method of claim 14, Forming an oxide film around the channel through heat treatment in an oxygen atmosphere; And rounding the corners of the channel by removing an oxide film through wet etching. The method of claim 14, And forming a silicon oxide layer partially below the silicon fin when the silicon oxide layer is formed. The method of claim 14, The antioxidant film is SiN channel formation method, characterized in that the SiN. The method of claim 14, Forming an oxide film on the side of the silicon fin, the oxide film on the silicon fin and the channel forming method for the omega gate, characterized in that further depositing an oxide film to a thickness of 200Å over the entire surface of the substrate. Patterning the bulk silicon substrate to form silicon fins formed vertically on the substrate; Forming a silicon oxide layer on the substrate and the silicon fins; Planarizing the silicon oxide layer until the silicon fins are exposed; Using the exposed silicon fins to regrow a semiconductor material over the exposed silicon fins to form an omega channel over the substrate; And Removing the silicon oxide layer through wet etching; and forming a channel for the omega gate. The method of claim 19, Forming an oxide film around the channel through heat treatment in an oxygen atmosphere; And rounding the corners of the channel by removing an oxide film through wet etching. The method of claim 19, And after the planarization of the silicon oxide layer, partially removing the silicon oxide layer by wet etching so that the silicon fins can protrude over the silicon oxide layer. The method of claim 19, Prior to regrowing the semiconductor material, heat treating and cleaning the exposed silicon fin surface to uniformly adjust the lattice arrangement of the silicon fin surface. The method of claim 19, And the semiconductor material is any one of silicon, SiGe, and group III-V semiconductors. Forming a channel for an omega gate by a method according to any one of claims 1 to 23; Forming a field oxide film inside the substrate on either side of the channel for providing electrical isolation between adjacent transistor cells; Depositing a dielectric material to surround the substrate and the channel to form a gate oxide film; And Forming a gate electrode so as to surround the channel. An omega gate semiconductor device manufactured by the method of claim 24.

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