TWI627708B - 具有保留處理晶圓部之裝置層轉移 - Google Patents
具有保留處理晶圓部之裝置層轉移 Download PDFInfo
- Publication number
- TWI627708B TWI627708B TW105142969A TW105142969A TWI627708B TW I627708 B TWI627708 B TW I627708B TW 105142969 A TW105142969 A TW 105142969A TW 105142969 A TW105142969 A TW 105142969A TW I627708 B TWI627708 B TW I627708B
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- dielectric layer
- wafer
- buried dielectric
- permanent substrate
- Prior art date
Links
- 238000012546 transfer Methods 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 124
- 238000000034 method Methods 0.000 claims abstract description 43
- 238000012545 processing Methods 0.000 claims abstract description 43
- 239000012212 insulator Substances 0.000 claims abstract description 27
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 104
- 239000003990 capacitor Substances 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 21
- 239000012790 adhesive layer Substances 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 10
- 229910052715 tantalum Inorganic materials 0.000 claims description 9
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 239000000853 adhesive Substances 0.000 claims description 6
- 230000001070 adhesive effect Effects 0.000 claims description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 239000010453 quartz Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 229910052594 sapphire Inorganic materials 0.000 claims description 2
- 239000010980 sapphire Substances 0.000 claims description 2
- 229910052797 bismuth Inorganic materials 0.000 claims 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 92
- 230000014759 maintenance of location Effects 0.000 description 20
- 239000000463 material Substances 0.000 description 14
- 230000035515 penetration Effects 0.000 description 5
- 238000003672 processing method Methods 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- SIKJAQJRHWYJAI-UHFFFAOYSA-N Indole Chemical compound C1=CC=C2NC=CC2=C1 SIKJAQJRHWYJAI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 229910000420 cerium oxide Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910016570 AlCu Inorganic materials 0.000 description 1
- 229910052684 Cerium Inorganic materials 0.000 description 1
- 229910018503 SF6 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 1
- BCZWPKDRLPGFFZ-UHFFFAOYSA-N azanylidynecerium Chemical compound [Ce]#N BCZWPKDRLPGFFZ-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 229940104869 fluorosilicate Drugs 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- PZOUSPYUWWUPPK-UHFFFAOYSA-N indole Natural products CC1=CC=CC2=C1C=CN2 PZOUSPYUWWUPPK-UHFFFAOYSA-N 0.000 description 1
- RKJUIXBNRJVNHR-UHFFFAOYSA-N indolenine Natural products C1=CC=C2CC=NC2=C1 RKJUIXBNRJVNHR-UHFFFAOYSA-N 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/13—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body combined with thin-film or thick-film passive components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Abstract
本發明提供集合體,包括矽絕緣體(SOI)基板的裝置層、及取代該SOI基板的處理晶圓的取代基板,還提供用於將該SOI基板的裝置層從處理晶圓移送至取代基板的方法。在處理晶圓的第一區段中形成裝置結構,並且移除與處理晶圓的第一區段毗連的處理晶圓的第二區段,以曝露矽絕緣體基板的埋置型介電層的表面。使永久基板附接至埋置型介電層的表面。當永久基板附接至埋置型介電層的表面時,永久基板中界定的凹穴內側接收處理晶圓的區段。
Description
本發明大體上關於半導體裝置及積體電路製造,並且特別的是,關於集合體(assembly),其包括上覆半導體絕緣體(semiconductor-on-insulator;SOI)基板的裝置層、及取代SOI基板的處理(handle)晶圓的取代基板,此外還有關於將SOI基板的裝置層從SOI基板的處理晶圓移送至取代基板的方法。
使用上覆半導體絕緣體技術製造的裝置與主體矽基板中直接建置的對照裝置相比較,可呈現某些效能提升。大體上,SOI晶圓包括半導體材料的薄裝置層、處理晶圓、以及薄埋置型絕緣體層,例如:埋置型氧化物(buried oxide)或BOX層,其使得裝置層與處理晶圓實體分離並且電氣隔離。積體電路在製造時,可使用在SOI晶圓的正面表面處的裝置層的半導體材料,並且可能還使用處理晶圓的半導體材料。
晶圓薄化因為需要使封裝更薄而盛行,以便符合堆疊與高密度晶片封裝的需求。SOI晶圓可通過將
處理晶圓移離其構造而薄化,而且一旦薄化,便對背面表面進行附加操作。為了在薄化、以及薄化後進行的任何附加操作期間提供機械支撐,正面表面可採黏著方式接合至暫時基板。進行附加操作之後,永久基板可附接至背面表面而取代處理晶圓,並且可將暫時基板移離正面表面。
需要改良型集合體,其包括SOI基板的裝置層、及該SOI基板的處理晶圓用的取代基板,還需要用於將該SOI基板的裝置層從處理晶圓移送至取代基板的改良型方法。
在本發明的一具體實施例中,一種方法包括在矽絕緣體基板的處理晶圓的第一區段中形成裝置結構,移除與該處理晶圓的該第一區段毗連的該處理晶圓的第二區段,以曝露該矽絕緣體基板的埋置型介電層,以及使永久基板附接至該埋置型介電層的表面。當永久基板附接至埋置型介電層時,永久基板中界定的凹穴內側接收處理晶圓的第一區段。
在本發明的一具體實施例中,一種使用矽絕緣體基板形成的集合體。集合體包括矽絕緣體基板的裝置層、以及矽絕緣體基板的埋置型絕緣體層。埋置型絕緣體層具有與裝置層接觸的第一表面、以及與第一表面對立的第二表面。集合體包括於埋置型絕緣體層的第二表面上所佈置的矽絕緣體基板的處理晶圓的區段、以及處理晶圓的區段中的裝置結構。集合體更包括附接至埋置型絕緣體
層的永久基板。永久基板包括組配成用以接收處理晶圓的區段的凹穴。
10‧‧‧集合體或SOI基板
12‧‧‧半導體絕緣體(SOI)基板
14‧‧‧暫時基板
16‧‧‧裝置層
18‧‧‧埋置型介電層或中介埋置型介電層
18a、18b、37‧‧‧表面
20‧‧‧處理晶圓
21‧‧‧保留區段
22‧‧‧深溝槽電容器
23‧‧‧表面或側表面
24‧‧‧深溝槽
25、32a‧‧‧表面或頂端表面
26‧‧‧互連結構
28‧‧‧接合墊
30、35‧‧‧黏著層
32‧‧‧永久基板
34‧‧‧中間集合體
36‧‧‧凹穴
38‧‧‧最終集合體
40‧‧‧連接結構
附圖合併於並且構成本說明書的一部分,繪示本發明的各項具體實施例,並且連同上文本發明的一般性說明、及下文具體實施例的詳細說明,作用在於闡釋本發明的具體實施例。
第1圖根據本發明的一具體實施例,為集合體形成用處理方法初始製造階段基板一部分的截面圖,其中該集合體是採倒置方式展示。
第2圖為第1圖的處理方法的後續製造階段上的基板部分的截面圖。
第3圖為第2圖的處理方法的後續製造階段上的基板部分的截面圖,其中該集合體是採非倒置方式展示。
請參閱第1圖,並且根據本發明的一具體實施例,集合體10包括上覆半導體絕緣體(SOI)基板12、以及已在SOI基板10上形成裝置與電線後採可移除方式附接至SOI基板10的正面的暫時基板14。SOI基板12可包括裝置層16、形式為埋置型氧化物(buried oxide;BOX)層的埋置型介電層18、以及處理晶圓20。裝置層16通過中介埋置型介電層18而與處理晶圓20分離,並且比處理晶圓20薄非常多。埋置型介電層18具有與處理晶圓20直接接觸
的表面18a、以及與裝置層16直接接觸的另一表面18b,而且這些表面18a、18b通過埋置型介電層18的厚度來分離。
裝置層16與處理晶圓20可由諸如矽的單晶半導體材料所構成。裝置層16可含有CMOS電晶體或雙極性接面電晶體、被動物、矽化矽(silieided silicon)、淺溝槽隔離氧化物等。埋置型介電層18可由電絕緣體所構成,並且特別的是,可以是由二氧化矽(例如:SiO2)所構成的埋置型氧化物層。裝置層16通過埋置型介電層18與處理晶圓20電性隔離。
前段(Front-end-of-line;FEOL)處理用於使用裝置層16製造一或多個積體電路的裝置結構,並藉以在採可移除方式附接暫時基板14之前,先形成晶片。裝置結構如上所述可以是雙極性接面電晶體、場效電晶體、被動物、及/或共面波導(coplanar waveguide;CPW)傳輸線,而晶片上由集合體10所形成的積體電路可經組配而在高頻與高功率應用(例如:無線通訊系統及行動裝置用的功率放大器)中及高速邏輯電路中用於終端用途。積體電路可包括諸如開關、功率放大器、功率管理單元、濾波器等各種功能塊。
在一代表性具體實施例中,裝置結構可包括延伸穿過裝置層16並穿透至給定深度d進入處理晶圓20的深溝槽24中形成的一或多個深溝槽電容器22。多個深溝槽24與深溝槽電容器22可設置成陣列(array)以形成
多個裝置結構。深溝槽24可通過塗敷硬遮罩、利用光微影與蝕刻圖案化硬遮罩、然後使用反應性離子蝕刻(reactive ion etch;RIE)程序界定深溝槽來形成。蝕刻程序可採單一蝕刻步驟或多重蝕刻步驟來進行,可憑靠一或多種蝕刻化學品,並且可在受到控制的條件下進行以限制深溝槽24進入處理晶圓20的穿透深度。
各深溝槽電容器22可包括各別深溝槽24的側壁上所形成作為襯墊的絕緣體層、以及由諸如經摻雜多晶矽的導電體所構成的插塞,其佔據剩餘空間。絕緣體層運作為深溝槽電容器22中的電容器介電質,插塞運作為深溝槽電容器22的電極或板材,而相鄰於深溝槽24的處理晶圓20運作為深溝槽電容器22的另一電極或板材,並且可用n型或p型摻質進行摻雜以降低寄生電阻。
中段(Middle-of-line;MOL)與後段(back-end-of-line;BEOL)處理接在前段處理後進行以形成多階互連結構,大體上是以參考元件符號26來指出,上覆於SOI基板12的裝置層16。互連結構26可由複數個接線層中的接線所構成,此接線供應用於信號、時脈、電力等的傳導路徑。互連結構26的接線與晶片的積體電路耦合,並且特別的是,可與深溝槽電容器22耦合。諸如二極體、電阻器、電容器、變容器及電感器等其它主動與被動電路元件可整合成互連結構26。
接線層可通過沉積、光微影圖案化、蝕刻、以及鑲嵌及/或消去性圖案化拋光技術特性來形成。接線用
的候選導體包括金屬,例如銅(Cu)、鋁(Al)、鋁銅(AlCu)、以及與諸如鉭(Ta)、鈦(Ti)、氮化鉭(TaN)及氮化鈦(TiN)等耐火金屬組合的鎢(W),其可通過化學氣相沉積、物理氣相沉積、蒸鍍、或通過與電鍍或無電式鍍覆相似的電化學程序來沉積。不同接線層的接線嵌埋於介電層中,其可由諸如二氧化矽、氮化矽、濃縮氫的碳氧化矽(SiCOH)、及氟矽酸玻璃(fluorosilicate glass;FSG)等任何合適的有機或無機介電材料所構成,其舉例而言,可通過化學氣相沉積來沉積。
特別的是,互連結構26的最頂端接線層可包括接合墊28,其可用以建立與晶片上積體電路的外部連接。接合墊28可由銅、鋁、或這些金屬的合金所構成。接合墊28舉例而言,可作用為耦合至正供應電壓(VDD)或接地(VSS)用以供電給晶片上主動電路系統的配電接墊,作用為用於使信號與晶片上主動電路系統往來連通的輸入/輸出(I/O)接墊,或作用為與晶片的主動電路系統電性隔離的虛設(dummy)接墊。
暫時基板14採可移除方式附接至互連結構26位於SOI基板12正面處的頂端表面,而處理晶圓20在薄化前、且完成前段、中段、及後段處理後則保持原封不動。舉例而言,暫時基板14可通過黏著層30採黏著方式接合至互連結構26的頂端表面,以便提供可釋離或可移除附接。暫時基板14厚到足以在處理晶圓20為了將其背面的SOI基板12薄化而於後續製造階段縮減厚度時,容許進
行機械裝卸。暫時基板14可由石英、玻璃或不同材料所構成。黏著層30可由聚合物黏著劑所構成,例如:聚亞醯胺黏著層,或更具體來說,HD3007聚亞醯胺黏著劑。黏著層30的黏著強度在選擇方面,可在使用例如雷射或機械釋離進行後續剝離時,使暫時基板14輕易自其附接至互連結構26的頂端表面的狀態釋離。
處理晶圓20通過研磨、蝕刻、及/或拋光並透過薄化,得以朝向與埋置型介電層18在表面18a處的界面移離其背面。薄化程序受到控制以保留處理晶圓20的殘餘厚度t,使得薄化結束後,埋置型介電層18的背面18a維持完全受到包覆。處理晶圓20的殘餘厚度在選擇方面,大於深溝槽24的穿透深度,可讓深溝槽電容器22進入處理晶圓20。在一具體實施例中,處理晶圓20的殘餘厚度可以是大於深溝槽24的穿透深度的5μm到20μm,讓深溝槽電容器22進入處理晶圓20。結果是,深溝槽24的完整性不因薄化程序而受損,而且深溝槽電容器22與深溝槽24在完成薄化處理晶圓20的程序之後,原封不動且不受干擾。
請參閱第2圖,其中相似的參考元件符號是指第1圖中相似的特徵,而且在處理方法的後續製造階段,處理晶圓20的殘餘厚度經光微影圖案化與蝕刻,以將處理晶圓20在包括深溝槽24處除外的半導體材料移除。結果為處理晶圓20保留於深溝槽24所在處的保留區段21。處理晶圓20的保留區段21包括側表面23,其自頂端
表面25延展至埋置型介電層18的表面18a。
處理晶圓20的保留區段21具有非零厚度,其等於處理晶圓20薄化後的厚度,還在垂直於此厚度的平面中具有寬度W1及長度。處理晶圓20相鄰於處理晶圓20的保留區段21處具有零厚度,從而使埋置型介電層18曝露。處理晶圓20的這個零厚度區域可剔除基板與裝置的耦合,例如:SOI開關,如此可改善切換性質,例如:插入損耗與線性。
若要圖案化處理晶圓20的殘餘厚度,由諸如光阻的光敏材料所構成的遮罩層可通過旋轉塗佈程序塗敷、預烘培、受透過光遮罩投射的光曝照、曝照後烘培、以及利用化學顯影劑顯影來界定將處理晶圓20的保留區段21包覆的蝕刻遮罩。蝕刻程序在有遮罩層的情況下,通過移除處理晶圓20的未受掩蔽區段,並且終止於埋置型介電層18的材料上,而用於形成處理晶圓20的保留區段21。蝕刻程序可採單一蝕刻步驟或多重蝕刻步驟來進行,可憑靠一或多種蝕刻化學品,可使用乾式電漿或濕式蝕刻程序,並且可在受到控制的條件下進行以限制SOI基板12的穿透深度。用於矽處理晶圓20的蝕刻程序的實施例是以六氟化硫為主的電漿蝕刻或以氫氧化鉀為主的濕矽蝕刻。
可對埋置型介電層18選擇性移除處理晶圓20的未受掩蔽區段,以使得埋置型介電層18在移除處理晶圓20後維持原封不動。“選擇性”一詞參照材料移除程序(例如:蝕刻)於本文中使用時,表示憑藉選擇適當的蝕
刻劑,靶材料的材料移除率高於經受材料移除程序的至少另一材料的移除率。
通過蝕刻程序界定處理晶圓20的保留區段21之後,可移除遮罩層。此遮罩層若由光阻所構成,可通過灰化或溶劑剝除,然後再通過習知的清潔程序來移除。
永久基板32附接至埋置型介電層18以建立中間集合體34,其仍包括暫時基板14。特別的是,埋置型介電層18的背面18a與永久基板32的頂端表面32a接觸而置,而且這些表面18a、32a後續通過例如熱程序(例如:氧化物接合)、或利用諸如HD3007聚亞醯胺的黏著層予以接合在一起。在此中間集合體中,裝置層16、埋置型介電層18、以及互連結構26安置於暫時基板14與永久基板32之間。當SOI基板12的埋置型介電層18與永久基板32接合在一起時,接合的表面18a、32a共面或實質共面。
在各項具體實施例中,永久基板32可以是由高電阻矽、藍寶石、石英、矽土玻璃、礬土等所構成的工程處理的高電阻晶圓。處理晶圓20可以是不昂貴的基板(例如:常見的矽晶圓),是在處理期間用於製造晶片的積體電路,然後由永久基板32所取代以提供最終集合體,可期望呈現改善的效能度量。
永久基板32包括凹穴36,其相對於與埋置型介電層18的表面18a附接的表面32a而凹陷。凹穴36經策略性安置而與在裝配時含有深溝槽電容器22的處理晶圓20的保留區段21對準。凹穴36具有表面37,其經
幾何塑形而反映處理晶圓20的保留區段21的表面23、25。凹穴36具有深度D,其大於處理晶圓20薄化後的厚度,並且特別的是,大於處理晶圓20的保留區段21的厚度。凹穴36具有寬度W2(及長度),其大於處理晶圓20的保留區段21的寬度(及長度)。
在代表性具體實施例中,永久基板32可利用黏著層35附接至埋置型介電層18。凹穴36的尺寸可在處理晶圓20的保留區段21間提供間隙,用以容納黏著層35的厚度及置放容限(tolerance)。在一具體實施例中,凹穴36的深度可以是比處理晶圓20的保留區段21的殘餘厚度更大的4μm至8μm,並且凹穴36的寬度可小於或等於30μm但大於處理晶圓20的保留區段21的寬度,用以容納裝配期間的置放容限、以及容納黏著層35。
在一替代具體實施例中,永久基板32不使用黏著劑也可附接至埋置型介電層18。在此實例中,凹穴36的尺寸可以更小,以致與處理晶圓的保留區段21的餘隙得以減小或消除。在一特定具體實施例中,凹穴36的尺寸可等於或稍大於處理晶圓20的保留區段21的尺寸。
永久基板32的一部分得以選擇性移除以容納保留區段21,其自埋置型介電層18上有形成裝置結構的表面18a突出。若要形成凹穴36,可將遮罩層塗敷至永久基板32的表面,後續與埋置型介電層18耦合,然後利用光微影圖案化。為達此目的,此遮罩層可包含諸如光阻的光敏材料,其經受通過旋轉塗佈程序的塗敷、預烘培、
穿過光遮罩投射的光曝照、曝照後烘培,然後以化學顯影劑顯影,而在凹穴36的意欲位置與開口界定蝕刻遮罩。開口的尺寸在選擇方面可提供凹穴36所需要的寬度及長度。蝕刻程序在有遮罩層的情況下,用於形成凹穴36。蝕刻程序可採單一蝕刻步驟或多重蝕刻步驟來進行,可憑靠一或多種蝕刻化學品,並且可在受到控制的條件下進行以限制進入永久基板32的穿透深度。可在通過蝕刻程序形成凹穴36後移除遮罩層。此遮罩層若由光阻所構成,可通過灰化或溶劑剝除,然後再通過習知的清潔程序來移除。
請參閱第3圖,其中相似的參考元件符號是指第2圖中相似的特徵,而且在處理方法的後續製造階段,隨後移除暫時基板14以提供最終集合體38,但不干擾永久基板32與埋置型介電層18間的接合。舉例而言,中間集合體34可置放於加熱卡盤上以降低黏著層30所提供的黏著接合的強度,以使得可利用施力輕易移除暫時基板14。替代地,黏著層30可進行雷射釋離,接著移除暫時基板14,然後進行任選的濕式或電漿清潔以移除殘餘黏著劑。
暫時基板14起作用而有助於將裝置層16中及上的積體電路移送至永久基板32。最終集合體中的永久基板32取代初始集合體10中SOI基板12的處理晶圓20。諸如焊塊、銅柱、打線、或晶圓級晶片尺寸封裝的連接結構40可在接合墊28上形成,後面跟著晶片的背面研磨、分切及封裝。
在一替代具體實施例中,利用處理晶圓20的保留區段21的裝置結構類型可有別於代表性的深溝槽電容器22。舉例而言,此裝置結構的類型可包含一或多個電阻器、一或多個電容器、一或多個電晶體、一或多個電感器等。在一特定替代具體實施例中,此裝置結構可以是在處理晶圓20中形成有集極(collector)與副集極(sub-collector)的雙極性接面電晶體。另外,可複製此構造以包括與保留區段21相似的多個保留區段、以及與此等保留區段對準(registered)且與凹穴36相似的多個凹穴。
深溝槽電容器22常在SOI技術中使用。通過背面薄化移除處理晶圓20時,使埋置型介電層18的表面18a曝露,但區段21(以及其它類似的保留區段)除外。在處理晶圓20進行背面薄化使埋置型介電層18的剩餘部分曝露後,通過將區段21保留,本發明的具體實施例促進SOICMOS裝置與深溝槽電容器22在通過已工程處理性質進行特性分析的永久基板32上的整合。從而可以在相同的晶圓或晶片上使用深溝槽電容器及低RF損失基板。
本方法如以上所述,是用於製造積體電路晶片。產生的積體電路晶片可由製造商以空白晶圓形式(例如:作為具有多個未封裝晶片的單一晶圓)、當作裸晶粒、或以封裝形式來配送。在後例中,晶片嵌裝於單晶片封裝(例如:塑膠載體,有導線黏貼至主機板或其它更高層次載體)中、或多晶片封裝(例如:具有表面互連或埋置型互連任一者或兩者的陶瓷載體)中。無論如何,晶片可與其它晶
片、離散電路元件、及/或其它信號處理裝置整合,作為中間產品或或最終產品的部分。
本文中對“垂直”、“水平”等用語的參照屬於舉例,並非限制,用以建立參考架構。“水平”一詞於本文中使用時,定義為與半導體基板的習知平面平行的平面,與其實際三維空間方位無關。“垂直”與“正交”等詞是指垂直於水平的方向,如剛才的定義。“橫向”一詞是指水平平面內的維度。
一特徵可連至或與另一元件進行“連接”或“耦合”,其可直接連接或耦合至其它元件,或取而代之,可存在一或多個中介元件。如無中介元件,一特徵可“直接連接”或“直接耦合”至另一元件。如有至少一個中介元件,一特徵可“間接連接”或“間接耦合”至另一元件。
本發明的各項具體實施例的描述已為了說明目的而介紹,但用意不在於窮舉或受限於所揭示的具體實施例。許多修改及變例對於所屬技術領域中具有通常知識者將會顯而易知,但不會脫離所述具體實施例的範疇及精神。本文中使用的術語是為了最佳闡釋具體實施例的原理、對市場出現的技術所作的實務應用或技術改良、或讓所屬技術領域中具有通常知識者能夠理解本文中所揭示的具體實施例而選擇。
Claims (16)
- 一種製造半導體裝置的方法,其包含:提供包括裝置層、處理晶圓及介於該裝置層及該處理晶圓之間的埋置型介電層之矽絕緣基板;延伸穿過該裝置層及該埋置型介電層進入該處理晶圓的第一區段中形成一或多個深溝槽電容器;移除與該處理晶圓的該第一區段毗連的該處理晶圓的第二區段,以曝露該矽絕緣體基板的該埋置型介電層的表面;使永久基板附接至該埋置型介電層的該表面;以及當該永久基板附接至該埋置型介電層時,在該永久基板中界定的凹穴內側接收該處理晶圓的該第一區段。
- 如申請專利範圍第1項所述的方法,其中,該凹穴經尺寸調整並且定位以接收該處理晶圓的該第一區段,該永久基板具有與該埋置型介電層的該表面附接的表面,並且當該永久基板附接至該埋置型介電層的該表面時,該埋置型介電層的該表面與該永久基板的該表面共面。
- 如申請專利範圍第1項所述的方法,其中,在移除該處理晶圓的該第二區段之前,形成該一或多個深溝槽電容器。
- 如申請專利範圍第1項所述的方法,其中,在附接該 永久基板之前,形成該一或多個深溝槽電容器。
- 如申請專利範圍第1項所述的方法,其中,使該永久基板附接至該埋置型介電層包含:利用黏著層使該永久基板採黏著方式接合至該埋置型介電層,其中,該凹穴經尺寸調整並且定位,而在該第一區段與該永久基板之間,利用該黏著層的一部分接收該處理晶圓的該第一區段。
- 如申請專利範圍第1項所述的方法,其中,該處理晶圓的該第一區段的一部分佈置於該一或多個深溝槽電容器與該永久基板之間。
- 如申請專利範圍第1項所述的方法,更包含:在移除該處理晶圓的該第二區段之前,先將暫時基板附接至該矽絕緣體基板;以及在移除該處理晶圓的該第二區段之後,將該暫時基板移離該矽絕緣體基板,其中,該暫時基板在附接至該矽絕緣體基板時,通過該埋置型介電層與該永久基板分離。
- 如申請專利範圍第1項所述的方法,更包含:利用位於該凹穴的一位置的開口塗敷蝕刻遮罩至該永久基板;以及在該永久基板中蝕刻該凹穴。
- 如申請專利範圍第1項所述的方法,更包含:薄化該處理晶圓; 薄化該處理晶圓之後,塗敷將該處理晶圓的該第一區段包覆的蝕刻遮罩;以及蝕刻該處理晶圓以移除該處理晶圓的該第二區段。
- 如申請專利範圍第1項所述的方法,其中,該永久基板具有與該埋置型介電層的該表面附接的表面,並且當該永久基板附接至該埋置型介電層的該表面時,該埋置型介電層的該表面與該永久基板的該表面共面。
- 一種使用矽絕緣體基板形成的集合體,該集合體包含:該矽絕緣體基板的裝置層;該矽絕緣體基板的埋置型介電層,該埋置型介電層具有與該裝置層接觸的第一表面、及第二表面;該矽絕緣體基板的處理晶圓的區段,佈置於該埋置型介電層的該第二表面上;永久基板,附接至該埋置型介電層,該永久基板包括組配成用以接收該處理晶圓的該區段的凹穴;以及一或多個深溝槽電容器,延伸穿過該裝置層及該埋置型介電層進入該處理晶圓的該區段中。
- 如申請專利範圍第11項所述的集合體,其中,該凹穴經尺寸調整並且定位以接收該處理晶圓的該區段,該永久基板具有表面,並且該埋置型介電層的該第二表面與該永久基板的該表面共面。
- 如申請專利範圍第11項所述的集合體,更包含: 黏著層,組配成用以使該永久基板採黏著方式接合至該埋置型介電層,其中,該凹穴經尺寸調整並且定位,而在該區段與該永久基板之間,利用該黏著層的一部分接收該處理晶圓的該區段。
- 如申請專利範圍第11項所述的集合體,其中,該處理晶圓的該區段的一部分佈置於該一或多個深溝槽電容器與該永久基板之間。
- 如申請專利範圍第11項所述的集合體,其中,該永久基板具有表面,並且該埋置型介電層的該第二表面與該永久基板的該表面共面。
- 如申請專利範圍第11項所述的集合體,其中,該永久基板由高電阻矽、藍寶石、石英或礬土所構成。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/982,576 US9818637B2 (en) | 2015-12-29 | 2015-12-29 | Device layer transfer with a preserved handle wafer section |
US14/982,576 | 2015-12-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201735262A TW201735262A (zh) | 2017-10-01 |
TWI627708B true TWI627708B (zh) | 2018-06-21 |
Family
ID=59010646
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW105142969A TWI627708B (zh) | 2015-12-29 | 2016-12-23 | 具有保留處理晶圓部之裝置層轉移 |
Country Status (4)
Country | Link |
---|---|
US (2) | US9818637B2 (zh) |
CN (1) | CN107039291B (zh) |
DE (1) | DE102016226280B4 (zh) |
TW (1) | TWI627708B (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9881925B2 (en) * | 2016-06-24 | 2018-01-30 | International Business Machines Corporation | Mirror contact capacitor |
US10658386B2 (en) | 2018-07-19 | 2020-05-19 | Psemi Corporation | Thermal extraction of single layer transfer integrated circuits |
US10573674B2 (en) * | 2018-07-19 | 2020-02-25 | Psemi Corporation | SLT integrated circuit capacitor structure and methods |
TWI731260B (zh) * | 2018-08-30 | 2021-06-21 | 奕力科技(開曼)股份有限公司 | 半導體基板結構及其製造方法 |
US11404534B2 (en) * | 2019-06-28 | 2022-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside capacitor techniques |
US12002758B2 (en) * | 2021-11-04 | 2024-06-04 | International Business Machines Corporation | Backside metal-insulator-metal (MIM) capacitors extending through backside interlayer dielectric (BILD) layer or semiconductor layer and partly through dielectric layer |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070045820A1 (en) * | 2005-08-26 | 2007-03-01 | Innovative Micro Technology | Trench plating process and apparatus for through hole vias |
US20100230735A1 (en) * | 2009-03-12 | 2010-09-16 | International Business Machines Corporation | Deep Trench Capacitor on Backside of a Semiconductor Substrate |
US20110233785A1 (en) * | 2010-03-24 | 2011-09-29 | International Business Machines Corporation | Backside dummy plugs for 3d integration |
US20130147007A1 (en) * | 2011-12-09 | 2013-06-13 | International Business Machines Corporation | Deep isolation trench structure and deep trench capacitor on a semiconductor-on-insulator substrate |
US20150001580A1 (en) * | 2013-07-01 | 2015-01-01 | International Business Machines Corporation | Silicon controlled rectifier with integral deep trench capacitor |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5414276A (en) | 1993-10-18 | 1995-05-09 | The Regents Of The University Of California | Transistors using crystalline silicon devices on glass |
US6582985B2 (en) | 2000-12-27 | 2003-06-24 | Honeywell International Inc. | SOI/glass process for forming thin silicon micromachined structures |
US7176528B2 (en) | 2003-02-18 | 2007-02-13 | Corning Incorporated | Glass-based SOI structures |
JP2005201818A (ja) | 2004-01-16 | 2005-07-28 | Alps Electric Co Ltd | 圧力センサ |
US7964807B2 (en) | 2007-09-21 | 2011-06-21 | Kulite Semiconductor Products, Inc. | Pressure switch employing silicon on insulator (SOI) technology |
US20110241185A1 (en) * | 2010-04-05 | 2011-10-06 | International Business Machines Corporation | Signal shielding through-substrate vias for 3d integration |
FR2965974B1 (fr) | 2010-10-12 | 2013-11-29 | Soitec Silicon On Insulator | Procédé de collage moléculaire de substrats en silicium et en verre |
US8536021B2 (en) | 2010-12-24 | 2013-09-17 | Io Semiconductor, Inc. | Trap rich layer formation techniques for semiconductor devices |
JP5926527B2 (ja) | 2011-10-17 | 2016-05-25 | 信越化学工業株式会社 | 透明soiウェーハの製造方法 |
US8586444B2 (en) * | 2012-03-23 | 2013-11-19 | International Business Machines Corporation | Creating deep trenches on underlying substrate |
US20150262902A1 (en) * | 2014-03-12 | 2015-09-17 | Invensas Corporation | Integrated circuits protected by substrates with cavities, and methods of manufacture |
-
2015
- 2015-12-29 US US14/982,576 patent/US9818637B2/en active Active
-
2016
- 2016-12-23 TW TW105142969A patent/TWI627708B/zh active
- 2016-12-28 CN CN201611235733.9A patent/CN107039291B/zh active Active
- 2016-12-29 DE DE102016226280.7A patent/DE102016226280B4/de active Active
-
2017
- 2017-08-31 US US15/692,666 patent/US10037911B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070045820A1 (en) * | 2005-08-26 | 2007-03-01 | Innovative Micro Technology | Trench plating process and apparatus for through hole vias |
US20100230735A1 (en) * | 2009-03-12 | 2010-09-16 | International Business Machines Corporation | Deep Trench Capacitor on Backside of a Semiconductor Substrate |
US20110233785A1 (en) * | 2010-03-24 | 2011-09-29 | International Business Machines Corporation | Backside dummy plugs for 3d integration |
US20130147007A1 (en) * | 2011-12-09 | 2013-06-13 | International Business Machines Corporation | Deep isolation trench structure and deep trench capacitor on a semiconductor-on-insulator substrate |
US20150001580A1 (en) * | 2013-07-01 | 2015-01-01 | International Business Machines Corporation | Silicon controlled rectifier with integral deep trench capacitor |
Also Published As
Publication number | Publication date |
---|---|
US9818637B2 (en) | 2017-11-14 |
US20180005873A1 (en) | 2018-01-04 |
DE102016226280B4 (de) | 2021-09-02 |
TW201735262A (zh) | 2017-10-01 |
CN107039291A (zh) | 2017-08-11 |
DE102016226280A1 (de) | 2017-06-29 |
US20170186643A1 (en) | 2017-06-29 |
US10037911B2 (en) | 2018-07-31 |
CN107039291B (zh) | 2019-09-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI627708B (zh) | 具有保留處理晶圓部之裝置層轉移 | |
US10157838B2 (en) | Backside device contact | |
US8900966B2 (en) | Alignment for backside illumination sensor | |
US7906363B2 (en) | Method of fabricating semiconductor device having three-dimensional stacked structure | |
US10790190B2 (en) | Backside contact to a final substrate | |
US7935571B2 (en) | Through substrate vias for back-side interconnections on very thin semiconductor wafers | |
CN104752378A (zh) | 半导体器件及其制造方法 | |
JP2008218832A (ja) | 半導体装置の製造方法、及び、半導体装置 | |
US9859382B2 (en) | Integrated CMOS wafers | |
CN105742337A (zh) | 包括隔离结构的半导体器件以及制造半导体器件的方法 |