TWI618120B - Epitaxial process - Google Patents

Abstract

An epitaxial process comprising the following steps. First, a recess is formed in a substrate. Next, a seed layer is formed to cover a surface of the recess. Successively, a buffer layer is formed on the seed layer. Further, an etching process is performed on the buffer layer to shape the buffer layer. Then, an epitaxial layer is formed on the buffer layer.

Description

Epitaxial process

The present invention relates to an epitaxial process, and more particularly to an epitaxial process for shaping a buffer layer beneath an epitaxial layer.

As semiconductor processes enter the deep submicron era, such as processes below 65 nanometers (nm), the drive current of MOS transistor components has become increasingly important. In order to improve the performance of components, the so-called "strained-silicon technology" has been developed in the industry. The principle is mainly to strain the germanium lattice of the gate channel portion, so that the charge passes through the strain gate channel. The movement force at the time increases, thereby achieving the purpose of making the MOS transistor operate faster. Among the currently known techniques, MOS transistors using strained silicon as a substrate have been used which utilize the lattice constant of bismuth (SiGe) or bismuth carbon (SiC) and single crystal Si (single crystal Si). Different characteristics cause the epitaxial layer or the tantalum carbon epitaxial layer to be structurally strained to form strain enthalpy. Since the lattice constant of the germanium epitaxial layer or the germanium carbon epitaxial layer is larger or smaller than that of the germanium, this causes a change in the band structure of the germanium, which causes an increase in carrier mobility, and thus can be increased. The speed of the MOS transistor.

Furthermore, the performance of the epitaxial layer is related to its size, the composition of the structure and its distribution, and its location, even to the relative position of the gate. How to improve the performance of the epitaxial layer, to improve the performance of the formed semiconductor structure or to achieve the required electrical requirements, has been an important issue in the field.

The present invention provides an epitaxial process that shapes a buffer layer in a recess in which an epitaxial layer is to be formed to control the volume of the epitaxial layer formed on the buffer layer and its cross-sectional profile.

The present invention provides an epitaxial process comprising the following steps. First, a recess is formed in a substrate. Next, a seed layer is formed to cover a surface of the recess. Successively, a buffer layer is formed on the seed layer. Further, an etching process is performed on the buffer layer to shape the buffer layer so that the buffer layer is substantially at the center and the thickness at the edge is substantially equal. Then, an epitaxial layer is formed on the buffer layer.

Based on the above, the present invention provides an epitaxial process in which a seed layer is sequentially formed to form a buffer layer, and an etching process is performed to shape the buffer layer, and then an epitaxial layer is formed on the buffer layer. on. In this way, the formed buffer layer can promote the epitaxial layer to easily grow on, and reduce defects such as poor row. Moreover, the volume and cross-sectional profile of the epitaxial layer can be further controlled by controlling the flatness of the shaped buffer layer and its remaining thickness to achieve the desired electrical requirements. Preferably, the volume of the formed epitaxial layer can be enlarged by etching and shaping a thinner buffer layer to increase the stress applied thereto. Therefore, the method of forming and shaping the buffer layer of the present invention can enhance the stress effect of the epitaxial layer.

110‧‧‧Base

120‧‧‧ gate

122‧‧‧ dielectric layer

124‧‧‧electrode layer

126‧‧‧ cover

130‧‧‧ spacer

140‧‧‧ seed layer

150, 150' ‧ ‧ buffer layer

160‧‧‧ epitaxial layer

162‧‧‧Blocked epitaxial layer

164‧‧‧Cover layer

C‧‧‧gate channel

D1‧‧‧depth

K1, K2, K3, K4, K5‧‧‧ steps

P1, P2‧‧‧ etching process

R‧‧‧ groove

S1, S2, S3‧‧‧ surface

T1, T2, T3‧‧‧ top surface

T4‧‧‧ bottom

FIG. 1 is a flow chart showing an epitaxial process according to an embodiment of the present invention.

2-8 are schematic cross-sectional views showing an epitaxial process according to an embodiment of the present invention.

FIG. 1 is a flow chart showing an epitaxial process according to an embodiment of the present invention. 2-8 are schematic cross-sectional views showing an epitaxial process according to an embodiment of the present invention. In the present embodiment, the second embodiment is exemplified to clearly reveal the epitaxial process to be disclosed in the present invention, but the number of gates is not limited thereto. Furthermore, the present invention is exemplified by an epitaxial layer formed beside the gate, but the invention is not limited thereto. Moreover, the present invention forms a PMOS transistor by forming or doping a germanium element or forming a germanium layer and forming a germanium epitaxial layer or the like, but the invention is not limited thereto. In other embodiments, other tri-group elements may also be doped or doped to form an epitaxial layer of a PMOS transistor. Alternatively, a group of five elements such as carbon or phosphorus may be introduced or doped to form an epitaxial layer of the NMOS transistor.

Please refer to Figure 1 and Figure 2-3. According to step K1 of Fig. 1, a groove is formed in a substrate. In detail, as shown in FIG. 2, a substrate 110 is provided. The substrate 110 is, for example, a substrate, a germanium-containing substrate, a tri-five-layer overlying substrate (eg, GaN-on-silicon), a graphene-on-silicon or a silicon-on-insulator (silicon- On-insulator, SOI) A semiconductor substrate such as a substrate.

Next, a plurality of gates 120, such as two gates 120, are formed on the substrate 110. The gate 120 can include a dielectric layer 122, an electrode layer 124, and a cap layer 126. The dielectric layer 122 can be, for example, an oxide layer, a buffer layer, or a high-k dielectric layer, etc., depending on the semiconductor process to which the present invention is associated. For example, the present invention can be combined with a polysilicon process, a gate-first process, a gate-Last process, etc., wherein the back gate can further comprise a pre-high dielectric constant dielectric layer. After the Gate-Last for High-K First or a post-high dielectric constant layer (Gate-Last for High-K Last) process, depending on actual needs. In this embodiment, the gate layer process is followed by a gate dielectric process with a pre-high-k dielectric layer. The dielectric layer 122 can include, for example, a buffer layer and a high-k dielectric layer. The buffer layer can be, for example, an oxide layer for buffering the high-k dielectric layer and the substrate 110. The high-k dielectric layer can be, for example, a metal-containing dielectric layer, which may include a hafnium oxide or a zirconium oxide, but the invention is not limited thereto. Furthermore, the high dielectric constant gate dielectric layer may be selected from the group consisting of hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), and niobium oxynitride (hafnium). Silicon oxynitride, HfSiON), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y _{2 )} O ₃ ), zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO _{4 )} ), strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZrxTi1-xO ₃ , PZT) and barium strontium titanate (BaxSr1-) A group consisting of xTiO ₃ , BST), but the invention is not limited thereto. The electrode layer 124 can be, for example, a polysilicon layer for use as a sacrificial gate, and is replaced with a metal gate by a replacement metal gate (RMG) process in a subsequent process; the cap layer 126 is, for example, A single layer or a double layer structure such as a nitride layer or/and an oxide layer, but the invention is not limited thereto.

Thereafter, two spacers 130 are formed on the substrate 110 on the side of the gate 120 to define the position of the epitaxial layer in the substrate 110 to be formed on the side of the gate 120, wherein the epitaxial layer is formed relative to the gate The position of the pole 120 directly affects the stress applied by the epitaxial layer to one of the gate channels C below each gate 120. The spacer 130 may be, for example, a single layer or a double layer structure such as an oxide layer, a nitride layer or an oxynitride layer. To simplify the description, the spacers 130 of the present embodiment are nitride spacers, and before or after the spacers 130 are formed, other spacers may be formed to form other portions. example For example, a spacer (not shown) may be formed before the spacer 130 is formed to define a lightly doped source/drain (not shown) formed in the substrate 110 on the side of the gate 120; Alternatively, after the spacers 130 are formed, a spacer (not shown) is formed to define a source/drain (not shown) formed in the substrate 110 on the side of the gate 120. The front and back sequence of the formation of the spacers 130 or other spacers may be reversed, and the spacers may be partially or completely removed after corresponding formation of the epitaxial layer, lightly doped source/drain or source/drain, as desired. The structure depends.

Thereafter, an etching process P1 is performed to form a recess R on at least one side of each of the gates 120. Preferably, a recess R is formed in each of the opposite sides of the gate 120. For convenience of explanation, as shown in FIG. 2, a groove R is formed in the base 110 between the two gap walls 130. The etching process P1 can be, for example, a dry etching process or/and a wet etching process. For example, the etching process P1 may include performing a dry etching process to form a predetermined depth d1 of the recess R, and performing a wet etching process to adjust the shape and size of the recess R. In the present embodiment, the groove R has a diamond-shaped cross-sectional structure, but the invention is not limited thereto. In other embodiments, the groove R may have a cross-sectional structure of other shapes, such as a U-shaped cross-sectional structure, a hexagonal cross-sectional structure, or an octagonal cross-sectional structure. The epitaxial process proposed by the present invention can be applied to the groove R having a cross-sectional structure of various shapes (or an epitaxial layer which can be applied to a cross-sectional structure having various shapes which are subsequently formed in the groove R).

According to step K2 of Fig. 1, a seed layer is formed to cover a surface of the groove. As shown in FIG. 4, a seed layer 140 is formed to cover a surface S1 of the recess R. The seed layer may be formed, for example, by a chemical vapor deposition (CVD) process including a helium-containing gas, but the invention is not limited thereto. In this embodiment, the method of forming the seed layer may pass only dichlorosilane (DCS) gas. To form a pure tantalum layer on the surface S1 of the groove R, but the invention is not limited thereto. Furthermore, the method of forming the seed layer may be additionally introduced with other gases to form a surface S1 containing the tantalum layer on the groove R, depending on the actual process needs or the desired structure. For example, hydrogen chloride (HCl) gas may be used in combination to selectively form a layer of ruthenium, wherein the ratio formed at each specific position can be obtained by adjusting dichloromethane gas and hydrogen chloride gas. In other words, by simultaneously introducing the methylene chloride gas and the hydrogen chloride gas, a portion of the region can be removed by etching while the seed layer 140 is formed, and the contour of the formed seed layer 140 can be more precisely controlled under the macroscopic view. .

According to step K3 of Fig. 1, after the seed layer 140 is formed, a buffer layer is subsequently formed on the seed layer. As shown in FIG. 5, a buffer layer 150 is formed on the seed layer 140. The buffer layer 150 can be, for example, a low concentration germanium layer for buffering the surface of the recess R or the pure germanium seed layer 140 and the higher concentration epitaxial layer subsequently formed on the buffer layer 150. Reduce structural defects such as the difference between the epitaxial layers. Therefore, the seed layer 140 and the buffer layer 150 comprise different materials or different materials of different concentrations. Preferably, the buffer layer 150 has a germanium content of less than 50%. Still more preferably, the buffer layer 150 has a germanium content in a gradient distribution, the concentration of which can be increased internally by the outer (substantially contacting the seed layer 140). The seed layer 150 can be formed, for example, by a chemical vapor deposition (CVD) process including a helium-containing gas, but the invention is not limited thereto. For example, the seed layer 150 may be formed, for example, by passing hydrogen chloride (HCl), dichlorosilane (DCS), and germanium (GeH ₄ ) gas, wherein the helium gas may be, for example, hydrogenated germanium (germane , GeH ₄ ) gas, but the invention is not limited thereto. For example, a standard Cubic Centimeter per Minute (sccm) methylene chloride and a 250 sccm helium gas can be introduced at 10 torr, or the helium gas flow rate can be 70. ~380 sccm. In addition, a hydrogen chloride (HCl) gas may be further used in the deposition state to simultaneously remove a portion of the region by etching, and the buffer layer 150 may be formed at a specific position under a giant view.

Furthermore, the buffer layer 150 can be selectively doped with boron ions. One use of the buffer layer 150 prevents the boron component in the boron-containing epitaxial layer subsequently formed thereon from diffusing outward to the substrate 110, so that the boron content of the buffer layer 150 can be adjusted, even without boron. To achieve this. It is emphasized here that the buffer layer 150 formed at this time has an uneven and rough surface S2. If the epitaxial layer is directly formed on the buffer layer 150, the structural defects of the epitaxial layer and the formed volume and Problems with uncontrollable profile profiles affect device performance.

Therefore, according to step K4 of FIG. 1, an etching process is performed on the buffer layer to shape the rough surface of the buffer layer. As shown in FIG. 6, an etching process P2 is performed to shape the buffer layer 150 to form a buffered layer 150' having a surface S3 at the center of the bottom of the groove and in the groove. The thickness at the edges is substantially the same. In this way, the foregoing problem can be solved, that is, the defect of the epitaxial layer formed on the buffer layer 150' is reduced, and the volume and cross-sectional profile of the epitaxial layer are controlled, and even the step of shaping is removed. The buffer layer 150 (rough surface S2) forms a flat surface S3, so that the volume of the formed epitaxial layer can be enlarged, and the stress performance applied to the gate channel C can be improved.

The etching process P2 may, for example, pass at least one etching gas to etch a specific region or a buffer layer 150 of a specific crystal face. In an embodiment, the etching gas may be, for example, hydrogen chloride gas, which may etch a buffer layer 150 of a specific crystal face to remove more uneven regions to form the buffer layer 150 ′, but the invention is not limited thereto. . Furthermore, the etching process P2 may, for example, further include the introduction of at least one deposition gas to compensate for the over-etched portion during the etching process, and to control the etching rate at a specific location. The deposition gas may, for example, comprise methane (silane, SiH ₄ ), dichlorosilane (DCS) or/and germane (GeH ₄ ) gas. It is emphasized here that since the etching rate of the etching process P2 must be greater than the deposition rate, the characteristics of the etching or shaping buffer layer 150 can be maintained at a macroscopic view. Furthermore, the total flow rate of the etching gas of the etching process P2 may be greater than the total flow rate of the deposition gas to maintain its etching or shaping characteristics. For example, when the etching process P2 simultaneously introduces hydrogen chloride gas as an etching gas, and the methylene chloride gas and the helium gas act as a deposition gas, the hydrogen chloride gas is preferably 200 sccm, and the methylene chloride gas is 50 sccm. The gas mixture is 120 sccm, so the total flow rate of the etching gas (ie, the flow rate of hydrogen chloride gas) is greater than the total flow rate of the deposition gas (ie, the flow rate of the methylene chloride gas plus the helium gas), so that a specific region can be obtained. There is a suitable etching rate, but the invention is not limited thereto. In addition, the etching process P2 is preferably performed at a low voltage to have different etching rates for each of the lattice faces, and the shaping step of the buffer layer 150 can be precisely controlled, and the thickness of the buffer layer 150' can be controlled. For example, it is carried out at a low pressure of from 0.1 torr to 200 torr. Preferably, it may be a low pressure of 1 to 100 torr, and more preferably a low pressure of 5 to 50 torr.

Further, the etching process P2 is preferably performed in-situ, so that the buffer layer 150' or the like is not oxidized or contaminated by vacuum. In other words, the etching process P2 can be performed in the same process chamber, for example, with the formation of the seed layer 140, the formation of the buffer layer 150', and the formation of the subsequent epitaxial layer. More preferably, in the same process, only the different processes of different gases or the same gas may be used to perform the etching process P2, the seed layer 140 is formed, the buffer layer 150' is formed, and the subsequent epitaxial layer is formed, as needed. This ensures quality and simplifies the process and reduces costs.

Then, according to step K5 of FIG. 1, an epitaxial layer is formed on the buffer layer. As shown in Figures 7-8, an epitaxial layer 160 is formed over the buffer layer 150'. In an embodiment, the epitaxial layer 160 includes a germanium epitaxial layer, but the invention is not limited thereto. In the present embodiment, the epitaxial layer 160 includes a strip-shaped epitaxial layer 162 and a capping epitaxial layer 164 from bottom to top.

In detail, as shown in FIG. 7, a bulk epitaxial layer is formed on the buffer layer. At this time, the bulk epitaxial layer 162 needs to fill the groove R of FIG. Preferably, a top surface T1 of the bulk epitaxial layer 162 is located on the same water surface as at least one top surface T2 of the substrate 110, so that the stress effect of the bulk epitaxial layer 162 can be fully exerted without forming It is recessed on the bulk epitaxial layer 162, resulting in difficulty in subsequent structural coverage. The bulk epitaxial layer 162 may be, for example, a germanium epitaxial layer and has a germanium content of more than 15%, and a stress is applied to the gate channel C at a concentration high enough because the bulk epitaxial layer 162 is the main layer. A stressed epitaxial layer. The bulk epitaxial layer 162 can be formed, for example, by a vapor deposition process, but the invention is not limited thereto. For example, 50 sccm of methylene chloride and 600 sccm of hydrazine hydride gas may be introduced at 10 torr, or the flow rate of the hydrazine hydride gas may be between 380 and 800 sccm. Furthermore, the bulk epitaxial layer 162 may be doped with boron plasma to increase its conductivity. For example, 220 sccm of diborane (Diborane, B ₂ H ₆ ) or diborane of 70 to 280 sccm is introduced, but the invention is not limited thereto.

Then, as shown in FIG. 8, a capping epitaxial layer 164 is formed on the bulk epitaxial layer 162. A top surface T3 of the capping epitaxial layer 164 is higher than the top surface T2 of the substrate 110. In this embodiment, the capping epitaxial layer 164 may be, for example, a germanium layer to prevent outward diffusion of germanium or the like in the bulk epitaxial layer 162 underneath. The capping epitaxial layer 164, in turn, can be, for example, a layer of germanium, with the germanium decreasing from bottom to top. Preferably, the maximum germanium content of the capping epitaxial layer 164 (ie, the germanium content on a bottom surface T4) is lower than the germanium content of the bulk epitaxial layer 162, and the germanium content of the top surface T3 of the capping epitaxial layer 164. It is essentially zero. Furthermore, the cover layer The layer 164 can also be selectively doped with boron plasma to increase its conductivity.

In the future, other subsequent semiconductor processes, such as implant source/drainage (not shown) doping or self-aligned metal salicide processes, may be continued, and are not described here. In addition, the time point of the dopant source/drain (not shown) may also be implemented before the etching process P1 for forming the recess R or when the bulk epitaxial layer 162 is formed.

In summary, the present invention provides an epitaxial process in which a seed layer is sequentially formed to form a buffer layer, and an etching process is performed to shape the buffer layer, and then an epitaxial layer is formed to shape the layer. On the buffer layer. In this way, the formed buffer layer can promote the epitaxial layer to easily grow thereon, and reduce defects such as dislocation. Moreover, the volume and cross-sectional profile of the epitaxial layer can be further controlled by controlling the flatness of the shaped buffer layer and its remaining thickness to achieve the desired electrical requirements. Preferably, the volume of the formed epitaxial layer can be enlarged by shaping a thinner buffer layer. Therefore, the method of forming and shaping the buffer layer of the present invention can enhance the stress effect of the epitaxial layer applied to the gate channel.

Furthermore, the etching process of the present invention can etch a specific region or a buffer layer of a specific crystal face while etching a desired shaped buffer layer. The etching process can include at least one etching gas and optionally a deposition gas. However, the etching rate of the etching process must be greater than the deposition rate to achieve its etching function. Intuitively, the total flow rate of the etching gas of the etching process can be set to be larger than the total flow rate of the deposition gas to ensure its etching or shaping characteristics. In this way, by simultaneously introducing the etching gas and the deposition gas, and adjusting the composition and ratio of the two, a more flexible control of the etching rate of the specific region can be achieved; in other words, different regions have different etchings. rate, And to achieve the effect of shaping.

Preferably, the etching process may comprise hydrogen chloride gas as an etching gas, and optionally further comprises methane, methylene chloride or/and a helium gas as a deposition gas. Furthermore, the steps of forming a seed layer, forming a buffer layer, performing an etching process, and forming an epitaxial layer are preferably performed in the same process chamber, or the etching process may be performed in situ to prevent a vacuum in the process. Contamination of various material layers. More preferably, these steps can be formed in different ratios of different gases or the same gas in the same process chamber, thereby simplifying the process and reducing pollution, thereby improving yield and quality.

In addition, the epitaxial process of the present invention is also applicable to a non-planar field effect transistor such as a Fin Field-effect Transistor (FinFET), which means that the gate is spanned over the fin structure and utilized. After the gate and the spacer are used as a mask to etch the fin structure to form the recess, then, as described above, a seed layer is sequentially formed to form a buffer layer, and an etching process is performed to shape the buffer layer. Finally, an epitaxial layer is formed on the shaped buffer layer.

Claims (17)

An epitaxial process includes: forming a recess in a substrate; forming a seed layer covering a surface of the recess; forming a buffer layer on the seed layer, wherein the buffer layer comprises a layer And the buffer layer has a germanium content of less than 50%; an etching process is performed on the buffer layer to shape the buffer layer; and an epitaxial layer is formed on the buffer layer. The epitaxial process of claim 1, wherein the seed layer comprises a dichlorosilane (DCS) gas. The epitaxial process of claim 1, wherein the buffer layer comprises a hydrogen chloride (HCl), dichlorosilane (DCS), germanium (Gemanium, GeH ₄ ) gas. The epitaxial process of claim 1, wherein the etching process comprises introducing at least one etching gas. The epitaxial process of claim 4, wherein the etching gas comprises hydrogen chloride gas. The epitaxial process of claim 4, wherein the etching process comprises introducing at least one deposition gas. The epitaxial process of claim 6, wherein the deposition gas comprises methane (silane, SiH ₄ ), dichlorosilane (DCS) or/and germanium (GeH ₄ ) gas. The epitaxial process of claim 6, wherein the total flow rate of the etching gas is greater than the total flow rate of the deposition gas. The epitaxial process described in claim 6 wherein the etching rate of the etching process is greater than the deposition rate. The epitaxial process described in claim 1, wherein the etching process is performed in situ. The epitaxial process of claim 1, wherein the etching process, the formation of the seed layer, the formation of the buffer layer, and the formation of the epitaxial layer are all in the same process chamber. The epitaxial process of claim 11, wherein the etching process is performed, the seed layer is formed, the buffer layer is formed, and the epitaxial layer is formed to pass different gases. The epitaxial process of claim 1, wherein the epitaxial layer comprises a germanium epitaxial layer. The epitaxial process of claim 1, wherein the epitaxial layer comprises a piece of epitaxial layer and a capped epitaxial layer from bottom to top. The epitaxial process described in claim 14 wherein the bulk epitaxial layer package It contains a layer of epitaxial layer and its germanium content is higher than 15%. The epitaxial process of claim 1, wherein the seed layer and the buffer layer comprise different materials. The epitaxial process of claim 1, wherein the seed layer comprises a layer of germanium.